CHAPTER 44.1 Remainder

From the remainders, we get the 8-bit number as follows:N2 = 1 0 0 1 0 0 1 1

4.2 Remainder

From the remainders, we get the 8-bit number as follows:N2 = 1 0 0 1 0 0 0 1

4.3 Remainder

From the remainders, we get the 12-bit number as follows:N2 = 0 1 0 0 0 1 1 1 1 1 0 1

Note that the MSB must be zero since we have only eleven remainders.

4.1

4.4 Remainder

From the remainders, we get the 12-bit number as follows:N2 = 0 0 1 1 0 1 1 0 1 0 0 0

Note that the MSB must be zero since we have only eleven remainders.

4.2

4.5 We first find the 8-bit number for +121:

Remainder

The 8-bit number for +121 is 01111001.

To find the 8-bit number for -121, we first invert the 8-bit number for +121: 10000110.

Then we add 1 to obtain the 8-bit number for -121: 10000111.

4.6 We first find the 8-bit number for +101:

Remainder

The 8-bit number for +121 is 01100101.

To find the 8-bit number for -121, we first invert the 8-bit number for +121: 10011010.

Then we add 1 to obtain the 8-bit number for -121: 10011011.

4.3

4.7 Remainder

The 2's complement binary equivalent is thus,001101111011

4.8 Remainder

The 2's complement binary equivalent is thus,001010110111

4.4

4.9 To find the decimal value for 10010001, we must first subtract 1 from the LSB thus giving:

10010000Next, we invert the 1's and 0's as follows:

01101111Finally, we evaluate the decimal:

4.10 To find the decimal value for 10001001, we must first subtract 1 from the LSB thus giving:

10001000Next, we invert the 1's and 0's as follows:

01110111Finally, we evaluate the decimal:

4.11 The following table presents the maximum decimal number versus the number of bits for simple binary:

No. Bits Max. Dec. No. Simple Binary

12 212 -1 = 409513 213 -1 = 819114 214 -1 = 16383 15 215 -1 = 3276716 216 -1 = 65535

Consequently, 15 bits are needed to represent 27541 in simple binary. For a two's complement binary number, the MSB will be zero so 16 bits will be required.

4.5

4.12 The following table presents the maximum decimal number versus the number of bits for simple binary:

No. Bits Max. Dec. No. Simple Binary

12 212 -1 = 409513 213 -1 = 819114 214 -1 = 16383 15 215 -1 = 3276716 216 -1 = 65535

Consequently, 14 bits are needed to represent 12034 in simple binary. For a two's complement binary number, the MSB will be zero so 16 bits will be required.

4.13 The following table presents the maximum decimal number versus the number of bits for simple binary:

No. Bits Max. Dec. No. for Simple Binary8 28 -1 = 2559 29 -1 = 51110 210 -1 = 102311 211 -1 = 204712 212 -1 = 4095

Consequently, 10 bits are needed to represent 756 in simple binary. However, for -756, an additional bit is required to represent the sign. Hence, 11 bits will be required. The representation of -756 in 2's complement binary is 10100001100.

4.14 The following table presents the maximum decimal number versus the number of bits for simple binary:

No. Bits Max. Dec. No. for Simple Binary8 28 -1 = 2559 29 -1 = 51110 210 -1 = 102311 211 -1 = 204712 212 -1 = 4095

Consequently, 10 bits are needed to represent 534 in simple binary. However, for -534, an additional bit is required to represent the sign. Hence, 11 bits will be required. The representation of -534 in 2's complement binary is 11011101010.

4.6

4.15 N = 12Vru = 8VVrl = -8VVin = input voltage

(a) By Eq. B in Fig. 4.7:

(b) By Eq. B in Fig. 4.7:

(c) Since 10.9V falls outside the input range, Do will have the maximum output:

(d) Since -8.5V falls outside the input range, D0 will take the minimum value:

4.7

4.16 N = 12Vru = 8VVrl = -8VVin = input voltage

(a) By Eq. B in Fig. 4.7:

(b) By Eq. B in Fig. 4.7:

(c) Since 11V falls outside the input range, Do will have the maximum output:

(d) Since 9.2V falls outside the input range, D0 will take the maximum value:

4.8

4.17

a) By Eq. B in Fig. 4.7:

b) The input is below the input range. Hence the output will be 0,D0 = 0

c) Since 11.5V falls outside the input range, the output will be the maximum possible. The output will be:

d) By Eq. B in Fig. 4.7:

4.9

4.18

a) By Eq. B in Fig. 4.7:

b) The input is below the input range. Hence the output will be 0,D0 = 0

c) By Eq. B in Fig. 4.7:

d) By Eq. B in Fig. 4.7:

4.10

4.19 We need Equation A of Figure 4.7 to solve this problem.(a) When the 1.5V signal is amplified with a gain of 10, it becomes 15V which exceeds the input range of the A/D converter (it is saturated). According to Figure 4.7, the maximum output is 2N/2-1 = 112/2-1 = 2047(b) With the gain of 10, the input becomes 8V. The output, in decimal, is then:

(c) When amplified, -1.5V results in an input to the A/D converter which is below the input range (it is saturated). The largest negative output is –2N/2 = -2048(d)With the amplifier, this voltage results in an input to the A/D of –8V. The output is then:

4.20 We need Equation A of Figure 4.7 to solve this problem.(a) When the 5.2V signal is amplified with a gain of 10, it becomes 52V which exceeds the input range of the A/D converter (it is saturated). According to Figure 4.7, the maximum output is 2N/2-1 = 112/2-1 = 2047(b) When the 1.5V signal is amplified with a gain of 10, it becomes 15V which exceeds the input range of the A/D converter (it is saturated). According to Figure 4.7, the maximum output is 2N/2-1 = 112/2-1 = 2047(c) When amplified, -5.2V results in an input to the A/D converter which is below the input range (it is saturated). The largest negative output is –2N/2 = -2048(d) When amplified, -1.5V results in an input to the A/D converter which is below the input range (it is saturated). The largest negative output is –2N/2 = -2048

4.21

From Eq. 4.1:

Input Resolution Error

The quantization error (as a percent reading) for an input of 1.36V is:

4.22

4.11

From Eq. 4.1:

Input Resolution Error

The quantization error (as a percent reading) for an input of 2.45V is:

4.23 Quantization error is computed using equation 4.1.

For 8 bits this becomes

and this is 0.42% of the 7.5V input.

For 12 bits this becomes

and this is 0.026% of the 7.5V input.

For 16 bits this becomes

and this is 0.0016% if the 7.5V

input.

4.12

4.24 Quantization error is computed using equation 4.1.

For 8 bits this becomes

and this is 0.49% of the 8V input.

For 12 bits this becomes

and this is 0.031% of the 8V input.

For 16 bits this becomes

and this is 0.0019% if the 8V

input.

4.25

From Eq. 4.1,

Input Resolution Error

The quantization error (as a percent reading) for an input of -4.16V is:

4.13

4.26

From Eq. 4.1,

Input Resolution Error

The quantization error (as a percent reading) for an input of -2.46V is:

4.27 Since the signal from the transducer varies between 15mV (0.015V) and the A/D converter input range is 10V, we can select a gain of 100 which will yield an input of 1.5V. A gain of 100 is chosen such that the amplified signal is not saturated (i.e. greater than the input range).

The quantization error from Eq. 4.1 is as follows:

Quantization Error

The transducer voltage is 3.75mV but after a gain of 100 it becomes 0.375V. Thus, the quantization error as a percent reading is as follows:

If the transducer output were attenuated by a factor of 2/3 (to 10 mV) the gain could be set to 1000 without saturating the A/D converter. The 3.75 mv output would then become 3.7510-3(2/3)1000 = 2.5 V at the input to the A/D converter and the resolution error would be reduced to 0.098%.

4.14

4.28 The amplified input must not exceed 10V.When amplified, the maximum input will be 0.075V, 0.75V and 3.75V for gains of 10, 100 and 500 respectively. So we can use the maximum gain of 500.The input resolution error is:

This is 0.033% of the maximum 7.5V input.

4.29 The amplified input must not exceed 10V.When amplified, the maximum input will be 0.1V, 1V and 5V for gains of 10, 100 and 2000 respectively. The gain of 2000 will saturate the amplified signal and become greater than the input limit of 10V. Thus the maximum gain that can be used is 100. The input resolution error is:

This is 0.024% of the maximum 10V input.

4.30

The output range will be divided into increments of:

An input of 32 would then give an output of:

4.15

4.31

The output range will be divided into increments of:

An input of 45 would then give an output of:

4.32The reference voltage increment is:

Trial digital output (D0) D0V Pass/Fail Actual digital output

100000000000 (2048) 5.0 F010000000000 (1024) 2.5 P 010000000000 (1024)011000000000 (1536) 3.75 F 010000000000 (1024)010100000000 (1280) 3.12 P 010100000000 (1280)010110000000 (1408) 3.44 F 010100000000 (1280)010101000000 (1344) 3.28 P 010101000000 (1344)010101100000 (1376) 3.36 F 010101000000 (1344)010101010000 (1360) 3.32 F 010101000000 (1344)010101001000 (1352) 3.30 F 010101000000 (1344)010101000100 (1348) 3.2901 F 010101000000 (1344)010101000010 (1346) 3.286 P 010101000010 (1346)010101000011 (1347) 3.289 P 010101000011 (1347)

The output is 010101000011 or 1347 in decimal.

4.16

4.33 The voltage increment is V = 16/212 = 0.00390625 V. Since this converter is offset binary, the expected input for a given digital output Do is 0.0039806Do - 8.0. The expected input for the final output is 4.2 V.

Trial Do VDo - 8. Pass/Fail Actual Digital Output

100000000000 (2048) 0.0 P 100000000000 (2048)110000000000 (3072) 4.0 P 110000000000 (3072)111000000000 (3584) 6.0 F 110000000000 (3072)110100000000 (3328) 5.0 F 110000000000 (3072)110010000000 (3200) 4.5 F 110000000000 (3072)110001000000 (3136) 4.25 F 110000000000 (3072)110000100000 (3104) 4.125 P 110000100000 (3104)110000110000 (3120) 4.1875 P 110000110000 (3120)110000111000 (3128) 4.21875 F 110000110000 (3120)110000110100 (3124) 4.203125 F 110000110000 (3120)110000110010 (3122) 4.195313 P 110000110010 (3122)110000110011 (3123) 4.199219 P 110000110011 (3123)

The final output is 110000110011 in binary or 3123 in decimal. The same result is obtained from Eq. B in Figure 4.7.

4.34

non-linearity error biasADC span error biasADC zero biasamplifier gain biasMUX crosstalk precisionquantization precisionaperture precisiondrift precision

4.35 How many channels available?How many bits does the ADC output?Is there programmable gain and what values of gain are possible?Maximum number of samples per second?Is there capability for automatic timing of data taking?Is there a simultaneous sample and hold capability?Is there a capability for digital input?Is there a capability for frequency input? (not discussed in chapter)Is there a capability for analog output?What range of input voltages will not permanently damage the system?What software is available for the system?If intended for a harsh environment, how durable is the package?

4.17