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  • 7/27/2019 Chapter 5 - Analog Integrated Circuit Design by John Choma

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    LECTURE SUPPLEMENT #5 . . .[LS #5]

    CHAPTER #05

    MOSFET Biasing Networks

    Dr. John ChomaProfessor of Electrical Engineering

    University of Southern California

    Ming Hsieh Department of Electrical Engineering

    University Park: Mail Code: 0271Los Angeles, California 900890271

    2137404692 [USC Office]

    2137407581 [USC Fax]

    8183841552 [Cell][email protected]

    PRELUDE:This chapter establishes the circuit concepts and circuit design strategies that underpin practicalbiasing networks suitable for use in high performance, MOSFET technology analog integrated

    circuits. We shall begin with an abridged review of the preceding chapter so that a strong tech-

    nical foundation is forged to support the development of a family of practical biasing networks.

    We shall see that these structures range from simple voltage references and current mirrors to

    networks boasting biasing that is rendered nominally independent of supply voltages. Included

    among the topical issues addressed in this chapter are conventional and low voltage reference

    circuits, traditional and advanced high performance current sources and sinks, regulated current

    sinks, and networks that feature constant or electronically tunable forward transconductances.

    July 2013

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    Chapter 5 MOSFET Biasing

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    tance are addressed, as are topologies boasting improved current source and current sink imped-

    ance properties.

    As a foundational prelude to our bias circuit discussions, the salient features of thestatic volt-ampere characteristics of MOSFETs, which we addressed in the preceding chapter, are

    reviewed. The analytical comfort level that hopefully derives from this review is indispensable

    because mathematically tractable analyses serving to complement ultimate computer-aided cir-cuit studies demand reasonable and insightfully understood device modeling approximations.

    We shall also focus on the transient responses of biasing networks subjected to the sudden

    application or removal of static power. This focus is important because the transients associatedwith circuit startup or even shutdown can prove to be destructive to sensitive, deep submicron

    transistors.

    5.2.0. STATIC MODEL OF A MOSFET

    Figure (5.1) gives the circuit schematic symbol of both n-channel and p-channel transis-

    tors. In this diagram, we explicitly show the bulk terminals appropriately connected so that bulk-

    source and bulk-drain PN junctions intrinsic to the utilized transistors are reverse biased. Inother schematic representations, we may choose not to show these bulk terminal connections.

    Regardless and unless stipulated otherwise, we presume that bulk connections are made to ensure

    the reverse biasing of PN junctions internal to the transistor.

    Figure (5.1). (a).Schematic symbol of an NMOS transistor in which the positive

    reference polarity convention for drain current and both gate-source

    and drain-source voltages are delineated. (b).Schematic symbol ofa counterpart PMOS transistor. In both diagrams, the bulk substrate

    terminals are presumed incident with signal ground.

    Figure (5.1a) delineates the positive reference polarity conventions for the drain cur-

    rent, Id, the gate-source voltage, Vgs, the drain-source voltage, Vds, and the gate-drain voltage,Vgd, are indicated. Unless otherwise specified, we assume that the substrate terminals of the p-

    type bulk of NMOS devices are connected to the smallest of available circuit potentials, which

    we indicate in the figure as Min. B. If these minimal and possibly negative circuit potentialsare constant, the bulk terminals lie at signal ground. For the p-channel device in Figure (5.1b), it

    is more convenient to cast the static volt-ampere characteristics in terms of the source-gate vol-

    tage, Vsg, the source-drain voltage, Vsd, and the drain-gate voltage, Vdg. We assume that the sub-strate terminals of the n-type bulk of all PMOS devices are incident with the most positive of

    available circuit potentials, which we delineate in the figure as Max. B+. To the extent thatthese maximum potentials are constant, the bulk nodes of PMOS transistors, like those of NMOS

    devices, are connected to signal ground. At this point in our electronic circuit travels, we should

    easily remember that positive drain current flows into an NMOS device, while positive drain cur-

    Vgs

    Vds

    Id

    Id

    (a).

    Vdg

    (b).

    Vsd

    Vsg

    Vgd

    To Min.B

    To Max.B

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    Chapter 5 MOSFET Biasing

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    rent flows out of a PMOS transistor.

    In Figure (5.1a), let Vhndesignate the threshold voltage of the NMOS transistor. If the

    transistor is biased for operation in its saturation regime where VdsVdsatVgsVhn, the simplesquare law, Schichman-Hodges model relating the drain current to the applied gate-source vol-

    tage is

    2 2no ox nd gs hn gs hn C KW WI V V V V ,2 L 2 L (5-1)

    wherenois the mobility of free electrons in the inverted channel immediately below the oxide-semiconductor interface. Specifically, no is the carrier mobility when lateral electric fieldintensities induced in the channel by applied drain-source voltages are much smaller than the

    critical field intensity, which is in the neighborhood of 5 V/m. Continuing, (W/L) is the gatewidth to drawn channel length ratio, or simply, gate aspect ratio. Parameter Coxsymbolizes thedensity of the capacitance associated with the gate oxide layer, is

    ox ox oxC T . (5-2)In (5-2), ox is the dielectric constant of silicon dioxide (345 fF/cm), while Tox is the averagethickness of the insulating gate oxide.

    The companion volt-ampere relationship for the saturated p-channel transistor in Figure

    (5.1b) is

    2 2po ox p

    d sg hp sg hp

    C KW WI V V V V ,

    2 L 2 L

    (5-3)

    which requires VsdVsgVh. In this relationship,pois the low field value of the mobility offree holes in the inverted channel. Note that the gate-source voltage, Vgs, in (5-1) is replaced bythe source-gate voltage, Vsg. The replacement of Vgsby Vsgallows threshold voltages Vhnin (5-1)

    and Vhpin (5-3) to be couched as positive voltages. We recall that the threshold voltage in MOS-

    FETs operated without the source terminal connected directly to the bulk terminal modulates

    minimally for thin gate oxide layers.It is expedient for us to write the volt-ampere equations in (5-1) and (5-3) in the forms,

    2

    d n gs hn

    2

    d p sg hp

    I V V for NMOS ,

    I V V for PMOS

    (5-4)

    where

    no ox nn

    po ox p

    p

    C KW W for NMOS

    2 L 2 L.

    C KW W

    for PMOS2 L 2 L

    (5-5)

    We observe that the introduced transconductance coefficient parameters, nandp, which havedimensional units of mhos/volt, scale linearly with gate aspect ratio, W/L.

    The compact static volt-ampere equations in (5-4) show that for given threshold vol-tage, gate aspect ratio, gate oxide capacitance density, and channel carrier mobility, the drain

    current is determined exclusively by one voltage variable; namely, gate-source voltage Vgs in

    NMOS and source-gate voltage Vsg in PMOS. The lack of drain current dependence on drain-

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    source or source-drain voltage means that the electrical characteristics of the drain-source port of

    a MOSFET are modeled as an ideal current source. In other words, (5-4) suggests that the draincurrent can be represented as an ideal, albeit nonlinear, voltage controlled current source, with

    either Vgsor Vsg serving as the controlling voltage. Since the gate terminal is incident with an

    insulating oxide layer serving as an interface between the gate contact metallization (or polysili-con) and the semiconductor surface, the gate conducts zero static current. Accordingly, the

    drain-source terminal pair emulates an ideal voltage controlled current source, as inferred by thesimple models offered in Figure (5.2). In short, the simple static model of (5-4) stipulates that

    when MOSFETs operate in their saturation regions, their drain currents are functionally depen-dent, albeit to first order, on only gate-source voltages. Conversely, a current forced to flow in

    the MOSFET drain establishes, by virtue of (5-4), a unique gate-source potential. We should

    note further that if both the NMOS and PMOS devices are operated to conduct a fixed staticdrain current, progressively larger gate aspect ratios result in a gate-source (or a source-gate) vol-

    tage that approaches threshold value.

    Figure (5.2). (a).Simplified static model of an NMOS transistor biased for operation in satura-

    tion. The drain current,Id, is exclusively a function of the gate-source voltage,

    Vgs. (b).Simplified static model of a PMOS transistor biased for operation insaturation. To first order the drain current, Id, is exclusively a function of the

    source-gate voltage, Vsg. The ground connection at the bulk terminals of both de-

    vices indicates signal ground only.

    5.2.1. TEMPERATURE SENSITIVITY

    In contrast to a BJT, whose static collector current exhibits positive temperature coeffi-

    cient, the static volt-ampere characteristics of a MOSFET display negative temperature sensitiv-

    ity. In other words, for constant gate-source or source-gate voltages, the observed drain currentdecreases with increasing interfacial operating temperatures. Two principle phenomenological

    reasons contribute to the negative temperature coefficient of a MOSFET. The first of these de-

    rives from the fact that the carrier mobility in the inverted channel of a transistor decreases nomi-

    nally as a three-halves power law of absolute temperature. In particular,

    Vgs

    Vds

    Id

    Id

    (a).

    Vdg

    (b).

    Vsd

    Vsg

    Vgd

    Drain

    Gate

    Source

    Source

    Gate

    Drain

    Vgs

    Vds

    Vdg

    Vsd

    Vsg

    Vgd

    Drain

    Gate

    Source

    Source

    Gate

    DrainI=

    (V

    V

    )

    d

    n

    gs

    hn

    2

    I=

    (V

    V

    )

    d

    p

    sg

    hp

    2

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    3 2o

    oT

    (T) (T ) ,T

    (5-6)

    where(T)designates electron mobilitynoin NMOS or hole mobilitypoin PMOS at any arbi-trary absolute temperature, T. On the other hand To is the reference temperature at which thereference mobility value, (To), is extracted. Since parametersnand pin (5-5), to which the

    drain currents in (5-4) are proportional, are linear functions of carrier mobility, the immediateeffect of increased operating temperature is clearly a diminished drain current.

    In addition to a temperature-induced degradation of mobility, the threshold voltage of aMOS technology transistor increases with temperature. This threshold potential increase further

    diminishes the drain current observed for a given gate-source voltage at increasing operating

    temperatures. The positive temperature coefficient of threshold voltage derives from its intimatedependence on the Fermi potential, which effectively defines the oxide-semiconductor interface

    potential corresponding to the onset of channel inversion in a MOSFET. To first order,

    h o ho oh h o F

    F o

    V (T ) V T T V (T) V (T ) 2 V ,

    2V T

    (5-7)

    where Vh(T)is the threshold voltage value of either NMOS or PMOS at absolute temperature T,

    and the Fermi potential, VF, is given by

    subF T

    i

    NV V .

    nln

    (5-8)

    In the last expression, Nsub denotes the impurity concentration in the substrate (acceptor

    concentration for NMOS and donor concentration for PMOS), ni is the intrinsic carrierconcentration of silicon, and VT is the familiar Boltzmann voltage. But VF itself varies with

    temperature owing to two well-known facts. In particular, VTis linearly dependent on absolute

    temperature and ninominally increases by as much as two to four fold for each 10 Cincrease inoperating temperature. When due consideration is given to mobility and threshold effects, the

    sensitivity of the drain current to absolute temperature is found to be

    d

    0.25I d d FT

    od

    I I 4V3 TS .

    T T 2 T I

    (5-9)

    In (5-9),=nfor NMOS,=pfor PMOS, and it is understood that VF,Id, andin the brack-eted factor on the right hand side are each evaluated at the reference temperature, To. The first

    term in the bracketed quantity derives from the temperature dependence of carrier mobility,while the second term within the bracketed quantity reflects threshold voltage sensitivity to

    temperature. Accordingly, the per-unit, or percentage, change in drain current induced by a

    specified percentage change in operating temperature is negative and larger in magnitude than1.50. We note, however, that for progressively larger drain currents, the temperature sensitivityof drain current tends toward a constant of (1.50).

    EXAMPLE #5.1:

    In an attempt to dramatize the foregoing temperature issues, consider anNMOS MOSFET having a substrate impurity concentration ofNsub= 10

    15

    atoms/cm3. At a reference temperature of To= 27 C = 300.16 K, the

    MOSFET, which is biased for a drain current of Id= 1 mA, deliversn=

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    50 mmhos/volt, and a threshold voltage of Vhn= 400 mV. Assume a refer-

    ence temperature intrinsic carrier concentration of 1010

    atoms/cm3. Deter-

    mine the requisite gate-source voltage, Vgs, such that the room tempera-

    ture, 1 mA value of drain current is sustained at an elevated operating

    temperature of 75 C.

    SOLUTION #5.1:

    (1). From (5-4), the gate-source voltage commensurate with 1 mAof drain current at 27 C is,

    withn= 50 mmhos/voltand Vhn= 400 mV, Vgs= 541.4 mV. Also, at To= 27 C = 300.16K, the Boltzmann voltage, VT, is

    oT

    kTV 25.88 mV ,

    q (E1-1)

    where k = 1.38(1023) joules/Kis Boltzmanns constant, and q = 1.6(1019) coulombsis the

    magnitude of electron charge. ForNsub= 1015atoms/cm3and ni= 10

    10atoms/cm3at 27 C,

    the Fermi potential in (5-8) is VF= 297.9 mV at the reference temperature.

    (2). Using (5-7), the threshold voltage increases to Vhn= 495.3 mV at T = 75 C = 348.16 K,

    which is an increase of almost 24%. Appealing to (5-6), the ratio of the carrier mobility at348 Kto the carrier mobility at 300 Kis

    3 2 3 2o

    o

    T(T) 3001 1.249 .

    (T ) T 348

    (E1-2)

    Since parameter n is directly proportional to carrier mobility, n decreases by a factor of1.249to a 75 Cvalue ofn= 40.02mmhos/volt.

    (3). If a biasing circuit were to be implemented to deliver constant gate-source voltage to the

    transistor of present interest, n= 40.02 mmhos/volt, Vhn= 495.3 mV, and Vgs= 541.4 mV(the gate-source voltage value computed at 27 C), the drain current in (5-4) becomes Id=

    85.03A. This revised current level is a decrease from the original drain current value by awhopping factor of almost 12! On the other hand, sustaining a 1 mAdrain current in the face

    of the foregoing temperature-induced perturbations in parameter nand threshold voltage Vhnrequires an updated gate-source voltage of Vgs= 653.4 volts. In other words, the gate-source

    voltage must increase by 20.7%over the 48 Cincrease in operating temperature.

    ENGINEERING COMMENTARY:

    This example teaches that the temperature-induced effects on the drain current conducted by

    a MOSFET biased in saturation can be substantial. In the present case, the factor of 12de-

    crease in quiescent drain current is certainly large enough to motivate significant concern as

    to the ability of the circuit in which the considered MOSFET is embedded to sustain perfor-

    mance specifications over the stipulated 48 Crise in operating temperature. The design les-

    son learned is that if the desired signal performance of a circuit is critically dependent on

    quiescent current level, constant gate-source voltage is not a prudent bias design strategy.

    In the present case, the gate-source voltage that sets the drain current on the subject transistormust increase by 20.7%over the 48 Crise in temperature. While this requirement may ap-

    pear foreboding, it reflects realistic biasing compensation. To place this contention into

    engineering perspective, the requisite increase in gate-source voltage, say Vgs, is Vgs =

    Vgs(75 C) Vgs(27 C) = 112.0 mV, which amounts to an average temperature rate of vol-tage increase of 2.33 mV/C. Thus, the incorporated biasing compensation must sense

    temperature (perhaps by sensing current). In response to this sensing, it must then increase

    the gate-source bias by about 2.33 mVfor every degree centigrade increase in temperature.

    This mandated average increase is indeed a reasonable design goal for properly designed

    biasing compensation. As a general rule, the majority of MOSFETs achieve nominally

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    temperature invariant drain current when the applied gate-source voltage is made to increase

    at a rate in the range of 1.5 mV/C to 2.5 mV/C. Interestingly enough, the +2.33 mV/C

    requirement computed in this example differs only slightly from the average temperature rate

    at which the base-emitter biasing voltage applied to a BJT must decrease to preserve constant

    static collector current.

    5.2.2. IMPROVED STATIC MODELSWe should remain mindful of the fact that the static volt-ampere characteristics given

    by (5-4), which we shall invoke habitually in our first order, design-oriented circuit analyses, are

    only first order approximations of the static characteristics we actually observe and monitor inthe laboratory. Unfortunately, the deviations between first order theoretic predilections and

    engineering observations are aggravated as devices are scaled to deep submicron dimensions.

    The primary shortfalls implicit to (5-4), insofar as static circuit responses of minimal geometrytransistors are concerned, are the neglect of channel length modulation (CLM), bulk-induced

    threshold modulation (body effect or BITM), carrier mobility degradation induced by lateral

    electric fields, and, to a somewhat lesser extent, drain induced barrier lowering (DIBL). The cir-cuit level influence of these and other high order MOSFET phenomena are best studied via

    computer-aided investigations that exploit device models more advanced than are those premisedon long channel simplifications. But it is important that we perform these computer-based stu-dies only after we execute an insightfully understood manual analysis with our relatively simple,

    first order transistor models so that we can understand and appreciate the quantitative impact of

    high order phenomenology. Such understanding and appreciation are vital prerequisites for

    enabling our creative abilities that implement circuit compensation or outright circuit architec-tural changes. In effect, the fundamental goal of such circuit enhancements and alterations is to

    render high order, and generally poorly controlled, phenomenology inconsequential to the task of

    meeting our design targets.

    Although we have pondered the aforementioned modeling shortfalls in the precedingchapter, it is prudent to itemize their respective circuit level effects before undertaking our de-

    sign-oriented investigation of MOSFET biasing networks.

    5.2.2.1. Channel Length Modulation

    Three fundamental effects of CLM are observed in short channel MOS technologytransistors. The first of these is a slight positive slope to the saturated volt-ampere characteris-

    tics, which is rendered transparent by Figure (4.17). This slope is inversely proportional to the

    channel length modulation voltage, V, and thus, it is functionally related to the drawn channel

    length, L. It manifests a drain current that is slightly larger than the drain current predicted bythe square law model in (5-4). The additional drain current is a nominally linear function of the

    excess drain-source voltage, (VdsVdsat)1; in particular for NMOS,

    2 ds dsat d n gs hnV V

    I V V 1 .V

    (5-10)

    1The focus here is on NMOS transistors. But similar statements apply to PMOS transistors, where we could

    minimize the impact of channel length modulation by setting the source-drain biasing voltage, Vsd, to a value that isclose to the source-drain saturation voltage. While we shall generally address modeling issues in the context of

    NMOS transistors, we shall understand that, subject to minor notational differences, our assertions apply equally

    well to PMOS transistors.

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    We understand by (5-10) that biasing an NMOS transistor at a drain-source voltage

    that is only slightly larger than its drain-saturation voltage minimizes the circuit-level impact ofCLM. Of course, setting the drain-source voltage close to the drain saturation voltage limits the

    amount of signal swing that can be tolerated at the drain port while maintaining a specified

    linearity target. Alternatively, CLM is inconsequential in transistors featuring long channellengths. To be sure, long channel lengths generally require correspondingly large gate widths,

    which combine with these long channel lengths to produce increased device capacitances andtherefore, potentially reduced circuit bandwidths. But in biasing circuits, which operate in the

    steady state at zero frequency, bandwidth is not an important metric. Indeed constrained band-widths in biasing structures often prove advantageous from the viewpoint of avoiding exces-

    sively underdamped biasing responses to a bus line voltage that is applied suddenly.

    The second effect of CLM is that the large signal model evidenced at the drain-source

    port of a MOSFET is no longer an ideal current source controlled nonlinearly by applied gate-source voltage. Instead, the output port now appends a shunting resistive branch across the sub-

    ject voltage controlled current source. Unfortunately, the appended resistance is nonlinearly re-

    lated to both drain-source and gate-source voltages, which generally motivates our defaulting tocomputer-aided analysis whenever CLM looms significant. However, the appended resistance is

    large in devices that have large channel lengths and/or operate at low saturation currents.

    Finally, CLM alters the small signal performance of a MOSFET by imposing a channel

    resistance (ro)across the drain-source port of a MOS technology transistor. As is confirmed inthe preceding chapter, this resistance shunts the drain-source signal current source, which is con-

    trolled by applied gate-source signal voltage. The resistance shunting impinges on small signal

    MOSFET performance in two ways. First, it reduces the achievable I/O gain because the ap-pended resistance places an additional load between drain and source terminals in an amplifier.

    Second, it establishes a finite resistance at the drain output port, as opposed to the infinitely large

    driving point output resistance manifested at the drain port by the long channel approximation.Thus, while the Schichman-Hodges model affords a common source amplifier that behaves as an

    ideal transconductor, in the senses of infinitely large input and output impedances at low signalfrequencies, CLM brings such a transconductor into non-ideal state of engineering reality.

    5.2.2.2. Bulk-Induced Threshold Modulation

    Bulk-induced threshold modulation (BITM) incurs both large signal and small signaleffects. From the large signal perspective, the body effect increases the threshold voltage of a

    MOSFET as a nonlinear function of the reverse bias imposed across the bulk-source PN junc-

    tion. In extreme situations, this means that if the subject reverse bias includes a signal compo-nent, it is possible that sufficiently large signals can incur intermittent or aperiodic cutoff of the

    transistor. Such an extreme can materialize, for example, if the gate aspect ratio is so large that a

    desired drain current can be sustained when the gate-source voltage is ever so slightly above the

    threshold potential. At a minimum, threshold voltage perturbations induced by large signalswings can exacerbate nonlinearity problems, despite the care ostensibly taken to pin the quies-

    cent operating point of the transistor in a reasonably linear region of its characteristics curves.

    We remember that BITM is minimal for thin gate oxide layers.

    From a small signal perspective, Figure (4.22), with the help of (4-172) and (4-173),confirms that the body effect establishes a controlled current source in shunt with the drain-

    source terminals of a MOSFET. Depending on the nature of the bulk-source signal voltage, thisadditional controlled source changes the I/O gain of an amplifier. And if the bulk-source signal

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    voltage is nonzero, it can alter appreciably the driving point output impedance seen looking into

    the transistor drain. We note again from (4-173) that a thin gate oxide reduces the nettransconductance associated with the additional voltage controlled current source in the drain cir-

    cuit. But an even more important observation is that if this additional controlled source is

    significant to the enumeration of gain and/or output impedance, there is cause for designconcern. In particular, a significant effect on the small signal characteristics implies that body

    effect has a similarly significant influence on static MOSFET responses, which bodes poorlyfrom an I/O linearity perspective.

    5.2.2.3. Carrier Mobility Degradation

    The immediate impact of carrier mobility degradation induced by the lateral electricfields caused by drain-source voltages is a reduction of the drain saturation voltage. This effect

    is highlighted and analytically addressed by (4-130) through (4-133). These relationships show

    that the reduction in drain saturation current is minimal for long channel lengths. A reduceddrain saturation voltage is actually good news in that it enables us to bias the transistor at

    progressively smaller drain-source voltages while sustaining saturation regime operation. But

    carrier mobility degradation reduces the drain current, which is to say that progressively largergate-source biases are required to offset this current reduction. Obviously, increased gate-sourcevoltage causes an increase in drain saturation voltage.

    5.3.0. CURRENT SINKS AND SOURCES

    Current sinks and sources are ubiquitous in analog networks. One reason thatunderpins the popularity of these subcircuits is that the forward transconductance, drain-source

    channel resistance, and several other low and high frequency parameters in the small signal

    transistor model are dependent on quiescent transistor currents. In an attempt to minimize

    network nonlinearities, it is incumbent on us to keep quiescent variables as constant as possible,

    which is to say that it is desirable to derive critical static currents from nominally ideal sources orsinks of constant current. Additionally, and as we witnessed in the preceding chapter, a constanttail current in a balanced differential amplifier not only keeps pertinent small signal transistor

    parameters constant, but its value also sets the allowable input signal amplitude that affords

    acceptable linearity.

    5.3.1. SIMPLE CURRENT MIRROR

    We commence our present discussion by studying the current mirrors offered in Figure

    (5.3). We shall analyze only the NMOS mirror in Figure (5.3a). The analysis of the PMOS mir-ror in Figure (5.3b) proceeds along the same lines as that of its NMOS counterpart and is left as

    an exercise for the reader.

    In both of the two circuit diagrams before us, input currentIrefis often realized as an off

    chip current source. In light of the design flexibilities afforded by discrete, off the shelf compo-nents, we can view this branch element as an ideal, constant current source having infinitely

    large terminal impedance. While voltage Vddis presumably larger than node voltage Vkk, we as-

    sume Vkkis large enough to ensure that transistor M2 operates in its saturation domain. In thecase of transistor M1, saturation is assured because of the indicated electrical connection of its

    gate and drain terminals. From a cataloguing perspective, we usually think of the NMOS mirror

    as a current sink in that the drain current, Ik, flows into ground from a general branch element

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    that is not delineated in the figure. On the other hand, the PMOS mirror is viewed as a current

    source since drain currentIkflows into a general branch element, which is also not delineate dinthe subject figure.

    Figure (5.3). (a).Schematic diagram of an NMOS current mirror. (b).The PMOS counter-

    part to the NMOS current mirror. In both diagrams, the gate aspect ratio of

    transistorM2is larger than that of transistorM1by a factor of k21.

    In Figure (5.3a), the drain-source voltage, Vds, of transistor M1is identical to its gate-source bias, which we indicate as Vref. This means that the drain saturation voltage of this

    transistor, Vdsat1, is Vdsat1= (VrefVhn) = (Vds1Vhn). Note that as we inferred in the precedingparagraph, this transistor operates in saturation in that the inequality, Vds1> Vdsat1= (Vgs1Vhn)= (Vds1Vhn), is clearly satisfied. Because the gate of a MOSFET conducts no quiescent cur-rent,Irefis identical to the drain current,Id1ofM1. Accordingly, (5-10) yields

    2

    hnd1 ref n1 ref hn

    VI I V V 1 ,

    V

    (5-11)

    where we have not bothered to differentiate between the two transistor threshold voltages and thetwo channel length modulation voltages. We have adopted this tack because the two NMOS de-

    vices are monolithic transistors that are physically identical. We include identical channellengths in this physical restriction, but we do allow geometrical differences between their respec-

    tive gate widths and thus, their corresponding gate aspect ratios. In case before us, the gate as-pect ratio of transistor M2 is k21-times the gate aspect ratio of M1. Moreover, both transistors

    return their source and bulk terminals to ground, thereby negating BITM. Thus, the two transis-

    tors function with the same threshold voltages. Since drain induced barrier lowering (DIBL) af-fects the threshold voltage, the latter statement presumes negligible or identical DIBL in both

    transistors.

    We note now that the circuit architecture forces the gate-source voltage, Vgs2, of transis-torM2to be identical to Vgs1, which is, of course, the previously introduced voltage, Vref. Thus,

    2 kk ref hnd2 k n2 ref hn V V VI I V V 1 ,V

    (5-12)

    But from (5-5),

    n221

    n1

    k .

    (5-13)

    It follows from (5-11) and (5-12) that

    M1

    M2

    x k21

    Vdd

    Vdd

    Iref

    Vkk

    Vref

    Vref

    Ik

    Id1

    Id1

    M1

    M2

    x k21

    Iref

    Vkk

    Ik

    (a). (b).

    Rout

    Rout

    x 1

    x 1

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    kk ref hn

    k 21 ref hn

    V V V1

    VI k I .

    V1

    V

    (5-14)

    In earlier chapters, we repeatedly asserted that the fundamental purpose of circuit

    analysis is not necessarily to arrive at an accurate response result. Instead, we advanced the

    pedagogy that the fundamental purpose of circuit analysis is to arrive at tractable results that pro-vide insights as to how the considered circuit might be designed to deliver consistently reliable

    and reproducible high quality responses. To these ends, the work we executed to generate (5-14)

    comprises an excellent example of the engineering assessment task that will consistently con-front us as we consider subsequent, and inevitably more complex, networks.

    To the foregoing end, (5-14) is hardly a precise result for output current Ik, since we

    have invoked a simple square law model for MOSFET volt-ampere characteristics, embellished

    only for a first order account of channel length modulation. We do notice, however, that for

    large V, which is achieved for long drawn channel lengths, currentIkcollapses approximately tok21Iref. This means that since k21is a reliably deterministic ratio of device gate aspect ratios, Ik

    mirrors constant currentIrefwithin a predictable scale factor of k21. In a word, as long as the offchip reference current, Iref, remains constant, output current Ik stays constant, independent of

    power line voltage Vdd, transistor threshold voltage, and all other transistor parameters and

    operating temperature. In turn, the numerical value of currentIkis set by a reliable and predicta-

    ble ratio of gate aspect ratios.

    Unfortunately, there are potential issues concerning scale factor k21, which derives di-

    rectly from (5-13). In particular, the transconductance coefficient,n, is directly proportional tocarrier mobility. As we witnessed in the preceding chapter, the mobility of carriers in the in-

    verted channel of an NMOS transistor is determined by the intensity of the drain to source elec-tric field, which in turn is a monotonically increasing function of the applied drain-source vol-

    tage. In Figure (5.3a), the drain-source (as well as gate-source) voltage applied to transistorM1is the voltage, Vref, while forM2, the drain-source bias is an invariably larger voltage, Vkk. If in-

    deed Vkk> Vref, the electric field intensity in the drain-source channel ofM2exceeds the electric

    field intensity in which the inverted channel of transistor M1 is immersed. This means that thecarrier mobilities inM1andM2are not identical, thereby rendering (5-13) an approximation. A

    reasonable rectification of this dilemma does not necessarily require that Vkkbe identical to vol-

    tage Vref,for carrier mobility is not overtly sensitive to voltage. But it is only sensible for us toattempt to ensure that voltage Vkkis not excessively larger than Vref. In addition to reducing the

    disparity between carrier mobilities in the two NMOS transistors, a secondary benefit of securing

    Vkkin the neighborhood of Vrefis that the parenthesized quantity on the right hand side of (5-14)collapses nearly to one. In short, channel length modulation phenomena are rendered virtually

    inconsequential.

    Another valuable metric for assessing the quality of a current source or current sink is

    the output resistance,Rout, which it presents to its output port. This output resistance is founda-tional to an assessment of the power supply rejection of a current sink. It tells us the amount, say

    Ik, by which the presumably constant current,Ik, changes when applied voltage Vkkis perturbed

    by the amount, Vkk. The voltage fluctuation may be the result of signal spurs, electrical noise,poor regulation, or other offending conditions that contaminate the line supporting voltage Vkk.

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    Moreover, if Vkk and Ik are small, which we expect them to be in a well-designed biasingenvironment, we can stipulate the linear constraint,

    kkk

    out

    VI .

    R

    (5-15)

    Equation (5-15) boasts two important engineering ramifications. The first of these is that if out-

    put resistance Routis known, the perturbation, Ikin current caused by a given change (parasiticor otherwise), Vkk, in voltage can be straightforwardly enumerated. The second ramification is

    that if Vkkand Ikare small, output resistanceRoutderives from a simple, low frequency, small

    signal analysis that culminates in the computation of the voltage to current ratio, Vkk/Ik. Be-

    cause of our presumed linearity between Vkkand Ik, we note that this ratio does not rely on an

    explicit awareness of either Vkkor Ik. Clearly,Rout= is the ideal circumstance in that it en-sures Ik= 0for all Vkk. We therefore deem it productive to embark on the task of determiningoutput resistanceRoutfor the NMOS sink in Figure (5.3a).

    We can conduct a circuit analysis that leads to an expression for the desired output

    resistance,Rout, simply by straightforwardly examining the entire network in Figure (5.3a) with

    each transistor supplanted by its small signal model. Although there is nothing philosophicallywrong with this solution tack, we shall adopt a slightly more creative analytical strategy. In

    particular, we must begin to prepare ourselves for complicated analytical projects. In these ad-

    vanced projects, replacing each active device by an equivalent circuit is likely to provoke inordi-nately cumbersome, tedious, and even annoying mathematics that accomplish little more than to

    mask the design insights we are attempting to glean.

    Figure (5.4). (a).Subcircuit comprised of diode-connected transistor M1that drives the gate of transistorM2in Figure (5.3a). (b).Low frequency, small signal model of the subcircuit in (a). (c).Cir-

    cuit used to evaluate the Thvenin output resistance, Vy/Iy= rd, of the subcircuit in (a). (d).

    The Thvenin equivalent source circuit seen by the gate of transistorM2in Figure (5.3a).

    In order to initiate our design-oriented analysis, let us replace the diode-connected

    subcircuit to the left of theM2gate in Figure (5.3a) by its Thvenin equivalent circuit. Such a

    M1

    Vdd

    Iref 0

    Vref

    Id1

    (a).

    To GateOf M2

    (b).

    ro1g Vm1 1 b1 m1 2g V

    V1 V2

    To GateOf M2

    To GateOf M2

    (c).

    ro1g Vm1 1

    V1

    Vy

    Iy

    (d).

    ro11/gm1rd

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    replacement demands that the subject subcircuit be electrically represented by a small signal, and

    therefore linear, equivalent circuit since Thvenin displayed neither interest in, nor compassionfor, nonlinear circuits. Figure (5.4a) displays the subcircuit partitioned from the remaining

    components of the current mirror we are investigating. In Figure (5.4b), we exploit the low fre-

    quency, small signal transistor model we produced as Figure (4.22a) to delineate the pertinentequivalent circuit of the reference subcircuit in Figure (5.4a). In this model, we have replaced

    the power line voltage, Vdd, by a short circuit since the small signal voltage value of a source ofconstant voltage is a null voltage. As it turns out, the present replacement of Vddby a short cir-

    cuit carries no engineering significance since the small signal model of the constant currentsource,Iref, to which Vddis applied as a series element, is an open circuit. To this end, we depict

    current sourceIrefby its replacement small signal source. Given that currentIrefis a constant, its

    small signal current has zero value, which of course reflects an open circuit. If we had accountedfor a finite terminal resistance associated with Iref, the small signal model of the subject source

    would have been its presumably large two-terminal shunting resistance, as opposed to the im-

    plied open circuit.

    The short circuiting of voltage source Vddand the open circuiting of current sourceIref,precludes any signal source from being applied to the biasing subcircuit. This situation imme-

    diately leads us to conclude that the Thvenin signal voltage activating the gate of transistor M2

    is zero. If, however, we had observed a small fluctuation inIrefand/or a small fluctuation in Vddunder the condition of a finite current source resistance, the subcircuit at hand would have re-

    sponded by delivering a presumably small, but nonzero, Thvenin voltage at its open circuited

    output port.

    With zero Thvenin voltage observed at the output port of the M1biasing subcircuit,the Thvenin equivalent of this subcircuit collapses to a simple Thvenin resistance. We can

    determine this resistance with the help of the model shown in Figure (5.4c). The latter model

    derives directly from the network in Figure (5.4b), where we have dispensed with the short cir-cuit replacement of line voltage Vddbecause of the open circuit replacement of reference current

    Iref. Additionally, we observe that since the bulk and source terminals of transistor M1 aregrounded, no bulk-source signal voltage, shown as voltage V2 in Figure (5.4b), is established.

    Thus, the bulk transconductance current, b1gm1V2, which quantifies the dependence of signaldrain current on signal bulk-source voltage, vanishes. We can then determine the Thvenin out-

    put resistance, say rd, in a conceptual manner that mirrors how an ohmmeter determines theresistance between any two terminals of a linear network. In particular, an ohmmeter squirts a

    small amount of current, say Iy in the present case, into the port of interest (the model output

    port). In response to this applied current, the ohmmeter measures the voltage Vy, which is thevoltage across, and in disassociated polarity with, the injected small current,Iy

    2. The ohmmeter

    then displays voltage Vynormalized to currentIyon the ohmmeter display; that is, it effectively

    measures the resistance of interest by displaying the voltage to current ratio, Vy/Iy. We show the

    mathematical form of this ohmmeter in the small signal model of Figure (5.4c).In the aforementioned diagram, the ohmmeter voltage, Vy, happens to be identical to the

    gate-source signal voltage, V1, which controls the current source, gm1V1. In other words, current

    gmV1 is the same as gm1Vy. But voltage Vy appears directly across, and in associated polaritywith, the controlled source,gm1Vy. We therefore argue that the branch conducting currentgm1Vy

    2A branch voltage is said to be in disassociated polarity with its branch current if said branch current flows toward

    the plus end of the branch voltage. On the other hand, a branch voltage is in associated polarity with its branch

    current if the branch current is directed toward the minus end of the voltage.

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    is equivalent to a branch resistance, Vy/gm1Vy= 1/gm1, as we depict in our final form subcircuit

    model of Figure (5.4d). Without even writing an equilibrium Kirchhoff equation, we can thenconclude that the Thvenin resistance, rd, presented to the gate of transistorM2by theM1subcir-

    cuit is

    o1

    d o1 m1 m1 o1 m1

    r1 1r r ,

    g 1 g r g

    (5-16)

    where the indicated approximation reflects the strong prospects thatgm1ro1>> 1. For large gate

    aspect ratio and/or a relatively large reference current, Iref, gm1 is reasonably large (tens ofmillimhos). In turn, the resistance seen at the output port of the diode-connected network is, as isthe resistance of a conventional PN junction diode, relatively small (high tens to a few hundreds

    of ohms in the case of a diode-connected MOSFET).

    The discovery that the small signal model of the diode-connected transistor, M1, is a

    simple resistance is hardly revolutionary. In particular, transistorM1functions effectively as atwo terminal branch element since its gate and drain terminals are connected together, as are its

    bulk and source terminals. Accordingly, when we replace the subject transistor by its low fre-

    quency (and therefore memoryless), small signal equivalent circuit, we clearly end up with a li-near, two terminal network that has no implicit energy storage elements. But a linear, two ter-minal, memoryless, network is, by definition, a two terminal linear resistance in that its terminal

    voltage is necessarily linearly related to its terminal current in a fashion that is prescribed by the

    adopted linear model.

    Figure (5.5) is the small signal schematic diagram of the entire NMOS current mirror inFigure (5.3a), wherein the gate circuit of transistorM2is supplanted by our Thvenin equivalent

    representation of this M1 subcircuit. Of course, we have determined that this Thvenin

    representation consists only of a simple two-terminal resistance, rd, as stipulated by (5-16).Moreover, our mathematical ohmmeter, comprised now of the independent current source, Ix,

    and its companion terminal voltage Vx, is appended to the output port of the mirror. Since there

    is no Thvenin voltage driving the gate of transistor M2, the gate-source signal voltage, Va, ap-plied toM2 is zero. This zero signal voltage rendersgm2Va= 0

    3, whence, and again by inspec-

    tion, we see that output resistanceRoutis

    Figure (5.5). Low frequency, small signal model used to compute the output resistance,Rout, of the NMOS

    current mirror. In terms of mathematical ohmmeter variables, this resistance isRout= Vx/Ix.

    3A controlled current or a controlled voltage source must not be set to zero indiscriminately when evaluating a

    circuit resisitance. As in the present case, such a controlled source may assume a null value, but only if network

    conditions compel the source current (or voltage) to vanish.

    ro2

    rd

    g Vm2 a

    Va

    Vx

    Ix

    Rout

    M1

    M2

    x k21

    Vdd

    Iref

    Vkk

    Vref

    Ik

    Id1

    Rout

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    xout o2

    x

    VR r .

    I (5-17)

    As noted earlier, we should like to have Rout large. Since Routin this case is merely the drain-

    source channel resistance of transistorM2, largeRoutrequires thatM2have a long channel length

    and/orM2should conduct a relatively small quiescent drain current.

    We note, perhaps with some chagrin, that the effort we expended to determine theThvenin network driving the M2gate turned out to be inconsequential in that Rout is indepen-

    dent of the electrical properties observed at the gate of transistor M2. Resistance Rout is

    understandably independent of gate parameters, because the gate of a MOSFET conducts nostatic current. Moreover, no excitation prevailed at theM2gate site. However, our efforts have

    not been expended in vain, for we shall commonly encounter diode-connected transistors to

    which we can directly apply the fruits of the aforementioned analysis.

    EXAMPLE #5.2:

    In the NMOS current mirror of Figure (5.3a), spurious signals perturb the

    voltages, Vdd and Vkk, in the respective amounts of Vdd and Vkk. Thereference current source, Iref, which can be presumed constant, has a ter-minal resistance of Rr. Determine the approximate resultant change, say

    Ik in the quiescent current, Ik, established by the mirror. Explain allapproximations, and offer suggestions as to how the spurious signal-in-

    duced output current fluctuation can be minimized in view of the stipu-

    lated voltage changes.

    SOLUTION #5.2:

    Figure (5.6). (a).Low frequency, small signal model of the M1subcircuit for the NMOS current mirror of

    Figure (5.3a). The model is used in Example #5.2. (b).Low frequency, small signal model of

    the NMOS current mirror of Figure (5.3a). This model is also used in Example #5.2.

    (1). We begin by determining the Thvenin equivalent circuit driving the gate of transistorM2.

    Unlike the discussion of the preceding section, this Thvenin representation embraces a

    Thvenin voltage owing to the non-ideal nature of current source Iref and the stipulated

    change, Vdd, in power line voltage. To this end, Figure (5.6a) depicts the small signal model

    of the M1 subcircuit. Rather than representing transistorM1by its small signal model, we

    rely on our recent experience, which affirms that a diode-connected transistor (M1)can be re-

    placed by a two-terminal resistance of value rd, as defined in (5-16). ResistanceRraccounts

    for the finite terminal resistance associated with current source Iref, while the perturbation,

    ro2g Vm2 a

    Va

    Rr

    rd

    Vt1

    Rt1

    Rt1

    Vdd k Vd1 dd

    Vkk

    Ik

    (a). (b).

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    Vdd, in voltage Vddcan be viewed as a small signal voltage source. Recall that in the preced-

    ing section, Vdd is effectively expunged because Vdd is taken as an ideal, constant voltage

    source. Moreover,Rrin the previous section of material is infinitely large owing to the pre-

    sumed ideal nature of current source Iref. The subject model produces a Thvenin voltage,

    Vt1, at the output port of theM1subcircuit of

    d

    t1 dd d1 dd d r

    rV V k V ,

    r R

    (E2-1)

    where kd1, the voltage divider in (E2-1), is

    d dd1

    d r r m1 r

    r r 1k .

    r R R g R

    (E2-2)

    The indicated approximation exploits our awareness that the resistance, rd, of a diode-con-

    nected MOSFET is small and approximately equal to 1/gm1, while we expect a reasonably

    well designed current source to exude a large current source terminal resistance,Rr.

    The Thvenin scenario is finalized by determining the Thvenin output resistance at the drain

    port of transistorM1. The simplicity of the network before us obviates the need to exploit

    our mathematical ohmmeter here. In particular, we always set to zero all independent energy

    sources in the process of evaluating a network resistance. In this case, there is only one such

    independent source; namely, Vdd. With Vddclamped to zero, inspection alone dictates a

    Thvenin resistance,Rt1, of

    o1t1 d r r r

    m1 o1 m1 m1

    r 1 1R r R R R ,

    1 g r g g

    (E2-3)

    where the approximations reflect large Rr and gm1ro1 >> 1. It follows that this Thvenin

    resistance is essentially determined by the terminal resistance associated with the diode-con-

    nected first transistor.

    (2). Figure (5.6b) offers the small signal model of the entire NMOS mirror. In this model, we

    have exploited the facts that the bulk-source signal voltage forM2is zero, the gate of transis-

    torM2is driven by the Thvenin model deduced in the preceding part of this solution, and

    the spurious change, Vkk, behaves as a small signal voltage source applied with respect toground at the drain terminal of transistor M2. Since the considered network is linear,

    superposition theory can be invoked to determine the net change, Ik, in current, Ik. In

    particular, with Vkk= 0, we see that the control voltage, Va, is Va= kd1Vdd; hence Ik=

    gm2Va= gm2kd1Vdd. On the other hand, Vdd= 0constrains voltage Vato zero. Resultantly,

    Ik= Vkk/ro2. It follows that

    kkk m2 d1 dd

    o2

    VI g k V .

    r (E2-4)

    Recalling (E2-2), we can write

    m2m2 d1

    m1 r

    gg k .

    g R (E2-5)

    But, transistorM2has a gate aspect ratio that exceeds the gate aspect ratio of transistorM1bya factor of k21. Additionally, the drain current flowing inM2is a factor of k21larger than the

    drain current ofM1. Since the forward transconductance of a saturated MOSFET is propor-

    tional to the square root of the product of gate aspect ratio and quiescent drain current,

    m2 21m2 d1

    m1 r r

    g kg k .

    g R R (E2-6)

    We conclude that the perturbation in drain currentIkis given by

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    kk 21 dd kk k m2 d1 dd

    o2 r o2

    V k V VI g k V .

    r R r (E2-7)

    ENGINEERING COMMENTARY:

    The result in (E2-7) tends to mirror expectations. In particular, the closerIrefis to an ideal

    current source and the closer transistor M2emulates an ideal controlled current source at its

    drain port, the less sensitive currentIkis to perturbations in the voltages, Vddand Vkk. Idealitywith respect to Irefmeans resistance Rr is infinity, in which case, the first term on the right

    hand side of (E2-7) vanishes. If the drain port ofM2emulates an ideal (controlled) currentsource, ro2 is infinitely large, and the second term on the right hand side of (E2-7) goes to

    zero. We also note that too large of a current mirroring factor, k21, aggravates the sensitivity

    of current Ik with respect to the power bus voltage, Vdd. The latter situation also reflects

    engineering expectation for if Vddfluctuates,Irefis perturbed (assuming Irefis a practical cur-

    rent source). OnceIreffluctuates,Iknecessarily changes for the current gain,Ik/Iref, is directlyproportional to k21. Indeed, Ik/Iref k21 if channel length modulation in transistor M2 isminimal.

    5.3.2. CURRENT MIRROR WITH SOURCE DEGENERATION[1]

    The current mirrors in Figure (5.3) offer limited design flexibility with respect to theoutput resistance,Rout. Recall from (5-15) that this output resistance establishes the sensitivity of

    output current,Ik, with respect to small perturbations in the applied voltage, Vkk. In particular, a

    targeted small sensitivity to applied voltage mandates a large output resistance. If we appeal to(5-17), we see that Routin Figure (5.3a) is determined exclusively by the channel resistance, ro2,

    implicit to NMOS transistor M2. Thus, the only direct means afforded us to adjust, or to tune,

    Routis to change currentIk(smallerIkfor largerRout). Unfortunately, this design degree of free-dom may not be available, for current mirrors are often implemented to establish a required cur-

    rent, Ik, which is presumably optimal, or at least preferred, for a particular application. Yet

    another problem arises when the application to which the design effort is focused requires that

    deep submicron transistors be utilized in the mirror. We recall that very small drawn channellengths beget proportionately small channel length modulation voltages, which in turn result in

    small drain-source channel resistances at given quiescent drain currents. We therefore expect

    that low bias current sensitivity to applied voltage is a challenge for deep submicron technolo-gies.

    Figure (5.7). Schematic diagram of a source-degenerated NMOS

    current mirror. An analogous source-degenerated

    PMOS mirror can also be forged.

    2

    x k21

    M1

    Rss R /kss 21

    Vdd

    Iref

    Vkk

    Ik

    Rout

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    A viable mitigation of the foregoing dilemma is offered by the so-called source-degene-

    rated NMOS current mirror offered in Figure (5.7). The schematic diagram is similar to that ofthe simple NMOS mirror in Figure (5.3a), save for the insertion of resistances,RssandRss/k21, in

    the transistor source terminals. These resistances are called source degeneration elements for, as

    we shall witness when we address MOSFET amplifiers, they reduce, or degenerate, the for-ward transconductances, and thus the overall I/O gain, of their respective transistors. We are

    also about to see that if the source degeneration resistances are selected in accordance with theelemental stipulations in the subject circuit schematic diagram, k21must necessarily equate to the

    ratio of the gate aspect ratio of transistor M2to the transistorM1gate aspect ratio. IfIk= k21Iref,the gate-source voltage, Vgs2, of transistorM2is forced to replicate the gate-source voltage, Vgs1,

    ofM1. This declaration follows from the Kirchhoff equilibrium relationship,

    ssgs1 ref ss gs2 k

    21

    RV I R V I ,

    k

    (5-18)

    whence, withIk= k21Iref,

    k

    gs1 gs2 ref ss 21 ref

    IV V I R 1 0 .

    k I

    (5-19)

    Of course, the Schichman-Hodges model affirms that if Vgs1= Vgs2producesIk= k21Iref, parame-

    ter k21is the ratio of the gate aspect ratio of transistorM2to the gate aspect ratio ofM1.

    There is another important ramification to the source degeneration resistances deployed

    in the mirror of Figure (5.7). In particular, if Vgs1= Vgs2, (5-18) confirms that the drop, IrefRss,

    across the source degeneration resistance, Rss, for transistorM1is identical to the voltage drop,IkRss/k21, across the source degeneration resistance, Rss/k21, used for transistor M2. The equal

    resistive drops means that the quiescent voltages established with respect to ground at each

    transistor source node are the same. In turn, equal source terminal voltages manifest equal bulk-source biases since both transistors have their respective bulk terminals returned to circuit

    ground. We can therefore conclude that the threshold voltages, Vhn1 and Vhn2, of M1 and M2,respectively, while subject to bulk-induced threshold modulation, are, at least in theory, identi-

    cally equal to a potential that is somewhat greater than the zero bias value of transistor thresholdvoltage.

    With Vgs1= Vgs2 Vgs, Vhn1= Vhn2 Vhn(inclusive of body effect) and V1= V2 V,

    (5-10) yields

    2hn

    ref n gs hn

    2

    kk ref ss dsat k 21 n gs hn

    VI V V 1

    V.

    V I R V

    I k V V 1V

    (5-20)

    These two relationships lead to

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    kk ref ss dsat

    k 21 ref hn

    V I R V 1

    VI k I ,

    V1

    V

    (5-21)

    which is similar in form to (5-14) for the simple (non-degenerated) NMOS current mirror. Since

    Vdsat= (VgsVhn), selecting Vkkin the neighborhood of (IrefRss+ Vgs)mitigates channel lengthmodulation. Alternatively, large V, which requires a suitably long drawn channel, likewise off-

    sets channel length modulation. Thus, if we satisfy one or both of these design targets, we

    achieveIkk21Iref, which is indicative of an ideal current mirror.

    If the shunt resistance associated with the reference current source, Iref, is infinitelylarge, currentIkproudly boasts no sensitivity to power line voltage Vdd. In other words, an ideal

    current source, Iref, implements infinitely large power supply rejection with respect to Vdd. On

    the other hand, the sensitivity ofIkto voltage Vkkis determined by output resistanceRoutin accor-dance with the generality set forth by (5-15). Deducing an analytical expression forRoutinitiates

    with our determining the Thvenin voltage and the Thvenin resistance associated with the gate-drain output port of theM1subcircuit. In this case, we can claim immediately that the Thvenin

    voltage driving the gate terminal of transistorM2is zero owing to the fact that the constant andideal current source, Iref, presents zero signal value to the mirror. Equivalently, we may assert

    that a small signal open circuit prevails in the network branch that interconnects voltage Vddwith

    the gate-drain terminal of transistor M1. Moreover, the Thvenin output resistance of the M1subcircuit bodes no significance in that the gate of transistor M2conducts no static current and

    therefore, no voltage is dropped across this resistance. Accordingly, we can presumably concen-

    trate on the small signal analysis of only theM2subcircuit of the mirror, with the understandingthat zero signal voltage is applied to its gate.

    True enough! But nonetheless, we shall proceed with finding the Thvenin resistance

    at the output port of the M1 subcircuit for two reasons. First, high frequency currents are con-ducted by MOSFET gates, whereupon it may be that the subject Thvenin resistance establishesa critical time constant with an M1 device capacitance. Second, we shall encounter source-

    degenerated, diode-connected transistors as building block components in our future networkdeliberations, so we are well advised to execute and file for future reference in our design note-

    books the pertinent circuit analysis and its results.

    Figure (5.8) is the small signal model for determining the M1Thvenin resistance,Rt1,

    which we shall calculate as the ratio, Vy/Iy, of mathematical ohmmeter variables. We recall ourmodeling experience with the diode-connected transistor in the conventional NMOS mirror of

    Figure (5.3a). This modeling experience suggests that theM1diode-connected unit we are pre-

    sently examining establishes a drain to source resistance of 1/gm1, if channel resistance ro1 islarge. In turn, our first blush estimate of the Thvenin output resistance isRt1= 1/gm1+ Rss. In-

    deed, this is a reasonably accurate first order estimate of Rt1, but it is not strictly correct in that

    body effect prevails herewith. In support of this contention, we note that unlike the network in

    Figure (5.3a), which grounds both the source and the bulk terminals of transistor M1, the dia-gram in Figure (5.7) portends only the grounding of the bulk terminal for transistor M1. It fol-

    lows that the model shown in Figure (5.8) properly incorporates a bulk transconductance effect

    of b1gm1V2, where V2 symbolizes the signal component of the bulk-source voltage applied totransistor M1. In general, we recall that a very thin gate oxide, Tox, begets very small b. Of

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    course,b=0implies no bulk-induced transconductance.

    Figure (5.8). Small signal model used to determine the Thvenin output resistance,Rt1, presented at the output

    port of theM1subcircuit in the source degenerated mirror of Figure (5.7).

    In the small signal model of Figure (5.8), we have delineated key branch currents in or-der to facilitate the construction of the requisite Kirchhoff equations. In particular,

    1 y y ss

    2 y ss

    V V I R

    ,V I R

    (5-22)

    and

    y y m1 1 b1 m1 2 o1 y ssV I g V g V r I R . (5-23)Upon substituting (5-22) into (5-23), followed by the obligatory rearrangement of terms, we find

    that

    y b1 m1 o1t1 o1 ssy m1 m1 o1

    V 1 1 g r 1R r R .I g 1 g r

    (5-24)

    The first term on the right hand side of this expression represents our familiar small signal resis-

    tance of a diode-connected transistor. Our inspection of the last term, which accounts for theresistance,Rss, placed in the source lead of transistorM1, suggests that the immediate effect of

    BITM is to increase very slightly the witnessed value of this series resistance. Nevertheless, ourfirst order estimate of the value of Thvenin resistanceRt1is apparently spot on. In particular, if

    gm1ro1>> 1(which is almost always true) andb1

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    Figure (5.9).Small signal model used to determine the Thvenin output resistance, Rout,

    presented at the output port of the source degenerated mirror in Figure (5.7).

    ssa b x

    21

    RV V I ,

    k

    (5-26)

    and

    ssx x m2 a b2 m2 b o2 x21

    RV I g V g V r I .

    k

    (5-27)

    Subsequent to our inserting (5-26) into (5-27), we find that

    x ss ssout b2 m2 o2x 21 21

    V R RR 1 1 g r .

    I k k

    (5-28)

    Forgm2ro2>> 1andb2

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    increased voltage, Vkk. In the present case, Vkkmust bias the drain-source terminals of transistor

    M2, and it must establish a suitable voltage across the circuit resistance, Rss/k21. We can alterna-tively state that for fixed Vkk, the second problem amounts to a constrained voltage swing at the

    drain-source port of transistor M2. The latter contention impinges at least indirectly on the de-

    gree of achievable circuit linearity in the source degenerated current mirror.

    5.3.3. CASCODE CURRENT MIRROR

    When the source degeneration resistance, Rss/k21, in Figure (5.7) is supplanted by atransistor that is biased at its gate with a diode-connected transistor, similar to the biasing of

    transistorM2in Figure (5.7), the source degenerated current mirror is transformed into what is

    known as a cascode current mirror. The cascode mirror is depicted schematically in Figure(5.10), where all transistor bulk terminals are grounded

    4. We note that since the source and bulk

    terminals of transistors M3 and M4 are connected to circuit ground, no BITM occurs in these

    devices. But threshold modulation in transistors M1 and M2 can be an issue since the sourceterminals of these transistors are not grounded. We also note that transistorsM1and M3have

    the same gate aspect ratios, and transistorsM2andM4also have equal gate aspect ratios But the

    latter ratios are a factor of k-timeslarger than the gate aspect ratios ofM1andM2.In Figure (5.10), we see that the output sinking current,Ik, is given approximately by

    k ref I k I . (5-31)

    This result is promoted by four observations. First, current Iref flows through the drain of

    transistorM3. Second, transistorsM3and M4 share the same gate-source voltages. Third, the

    gate aspect ratio of M4 exceeds that of M3 by a factor of k. Fourth, we have tacitly ignoredCLM. Dare we now quip Q.E.D as regards the approximate validity of (5-31)?

    Figure (5.10). Circuit schematic diagram of an NMOS cascode current mirror.

    The bulk terminals of all four transistors are grounded.

    As per our source degenerated mirror, let us assume that Iref derives from an idealsource of constant current, which is to say that it boasts infinitely large terminal resistance.

    Under this circumstance, the coupling of voltage Vddinto the gates of either transistor M2orM4

    is precluded. Resultantly, current Ik is rendered independent of Vdd. More importantly, the

    4In a twin well process, it may be possible to connect each transistor bulk terminal to its respective source terminal,

    thereby negating any bulk-induced modulation of threshold voltages.

    4

    2

    Vdd

    Iref

    Vkk

    Ik

    Rout

    M3

    M1

    x 1 x k

    x 1 x k

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    inability of Vdd to couple into the gate of M4means that no gate-source signal voltage can be

    established forM4. In turn, this situation gives rise to a drain to source signal current,gm4Va, aswe depict in the equivalent circuit of Figure (5.11a), that is forced to zero. The same null stature

    applies to the bulk transconductance source, b4gm4Vb, since the grounding of both the bulk andthe source terminals remands the bulk-source signal voltage, Vb, to zero. ResistanceRt3in thisequivalent circuit represents the Thvenin resistance presented to the gate of transistor M4by the

    diode-connected transistor, M3. This resistance is inconsequential since it conducts no currentand therefore, we can refrain from defining it analytically. Because Va = Vb = 0 in Figure

    (5.11a), the only element left standing in the small signal model of transistor M4 is the M4channel resistance, ro4. In effect, transistorM4in the cascode mirror behaves as a two terminal

    resistance and indeed, a rather large drain-source channel resistance.

    Figure (5.11). (a). Low frequency, small signal model of transistor M4 in the cascode mirror of Figure

    (5.10). (b). Low frequency, small signal model of the M2-M4 subcircuit in the cascodecurrent mirror of Figure (5.10).

    The resultant low frequency model of theM2-M4subcircuit is the topological structure

    appearing in Figure (5.11b). In this model, we have replaced transistor M4 by its channelresistance, ro4, which we now comprehend as an effective source degeneration resistance for

    transistorM4. Analogous to the previously defined Thvenin resistance,Rt3,Rt1is the presently

    inconsequential Thvenin resistance presented to theM2gate by the subcircuit formed of transis-torsM1andM3in Figure (5.10). But the most important undertone of this modeling exercise is

    that the model in Figure (5.11b) is topologically identical to the equivalent circuit we forged in

    Figure (5.9) for the conventional form of a source degenerated current mirror. The only

    observable electrical difference between the two models is that the source degenerationresistance,Rss/k21, in Figure (5.9) appears now as the resistance, ro4. This topological similarity

    synergizes with our earlier pronouncement to the effect that the cascode mirror is little more than

    a special case (indeed, an active form of a special case) of the source degenerated mirror. Itsimmediate and practical implication is that we can determine output resistance Rout in Figure

    ro4g Vm4 a b4 m4 bg V

    Va Vb

    Rt3

    = 0 = 0

    ro4

    ro4

    (a).

    ro2g Vm2 1 b2 m2 2g V

    V1 V2

    Rt1

    (b).

    Ix

    Vx

    Rout

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    (5.11b) merely by modifying the expression for Rout that we have already filed in our design

    notebook for the source degeneration case. Specifically, if we replaceRss/k21by ro4in (5-28), wesee, without need for annoying additional analysis, that

    xout b2 m2 o4 o2 o4 m2 o4 o2x

    VR 1 1 g r r r 1 g r r .

    I

    (5-32)

    Because resistance ro4is doubtlessly significantly larger than the former degeneration resistance,Rss/k21, the output resistance, Routof the cascode current mirror is laudably much larger than its

    companion output resistance for the conventional mirror.

    It is important to appreciate that the channel resistance, ro4, which functions as sourcedegeneration for transistor M2 in Figure (5.10), is large and assuredly much larger than the

    passive degeneration resistance, Rss/k21, which we deployed in the previous current mirror.

    Unlike the passive resistance, Rss/k21, which necessarily supports a static drop of IkRss/k21, theactive degeneration resistance, ro4, does not need to support a static voltage of Ikro4 across its

    terminals. Instead, the static voltage required across the drain-source terminals of transistorM4,

    where ro4is realized, is a drain saturation voltage, which can be as small as only a few tenths of a

    volt. This voltage drop is far smaller than the static drop necessarily established across a passiveresistance of value ro4. For example, if ro4= 20 K, a meagerIk= 1 mAdevelops 20 voltsacrossa passive form of resistance ro4. Good luck selling a cell telephone, a global positioning satellite

    (GPS) unit for automotive use, or other portable electronic system that requires at least a 20-voltbattery for activation. In a word, voltage Vkkin the cascode mirror of Figure (5.10) need only be

    large enough to ensure that transistorsM2andM4operate in their saturation domains.

    Let us examine more carefully the constraints to which voltage Vkk is necessarily

    subjected. We begin by remembering that the gate-source voltages of transistorsM3andM4are

    the same; that is, Vgs3= Vgs4 Vgs. In view of the facts that transistor M2has the same gate

    aspect ratio and conducts the same drain current that flows through transistor M4, Vgs2Vgs4=Vgs. This gate-source voltage equality presumes that channel length and bulk-induced threshold

    modulations inM4are negligible. A similar statement applies to transistorsM1andM3; that is,Vgs1Vgs3Vgs. We therefore deduce

    gs1 gs3 gs4 gs2 gsV V V V V . (5-33)

    Figure (5.10) additionally confirms that Vkkmust supply drain-source bias to bothM2andM4:

    kk ds2 ds4V V V . (5-34)

    In order for transistorM2to remain in saturation, we require Vds2(Vgs2Vhn2), where Vhn2, is,of course, the threshold voltage of transistor M2. Remember that the threshold voltages of

    transistorsM1andM2can be expected to differ from the threshold potential, Vhn4, ofM4owing

    to body effects incurred by the grounding of the bulk terminals of transistorsM1andM2. Since

    gs2 gs1 gs3 ds4 gs ds4

    V V V V 2V V , (5-35)

    M2is saturated if

    ds2 gs2 hn2 gs ds4 hn2V V V 2V V V . (5-36)

    Inserting this result into (5-34) establishes

    kk ds2 ds4 gs hn2V V V 2V V . (5-37)

    Since

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    dsat1 gs1 hn2 gs hn2

    dsat3 gs3 hn4 gs hn4

    V V V V V

    ,V V V V V

    (5-38)

    we conclude that

    kk gs hn2 dsat1 dsat3 hn4V 2V V V V V ; (5-39)

    that is, voltage Vkkmust be at least as large as nominally one threshold potential above twice thedrain saturation voltage of a transistor. Depending on the channel length of the utilized

    transistors, the drain saturation voltage can be in the range of 200 mVto 500 mV, while a gate-source threshold voltage can be of the order of 400 mVto 800 mV. Accordingly, we can expect

    that voltage Vkkmust lie in the range, 800 mV < Vkk< 1.8 V.

    5.3.4. WILSON CURRENT MIRROR[1]-[2]

    Figure (5.12) depicts the basic schematic diagram of the Wilson current sink. As in thecascode network, we have not shown the bulk terminal connections of transistors, but we

    nonetheless assume that these terminals are incident with circuit ground. Thus, bulk-induced

    threshold modulation takes place in transistors M1 and M2. However, our analyses anddiscussions of the Wilson mirror adopt the simplifying stance of gate oxide layers that are thinenough to allow for the tacit neglect of threshold voltage modulation in all active devices.

    Figure (5.12). Circuit schematic diagram of an NMOS Wilson current

    mirror. The bulk terminals of all four transistors are

    presumed returned to circuit ground.

    If we compare the network before us with that of the cascode configuration in Figure

    (5.10), we see that the Wilson circuit interchanges the roles of transistors M3andM4. In other

    words, transistorM3functions as a diode in the cascode circuit, while in the Wilson network, it

    serves effectively as a grounded source amplifier. More than simply a grounded source am-plifier,M3implements active feedback from the source of transistorM2to the source terminal of

    M1. This feedback serves to protect currentIk from spurious vulnerabilities. For example, sup-

    pose currentIkincreases by an amount that is not so large as to threaten the removal of transis-torsM2andM3from their saturation domains. Since the diode-connected device,M4, acts as a

    two terminal resistance, the increase in current Ik manifests a commensurate increase in the

    drain-source voltage of M4and hence, in the gate-source voltage of transistor M3. The rise inM3gate-source voltage produces a decrease in the drain-source voltage of M3for, as we learned

    4

    2

    Vdd

    Iref

    Vkk

    Ik

    Rout

    M3

    M1

    x 1 x k

    x 1 x k

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    in the preceding chapter, I/O (gate to drain) phase inversion is implicit to common source

    amplifiers. The decrease inM3drain-source voltage pulls down the voltage observed at the gateofM2. With the gate voltage ofM2falling and the source voltage of the same device rising, as

    we have already noted, the gate-source voltage of M2diminishes. This decrease in theM2gate-

    source voltage is met with a decrease in the indicated drain current, Ik. Accordingly, the originalspurious increase inIkis met with a mitigating current decrease to incur an effective stabilization

    of the sinking output current. In other words, the original current increase is ostensibly cancelledby the feedback that is implicit to the Wilson circuit.

    TransistorsM1andM3have identical gate aspect ratios, as do transistors M2andM4.But we note that the gate aspect ratios of M2andM4are a factor of klarger than the respective

    gate aspect ratios ofM1andM3. We shall demonstrate that the indicated output resistance,Rout,

    is potentially very large, despite being somewhat compromised by the designable factor, k. This

    laudable attribute does not stem principally from the source degeneration presented toM2by thediode-connected transistorM4. Instead, it arises largely from the series-shunt feedback we have

    addressed in the preceding paragraph. We shall more definitively investigate the feedback impli-

    cit to the Wilson cell when we study the common source-Wilson cascode broadband amplifierlater in this text.

    We see that the applied input current, Iref, flows through the drain of transistor M3.

    Since the gate-source voltages, Vgs3and Vgs4, ofM3andM4, respectively, are identical,M3andM4comprise a traditional two-transistor current mirror. The drain current resultantly conductedby transistorM4is necessarily kIref, where we have made use of the fact that the gate aspect ratio

    ofM4is larger than that of transistorM3by factor k. In asserting this mirrored current value, we

    have ignored the effects of CLM in M3 and M4. The mirrored current flows through M2,whence we conclude that output currentIkapproximates kIref.

    Let us now support the foregoing intuitive disclosures with a more focused analysis.

    We begin by monitoring the drain-source voltage, Vds3, of transistorM3as Vds3= (Vgs2Vgs1+Vgs4). Then, by the square law model, modified to account for CLM,

    2 gs2 gs1 gs4 gs3 hn

    ref n gs3 hn

    V V V V V

    I V V 1 .V

    (5-40)

    Since Vgs3Vgs4,

    2 gs2 gs1 hn

    ref n gs3 hn

    V V VI V V 1 .

    V

    (5-41)

    For transistorM4,

    2

    hnk n gs3 hn

    V

    I k V V 1 ,V

    (5-42)

    where we have exploited identical threshold voltages of M3andM4resulting from the absenceof body effect in these two devices. Moreover, the CLM voltage, V, should be nominally the

    same inM3and M4, as long as no wide disparity prevails between the drain-source voltages of

    these two devices. We can combine (5-41) and (5-42) to obtain

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    hn

    k ref gs2 gs1 hn

    V1

    VI kI .

    V V V1

    V

    (5-43)

    In addition to confirming our mirroring intuition, the last expression renders clear the fundamen-

    tal purpose of diode-connected transistorM1. To wit, ifM1were supplanted by a short circuit,so that the input current, Iref, is applied directly to the drain of M3, Vgs1in (5-43) is effectively

    zero. This means that the parenthesized correction factor on the right hand side of (5-43) be-

    comes

    hn

    gs2 hn

    V1

    V,

    V V1

    V

    thereby making it likely thatIkis noticeably smaller than the mirrored value, kIref, of this current.But with M1 included in the circuit, it is plausible that Vgs2 equals, or at least closely approx-

    imates, Vgs1, wherein we conclude thatIkkIref. Thus, the mirroring factor we have noted is ren-dered virtually insensitive to channel length effects

    5. We should point out that achieving Vgs1

    Vgs2is not a challenge. In particular, sinceM1andM2are physically identical transistors whose

    gate aspect ratios are scaled in accord with the quiescent currents they respectively conduct, their

    gate-source voltages should be nominally equal, assuming reasonably robust CLM voltages.Moreover, while it is necessary for the relative gate aspect ratio of transistor M4to be k, there is

    nothing sacred about setting the gate aspect ratio of transistorM2to k. In a word, it may be both

    prudent and desirable in the course of simulating the network to adjust the relative gate aspect

    ratio ofM2to effect voltage Vgs2closely matched to voltage Vgs1.

    In order to determine the output resistance, Rout, of the Wilson mirror, we turn to the

    low frequency, small signal equivalent circuit we display in Figure (5.13). This model reflects

    two simplifying and reasonable assumptions. The first of these assumptions is that BITM, whichis nonexistent in transistorsM3andM4, is negligible in transistorsM1andM2. This stipulation

    is entirely reasonable for the thin gate oxide MOSFETs that are routinely available from state ofthe art integrated process foundries. Our second assumption is the tacit neglect of CLM, which

    is equivalent to asserting infinitely large drain-source channel resistances, in transistors M1and

    M4. The latter assumption is justifiable in thatM1andM4are diode-connected transistors that

    exhibit terminal resistances that are no larger than the small resistance values implied by theirrespective inverse forward transconductances. We recall from our previous experiences that the

    resistances of these diode-connected devices equate to the parallel combination of channel resis-

    tance (ro) and inverse forward transconductance (gm). In turn, this shunt interconnection pro-duces a resistance that closely approximates 1/gmsincegmrois invariably much larger than one.

    Finally, we have delineated various branch currents to facilitate writing the Kirchhoff equili-

    brium relationships for the Wilson small signal model.

    A conventional circuit analysis of the model reveals

    5It is worthwhile noting that transistorM1was not included in Wilsons initial seminal disclosure[2].

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    Figure (5.13). Approximate, low frequency, small signal model used to determine the driving

    point output resistance,Rout, of the Wilson current mirror in Figure (5.12).

    xx o2 x m2 am4

    IV r I g V ,

    g (5-44)

    where

    xb

    m4

    xa m3 o3 b b m3 o3

    m4

    IV

    g

    .I

    V g r V V 1 g r g

    (5-45)

    It follows that

    x m2out m3 o3 o2x m4 m4

    V g1R 1 1 g r r .

    I g g

    (5-46)

    We can argue that the transconductances, gm2andgm4, are identical because transistors M2and

    M4have identical gate aspect ratios and conduct the same quiescent current. Because the drain-

    source channel resistances of transistors M2and M3are large, as is the product, gm3ro3, (5-46)collapses to

    out m3 o3 o2R 2 g r r . (5-47)Since the current conducted byM2is k-timeslarger than the current flowing in transistorM3, ro2

    ro3/2, whence

    o3out m3 o3r

    R 2 g r .k

    (5-48)

    We conclude that the output resistance of the Wilson mirror is large and comparable to that of

    the cascode current mirror. We should note, however, that the Wilson output resistance iscompromised by a large ratio, k, of transistor gate aspect ratios

    EXAMPLE #5.3:

    Design the Wilson current mirror of Figure (5.12) for an output current, Ik,

    of 1 mAwhen the reference current, Iref, is 100 A. For the purposes of

    ro2g Vm2 a Ix

    Ix

    Vx

    Rout

    1/gm4

    1/gm1

    Varo3 g Vm3 b

    g Vm3 b

    g Vm2 a

    Vb

    I g Vx m2 a

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    this exercise, assume thatIrefderives from an ideal source of constant cur-

    rent. Although the value of voltage Vddis inconsequential because of thepresumed ideality of current source Iref, use a power line voltage, Vdd, of

    3.8 volts. Assume that Vkkis set to a steady state value of 2.7 volts. For

    the NMOS transistor, whose parameters appear in Table (4.1) and whosedrawn channel length is 1.5m, use HSPICE or its equivalent to simulate,and provide engineering commentary of, the following performancecharacteristics:

    (a). the static transfer characteristic,IkversusVkk, for 0 Vkk4 volts;(b).the real part of the driving point output impedance, Zout, as a function

    of signal frequency;

    (c). the shunt output port capacitance as a function of signal frequency;

    (d). the transient response to voltage Vkk, where Vkkis taken as a 2.7 volt

    pulse train having 2SECpulse widths and a 4SECperiod.

    SOLUTION #5.3:

    (1). Very little work is required to design the Wilson configuration. We begin by selecting thegate width of transistorsM1andM3in Figure (5.12). There is no with problem setting W1=

    W3= L = 1.5 m. But in this case, we shall make W1= W3= 5L = 7.5 min order to incurlarger transistor capacitances, which serve to subdue voltage response overshoots to suddenly

    applied line voltages. Since we needIk= 1 mA, W2= W4= 10W1= 75m. Making W1andW3too large begets very large W2and W4, which may incur layout challenges that we shall

    address in due time. As already noted, larger capacitances in bias networks are generally

    desirable in that they tend to mitigate, albeit perhaps incompletely, the overshoots associated

    with an abrupt application of voltage Vkk. We shall observe somewhat dramatic responseovershoots when we address the issue of the transient response to voltage Vkk.

    (2). The area and peripheral dimensions associated with device capacitances compute in accord

    with (4-155). We have

    11 2s1 s3 d1 d 3 1

    s1 s3 d1 d3 1

    A A A A 2W L 2.2 x 10 m.

    P P P P W 4L 13.5 m

    (E3-1)

    In addition,

    10 2s2 s4 d 2 d 4 2

    s2 s4 d 2 d4 2

    A A A A 2W L 2.25 x 10 m.

    P P P P W 4L 81 m

    (E3-2)

    In most simulators, these geometrical parameters are inputted in conventional MKS units

    (meters, meters2, etc.)

    (3). Figure (5.14) displays the simulated static transfer characteristic,Ikversus Vkk. We can con-

    firm that the current, Ik, ultimately reaches its constant value of 1.008 mAat Vkk1.6 volts.

    The current goes on to increase minutely to 1.0081 mAat Vkk= 4 volts. The 1.008 mAoutputcurrent is within 0.8%of the 1 mA design target. This minute increase in current suggests

    excellent power supply rejection, which we understand requires a high output r