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CHAPTER 6

A NEW SERIES PARALLEL SWITCHED MULTILEVEL

DC-LINK INVERTER TOPOLOGY

6.1 INTRODUCTION

The use of MLI appears to experience an increasing trend in view

of the extensive automation in industries (Hammond 1997). The medium to

high voltage interface further enhances the need and it is this perspective

owing to which a host of topologies keep emerging (Meynard et al 2002).

A good number of MLI topologies are in use over the past four decades

(Franquelo et al 2008, Rodriguez et al 2009, Rodriguez et al 2002a,

Jih-Sheng Lai et al 1996).There are conflicting requirements forcing to

explore different and or new configurations to meet the state of the art

necessities(Abu-Rub et al 2010). The technology trace pioneers the dc-link

oriented structures and directs changes to incorporate added benefits to suit

economic and power quality considerations besides living up to technological

innovation. There are a host of MLI topologies that continue to receive great

attention and each inherit their own merits based on count of switches,

capacitors, diodes and the number of output levels produced from a fixed

number of sources (Lezana et al 2008, Hinago et al 2010) .

The emergence of a new class of MLIs based on a multilevel dc-

link (MLDCL) and a bridge inverter to reduce the number of switches,

clamping diodes or capacitors appears to be a break through in multilevel

power conversion applications (Gui-Jia Su 2005). The MLDCLI can be

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formed by connecting a MLDCL which provides a dc voltage with the shape

of approximating the rectified shape of a dictated sinusoidal wave, with or

without pulse width modulation, to the bridge inverter, which in turn

alternates the polarity to produce an ac voltage. These inverters significantly

reduce the number of switches and gate drivers as the number of voltage level

increases. However, these structures do not entail a satisfactory operation with

unequal voltage sources. It thus perpetuates the need for better structures with

the ability to produce still higher number of levels using unequal voltage

sources and further component reduction.

The cascaded MLI with different voltages (Veenstra et al 2005) in

the dc buses of each H-bridge cell envisions the next in line called the hybrid

multilevel power inverter. It is possible to synthesize more levels than that

with a symmetric topology (Ruiz-Caballero et al 2010) if the voltage level of

each dc bus is properly chosen with the same number of switches. Among the

asymmetric multilevel inverters, cascaded multilevel H-bridge inverter with

different dc voltage sources is particularly attractive as it is free from

capacitor voltage balancing but the power devices are subjected to unequal

voltage stress (Manjrekar et al 1998, Manjrekar et al 2000).

Multilevel topologies using bulk capacitors as a medium to

synthesize voltage levels lead to unbalanced voltage levels (Marchesoni et al

2002). It augurs the need for an adequate control or modulation strategy to

balance the voltage in the different capacitors of each topology. It prevents the

usage of existing control strategies of MLIs and an alternate solution of

innovative topologies that eliminate the capacitor based voltage media.

6.2 PROBLEM DEFINITION

A new variety of MLDCLI which uses lower number of sources,

power switches and eliminates the necessity of capacitors is developed. The

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proposed topology coined as SPSMLDCLI synthesizes a nearly distortion less

sinusoidal output voltage owing to its inherent ability to increase the number

of levels. The performance of this SPMLDCLI is investigated through

MATLAB based simulation over a range of viable modulation indices and

validated using a FPGA based prototype (http://www.xilinx.com).

6.3 PROPOSED TOPOLOGY

The generalized structure of the proposed topology contains voltage

sources in the ratio Vo:Vn = 1:3, switches and a diode along with a H- bridge,

that offers a minimum of fifteen levels is shown in Figure 6.1. While the

switches Sa, Sb, Sc, Sa1, Sb1, Sc1, San, Sbn and Scn form the dc-link circuit, the

switches S1,,S2, S3 and S4 constitute the H- bridge inverter. The part of the

circuit enclosed between the dotted lines acts as the parent cell and is the

obligatory structure in the dc-link part. The structure external to the parent

cell is named as a teen cell and every addition of a teen cell gives way to raise

six levels and there by avails the benefit to extend to the desired level.

Figure 6.1 Generalized structure of SPSMLDCLI

The modes of operation of the basic fifteen level SPSMLDCLI are

explained with V0:V1:V2 = 1:3:3 to elicit the complete working of the power

module. The switches S1, S2 and S3,S4 in the H- bridge are turned on

alternatively, while both Sa1 and Sc in the dc-link part are allowed to conduct

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to arrive at the first level of voltage as seen in Figure 6.2. In addition to the

H-bridge, when the switch Sc1 in the dc- link conducts, the topology lands at

the second level as observed from Figure 6.3. Accordingly the status of the

switches are pictured for the remaining levels and the sequence for

synthesizing different voltage levels in the fifteen level SPSMLDCI is

summarized in Table 6.1. The entries in Table 6.2 compare the switch and

source requirements for the fifteen level topology with the existing MLI

topologies to highlight the reduction in the count.

Figure 6.2 SPSMLDCLI operating mode-level 1(± 50V)

Figure 6.3 SPSMLDCLI operating mode-level 2(± 100V)

Figure 6.4 SPSMLDCLI operating mode-level 3(± 150V)

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Figure 6.5 SPSMLDCLI operating mode-level 4(± 200V)

Figure 6.6 SPSMLDCLI operating mode-level 5(± 250V)

Figure 6.7 SPSMLDCLI operating mode-level 6(± 300V)

Figure 6.8 SPSMLDCLI operating mode-level 7(± 350V)

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Table 6.1 Switching sequence for 15 level

SwitchesVoltage

level Sa Sb Sc Sa1 Sb1 Sc1 DB S1 S3 S2 S4

+7

+6

+5

+4

+3

+2

+1

0

-1

-2

-3

-4

-5

-6

-7

Table 6.2 Comparison between topologies for 15 level

Multilevel dc-link inverterMultilevel

inverter

structure

Cascaded

H-bridge

Diode

clamped

Flying

capacitorCascaded

half

bridge

Diode

clamped

Flying

capacitor

Proposed

Main

switches28 28 28 18 18 18 10

Bypass

diodes- - - - - - 1

Clamping

diodes- 24 - - 12 - -

DC split

capacitors- 6 6 - 6 6 -

Clamping

capacitors- - 12 - - 6 -

DC

sources7 1 1 7 1 1 3

Total 35 59 47 25 37 31 14

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It is evident from the Table 6.2 that the number of power devices

required is only ten which is 76% less when compared with the basic MLI

topologies and 44% with MLDCLIs. It is equally significant to note that the

difference in the total component count stands at forty five when it is

compared with a similar conventional case. The exact number of levels in the

output voltage that a SPSMLDCLI can synthesise is generalized using the

relation (2(3n 1) 1) where n is the number of voltage sources excluding V0, if

arranged in the ratio V0: Vn=1:3.

The available power switches where a simple switch and an anti

parallel diode are patched to permit regeneration, experience a specific

phenomenon of inter-looping and consequently create two circulating current

paths as indicated with different colours in Figure 6.9. It may lead to a

possible distortion in the output voltage and deviate away from the ideal

waveform as seen from Figure 6.10 (a) and (b). The problem can however be

eliminated by replacing the switches with IGBT switches as shown in

Figure 6.11.

Figure 6.9 Inter-looping in dc-link structure

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(a) (b)

Figure 6.10 Output voltage using (a) Generic switches and (b) MOSFETs

Figure 6.11 Eliminating inter-looping with IGBTs

6.4 SIMULATION

The basic fifteen level SPSMLDCI is simulated using MATLAB

R2010a. The voltage sources in the topology are chosen accordingly to offer

an output of 220V and a resistance of 110 as the load. The approach seeks

the role of a PD -MC PWM technique with a carrier frequency of 4 KHz as

the firing strategy. The MLDCL voltage produced by the parent cell and the

unfolded ac output voltage waveform from the H-bridge along with harmonic

spectrum are shown in Figures 6.12 and 6.13 respectively. The output current

waveform for an inductive load of 5 mH is displayed in Figure 6.14.

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The variation of THD as a function of the fundamental component

over a range of modulation indices for both the proposed and CHBMLDCLI

is depicted in Figure 6.15 and observed that as the output voltage magnitude

increases the THD decreases. It serves to bring out that the new structure

eclipses a much lower harmonic content of the output voltage for a projected

target.

Figure 6.12 Dc-link voltage waveform

Figure 6.13 Output voltage waveform and harmonic spectrum

Figure 6.14 Inductive load current

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Figure 6.15 Fundamental component Vs THD

6.5 HARDWARE IMPLEMENTATION

The prototype of SPSMLDCI shown in Figure 6.16 is constructed

using MOSFETs (IRF 840), diode (BYQ 28E), IGBTs (FIO 5O-12BD) and a

resistive load of 110 to operate under similar operating conditions applied in

the simulation. It seeks the role of Xilinx based system generator facility

available as a toolbox in MATLAB R2010a to generate the multi carrier

PWM pulses for the power switches. The scheme involves an appropriate

mechanism through which the VHDL code required to suit a Spartan based

FPGA is acquired and there from buffered to turn on the power switches in

the SPSMLDCLI. The flow diagram of the strategy is explained through

Figure 6.17.

Figure 6.16 Prototype of SPSMLDCLI

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Figure 6.17 Flow chart for pulse generation using FPGA

The experimental prototype depicting the interface of power

module and control algorithm is photographed in Figure 6.16. The gating

signals captured through Tektronix TPS 2024 scope are shown in Figure 6.18.

The dc- link and the load voltage waveforms along with the harmonic

spectrum corresponding to a modulation index of 0.9 and an output of 220 V

are portrayed in Figure 6.19. The fact that the same fundamental output is

obtained for the designed output level both using simulation and hardware

with comparable THD values goes to validate the PWM technique in addition

to highlighting the practical feasibility of the proposed MLI configuration.

The entries in Table 6.3 serve to adequately validate the simulated and

hardware results through a close comparison of their harmonic components of

the output voltage over a range of specified targets.

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(a) (b)

Figure 6.18 Gating signals (a) Parent cell and (b) H- bridge

(a) (b)

Figure 6.19 (a) Dc-link voltage and load voltage waveforms and (b) Load

voltage spectrum

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Table 6.3 Comparison of simulation and experimental results

Simulation HardwareV01

(V) THD (%) THD (%)

100 19.4 18.28

120 15.58 16.52

140 12.77 14.02

160 12.14 11.28

180 9.69 10.12

200 9.70 10.52

220 8.28 8.50

6.6 SUMMARY

A new SPSMLDCLI structure with a reduced number of power

switches has been suggested to steal home an innovation in this domain. The

philosophy has been to eclipse the increase in the voltage levels through a

new topology that imbibes a parent and a fitting number of teen cells along

with a single full bridge to cater to bidirectional power flow. It has been able

to aggregate a much better performance in the sense it facilitates more or less

a sinusoidal output voltage. The measure by which it excels has been strongly

authenticated through a series of results with a view to illustrate its

applicability in the present day context. The fact that any level of target can

be achieved using this configuration will go a long way in exploring new

dimensions in this domain.