chapter11: symbolic signal flow graph methods in...

Chapter11: SYMBOLIC SIGNAL FLOW GRAPH METHODS IN

SWITCHED-CAPACITOR DESIGN

M. Helena Fino, STUDENT MEMBER IEEE Universidade Nova de Lisboa

Faculdade de Ciências e Tecnologia DEE Email: [email protected]

José E. Franca, SENIOR MEMBER IEEE

Instituto Superior Técnico Centro de Microsistemas

Email: [email protected]

Adolfo Steiger Garção Universidade Nova de Lisboa

Faculdade de Ciências e Tecnologia DEE Email: [email protected]

11.1 Introduction

In previous chapters the use of symbolic methods has been largely dedicated

to the lower levels of analog circuit design encompassing circuit elements such as

amplifiers and comparators [1, 2, 3]. In this chapter we shall describe symbolic

signal flow graph (SFG) computational techniques for the analysis and synthesis

of switched-capacitor (SC) circuits. This is based on a hierarchical approach in

which signal processing building blocks are defined in terms of basic elements

whose characterization resides in a knowledge-base. This knowledge-base can be

developed both for analog and digital discrete-time building blocks using the

common SFG representation of their operation but, for conciseness, we shall

consider herein its specific implementation only for discrete-time SC signal

processing building blocks.

Besides the Introduction this chapter comprises six additional sections.

Section 11.2 discusses the flow of information for circuit analysis and synthesis

11-1

of SC building blocks and establishes the hierarchical plans to be considered for the

development of an automated design environment. Section 11.3 describes the SFG-

based method for generating the symbolic transfer functions of SC networks. After

giving a brief description of the SC elementary blocks and the corresponding SFG

representation we shall introduce a simple rule-based approach for automatic

identification. Then, Section 11.4 describes the symbolic analyzer where a pattern

matching technique is used for generating the SFG representation of SC building

blocks and yielding the corresponding symbolic z-domain transfer function. The

use of such symbolic analyzer is discussed in Section 11.5 for carrying out highly

flexible step-by-step synthesis of SC building blocks, and in Section 11.6 for

automatic knowledge capturing of those SC building blocks. Finally, Section 11.7

summarizes and concludes the chapter.

11.2 Analysis and Synthesis in Circuit Design

Circuit design can be broadly characterized by the close interrelation of

synthesis and analysis procedures. Here, we define synthesis as the process through

which the designer usually assembles simple, fully characterized circuit primitives

to create more complex, unknown circuit topologies. These circuit topologies are

then characterized and verified using analysis procedures, which throughout this

chapter are based on symbolic computational techniques. This section provides a

simple description of the basic flow of information for both Analysis and Synthesis,

as well as the most relevant procedures required for automating both.

11.2.1 Flow of Information for Analysis

Fig. 11-1 illustrates the flow of information during the analysis of a simple

11-2

SC building block. Once the Description of a Building Block is given an

Interpretation process identifies the constituting SC elementary blocks, and then

characterizes each of them in order to determine the behavior of the overall SC

building block. Such interpretation is carried out based on a set of primitives

usually consubstantiated in a set of rules which define the structure of the

elementary blocks and the corresponding characterization. From the interpretation

process, the SFG representing the operation of the SC building block is obtained.

An Equation Extractor is then applied to such SFG yielding the symbolic z-

domain transfer function of the building block under analysis. Later, the transfer

function symbols can be instantiated to numerical values so that in the Evaluation

phase the frequency response of the circuit is obtained and relevant performance

criteria are evaluated.

NumericalInstantiation

Building BlockDescription

EquationExtractor

Interpretation -a.z- 1/2- (1 / b)

ab

xxy

yy

a=1, b=2 => H(z) =

- 1/2

x y x

z- 1/2

num

a.zb (1 - z )- 1

H(z) =

2 (1 - z )- 1

Evaluation

Primitives

1(1 - z )-1

11-3

Fig. 11-1: Flow of information during the analysis of an SC building block.

11.2.2 Formulation Method for Building Block Interpretation

As mentioned before, the building block interpretation is based on a set of

primitives that characterize the SC elementary blocks, and is usually accomplished

in two phases. In the identification phase, the building block description is browsed

so that by applying appropriate pattern matching techniques all the constituting

elementary blocks are recognized. Then, in the Characterization phase, the

characterization of each one of the constituting elementary blocks is computed

and the overall characterization of the building block is thus obtained.

In order to assist the interpretation process for the characterization of the

building block the core of primitives should provide one set of rules concerned

with the identification phase of the interpretation process, and another set of rules

concerned with the evaluation of the characterization of the elementary blocks.

Later, in Section 11.3, we shall discuss the relevant rules for the core of primitives

for SC analysis and synthesis and which are based on discrete-time SFG

representation techniques.

11.2.3 Flow of Information for Synthesis

The typical flow of information during the synthesis of an SC building block

circuit is represented in Fig. 11-2. The first step consists of obtaining the numerical

z-domain transfer function to meet the target specifications. This is accomplished

using well known computer-based routines, e.g. [4], and therefore will not be

considered here. The second step is the Building Block Topology Synthesis where

the topological characterization of a building block is obtained and the

11-4

corresponding symbolic z-domain transfer function is evaluated. This step makes

use of the same set of primitives previously mentioned for analysis and which

characterize the relevant SC elementary blocks. In the Dimensioning phase, the

symbolic expressions of the coefficients of the z-domain transfer function are

equated to the previously obtained numerical coefficients.

NumericalSpecifications

Dimensioning

H(z) = z- 1/2

2 (1 - z )- 1

ax

xy

yyb

-a.z- 1/2- (1 / b)

1 and

Building BlockDescription

− 1/2− 1/2 z2 (1 - z )- 1=

a.zb (1 - z )- 1

a.z - 1/2

b (1 - z )- 1H(z) =

2

y x y

z- 1

1x

xy

yy y x y

z- 1

Evaluation

(1 - z )- 1

Building BlockTopology Synthesis

Equation Extraction

Fig. 11-2: Typical flow of information for synthesis of an SC building block.

Since the resulting system of equations is usually not solvable by algebraic

means it is necessary to place additional constraints on the symbolic expressions of

the coefficients. These constraints are usually based on structural knowledge of

11-5

the building block topology.

Finally, in the Evaluation phase, the frequency response of the building

block is obtained and relevant performance criteria, e.g. variability of the frequency

response against capacitance ratio errors, are evaluated.

11.2.4 Equation Extractor for Dimensioning

In the flow of information for analysis we have introduced an equation

extractor responsible for producing the symbolic z-domain transfer function of the

SC building block represented by the appropriate SFG. In the above synthesis

process, however, the Equation Extractor must also produce additional equations

introducing constraints on the symbolic expressions of the coefficients in order to

make possible to automatically dimension all the building block parameters. The

equations are based on structural information of the building block and may be

automatically evaluated be applying a structural evaluator to the netlist description

of the block. The particular case for SC networks will be described in detail in

Section 11.6.

11.3 Switched-Capacitor Primitives and Identification

Techniques

11.3.1 SFG Representation of SC Elements

SC networks consist of the interconnection of SC elementary blocks,

comprising such elements as switches, capacitors and operational amplifiers, whose

discrete-time operation is characterized with respect to the associated timing

diagram. By using classical SC circuit analysis techniques [5, 6, 7] we can derive

11-6

for various SC elementary blocks the corresponding SFG representation, as

summarized in

Fig. 11-3. Note that all SC elementary blocks represented here refer to the same

timing diagram indicated at the bottom of the figure. Some icons are also indicated

in order to simplify schematic representations. All SFGs shown in Fig. 11-3

comprise three different transmission factors, za,zb and K, that provide some

physical insight into the operation of the corresponding SC elementary blocks. The

transmission factors za and zb represent, respectively, the time delay (advance) of

the input and output sampling instants of the SC elements with reference to the

associated timing diagram. The transmission factor K indicates the relationship

between the sampled input and output variables. When the SC element transforms

a sampled input voltage signal into a sampled output packet of charge K

represents the equivalent capacitance value, as is the case of all quasi-passive SC

elementary blocks, i.e. Toggle Switch Inverter (TSI), Open Floating Resistor

(OFR), Toggle Switch Capacitor (TSC), Parasitic Compensated Toggle Switched

Capacitor (PCTSC), and Inverting Parasitic Compensated Toggle Switched

Capacitor (IPCTSC) [8]. In the case of the active SC elementary block also

represented in Fig. 11-3, K represents the equivalent transimpedance value (here

the inverse of a capacitance) describing the transformation of a sampled input

packet of charge into a sampled output voltage signal. The sign associated with the

transmission factor K indicates the phase of the input (output) variables with

respect to the positive reference phases. Positive voltages are defined from a node

to ground while positive packets of charge are defined for a flow into an output

node or for a flow from an input node.

11.3.2 Rule-Based Identification

11-7

For the identification of the SC elementary blocks comprising a given SC

network, a pattern-matching technique is employed based on Structural Rules

residing in the system knowledge-base.

11-8

Toggle switched-inverter (TSI)

Memory capacitor

- a + b

Open floating resistor (OFR)

Toggle switched-capacitor (TSC)

Inverting parasitic-compensated TSC (IPCTSC)

a) b) c)

Parasitic-compensated TSC (PCTSC)

Feedback capacitor

-b-a 0

d)

y

x

x . K . y

x . K . x

x . K . y

x . 2K . x . 2K . y

x . 2K. x . 2K . y

yxyyx

2C

2C∆Qv

∆Qyx

vC

xyyxC

∆Qv

x y

y x

C

∆Qv

x xC

∆Qv

∆Q

x

yy x

2C

2Cxv

∆Q

xC

V

y

- a

(K = + C)

(K = -C)

(K = + C)

(K = - 1 / C)

(K = + C)

(K = - C)V

K zz

∆Q

V

K z+ b- az

∆Q

z- bz- a

V∆Q(1 - z )- 1

K

- a - 1 z + az

∆QV

K

z + bz- a

V ∆Q

K

∆Q

z

V

z + aK

(K = - C)

- 1- a

VK (1 - z ) z+ az

∆Q

- a

Fig. 11-3: Elementary blocks for SC networks. a) Structure. b) Icons. c) SFG. d) Switch-timing.

11-9

An example of the Prolog [9] structural rule defining a TSI is shown below.

Such TSI comprises four switches and a capacitor. The first switch, operating with

phase Phasei is connected between the input node (Inp) of the element and node

X. Connected between this node and ground is another switch operating with phase

Phaseo. Between the same node X and node Y is a capacitor with capacitance

value C. A third switch, which also operates with the same phase Phasei is

connected between node Y and ground. Finally, a switch operating in the same

phase Phaseo as the one connected to the input node is connected between node Y

and the output node.

tsi(N,Inp,Outp,Phasei,Phaseo,C):- sw(N,Inp,X,Phasei), /* switch */ sw(N,X,gnd,Phaseo), capa(N,X,Y,C), /* capacitor */ sw(N,Y,gnd,Phasei), sw(N,Y,Outp,Phaseo).

Rule 11-1: Structural rule for the identification of a Toggle Switch Inverter.

11.4 SFG-Based Symbolic Analysis of SC Networks

11.4.1 Formulation Method

The SFG of an SC network is generated from its circuit description

employing information residing in the knowledge-base, as schematically illustrated

in Fig. 11-4. Once an SC elementary block has been identified based on the

structural rules discussed above the corresponding SFG can be evaluated based on

two groups of Evaluation Rules. One group of evaluation rules is concerned with

the calculation of the delay term as a function not only of the switching phases but

11-10

also of the reference phase, the clock period, Period, and the unit delay, Deluni, to

be considered. This is illustrated below in Rule 11-2 for the simple example of the

TSI SC element previously considered.

Building Block Description

SC elementary block characterization

structural descriptionelementary

SFG

Identification

SFG generator

Interpretation

Fig. 11-4: The SFG of an SC network is derived from its description based on the characterization of SC elementary blocks residing in the knowledge-base.

calcdelay(Period,Tframe,Pref,P1,P2,Deluni,Delay):- member([P1,TiP1,ToP1],Tframe), /* ToP1- falling edge of phase P1*/ member([P2,TiP2,ToP2],Tframe), /* ToP2 - falling edge of phase P2*/ member([Pref,TiPref,ToPref],Tframe),/* ToPref - falling edge of the ref.phase */ delays(Period,ToP1,ToP2,ToPref,Dels), /* Delay in input voltage sampling */ delayt(Period,ToP1,ToP2,ToPref,Delt), /* Delay in charge transfer*/ Deltotal is Dels + Delt, quo(Deltotal,Deluni,Delay). /* Delay =Deltotal/Deluni */

Rule 11-2: Rule for the evaluation of the delay term of an SC elementary block.

As we can see, the predicate calcdelay starts by obtaining the falling edge

instants ToP1 and ToP2 of the phases P1 and P2 that control the operation of the SC

elementary block, as well as the falling edge instant ToPref of the phase taken for

reference, Pref. Then, the predicate delays is invoked so that the delay Dels

associated with the input voltage sampling instant is computed. Once the delay

11-11

Delt related to the charge transfer instant is calculated by the predicate delayt the

total delay factor, Deltotal, is obtained by adding together Dels and Delt. Finally

the Delay term is obtained by normalizing the previously calculated total delay

with respect to the unit delay, Deluni.

The predicate delays is consubstantiated by Rule 11-3 and Rule 11-4 shown

below. Rule 11-3 is applied when the input voltage sampling instant, ToP1 of the

capacitance pertaining to the SC element occurs after the corresponding charge

transfer instant, ToP2. In this case, the charge transfer process will only take place

in the next clock cycle, i.e. at ToP2+Period, and Dels will be given by the

difference between ToP1 and ToP2+Period. Rule 11-4 is applied when the

sampling instant occurs prior to the charge transfer instant, and Dels is given by the

difference between ToP1 and ToP2..

delays(Period, ToP1,ToP2,ToPref,Dels):- ToP1 @>ToP2,!, /* sampling phase is after the charge transfer phase */ To is ToP2 + Period, Dels is ToP1 - To.

Rule 11-3: Rule for evaluating the delay associated to the input voltage sampling of an SC elementary block when the sampling instant, ToP1, occurs after the

charge transfer instant, ToP2.

delays(Period, ToP1,ToP2,ToPref,Dels):- Dels is ToP1 - ToP2.

Rule 11-4: Rule for evaluating the delay associated to the input voltage sampling of an SC elementary block when the sampling instant, ToP1, occurs prior to the

charge transfer instant, ToP2.

The predicate for the evaluation of the delay associated to the charge transfer

process, Delt, is consubstantiated by Rules 11-5 and Rule 11-6 shown below. Rule

11-5 is applied when the charge transfer instant, ToP2, of the capacitance pertaining

11-12

to the SC element occurs prior to the reference instant, ToPref. Here, Delt is given

by the difference between ToP2 and ToPref.

delayt(Period, ToP1,ToP2,ToPref,Delt):- ToP2 @<= ToPref,!, Delt is ToP2 - ToPref.

Rule 11-5: Rule for evaluating the delay associated to the charge transfer process of an SC elementary block when the charge transfer instant, ToP2, occurs prior to

the reference phase, ToPref.

Rule 11-6 considers the case when the charge transfer instant occurs after the

reference phase, so that the reference phase of the next clock cycle, ToPref + Period

must be considered. In this case, Delt will be given by the difference between ToP2

and ToPref + Period.

delayt(Period, ToP1,ToP2,ToPref,Delt):- Tref2 is ToPref + Period, Delt is ToP2 - Tref2.

Rule 11- 6: Rule for evaluating the delay associated to the charge transfer process of an SC elementary block when the charge transfer instant, ToP2, occurs after the

reference phase, ToPref.

The second group of rules for the SFG evaluation of SC elements concerns

the symbolic characterization of the weight factor Y, given the capacitance value,

C, of the capacitor pertaining to the SC element and the previously calculated

delay, Delay. The simple case for a TSI element is illustrated in Rule 11-7. As we

can see, the transmission factor, K, is firstly evaluated (here K=-C) and then the

TSI SFG weight, Y, is obtained by invoking predicated ratFormpf , which returns

in the third argument the symbolic representation of the ratio between the first two

11-13

arguments.

ratpol(tsi,C,Delay,Y):- /* Y = -C * z^Delay /1 */ minus([C],K), ratFormpf(K*z^Delay,[1],Y). /* ratFormpf( num, den, num/den) */

Rule 11-7: Rule for evaluating the SFG weight factor of a TSI.

In order to generate the overall symbolic SFG corresponding to a given SC

network the automatic SFG generator first browses the associated netlist so that the

operational amplifiers with a feedback capacitor are recognized and, for each of

them, both the phase at which the output voltage of the amplifier is sampled

(Phaseref) and the unit delay are determined. For determining the unit delay, two

distinct cases must be considered. Should the circuit function with a sampled and

held input signal, then the unit delay is equal to the period of the clock signal

controlling the operation of the circuit. Otherwise, the number of distinct phases,

nphases, at which the input signal is sampled is determined and the unit delay is

obtained by dividing the period of the clock by nphases. To conclude the overall

SFG generation, the remaining SC elementary blocks are identified using the rule-

based techniques discussed before. The SFG of each one of those SC elementary

blocks is calculated by applying the rules residing in the knowledge-base and

taking into account both the reference phase and the unit delay computed for the

operational amplifier that is fed by the SC elementary block under consideration. In

order to avoid conflicts in the identification phase the more complex SC elements,

e.g. those which are parasitic compensated, are identified firstly and their

constituting capacitors marked as already pertaining to an identified element.

After generating the symbolic SFG of a circuit, Mason's rule [10] is applied

for determining the overall z-domain transfer function, also in symbolic form. Once

the symbols in the z-domain transfer function are instantiated to numerical values

11-14

the frequency response of the network can be obtained. Further performance

criteria, such as the variability of the frequency response against capacitance ratio

errors, can also be easily obtained either by instantiating different capacitance

values or by instantiating nominal capacitance values as well as their associated

tolerances.

11.4.2 Working Example

An example considering an SC decimator using an active-delayed block

architecture [11] is illustrated in Fig. 11-5. Given the decimator netlist, the

operational amplifiers OP1 and OP2 are recognized and, to each of them, the

reference phases 5 and 1, respectively, are associated. Then, the remaining SC

elementary blocks of the circuit are identified: for those belonging to block1, the

delay factor of the corresponding SFG is calculated considering phase 5 as their

reference phase; for the elements pertaining to block2, phase 1 is considered as the

reference phase. The SFG obtained for the SC decimator in Fig. 11- 5a and with

time frame represented in Fig. 11-5b is graphically illustrated in Fig. 11-5c.

11.5 Step-by-Step SC Synthesis and Knowledge Capture

The first step in the synthesis process consists in obtaining a network

topology that may be submitted to the dimensioning process. For this the designer

may opt for either using a previously defined and fully characterized building block

topology or for exploring a new topology by assembling simple, fully

characterized circuit primitives to create a more complex, unknown network

topology

In the process of creating new topologies based on a set of fully characterized

11-15

circuit primitives a symbolic calculation is carried out for every step of the

construction of the network, so that the designer gains a qualitative insight into the

key parameters responsible for the behavior of the circuit.

11-16

c)

block1inp

2.d .1

3.d .1

4.d .1

5.d .1

1.d .6

2.d .6

1.d .7

a

OP1

3.a .5

z-1b)

5. e . 7

5.c .1

1.c .6

2.c .6

3.c .6

4.c .6

5.c .7

4.c .1

3.c .1

2.c .2

1.c .1

reference phase for block2

b

OP2

3.b .1

1

outp

a)

-1/a -1/b 1

outpinp

reference phase for block1

waveform 7

waveform 5waveform 6waveform 4

waveform 3waveform 2

waveform 1

d .z -99

d .z 8 -8

-d .z -77

-d .z -66

-d .z -55

-d .z -44

-d .z -33

-d .z -22

-d .z -11

9

-c .z-99

-c .z8 -8

-c .z-77

-c .z -66

-c .z-55

-c .z-44

-c .z-33

-c .z-22

c .z -11c 0

-9e .z

4.2d .4.2d .69 9

3.2d .3.2d .68 8

0

1

6

5

4

3

2

0

1

2

3

4

5

6

7

8

9

block2

Fig. 11-5: SFG generation for an SC decimator with ADB architecture. a) Circuit. b) Time Frame c) Signal Flow Graph.

11-17

During such step-by-step synthesis process the knowledge created may be

kept in the system knowledge-base so that it may be reused whenever it is needed

to parameterize the same network to meet given target specifications.

11.5.1 Step-by-Step Synthesis

For illustration purposes we consider the step-by-step synthesis of a classical

SC biquadratic section [7, 12]. As illustrated in Fig. 11-6, the first step consists in

generating a basic structure that implements the quadratic denominator of the

transfer function. In Fig. 11-6a.1 this is accomplished by connecting in a loop one

negative SC integrator and one positive SC integrator. By using the symbolic

analyzer the designer obtains the SFG and symbolic expression for the

denominator D(z), respectively, depicted in Fig. 11-6a.2 and Fig. 11-6a.3. Then, as

shown in Fig. 11-6b.1, it is necessary to damp the loop, with the addition of a

damping capacitor E; this yields the SFG and symbolic expression for the

denominator D(z) represented, respectively, in Fig. 11-6b.2 and in Fig. 11-6b.3.

Then, in order to realize the quadratic numerator function feedforward branches

must be added from the input terminal to the output of the circuit. In Fig. 11-6c.1

we consider the case of adding two branches to the input of the first operational

amplifier yielding the SFG and transfer function shown, respectively, in Fig. 11-

6c.2 and in Fig. 11-6c.3. The same operation is repeated in Fig. 11-6d.1 for the

second operational amplifier and thus finally leading to a network topology whose

SFG and symbolic transfer function are described, respectively, in Fig. 11-6d.2

and in Fig. 11-6d.3.

11-18

.

Fig.

11-

6: U

sing

the

sym

bolic

ana

lyze

r for

the

step

-by-

step

synt

hesi

s of a

n SC

biq

uadr

atic

D

OP1

e.A

.o

B

OP2

e.C

.e

E

a.1

)

D

OP1

e.A

.o

B

OP2

e.C

.e

b.1

)

a.3

)

b.3

)

D (z

) =1

+ (A

C/B

D -

2) z-1

+z-2

BD

( 1- z

)

-12

D (z

) =1

+ (A

C/B

D +

AE/

BD

- 2)

z-1+

(1 -

AE/

BD

) z-2

BD

( 1- z

)

-12

-1D

(1-z

)-1B

(1-z

)-1

-1-A

z-1C

E -E

z-1

a.2

)

b.2

)

-1D

(1-z

)-1

-1B

(1-z

)-1-A

z-1

C

11-19

Fig.

11-

6: (c

ont.)

D(1

-z )-1

-1B

(1-z

)-1-1

-Az-

1

C

E -E

z-1

-Hz-1

G

c.1

) c

.2)

inps

outp

D

OP1

e.A

.oe.

C.e

B

OP2

E

ee.G.e

e.H.o

C

-1-1

D(1

-z )

B(1

-z )

-1-1

-Az-1

Ez

-E-1

-Hz-1

GI

-1-J

z

outp

D

OP1

e.A

.oe.

C.e

B

OP2

E

e

e.G.e

e.H.o

e.I.e

e.J.o

inps

H(z

) =A

H z

-2−

AG

z-1

+(B

D -

AE)

z-2

+(2

BD

+ A

C +

AE)

z-1

BD

d.1

) d

.2)

d.2

)

c.2

)

H(z

) =(A

H -

JD) z

-2−

(AG

+ ID

+ JD

) z-1

−ID

inpsin

ps

outp

outp

+(B

D -

AE)

z-2+

(2B

D +

AC

+ A

E) z

-1B

D

11-20

11.5.2 Building Block Characterization

The complete parameterization of a building block may only be attained if the

system is able not only to generate its symbolic z-domain transfer function but also

provide the additional structural knowledge needed to size the final capacitance

values [13].

The process of generating the symbolic characterization of an SC filter is

depicted in Fig. 11-7. Firstly, it determines such capacitors whose capacitance

value may be usually pre-set to some fixed value so that the extra degrees of

freedom for design are eliminated. After obtaining the symbolic z-domain transfer

function, a structural evaluation process is also applied to the building block

topology to produce the relevant knowledge concerning the capacitance values.

This is the case of the Integrating Capacitors which can be pre-set to unit such that

the associated capacitance ratios are replaced by absolute capacitance values, as

illustrated in Fig. 11-8a.

Building Block Topology Description

Interpretation z-tansfer function generation

Structural Evaluation

Equation Extraction

z-transfer function

Integrating Capacitors

Topology Description

Coupling Capacitors

SC Equivalences

Normalizing Capacitor Sets

Voltage Capacitor Sets

Fig. 11-7: Symbolic characterization for SC filter design.

11-21

X

Y

B

X

Y

1

DB

e.A.o

e.F.ee.A.e

DB

e.1.o

e.F.ee.C.e

DB

e.A.o

e.F.ee.C.e

a.1) a.2)

b.2)

b.1) b.3)

c.1) c.2)

e.J.o

e.I.e

e.J.o

e.J.e

J

Fig. 11-8: Reducing design variables: a) by replacing capacitance ratios with nominally equivalent absolute capacitance values, b) by pre-setting coupling

capacitors, c) by using established equivalencies between SC branches.

In Fig. 11-8b further constraints on the capacitance values may also be

applied either by pre-setting the value of the Coupling Capacitor A to unit [12] or

by pre-setting the Coupling Capacitors A and C to the same value A. In Fig. 11-

11-22

8c a pair of switched-capacitors connected between the same nodes are pre-set to

the same value, leading also to the elimination of one circuit variable.

The SC Structural Evaluation process also determines the Voltage

Capacitor Sets which can be affected by voltage scaling operations, as well as the

Normalizing Capacitor Sets upon which we can apply capacitance scaling and

sizing the unit capacitance value for capacitance normalization.

Voltage scaling operations, illustrated in Fig. 11-9, consist in scaling the

output voltage level of each operational amplifier in the circuit to the required

value.

D

F2

A

V

D.k

F2.k

A.k

V/k

V/k i

i

i

i

i

Fig. 11-9: Voltage scaling of an operational amplifier output.

The determination of this value is usually calculated by numerical simulation

of the circuit and may be used to trade-off the dynamic range of the circuit against

capacitance spread and hence the total capacitor area. In order to perform such

voltage scaling the required output voltage level V of each operational amplifier is

calculated and then all the capacitors connected or switched to the associated

output terminal are multiplied by a factor k

i

i = Vi V where V represents the initial

output voltage level.

For the capacitance scaling operation, illustrated in Fig. 11-10, the SC

Structural Evaluator starts by grouping the circuit capacitors into non overlapping

capacitor sets such that the capacitors in the capacitor set Si are those capacitors

11-23

which are connected or switched to the input terminal of operational amplifier i.

Then, for every capacitors set Si , each capacitor is multiplied by a factor

mi =Cµ

Ci,min where Cµ is the adopted unit capacitance value and Ci,min is the

smallest capacitor in the capacitor set Si .

H

G

D

F

E

Cx

(m = C2

D.m

F .m

G.m

C.m

H.m

mCµ

µ/E)2

Fig. 11-10: Capacitance scaling considering E as the minimum capacitance value.

11.5.3 Dimensioning

The last step in the synthesis process consists in the determination of the

capacitance values of the building block by equating its symbolic and numerical

transfer functions. As mentioned before, further constraints must usually be

considered on the capacitance values in order to sizing the final capacitance values.

The constraints criteria are based on structural information generated by the

characterization process. In Fig. 11-11, a flow chart representing the unscaled

dimensioning, as well as the types of constraints considered is represented. In order

to find a first set of unscaled capacitance values the system equates the numerical

and the symbolic transfer functions of the selected building block topology. For the

resulting system of equations the number of extra degrees of freedom, Nextra, is

determined. If the system of equations possesses no extra degrees of freedom, then

the capacitance values are immediately calculated and, if a valid solution is found,

11-24

the numerical netlist of the circuit is produced.

numericalH(z)

computesNextra

cinteg=1Nextra=Nextra-Ncinteg

Cequal or Ccouple-basedconstraints

Nextra=0 ?

N

N

building blocksymbolic

characterization

evaluatecapacitance

values

evaluatecapacitance

values

Valid

[cn]

generatenumerical netlist

constraints=[(1,cinteg)]

End

NEnd

generate numerical netlistconstraints=[(1,cinteg),[cn]]

valid ?

evaluatecapacitance

values

generatenumerical netlist

End

Nextra=0 ?Y

Y

Y

Fig. 11-11: Unscaled dimensioning of a circuit for a target numerical transfer function.

If, on the other hand, the values found are not valid, then a new network

topology must be selected. Whenever extra degrees of freedom are found,

constraints are imposed to the network by pre-setting to unit the Integrating

11-25

Capacitors. Again, if no additional degrees of freedom are found, then the

capacitance values are immediately calculated leading to the generation of the

numerical netlist of the network. The system keeps track of the capacitors that

have been pre-set to unit. If, on the contrary, extra degrees of freedom still need to

be eliminated, then it is necessary to start an interactive process of exploring

additional constraints to be applied. Usually, this is based on such criteria as pre-

setting to unit or to a common value, respectively, the capacitance values pertaining

to the list of coupling capacitors, ccouple, or to the list of those capacitors, cequal,

which, once having set the corresponding capacitance to a common value yield the

application of SC equivalencies. This process usually leads to a set of design

equations from which the capacitance values can be univocally determined. If a

satisfactory solution is obtained, then the numerical netlist of the building block is

automatically generated and a list of the constraints imposed during the unscaled

dimensioning process is produced. If no satisfactory solution is found, then a

message is sent suggesting an alternative network topology should be considered.

11.6 Automatic Synthesis

In this Section we shall present a program for the automatic symbolic

synthesis of SC networks, including those which employ multirate techniques. The

program, Switcake ( Switched capacitor knowledge-based environment), was

implemented in BIM Prolog.

11.6.1 Building Block Knowledge-Base

In the previous section we have described the symbolic characterization that

must be generated for each network topology so that its dimensioning may be

11-26

accomplished in a fully automatic way.

For representing the knowledge automatically generated for the symbolic

characterization of SC networks we have used a frame-based system [14, 15] to

enable keeping the knowledge in a structured way, by defining concepts

characterized by its attributes. Considering the case of SC networks, we have

defined the basic concept, circdesc, represented in Frame 11-1.

Frame: circdesc { netlist: /* supports netlist */ Demons: emptynet actgraph genstruct timeframe: /* supports timeframe */ Demons: emptygraph actztransf gengraph graph: /* supports SFG */ cfeedb: /*suports list of integrating capacitors */ ccouple: /* supports list of coupling capacitors */ cequal: /* supports list of capacitors for SC equivalences */ cinpamp: /* supports list of capacitors for capacitance scaling */ coutpamp: /* supports list of capacitors for voltage scaling */ supertype: symbcirc }

Frame 11-1: Frame circdesc for supporting knowledge related to the symbolic characterization of SC networks

Besides enabling the representation of knowledge in a structured way, frame-

based systems also account for the implementation of Demons, i.e. procedures

which are activated without the explicit influence of the user. In this case, besides

those demons used for maintaining the knowledge-base consistency, two additional

demons, genstruct and gengraph, are defined. While the former is activated once

the netlist of a building block has been introduced, thus immediately generating the

11-27

corresponding structural knowledge, the latter is activated once the time frame has

been edited, and thus generating the corresponding SFG.

By considering the output of the network at different nodes, we obtain

distinct z-domain transfer functions. Hence, we have considered an additional

concept for supporting the network z-domain transfer function, which inherits all

the attributes of the corresponding network characterization, as illustrated in

Frame 11-2.

Frame: symbcirc { isa: circdesc /* inherits the attributes of circdesc */ outnode: /* supports the definition of the output node*/ Demons: genztransf /* generates H(z) */ ztransf: /* supports H(z) */ .. }

Frame 11-2: Frame symbcirc for supporting z-domain transfer function of an SC network.

11.6.2 Working Example 1 - 2nd order lowpass IIR SC decimator

In this first example we consider the design of a 2nd order lowpass SC

decimator, with Chebyshev approximation, maximum passband ripple of 0.05 dB

and cut-off frequency of 6 kHz. For a decimating factor M = 4 the resulting

normalized z-domain transfer function is expressed by

H(z) =

z−1.5 niz− i

i=0

7∑

z−8 − 2. 40z−4 + 1. 52 (11-1)

where the numerical numerator coefficients are given in Table 11-1.

11-28

TABLE 11-1: NUMERATOR COEFFICIENTS FOR THE 2ND ORDER LOWPASS SC DECIMATOR, WITH M = 4.

i 0 1 2 3 4 5 6 7

ni*103 4.83332 13.9711 22.0784 29.2108 27.8761 18.956 10.8368 3.48675

The implementation of the above z-domain transfer function is accomplished

using the optimum SC decimating architecture [16] represented in Fig. 11-12.

d

3e.a.o

e.f.e

e.c.e

1. x

.e 0

2. x

.e

1

3. x

.o

2

4. x

.o

3

4. y

.o

3

3. y

.o

2

2. y

.e

1

1. y

.e

0

4

inp

2

1

inp

b

Fig. 11-12: Basic topology for a 2nd order SC decimator with M = 4.

In Fig. 11-13 we illustrate the knowledge generated during the several steps

in editing the description of the basic topology represented in Fig. 11-12. Once the

netlist of this basic structure is given the corresponding structural characterization

is automatically generated yielding the frame iir2nd represented in the third

column. The next step in the characterization process corresponds to the definition

of the clocking scheme that controls the circuit as well as its output sampling phase.

In this example, the clocking scheme illustrated in Fig. 11-14 with the output

voltage at phase e has been considered. Once this information is given the SFG of

the circuit is automatically generated.

11-29

Operations

Save Timeframe

Edit Timeframe

Edit Netlist

Frame iir2ndDemons

genstruct

gengraph

Save Netlist

netlist: [[tsi,inp,1,1,e,x0],[tsi,inp,1,2,e,x1], [tsi,inp,1,3,o,x2],[tsi,inp,1,4,o,x3], [ampop,1,gnd,2],[capacitor,1,2,d], [tsi,2,3,e,o,a],[tsi,inp,3,4,o,y3], [tsi,inp,3,3,o,y2],[tsi,inp,3,2,e,y1], [tsi,inp,3,1,e,y0],[ampop,3,gnd,4], [capacitor,3,4,b],[switch,4,outp,e], [ofr,4,3,e,o,f],[ofr,4,1,e,o,c]]ccouple: [a,c,f]cequal: nilcfeedb: [b,d]cinpamp: [[c,d,x0,x1,x2,x3], [a,b,f,y0,y1,y2,y3]]coutpamp: [[a,d],[b,c,f]]

timeframe: [8,[2,2,3],[1,4,5],[o,1,4], [e,5,8],[3,0,1],[4,6,7]]

graph: [[(1,2),[[([0] , 0 , [-1])],[([-d] , -4 .0 , [d])]]], [(3,4),[[([0] , 0 , [-1])],[([-b] , -4 .0 , [b])]]], [(inp,1),[[([-x0] , -1 .5 , [0])],[([0] , 0 , [1])]]], [(inp,1),[[([-x1] , -2 .5 , [0])],[([0] , 0 , [1])]]], [(inp,1),[[([-x2] , -3 .5 , [0])],[([0] , 0 , [1])]]], [(inp,1),[[([-x3] , -4 .5 , [0])],[([0] , 0 , [1])]]], [(2,3),[[([-a] , -4 .0 , [0])],[([0] , 0 , [1])]]], [(inp,3),[[([-y3] , -4 .5 , [0])],[([0] , 0 , [1])]]], [(inp,3),[[([-y2] , -3 .5 , [0])],[([0] , 0 , [1])]]], [(inp,3),[[([-y1] , -2 .5 , [0])],[([0] , 0 , [1])]]], [(inp,3),[[([-y0] , -1 .5 , [0])],[([0] , 0 , [1])]]], [(4,3),[[([f] , 0 .0 , [0])],[([0] , 0 , [1])]]], [(4,1),[[([c] , 0 .0 , [0])],[([0] , 0 , [1])]]], [(4,outp),[[([0] , 0 , [1])],[([0] , 0 , [1])]]]]

Fig. 11-13: Representation of the knowledge generated during the editing process for the SC decimating topology represented in Fig. 11-12.

z -1

1

o e

423

0 1 2 3 4 5 6 7 8

Fig. 11-14: Representation of the clocking scheme considered for the SC decimating topology represented in Fig. 11-12.

11-30

Then, by either considering the output signal from node 2 or from node 4, the

symbolic characterization generated during the characterization process of the basic

decimator topology given is illustrated in Fig. 11-15.

Operations Demons

Select output node,no

Save output node,no

genztransf

genztransf

incall: iir2nd outnode: 2 ztransf: [[([(-x3,b)],-8.5e+00),([(-x2,b)],-7.50e+00), ([(-x1,b)],-6.5e+00), ([(-x0,b),] , -5.5e+00), ([(x3,b),(x3,f),(-y3,c)],-4.5e+00), ([(x2,b),(x2,f),(-y2,c)],-3.5e+00), ([(x1,b),(x1,f),(-y1,c)] , -2.50e+00), ([(x0,b),(x0,f),(-y0,c)] , -1.5e+00)], [([(b,d)] , -8.0e+00), ([(-2,b,d),(c,a),(-f,d)] , -4.0e+00), ([(b,d),(f,d)] , 0)]]

Frame iir2nd2

incall: iir2nd outnode: 4 ztransf: [[([(x3,a),(-y3,d)],-8.5e+00), ([(x2,a),(-y2,d)],-7.50e+00), ([(x1,a),(-y1,d)],-6.5e+00), ([(x0,a),(-y0,d)] , -5.5e+00), ([(y3,d)],-4.5e+00), ([(y2,d)],-3.5e+00), ([(y1,d)] , -2.50e+00), ([(y0,d)] ,-1.5e+00)], [([(b,d)] , -8.0e+00), ([(-2,b,d),(c,a),(-f,d)] , -4.0e+00), ([(b,d),(f,d)] , 0)]]

Frame iir2nd4

Frames

Fig. 11-15: Representation of the knowledge generated for the SC decimating topology represented in Fig. 11-12, during the characterization process.

By selecting iir2nd4 and equating the symbolic transfer function to the

numerical transfer function corresponding to the target specifications, we come to

the analysis equations represented in (11-2).

11-31

a.x3-d.y3 = 3.48675e-3 a.x2-d.y2 = 10.8368e-3 a.x1-d.y1 = 18.956e-3 a.x0-d.y0 = 27.8761e-3 d.y3 = 29.2108e-3 d.y2 = 22.0784e-3 dy1 = 13.9711e-3 dy0 = 4.83332e-3 b.d = 1.0 (11-2) -2.b.d + a.c - d.f = -2.4136 b.d + d.f = 1.54561

The existing extra degrees of freedom are automatically eliminated based on

the structural information of the selected topology. For this purpose, the first step in

the elimination of the extra degrees of freedom consists of pre-setting to unit the

integrating capacitors, yielding the system of equations (11-3). a.x3-y3 = 3.48675e-3 a.x2-y2 = 10.8368e-3 a.x1-y1 = 18.956e-3 a.x0-y0 = 27.8761e-3 y3 = 29.2108e-3 y2 = 22.0784e-3 y1 = 13.9711e-3 y0 = 4.83332e-3 (11-3) a.c - f = -0.4136 f = 0.54561

Since this system of equations still possesses an extra degree of freedom, the

coupling capacitor a is also preset to unit yielding the linear system of equations

(11-4) with no extra degrees of freedom. x3-y3 = 3.48675e-3 x2-y2 = 10.8368e-3 x1-y1 = 18.956e-3 x0-y0 = 27.8761e-3 y3 = 29.2108e-3 y2=22.0784e-3 y1 = 13.9711e-3 y0 = 4.83332e-3 (11-4) c - f = -0.136 f = 0.54561

Solving the system of equations (4) leads to the capacitance values shown in

Fig. 11-16a. In order to maximize the dynamic range at the output of the first

operational amplifier, a scaling factor of 5.8 dB is applied to the capacitors

connected at the output of this first operational amplifier thus leading to the

capacitance values in Fig. 11-17a. Finally, a capacitance scaling process is applied

11-32

leading to the values in Fig. 11-17b.

1st operational amplifier

2nd operational amplifier

-40

-30

-20

-10

0

0 4e+04 8e+04 1e+05

(b)

5.8dB

a = b = d =1 c = 1.320012e-1 f = 5.456094e-1 x0= 3.270948e-2 x1= 3.292703e-2 x2= 3.291519e-2 x3= 3.269754e-2 y0= 4.833332e-3 y1= 1.397106e-2 y2= 2.207841e-2 y3= 2.921078e-2

(a)

Fig. 11-16: a) Unscaled capacitance values and b) frequency response obtained after a first-cut sizing of the circuit in Fig. 11-16.

(a) (b)



-40

-30

-20

-10

0

0 4e+04 8e+04 1e+05

a = 1.0734e2 b = 2.0688e2 d = 1.587e1 c = 4.037037 f = 1.12885e2 x0= 1.00297 x1= 1.00702 x2= 1.0066 x3= 1.000 y0= 1.000 y1= 2.89058 y2= 4.5679 y3= 6.094

Fig. 11-17 a) Capacitance values after capacitance scaling. b) Frequency response of the circuit obtained after the final sizing of the circuit of Fig. 11-12.

11-33

11.6.5 Working Example 2 - Lowpass-notch SC biquad

This second example deals with the design of an SC biquad section with a

notch frequency at fz = 1800 Hz, a pole Q-factor of Qp = 30 at fp = 1700 Hz and

0 dB DC gain. Here, our first objective is concerned with the characterization

process of the basic structure whereby we illustrate that the various SC elements of

the circuit can be recognized even though a minimum switch configuration has

been used.

inps e

o

o

e

G

H

e

o

D

o

e

A

I

J

B

E

e

oC

F1 3

2

4

5

6 7

8

10

9

outp

o

ee

Fig. 11-18: SC Biquad for realizing a lowpass-notch filtering function.

The second purpose is concerned with the dimensioning process and is

related to the removal, based on SC capacitor equivalencies, of extra degrees of

freedom in the analysis equations.

The given specifications yield the z-domain transfer function

H(z) =

0.089093 −1.774911.z −1 + 0.089093. z−2

1−1.99029.z−1 + 0.99723.z −2 (11-5)

11-34

which can be implemented using the SC biquad section [12] represented in Fig. 11-18.

Once the netlist of this basic structure is given the corresponding structural

characterization is automatically generated, thus yielding the frame biquad

represented in Frame 11-3. Frame: biquad { inst :circdesc /* biquad is an instance of circedesc*/ netlist: [[switch,inps,1,e],[switch,1,gnd,o],[capacitor,1,3,G],..]; graph: ... cfeedb: [B,D] /* list of integrating capacitors */ ccouple: [A,C,E] /* list of coupling capacitors */ cequal: [[ I,J],[G,H]] /* list of capacitors for SC equivalences */ cinpamp:[[C,D,E,G,H],[A,B,F,I,J]] /* capacitance scaling */ coutpamp:[[A,D],[B,C,F,E]] /* voltage scaling */ ... }

Frame 11-3: Instance of circdesc supporting the caracterization of the biquad represented in Fig. 11-18.

From this basic structure, the characterization process generates all the

symbolic information for the possible structures that may be obtained by selecting

either E- or F-damping and, for each of them, considering the output from either the

first or the second operational amplifier. Thus, we now proceed to the

dimensioning process considering an E-damping biquad with the output taken from

the second operational amplifier. By equating the numerical transfer function in

(11-5) to the symbolic transfer function generated automatically [17] we come to

the analysis equations (11-6).

D.I = 0.89093 A.G-D.I-D.J = 1.774911 D.J-A.H = 0.89093

11-35

A.C+A.E-2.B.D = -1.99029 D.B = 1.0 D.B-A.E = 0.99723 (11-6)

By pre-setting to unit the integrating capacitors we obtain equations (11-7). I = 0.89093 A.G-I-J = 1.774911 J-A.H = 0.89093 A.C+A.E = 9.71e-3 A.E = 2.77e-3 (11-7)

Since the system still shows extra degrees of freedom, capacitor J is made

equal to I, so that the previously referred SC equivalence is applied and yielding

equations (11-8). I = 0.89093 A.G-2.I = 1.774911 I-A.H = 0.89093 A.C+A.E = 9.71e-3 A.E = 2.77e-3 (11-8)

The final degree of freedom is removed based on the coupling capacitors, i.e.

by pre-setting to unit capacitor A, and thus leading to equations (11-9). I = 0.89093 G-2.I = 1.774911 I-H = 0.89093 C+E = 9.71e-3 E = 2.77e-3 (11-9)

11-36

A=B=D=1.0

C=0.00694

E=0.00277

G=0.00694

I=J=0.89093

a) b)

-120

-80

-40

0

0 8.0e+02 2.0e+03 2.4e+03



11.5dB

Fig. 11-19: a) Unscaled capacitance values and b) frequency response of the resulting SC biquad.

The first set of values obtained from this last system of equations is shown in

Fig. 11-19a. From the frequency response obtained at the output of both operational

amplifiers we may conclude that a scaling factor of 11.5 dB should be applied to

the capacitors connected at the output of the first operational amplifier. The final

capacitance values obtained after capacitance scaling as well as the frequency

response of the circuit are represented, respectively, in Fig. 11-20a and in

Fig. 11-20b.

b)

-90

-70

-50

-30

-10

10

30

0.0e+00 1.0e+03 2.0e+03

A=1.0

D=29.9613

B=12.0365

C=2.5035

E=1.0

G=2.5035

I=J=10.7238

a)



Fig. 11-20: a) Capacitance values after capacitance scaling. b) Frequency response of the final biquad.

11.6.6 Working Example 3 - 3rd order ladder-based lowpass SC

decimator

In this example we shall consider the design of a 3rd order lowpass SC

decimator with Chebyshev approximation, nominal cutoff frequency of 3.6 MHz

11-37

and 0.25 dB maximum ripple in the passband. For a decimating factor M = 2 the

specifications given yield the z-domain transfer function

H(z) =0.064237z−1 + 0.150366z−2 + 0.125776z−3 + 0.036921z−4

3.0270359 − 4.732152z−2 + 3.459719z−4 − z−6 (11-10)

which is implemented using the ladder-based SC decimator, with a decimating

factor M = 2 [18], represented in Fig. 11-21.

inp

0.2x

.0.

2x .

b10

10

1.2x

.1.

2x .

b11

11

1.2x

.1.

2x .

b21

21

0.x

.b

30

0.x

.b

20

b.c .ao2 a.c .bo2

b.c .bo1 b.c .bo3

c1

l2

c3

b.c

.b l

b.c

.b s

1

2 3

4 5

6

OP1

OP2 O

P3

Fig.11-21: 3rd order ladder-based SC decimator with a decimating factor of 2.

Once the netlist of this basic structure is given the corresponding structural

characterization is automatically generated, yielding the decladder frame

represented in Frame 11-4.

A B

1 0 1

Fig. 11-22: Representation of the clocking scheme considered for the SC decimating structure of Fig. 11-21.

11-38

Frame: decladder { inst :circdesc /* decladder is an instance of circdesc*/ netlist: [pctsc,inp,1,0,b,b,x10],[ampop,1,gnd,2],[capacitor,1,2,c1],..] timeframe: ..... graph: ... cfeedb: [c1,c3,l2] /* list of integrating capacitors */ ccouple: [cl,co1,co2,co3,cs] /* list of coupling capacitors */ cequal: [] /* list of capacitors for SC equivalences */ cinpamp:[[c1,co1,cs,x10,x11],[co2,l2,x20,x21], [c3,cl,co3,x30]]) /* capacitance scaling */ coutpamp:[[c1,co2,cs],[co1,co3,l2],[c3,cl,co2]]/* voltage scaling */ .... }

Frame 11-4: Instance of circdesc supporting the caracterization of the ladder-based SC decimator represented in Fig. 11-21.

For the clocking scheme represented in Fig. 11-22 and considering the output

of the circuit at the output of op3 we arrive at the symbolic z-domain transfer

function

H(z) =ni.z

−i

i=o

4∑

d2.i .z−i

i =0

3∑

(11-11)

where the symbolic expressions of the numerator coefficients are

n4 =x30.c1.l2

n3 =-x11.co2.co3+x21.co3.c1

n2 = -x10.co2.co3+x20.co3.c1-x30.c1.l2-x30.c1.l2-x30.cs.l2+x30.co1.co2

n1 = -x21.co3.c1-x21.co3.cs (11-12)

n0 = -x20.co3.c1-x20.co3.cs+x30.c1.l2+x30.cs.l2

11-39

and the symbolic expressions of the denominator coefficients are

d6 = -c3.c1.l2

d4 = c3.c1.l2+c3.c1.l2+c3.c1.l2+cs.l2.c3-co1.co2.c3-

co2.co3.c1+cl.l2.c1 (11-13)

d2 = -c3.c1.l2-c3.c1.l2-c3.c1.l2-cs.l2.c3+co1.co2.c3-cs.l2.c3

+co2.co3.c1-cl.l2.c1-cl.l2.c1+cs.co2.co3-cs.cl.l2+co1.co2.cl

d0 = c3.c1.l2+cs.l2.c3+cl.l2.c1+cs.cl.l2

By equating the symbolic transfer function to the numerical H(z) in (11-10) we obtain the system of equations represented in (11-14).

x30.c1.l2 =0.036921

-x11.co2.co3+x21.co3.c1=0.125776

-x10.co2.co3+x20.co3.c1-x30.c1.l2-x30.c1.l2-x30.cs.l2+x30.co1.co2 =0.150366

-x21.co3.c1-x21.co3.cs = 0.064237

-x20.co3.c1-x20.co3.cs+x30.c1.l2+x30.cs.l2 =0 (11-14)

-c3.c1.l2 = -1

c3.c1.l2+c3.c1.l2+c3.c1.l2+cs.l2.c3-co1.co2.c3-co2.co3.c1+cl.l2.c1= 3.459719

-c3.c1.l2-c3.c1.l2-c3.c1.l2-cs.l2.c3+co1.co2.c3-cs.l2.c3+co2.co3.c1-cl.l2.c1-cl.l2.c1

+cs.co2.co3-cs.cl.l2+co1.co2.cl = -4.732152

c3.c1.l2+cs.l2.c3+cl.l2.c1+cs.cl.l2 = 3.0270359

By pre-setting to unit the integrating capacitors and the coupling capacitors co3 and cs1 we obtain the equations in (11-15).

-x11.co2+x21 =0.125776

-x10.co2+x20-3.x30+x30.co1.co2 =0.150366

-2.x21.co3 = 0.064237 (11-15)

-2.x20+2.x30 =0

11-40

4-co1.co2-co2+cl= 3.459719

-5+co1.co2+2.co2-3.cl+co1.co2.cl = 0.267848 2.cl = 1.0270359

Among all the coupling capacitors of the circuit, co3 and cs1 were selected,

for these are the ones which, once pre-set to unit, lead to a system of equations with

less terms containing products of variables.

Solving the design equations (11-15) lead us to the capacitance values shown

in Fig. 11-23a.

2.X11=-0.719702 2.X10=-0.918464 2.X21=-0.642374 X20= 0.0369215 X30= 0.0369215 Co1= 1.40100 Co2= 0.43878 Co3= 1.0 Cl3= 0.513518 Cs1= 1.0 C1 = 1.0 L2 = 1.0 C3 = 1.0

a) b)

3rd operational amplifier



-50

-40

-30

-20

-10

0

0 9.0e+06 1.8e+07

Fig. 11-23 a) Unscaled capacitance values and b) frequency response of the resulting circuit.

From this first dimensioning we then apply a scaling factor of 0.4733dB to

the capacitors connected at the output of the second operational amplifier and a

scaling factor of 2.7982 dB at the output of the first operational amplifier. The final

capacitance values obtained after admittance scaling as well as the frequency

response of the circuit obtained are represented, respectively, in Fig. 11-24a and

Fig. 11-24b.

11-41

11.7 Conclusions

In this chapter we addressed the application of symbolic SFG computational

techniques for the analysis and synthesis of SC networks. Firstly, we described the

rule-based implementation of the pattern matching technique adopted for

generating the SFG representation of an SC network. Then, we discussed the

corresponding SFG-based analysis and described the use of symbolic analyzers for

carrying out step-by-step synthesis procedures as well as the automatic synthesis

of SC networks. In particular, we discussed the knowledge generated during both

the analysis and dimensioning processes and presented a frame-based

implementation of the system knowledge-base for capturing such knowledge.

Various working examples were presented to illustrate the techniques and

methodologies described throughout this chapter.

b)

3rd operational amplifier



-50

-40

-30

-20

-10

0 9.0e+06 1.8e+07

2.X11=-1.0 2.X10=-1.276172 2.X21=-1.739837 X20= 1.0 X30= 1.0 Co1= 2.055650 Co2=11.884132 C´o2=16.401283 Co3= 28.60122 Cl3= 13.90837 Cs1= 1.917599 C1 =1.9175992 L2= 28.601221 C3= 27.084490

a)

Fig. 11-24: a) Final Capacitance values. b) Frequency response of the final ladder-based SC decimator.

11-42

References [1] F. Fernandez, A. Rodriguez-Vazquez, J. L. Huertas, "Interactive AC

Modeling and Characterization of Analog Circuits via Symbolic Analysis", Analog Integrated Circuits and Signal Processing, Vol. 1, pp. 183-208, November 1991.

[2] G. Gielen, "Symbolic Analysis Methods and Applications- An Overview",

Proc. IEEE ISCAS´1992, pp. 1141-1144, San Diego, USA, May 1993. [3] L. P. Huelsman, "Applications of Symbolic Analysis to Analog System

Design", Proc. IEEE ISCAS´1992, pp. 1165-1168, San Diego, USA, May 1993.

[4] G.Szentirmai, "S/Filsyn Quick Reference Manual", April 1983. [5] U. W. Brugger and G. S. Moschytz, "SFG Analysis of SC Networks

Comprising Integrators", Proc. IEEE ISCAS´1983, pp. 68-71, Newport Beach, USA, May 1983.

[6] G. S. Moschytz and U. W. Brugger, "Signal-Flow Graph Analysis of SC

Networks", IEE Proc., Pt.G, Vol. 131, No. 2, pp. 72-85, April 1984. [7] J. E. Franca, Switched-Capacitor Systems for Narrow Bandpass Filtering,

Ph.D. Dissertation, London, 1985. [8] K. R. Laker, "Equivalent Circuits for the Analysis and Synthesis of

Switched-Capacitor Networks", Bell System Technical Journal, Vol. 58, No.3, pp. 729-769, March 1979.

[9] L. Sterling and E. Shapiro, The Art of Prolog: Advanced Programming

Techniques, edited by E. Shapiro, MIT Press Series in Logic Programming, London, 1986.

[10] S. J. Mason, "Feedback Theory - Some Properties of Signal Flow Graphs",

Proc. IRE, Vol. 41, pp. 114-1156, September 1953. [11] J. E. Franca and S. Santos, "FIR Switched-Capacitor Decimators with

Active-Delayed Block Polyphase Structures", IEEE Transactions on Circuits and Systems, Vol. CAS-35, No.8, pp. 1033-1037, August 1988.

[12] P. E. Fleisher and K. R. Laker, "A Family of Active Switched Capacitor

Biquad Building Blocks", Bell System Technical Journal, Vol. 58, No.10, pp. 2235-2268, December 1979.

[13] M. H. Fino-Martins, J. E. Franca, A. Steiger-Garção, "A Computer-Aided

11-44

Tool for the Automatic Generation of Design Equations of Switched Capacitor Circuits", Proc. ECCTD'93, pp. 1705-1710, Davos, Switzerland, September 93.

[14] M. Minsky, "A Framework for Representing Knowledge", in Psychology of

Computer Vision , Ed. McGraw-Hill, New York, 1975, pp. 211-277. [15] L. Seabra-Lopes, "Golog: A Prolog Object Manager" (in portuguese),

Electrotechnical Department , F.C.T, New University of Lisbon, April 1993. [16] J. E. Franca and R. P. Martins, "IIR Switched-Capacitor Decimator Building

Blocks with Optimum Implementation", IEEE Transactions on Circuits and Systems, Vol. CAS-37 , No. 1, pp. 81-90, January 1990.

[17] M. H. Fino-Martins, J. E. Franca, A. Steiger-Garção, "Towards High-Level

Synthesis of Mixed-Signal Analog-Digital ASICs", in Analog-Digital ASICs- circuit techniques, design tools and applications , edited by R.S.Soin, F. Maloberti, J. Franca, Peter Peregrinus Lda., 1991.

[18] P. Santos, J. E. Franca, J. Martins, "Synthesis of Optimum Switched-

Capacitor State-Space Decimators", Proc. ECCTD'93, pp. 935-940, Davos, Switzerland, September 93.

11-45

chapter11: symbolic signal flow graph methods in...

Documents