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    EE415 VLSI Design

    ManufacturingManufacturingProcessProcess

    [Adapted f rom RabaeysDigital Integrated Circuits , 2002, J. Rabaeyet al.and presentation by J.Christiansen/CERN]

    EE415 VLSI Design

    Fabrication

    WafersProcessing

    Processed

    Wafer

    Chips

    Masks

    EE415 VLSI Design

    Traditional CMOS Process

    EE415 VLSI Design

    A Modern CMOS Process

    p-

    p-epi

    p well n well

    p+n+

    gate oxide

    Al (Cu)

    tungsten

    SiO2

    SiO2

    TiSi2

    Dual-Well Trench-Isolated CMOS

    field oxide

    EE415 VLSI Design

    oxidation

    optical

    mask

    process

    step

    photoresistcoatingphotoresistremoval (ashi ng)

    spin, rinse, dryacid etch

    photoresist

    stepper exposure

    development

    Typical operations in a single

    photolithographic cycle (from [Fullman]).

    Photo-Lithographic Process

    EE415 VLSI Design

    Growing the Silicon Ingot

    From Smithsonian, 2000

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    EE415 VLSI Design

    Patterning - Photolithography

    1. Oxidation

    2. Photoresist (PR) coating

    3. Stepper exposure4. Photoresist development and

    bake

    5. Acid etchingUnexposed (negative PR)Exposed (positive PR)

    6. Spin, rinse, and dry

    7. Processing stepIon implantationPlasma etchingMetal deposition

    8. Photoresist removal (ashing)

    mask

    SiO2 PR

    UV light

    EE415 VLSI Design

    CMOS Process at a Glance

    Define active areas

    Etch and fill trenches

    Implant well regions

    Deposit and patternpolysilicon layer

    Implant source and drainregions and substrate contacts

    Create contact and via windowsDeposit and pattern metal layers

    l One full photolithography

    sequence per layer

    (mask)l Built (roughly) from the

    bottom up

    5 metal 2

    4 metal 1

    2 polysilicon

    3 source and drain

    diffusions

    1 tubs (aka wells,active areas)

    exception!

    EE415 VLSI Design

    Example of Patterning of SiO2

    Si-substrate

    Silicon base material

    Si-substrate

    3. Stepper exposure

    UV-light

    Patternedoptical mask

    Exposed resist

    1&2. After oxidation and

    deposition of negativephotoresist

    PhotoresistSiO2

    Si-substrate

    Si-substrate

    SiO2

    8. Final result after

    removal of resist

    Si-substrate

    SiO2

    5. After etching

    Hardened resist

    SiO2

    Si-substrate

    4. After development and

    etching of resist, chemical orplasma etch of SiO

    2

    Hardened resist

    Chemical or plasmaetch

    EE415 VLSI Design

    Diffusion and IonImplantation

    1. Area to be doped is

    exposed

    (photolithography)

    2. Dif fusion

    or

    Ion implantation

    EE415 VLSI Design

    Deposition and Etching

    1. Pattern masking(photolithography)

    2. Deposit material over

    entire waferCVD (Si3N4)chemical deposition

    (polysilicon)sputtering (Al)

    3. Etch away unwanted

    materialwet etching

    dry (plasma) etchingEE415 VLSI Design

    Planarization: Polishing theWafers

    From Smithsonian, 2000

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    EE415 VLSI Design

    Self-Aligned Gates

    1. Create thin oxide inthe active regions,thick elsewhere

    2. Deposit polysilicon

    3. Etch thin oxide fromactive region (polyacts as a mask for thediffusion)

    4. Implant dopant

    EE415 VLSI Design

    Simplified CMOS InverterP-well Process

    cut line

    p well

    EE415 VLSI Design

    P-Well Mask

    EE415 VLSI Design

    Active Mask

    EE415 VLSI Design

    Poly Mask

    EE415 VLSI Design

    P+ Select Mask

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    EE415 VLSI Design

    N+ Select Mask

    EE415 VLSI Design

    Contact Mask

    EE415 VLSI Design

    Metal Mask

    EE415 VLSI Design

    VLSI Fabrication: The Cycle

    EE415 VLSI Design

    l The n -well CMOS process starts with a

    moderately doped (impurity concentrationless than 1015 cm -3) p-type siliconsubstrate.

    l Then, an oxide layer is grown on theentire surface. The first lithographic maskdefines the n-well region. Donor atoms,usually phosphorus, are implantedthrough this window in the oxide. Thisdefines, the active areas of the nMOS andpMOS transistors.

    l Thin gate oxide is grown on top of theactive regions. The thickness and thequality of the gate oxide are criticalfabrication parameters, since they affectthe characteristics of the MOS transistor,and its reliability.

    CMOS N-well Process (contd)

    EE415 VLSI Design

    CMOS N-well Process (contd)

    l The polysilicon layer isdeposited using chemical

    vapor deposition (CVD) andpatterned by dry (plasma)etching.

    l The created polysilicon lineswill function as the gateelectrodes of the nMOS and the

    pMOS transistors and theirinterconnects.

    l Also, the polysilicon gates act

    as self-aligned masks for thesource and drain implantationsthat follow this step.

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    EE415 VLSI Design

    CMOS N-well Process (contd)

    l Using a set of two masks, then+ and p+ regions are

    implanted into the substrateand into the n- well,respectively.

    l The ohmic contacts to thesubstrate and to the n-well areimplanted in this process step.

    EE415 VLSI Design

    CMOS N-well Process (contd)

    l An insulating silicon dioxidelayer is deposited over the

    entire wafer usingCVD.

    l Then, the contacts are definedand etched away to expose the

    silicon or polysilicon contactwindows.

    EE415 VLSI Design

    CMOS N-well Process (contd)

    l Metal is deposited over theentire chip surface usingmetal

    evaporation, and the metal linesare patterned through etching.

    l Since the wafer surface is non-

    planar, the quality and theintegrity of the metal linescreated in this step are very

    critical and are essential forcircuit reliability.

    EE415 VLSI Design

    CMOS N-well Process (contd)

    l The composite layout and theresulting cross-sectional view of

    the chip, showing one nMOSand one pMOS transistor (built-in n-well), the polysilicon and

    metal interconnections.

    l The final step is to deposit thepassivation layer(overglass -

    for protection) over the chip,except for wire-bonding pad

    areas.

    EE415 VLSI Design

    Advanced Metallization

    EE415 VLSI Design

    From Design to Reality

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    EE415 VLSI Design

    Design

    Rules

    EE415 VLSI Design

    CMOS Process LayersLayer

    Polysilicon

    Metal1

    Metal2

    Contact To Poly

    Contact To Diffusion

    Via

    Well (p,n)

    Active Area (n+,p+)

    Color Representation

    Yellow

    Green

    Red

    Blue

    Magenta

    Black

    Black

    Black

    Select (p+,n+) Green

    EE415 VLSI Design

    Layers in 0.25 mCMOS process

    EE415 VLSI Design

    Design Rules

    l Interface between the circuit designer and process

    engineer

    l Guidelines for constructing process masks

    l Unit dimension: minimum line width

    scalable design rules: lambda parameter

    absolute dimensions: micron rules

    l Rules constructed to ensure that design works even

    when small fab errors (within some tolerance) occur

    l A complete set includes

    set of layers

    intra-layer: relat ions between objects in the same layer

    inter-layer: relations between objects on different layers

    EE415 VLSI Design

    3D Perspective

    Polysilicon Aluminum

    EE415 VLSI Design

    Why Have Design Rules?

    l To be able to tolerate some level of fabricationerrors such as

    1. Mask misalignment

    2. Dust

    3. Process parameters

    (e.g., lateral diffusion)

    4. Rough surfaces

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    EE415 VLSI Design

    Intra-Layer Design RuleOrigins

    l Minimum dimensions (e.g., widths) of objects on each

    layer to maintain that object after fab minimum line width is set by the resolution of the

    patterning process (photolithography)

    l Minimum spaces between objects (that are not

    related) on the same layer to ensure they will not

    short after fab

    0.3 micron

    0.3 micron

    0.15

    0.15

    EE415 VLSI Design

    Inter-Layer Design RuleOrigins

    1. Transistor rules transistor formed by

    overlap of active and poly layers

    Transistors

    Catastrophicerror

    Unrelated Poly & Diffusion

    Thinner diffusion,but still working

    EE415 VLSI Design

    Inter-Layer Design RuleOrigins, Cont

    2. Contact and via rules

    M1 contact to p-diffusion

    M1 contact to poly

    Mx contact to My

    Contact Mask

    Via Masks

    0.3

    0.14

    both materialsmask misaligned

    M1 contact to n-diffusion

    Contact: 0.44 x 0.44

    EE415 VLSI Design

    Intra-Layer Design Rules

    Metal2

    4

    3

    10

    90

    Well

    Active

    3

    3

    Polysilicon

    2

    2

    Different PotentialSame Potential

    Metal13

    3

    2

    Contactor Via

    Select

    2

    or6

    2Hole

    EE415 VLSI Design

    Transistor Layout

    1

    2

    5

    3

    Transistor

    EE415 VLSI Design

    Vias and Contacts

    1

    2

    1

    Via

    Metal toPoly ContactMetal to

    Active Contact