charge-trap memories with high-k control...

G. Molas 1Workshop on Innovative Memory Technologies – June 24 th 2009

Charge-trap memories with high-k control dielectrics

Gabriel Molas

CEA-LETI MINATECAdvanced Memory Technology

[email protected]


Outline

• Context • Charge trap memories with high-k

control dielectrics• Modelling and simulation• Conclusions


9-109-109-109-1010-1310-1310-1310-1310-13Interpolythickness [nm]

High-kHigh-kHigh-kHigh-kONOONOONOONOONOFloating gateNAND Interpoly

CT-3DCT-3DCT-3DCTCTFG/CTFGFGFGCell type

202225283236404551NAND Flash Technology [nm]

201520142013201220112010200920082007Year of production

ITRS 2007 envisages High-k interpoly combined with cha rge trapping (CT) layers for sub-30nm nodes to maintain hig hcoupling ratio and good reliability

Context – TANOS NAND

TANOS 40nm SAMSUNG IEDM’06, VLSI’06TANOS 63nm SAMSUNG IEDM’05

�� Samsung TANOS (TaN / Al 2O3 / Si3N4 / SiO2 / Si) memory envisagedfor sub-30 nm (resistance to SILC, low cell to cell X c oupling…)


Context - Embedded charge traps1T SONOS + high-k dielectrics Split gate SONOS

Reduction of the programming consumption

(SSI instead of CHE)Reduction of the programming

voltages (high-k tunox and topox)

LETI program in progress

R. v. Schaijk, NVSMW 2006, NXP

Nitride charge trap memory

Patent US 2008/0290401, K. YASUI et al., Nov. 2008, RENESAS

AG

MG

AG

MG

LETI program in progress


Outline• Context • Charge trap memories with high-k

control dielectrics– High-k Control dielectric optimization– Nitride thickness– Metal gate

• Modelling and simulation• Conclusions


High-k Control dielectric

Comparison of various gate types on the erasing characteristics

Optimization of charge trap memories

- Study of various high-k materials- Introduction of a SiO 2interlayer

Impact of the nitride thickness on the memory retention

50nm

16nm

5.5nm

3.5nm

SANOS-like memories

Al2O3

Si3N4

SiO2

Nitride thickness

Control gate


Eg = -0.8276 [Hf] + 6.4461

4.5

5

5.5

6

6.5

7

0 0.2 0.4 0.6 0.8 1

Hf fraction

Opt

ical

Ban

dgap

[eV

]

Al2O3 HfO2

Bandgap:HfO2 < HfAlO < Al 2O3

High-k control dielectrics - HfAlOHfO2, Al2O3, and HfAlO deposited by ALCVD (H2O, TMA and HfCl 4 precursors) in ASM PULSAR 2000 tool ��used as control dielectrics

10-7 10-6 10-5 10-4 10-3 10-2 10-1 1000

1

2

3

4

5

6

∆∆ ∆∆VT [V

]

Stress Time [s]

VG: 10V��14V

HfO2

HfAlOAl 2O3

Programming speed:HfO2 > HfAlO > Al 2O3

Tuning the memory characteristics with the Hf:Al ratio


High-k control dielectrics - HTO / Al 2O3 bilayer

102 104 106 10880%

90%

100%

Al2O3 EOT 16nm => 6.6nm 20nm => 8.2nm

HTO/Al2O3 EOT 4/8 nm => 7.3nm

∆∆ ∆∆VT/ ∆∆ ∆∆

VT

,t=0s

[-]

Retention time [s]

SiO2

Poly-Si

Al 2O3

Si3N4

HTO

Al 2O3

Al 2O3

HTO

SANOS

SAONOS

Same EOT

• HTO/Al2O3 bilayers enable improved retention for the same EOT (so with no degradation of the programming voltages) M. Bocquet et al., SSE 2009


20 24 28 32 36 40100

101

102

103

104

105 Si3N

4

3nm 6nm 10nm

Life

Tim

e (@

∆∆ ∆∆VT / ∆∆ ∆∆

VT

prog

=95

%)

1/kT [1/eV]

Nitride layer

Thick Si 3N4 �� Better retention

Impact of the nitride thickness

Nitride thickness mostly impacts the retention at R T:

101 102 103 104 105 106 107 10870

80

90

100

∆∆ ∆∆VT / ∆∆ ∆∆

VT

init [%

]

Retention Time [s]

Si3N

4:

3nm 6nm 10nm

T=25°C

Same retention behavior at high temperature

RT°: difference

data retention

Si3N

4

3nm 6nm 10nm

HT°: no difference

M. Bocquet et al., IMW 2009


Impact of the control gate on erasing

10-6 10-5 10-4 10-3 10-2 10-1 1000

1

2

3

4

VG=-18V

VG=-12V

Blocking Oxide:HTO / Al2O3

VT -

VTo

[V]

Stress time [s]

Poly N+

Poly P+

Same speed between P+/N+ poly-Si gate

Poly - SiN+ / P+

Si3N4

SiO2

6nm

2.5nm

HTO

Al2O3 8nm

5nm

VT saturation appears for N+ type gate at high voltage s

P+ poly-Si gate: limited erase saturation

e-

h+

ControlGate

M. Bocquet et al., ESSDERC 2008


Metal gateCollaboration with Aixtron

Deposition of TaN and TaAlN gates (AVD ®) on “ANOS” stacks

Midgap metal gates reduce erase saturation with respect to N+ gates


Outline• Context • Charge traps memories with high-k

control dielectrics• Modelling and simulation

– Nitride ab-initio– Device physical modelling– Device TCAD simulation

• Conclusions


Ab-initio: SiN Band-gap calculations

β phase

•Consideration of defects: N and Si vacancies, saturated with H species (measured by MIR) � Are the defects electrically active (e- energy states in the gap)?

Objectives:

Study of the origin of charge trapping in SiN layers

E. Vianello, P. Blaise et al.


x VG

program Vprogram V GG>>0>>0

retention Vretention V GG=0=0

(1)

(1) Tunnel-In (FN, DT, mFN, B-T)

(2)

(2)

(2) Electron transport + capture/emission

(3)

(3) (3)

(3) Tunnel-Out

x

J in

Jout

Jout

Jout

Device physical modellingPoly-Si

SiO2

Si3N4

Al 2O3

[E. Vianello, ESSDERC 2008]

• Motion of electrons in SiN:Drift-Diffusion

•Interaction between the electrons in the CB and in the energy gap

••Emission rateEmission rate (Poole-Frenkel)


Jout Joute-

JoutJout

Si GateAl 2O3SiO2 Si3N4

e-

Thermal emission in Si 3N4

Trapped charge redistributionT=250°C

Immediately After programming

During retention0

2x1019

4x1019

0 3 60

2x1019

4x1019

Trapped chargedensity [1/cm 3]

T=250°C

T=250°C

Nitride thickness [nm]

Si GateAl 2O3SiO2 Si3N4

0 3 60

Nitride thickness [nm]

Quick migration to SiO 2 and Al 2O3 interfaces

0

2x1019

4x1019

Trapped chargedensity [1/cm 3]

T=250°C

Trapped charge density [1/cm 3]

Retention at high temperature: Nitride charge distribution

Small retention difference between thin and thick S iN

M. Bocquet et al., IMW 2009


In programming mode: Vg1=1V: Id limited by the conduction in the access transistor (weak inversion). Low consumption. Vmg=9V: generates the vertical electric field for S SI

TCAD: SONOS Split gate architectures

AG

MG

AG

MG

0 1 2 3 4 51E-3

0.01

0.1

1

10

100

1000

Vd=5VVg2= 0V 2V 4V 6V 8V 10V

Dra

in C

urre

nt Id

[uA

/um

]

Access Gate Voltage Vg1 [V]

Memory gate bias ↑↑↑↑

LETI program in collaboration with STM

Simulated structure defined using Synopsis tool

E. Nowak et al.


Outline• Context • Charge traps memories with high-k

control dielectrics• Modelling and simulation• Conclusions


Conclusions 1/2Charge trap memories with high-k control dielectrics

� Coupling ratio ( εεεε): good PE speed with Hf-rich samples

� Insulating capabilities: high bandgap, low E A with Al-rich samples

� Thermal stability (crystallization T°): increases w ith %Hf

High-k control dielectrics engineering of SANOSHfAlO: by tuning the Hf/Al concentration of HfAlO al loys, a good compromise can be achieved in terms of:

Impact of nitride thickness on retentionRetention at room temperature increases with SiN thi cknessThickness dependance disappears at high temperatures

Improvement of SANOS memory retention by using a HT O/Al2O3control dielectrics double layer

Impact of control gate on erasingMetal (TiN, TaN, TaAlN) an P+ control gates reduce erase saturation at high voltages


Physical modelling of nitride memories based on drift diffusion in nitride�� Quantitative description of the charge redistributi on in nitride at high temperature during retention

Conclusions 2/2Modelling and simulations

Ab-initio simulations of nitride layers (DFT, GW)�� Evaluation of the intrinsic properties of nitride (ban dgap, impacts of defects on electrical traps…)�� Simulation hypotheses based on physical and morphological characterisation of nitride layers

TCAD simulations allow to evaluate the potentiality of new architectures�� Reduced consumption in SONOS split gate memories in comparison with 1T architectures


Acknowledgments

B. De Salvo (leader of the advanced memory activity), M. Bocquet, E. Vianello, J. P. Colonna, M. Gély, E. Nowak, L.

Perniola, H. Grampeix, P. Blaise, P. Brianceau, F. Martin, C. Licitra, N. Rochat, E. Martinez, A. M. Papon, H. Dansas, P. Besson, P.

Scheiblin, V. Vidal, A. Toffoli, R. Kies, G. Ghibau do, G. Pananakakis, O. Boissière…

CEA-LETI – MINATEC Grenoble, France

CNRS – IMEP Grenoble, France

LETI cleanroom facilities

Aixtron, USA

IU.NET, Udine, Italy

charge-trap memories with high-k control...

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