Fraunhofer Center

Nanoelectronic Technologies

Königsbrücker Str. 180

01099 Dresden

contact

Sascha Bott

phone +49 351 2607 3035

sascha.bott@cnt.fraunhofer.de

Boris Vasilev

phone +49 351 2607 3017

boris.vasilev@cnt.fraunhofer.de

www.cnt.fraunhofer.de

ChemiCal-meChaniCal Planarization (CmP) - ProCess and simulation

task definition

Highly integrated circuits, like logic and me-

mory chips, consist of many material layers.

In the course of manufacturing the surfaces

have to be planarized over and over again to

obtain sufficient process windows for critical

processes like lithography and etching. Fur-

thermore planarization ensures defined sizes

of the structures, thus in the end reliable

functioning of the electronic elements. The

chemical-mechanical planarization (CMP) is

the state of the art to reach the necessary

planarization.

The continuous shrinking in the semicon-

ductor technology goes along with a higher

demand for accuracy, as well as a higher

number of materials used. Therefore it is

rather necessary to understand the various

CMP processes and to develop novel pro-

cesses for newly introduced materials to be

able to fulfill the demands of the coming

technology nodes.

This enables certain integration paths with

tailored CMP processes. The transformation

of the company structures in the chip pro-

duction like the foundry business with its

short time to market and product lifetime

of chip generations, need well synchronized

processes and designs. Therefore a CMP-suit-

able design becomes more and more crucial

to be capable of competing on the market.

methodology

Besides the development of planarization

processes for certain materials, especially

the planarization behavior of patterned wa-

fers is in the focus of research. Thereby the

influence of the structural parameters and

consumables on the topology evolution is

systematically examined and modeled using

specifically developed CMP test-wafers and

analysis routines. The obtained knowledge

can be used for process control and optimi-

zation in industrial production.

1 CMP test-layout with variation of

pattern density

2 Calculated pad-wafer-distance during

planarization for a CMP test-layout

F R A U N H O F E R C E N T E R N A N O E l E C T R O N i C T E C H N O l O g i E s

1 2

3

advantages

• Extensive experience in the field of

process characterization and modeling

• Provision of CMP models and support

with simulation studies

• Access to flexible CMP systems up to

300 mm wafer size for research and

deve lopment

• Industry established 300-mm-CMP-system

for efficient portability into large-scale

production

• Nearby location and cooperation with

semiconductor manufacturers and

research institutions in Silicon Saxony

applications

• Characterization, modeling and

simulation of the planarization behavior

of patterned wafers

• Fundamental tribological characterization

including parameter extraction

• CMP process development and –optimi-

zation, design for manufacturing strategy

development with semiconductor

product manufacturers

• Development and qualification of CMP

consumables, e.g. polishing pad,

conditioner and slurry in cooperation with

consumable suppliers

• CMP wafer processing on demand

co-operation partner:

Extending these models on the feature scale

to models on the chip scale, the design pro-

cess can be supported by remarks about the

manufacturability. It is an ambitious goal to

minimize the number of learning cycles con-

cerning CMP at the introduction of a new

technology with the help of simulations.

technical data

• CMP:

- CMP system – Applied Materials

Reflexion LK

- Delivery system – Flexible Slurry System

• Metrology:

- Ellipsometer – KLA Tencor SpectraCD 100

- 4-point-prober – KLA Tencor RS-100

- 3-D-AFM – Veeco X3D (Tapping, DT,

CD, Contact)

- Profiler – KLA Tencor HRP-340

• CMP test-chips:

- Wafer processing with CMP test-masks

and E-Beam direct write technology

- Supporting FEoL and complete BEoL

processes

- Further analysis methods (SEM, TEM,

XRD, TOF-SIMS, Raman, etc.)

• Simulation:

- Modeling on different scales, especially

feature and chip scale

- In-house developed simulation programs

and routines

- FEM based commercial software COMSOL

Multiphysics

- Workstation and Cluster computer3 Polisher – Applied Materials Reflexion LK

4 Patterned oxide wafer with CMP test-chip

4

Flexible slurry delivery system

3-D-depiction of a measured polishing pad surface (1 mm x 1 mm)

Determined logarithmic normal distribu-tion of the pad asperities’ curvatures