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Use of Thermal bumps in IC package

Dept of E&C, EWIT Page 1

Chapter 1.

Introduction

The Thermal copper pillar bump , also known as the "thermal bump", is a thermoelectric devicemade from thin-film thermoelectric material embedded in flip chip interconnects (in particular

copper pillarsolderbumps) for use in electronics and optoelectronic packaging, including: flip

chip packaging ofCPUandGPUintegrated circuits (chips),laser diodes, andsemiconductor

optical amplifiers(SOA). Unlike conventional solder bumps that provide an electrical path and amechanical connection to the package, thermal bumps act as solid-state heat pumps and add

thermal management functionality locally on the surface of a chip or to another electrical

component. The diameter of a thermal bump is 238 m and 60 m high.

The thermal bump uses thethermoelectric effect, which is the direct conversion of temperature

differences to electric voltage and vice versa. Simply put, a thermoelectric device creates a

voltage when there is a different temperature on each side, or when a voltage is applied to it, itcreates a temperature difference. This effect can be used to generate electricity, to measure

temperature, to cool objects, or to heat them.

The thermal bump was developed by Nextreme Thermal Solutions as a method for integrating

active thermal management functionality at the chip level in the same manner that transistors,resistors and capacitors are integrated in conventional circuit designs today. Nextreme chose the

copper pillar bump as an integration strategy due to its widespread acceptance byIntel,Amkor

and other industry leaders as the method for connecting microprocessors and other advanced

electronics devices to various surfaces during a process referred to as flip-chip packaging. Thethermal bump can be integrated as a part of the standard flip-chip process (Figure 1) or integrated

as discrete devices.

The efficiency of a thermoelectric device is measured by the heat moved (or pumped) divided by

the amount of electrical power supplied to move this heat. This ratio is termed the coefficient of

performance or COP and is a measured characteristic of a thermoelectric device. The COP isinversely related to the temperature difference that the device produces. As you move a cooling

device further away from the heat source, parasitic losses between the cooler and the heat source

necessitate additional cooling power: the further the distance between source and cooler, the

more cooling is required. For this reason, the cooling of electronic devices is most efficient whenit occurs closest to the source of the heat generation.

Use of the thermal bump does not displace system level cooling, which is still needed to moveheat out of the system; rather it introduces a fundamentally new methodology for achieving

temperature uniformity at the chip and board level. In this manner, overall thermal management

of the system becomes more efficient. In addition, while conventional cooling solutions scalewith the size of the system (bigger fans for bigger systems, etc.), the thermal bump can scale at

the chip level by using more thermal bumps in the overall design.
http://en.wikipedia.org/wiki/CPUhttp://en.wikipedia.org/wiki/CPUhttp://en.wikipedia.org/wiki/CPUhttp://en.wikipedia.org/wiki/GPUhttp://en.wikipedia.org/wiki/GPUhttp://en.wikipedia.org/wiki/GPUhttp://en.wikipedia.org/wiki/Laser_diodehttp://en.wikipedia.org/wiki/Laser_diodehttp://en.wikipedia.org/wiki/Laser_diodehttp://en.wikipedia.org/wiki/Optical_amplifier#Semiconductor_optical_amplifierhttp://en.wikipedia.org/wiki/Optical_amplifier#Semiconductor_optical_amplifierhttp://en.wikipedia.org/wiki/Optical_amplifier#Semiconductor_optical_amplifierhttp://en.wikipedia.org/wiki/Optical_amplifier#Semiconductor_optical_amplifierhttp://en.wikipedia.org/wiki/Thermoelectric_effecthttp://en.wikipedia.org/wiki/Thermoelectric_effecthttp://en.wikipedia.org/wiki/Thermoelectric_effecthttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Amkorhttp://en.wikipedia.org/wiki/Amkorhttp://en.wikipedia.org/wiki/Amkorhttp://en.wikipedia.org/wiki/Amkorhttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Thermoelectric_effecthttp://en.wikipedia.org/wiki/Optical_amplifier#Semiconductor_optical_amplifierhttp://en.wikipedia.org/wiki/Optical_amplifier#Semiconductor_optical_amplifierhttp://en.wikipedia.org/wiki/Laser_diodehttp://en.wikipedia.org/wiki/GPUhttp://en.wikipedia.org/wiki/CPU


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Chapter 2.

Study on Chip Scale Packaging Technologies

Solder bumping technology (the process of joining a chip to asubstratewithout shorting using

solder) was first conceived and implemented byIBMin the early 60s. Three versions of thistype of solder joining were developed. The first was to embed copper balls in the solder bumps

to provide a positive stand-off. The second solution, developed byDelco Electronics(General

Motors) in the late 60s, was similar to embedding copper balls except that the design employed

a rigid silver bump. The bump provided a positive stand-off and was attached to the substrate bymeans of solder that was screen-printed onto the substrate. The third solution was to use a

screened glass dam near theelectrodetips to act as a stop-off to prevent the ball solderfrom

flowing down the electrode. By then the Ball Limiting Metallurgy (BLM) with a high-lead (Pb)

solder system and a copper ball had proven to work well. Therefore, the ball was simplyremoved and the solder evaporation process extended to form pure solder bumps that were

approximately 125m high. This system became known as the controlled collapse chip

connection (C3 or C4).

During this same time, companies began to look at reducing or streamlining their packaging,from the earlier multi-chip-on-ceramic packages that IBM had originally developed C4 to

support, to what were referred to asChip Scale Packages(CSP). There were a number of

companies developing products in this area. These products could usually be put into one of two

camps: either they were scaled down versions of the multi-chip on ceramic package (of whichthe Tessera package would be one example); or they were the streamlined versions developed by

Unitive Electronics, et al. (where the package wiring had been transferred to the chip, and after

bumping, they were ready to be placed).

One of the issues with the CSP type of package (which was intended to be soldered directly to an

FR4 or flex circuit) was that for high-density interconnects, the soft solder bump provided less ofa stand-off as the solder bump diameter and pitch were decreased. Different solutions were

employed including one developed by Focus Interconnect Technology (former APTOS

engineers), which used a high aspect ratio plated copper post to provide a larger fixed standoff

than was possible for a soft solder collapse joint.

Today, flip chip is a well established technology and collapsed soft solder connections are used

in the vast majority of assemblies. Interestingly, the copper post stand-off developed for the CSPmarket has found a home in high-density interconnects for advanced micro-processors and is

used today by IBM for its CPU packaging.
http://en.wikipedia.org/wiki/Wafer_%28electronics%29http://en.wikipedia.org/wiki/Wafer_%28electronics%29http://en.wikipedia.org/wiki/Wafer_%28electronics%29http://en.wikipedia.org/wiki/IBMhttp://en.wikipedia.org/wiki/IBMhttp://en.wikipedia.org/wiki/IBMhttp://en.wikipedia.org/wiki/Delco_Electronicshttp://en.wikipedia.org/wiki/Delco_Electronicshttp://en.wikipedia.org/wiki/Delco_Electronicshttp://en.wikipedia.org/wiki/Electrodehttp://en.wikipedia.org/wiki/Electrodehttp://en.wikipedia.org/wiki/Electrodehttp://en.wikipedia.org/wiki/Chip_scale_packagehttp://en.wikipedia.org/wiki/Chip_scale_packagehttp://en.wikipedia.org/wiki/Chip_scale_packagehttp://en.wikipedia.org/wiki/Chip_scale_packagehttp://en.wikipedia.org/wiki/Electrodehttp://en.wikipedia.org/wiki/Delco_Electronicshttp://en.wikipedia.org/wiki/IBMhttp://en.wikipedia.org/wiki/Wafer_%28electronics%29


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CSP Benefits and Drawbacks

Benefits

CSP is the only way to achieve pervasive and ubiquitous computing. Further improvement in high-speed performance.

Drawbacks

Difficulty of PCB fabrication and mounting due to minute pin pitches. Long-term reliability not studied. Not serviceable.


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Chapter 3.

Study on copper pillar solder bumping

Recent trends in high-density interconnects have led to the use of copper pillar solder bumps(CPB) for CPU and GPU packaging. CPBs are an attractive replacement for traditional solder

bumps because they provide a fixed stand-off independent of pitch. This is extremely important

as most of the high-end products are under filled and a smaller standoff may create difficulties in

getting the under fill adhesive to flow under the die.

Figure 3.1 shows an example of a CPB fabricated by Intel and incorporated into theirPreslerline

of microprocessors among others. The cross section shows copper and a copper pillar(approximately 60 um high) electrically connected through an opening (or via) in the chip

passivation layerat the top of the picture. At the bottom is another copper trace on the package

substrate with solder between the two copper layers.
http://en.wikipedia.org/wiki/Pentium_Dhttp://en.wikipedia.org/wiki/Pentium_Dhttp://en.wikipedia.org/wiki/Pentium_Dhttp://en.wikipedia.org/wiki/Passivation_%28chemistry%29http://en.wikipedia.org/wiki/Passivation_%28chemistry%29http://en.wikipedia.org/wiki/Passivation_%28chemistry%29http://en.wikipedia.org/wiki/Pentium_D


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Chapter 4.

Study on Thin film technology used in

Thermal bump manufacture.

Thin films are thin material layers ranging from fractions of a nanometer to several micrometers

in thickness. Thin-film thermoelectric materials are grown by conventional semiconductor

deposition methods and fabricated using conventional semiconductor micro-fabrication

techniques.

Thin-film thermoelectrics have been demonstrated to provide high heat pumping capacity that far

exceeds the capacities provided by traditional bulk pellet TE products. The benefit of thin-filmsversus bulk materials for thermoelectric manufacturing is expressed in Equation 1. Here the

Qmax (maximum heat pumped by a module) is shown to be inversely proportional to the

thickness of the film, L.

. (4.1)

As such, TE coolers manufactured with thin-films can easily have 10x20x higher Qmax values

for a given active area A. This makes thin-film TECs ideally suited for applications involvinghigh heat-flux flows. In addition to the increased heat pumping capability, the use of thin films

allows for truly novel implementation of TE devices. Instead of a bulk module that is 1-3 mm inthickness, a thin-film TEC can be fabricated less than 100 um in thickness.

In its simplest form, the P or N leg of a TE couple (the basic building block of all thin-film TE

devices) is a layer of thin-film TE material with a solder layer above and below, providing

electrical and thermal functionality.


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Chapter 5.

Study of Thermal bump structure

The thermal bump is compatible with the existing flip-chip manufacturing infrastructure,

extending the use of conventional solder bumped interconnects to provide active, integratedcooling of a flip-chipped component using the widely accepted copper pillar bumping process.

The result is higher performance and efficiency within the existing semiconductor manufacturing

paradigm. The thermal bump also enables power generating capabilities within copper pillar

bumps for energy recycling applications.

Thermal bumps have been shown to achieve a temperature differential of 60 C between the top

and bottom headers; demonstrated power pumping capabilities exceeding 150 W/cm2; and when

subjected to heat, have demonstrated the capability to generate up to 10 mW of power per bump.

figure 5.1. shows cross section of thermal copper pillar bump


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Figure 5.2 shows a schematic of a typical CPB and a thermal bump for comparison. These

structures are similar, with both having copper pillars and solder connections. The primary

difference between the two is the introduction of either a P- or N-type thermoelectric layer

between two solder layers. The solders used with CPBs and thermal bumps can be any one of anumber of commonly used solders including, but not limited to, Sn, SnPb eutectic, SnAg or

AuSn.

Schematic showing traditional CPB next to a P-type and N-type pillar bump. The P- and N-type

bumps together make up a P/N couple that, when connected in series electrically, provides foreither Peltier cooling or Seebeck power generation.


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Chapter 6.

Working of Thermal bumps in an chip

Package

The thermal flow is shown by the arrows labeled heat. Metal traces, which can be severalmicrometres high, can be stacked or interdigitated to provide highly conductive pathways for

collecting heat from the underlying circuit and funneling that heat to the thermal bump.

Figure 6.1. Close-up schematic showing flow of heat through a thermal bump. Also shown arethe multi-layer metal traces often used in complex integrated circuits. These metal layers can be

beneficial for gathering heat from larger areas and funneling it into the thermal bump, reducing

the thermal constriction resistance in the circuit. A thermal via is shown in the printed wire boardfor improved heat rejection path.

The metal traces shown in the figure for conducting electrical current into the thermal bump may

or may not be directly connected to the circuitry of the chip. In the case where there are electricalconnections to the chip circuitry, on-board temperature sensors and driver circuitry can be used

to control the thermal bump in a closed loop fashion to maintain optimal performance. Second,

the heat that is pumped by the thermal bump and the additional heat created by the thermal bumpin the course of pumping that heat will need to be rejected into the substrate or board.


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Since the performance of the thermal bump can be improved by providing a good thermal path

for the rejected heat, it is beneficial to provide high thermally conductive pathways on the

backside of the thermal bump. The substrate could be a highly conductive ceramic substrate like

AlN or a metal (e.g., Cu, CuW, CuMo, etc.) with a dielectric. In this case, the high thermalconductance of the substrate will act as a natural pathway for the rejected heat. The substrate

might also be a multilayer substrate like a printed wiring board (PWB) designed to provide ahigh-density interconnect. In this case, the thermal conductivity of the PWB may be relativelypoor, so adding thermal vias (e.g. metal plugs) can provide excellent pathways for the rejected

heat.


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Chapter 7.

Applications of Thermal bump in a chip

Package

7.1. Hot spot cooling in ICs

Heat generation from silicon microprocessors is highly non-uniform both spatially andtemporally, with localized high heat fluxes that vary with the workload. Current electronics

cooling technologies based on conduction and convection can potentially cool moderately high

heat fluxes by utilizing either novel passive heat transport materials (such as carbon nanotubes)or advanced heat exchangers (such as microchannels), respectively. But they cannot provide site-

specific and/or on-demand localized cooling of high heat flux regions, thus resulting in over-

designed, inefficient, and bulky thermal systems. In contrast, solid state (thermoelectric)refrigeration can provide rapid, localized, and on-demand active cooling, as well as increased

cooling power densities.

Chip-scale thermoelectric coolers for high-performance microelectronics can be integrated into

microprocessor and electronics packages for high heat-flux thermal management for demanding

computation. In the example below, a thermoelectric cooler (TEC) is placed inside the chip

package, where the cooler is integrated onto conventional copper heat spreaders, just like the

type already used in chip packaging to disperse heat.

Fig7. 1. Thermal bump for hot spot cooling


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7.2. Temperature control of LEDs

The junction temperature of high-power light-emitting diodes (LED) can directly affect the

performance and longevity of some LED devices. As the junction temperature rises, a significantloss of light output (luminosity) can be expected. The forward voltage of an LED is also

dependent on the junction temperature. As the temperature rises, the forward voltage decreases

which can cause excessive current drain on other LEDs in the array. This in-turn leads to thermalrunaway conditions and ultimately to the failure of the device. High temperatures can also affect

the wavelength of an LED fabricated using gallium arsenide, gallium nitride or silicon carbide.

Bulk thermoelectric (TEC) devices have been used to provide temperature control of LEDs.However, today a major trend in photonics has been the move to smaller form factor, higher

power and more integrated packaging in order to enable a lower cost structure and concurrently

opening the door for higher volume manufacturing. In the course of this transition, conventionalTEC solutions have not kept pace with these needs due to their size and power density

limitations.

Nextreme's thin-film embedded thermoelectric coolers (eTECs) are smaller and thinner than

conventional products and show promise for direct integration using industry standard

manufacturing methods. In addition, thin-film eTECs have demonstrated a heat pumpingcapacity that far exceeds that provided by traditional bulk TECs. This makes eTECs ideally

suited for high heat density applications. The ability of these devices to be placed close to the

heat source means that they work at smaller temperature differences. The smaller the operational

temperature difference, the more efficient they become.

7.3. Semiconductor test

Semiconductor-at-speed testing for device characterization is designed to evaluate the futureperformance of devices while they are driven at near failure environmental conditions. In

addition, semiconductor die manufacturers use burn-in to eliminate the early life failures from

their lots. The temperature of the device in this process must be held constant for a significant


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period of time then switched as quickly as possible. Bulk TECs have been used to provide this

rapid heating and cooling in the past but with most things the conditions for these tests are

pushing the limits for both switching speeds and heat pumping capability.

Thin-film TECs have a larger heat pumping capability than standard bulk TECs but it is the

superior switching speed of the devices that may ultimately prove to be their most valuable assetfor this application. Recent measurements have shown that due to their smaller footprint andweight these thin-film TECs offer rapid switching that translates into more efficient use of

energy for device characterization. In addition, the high heat flux of Nextreme's TECs enable

direct cooling of today's high heat chips, eliminating the need for heat spreaders in the testsystem.

7.4. Deep drilling

Cooling of sensors and electronics used for down hole oil and geothermal wells is critical to theoperation of these systems in MWD (measurement while drilling) applications. The temperatures

and pressures imposed on the down-hole assembly, increase with well depth and are generally

higher than the survival temperatures of these sensors and electronics without cooling. Manyapproaches to cool or protect the sensing and electrical systems have been proposed and

implemented over the years including vacuum Dewar flasks and thermoelectric refrigerators,

sorption coolers, heat exchangers, cryogenic cells, Sterling coolers and vortex coolers. Almost all

of these methods rely on the drilling mud that is pumped through the drill string to provide thefinal medium to carry away heat from the down-hole assembly.

Maintaining optimal payload temperatures in a typical down hole environment of 230C requiresthat the MWD cooling system be capable of pumping a significant load and requires a low

thermal resistance path on the heat rejection (hot) side of the TEC. The application environment

of high temperature, high pressure, mechanical shock and vibration require the use of hightemperature thermoelectric materials and assemblies that are capable of withstanding the

mechanical environment.


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7.5. Polymerase Chain Reaction (PCR) Thermal Cycler Reference Design

The microscopic size and fast response time of Nextreme's thin-film eTECs thermoelectric

modules enable a new generation of thermal cyclers that feature significantly shorter throughputtimes, smaller sample sizes, and reduced footprint for a compact, field-level design, promoting

real-time testing in healthcare, forensics, and food safety.

PCR is a technique widely used in molecular biology to produce millions of copies of a specificDNA sequence in a short period of time. PCR-based testing is used in the diagnosis of hereditary

diseases; the identification of genetic fingerprints (used in forensic sciences and paternity

testing); and the detection and diagnosis of infectious diseases. The vast majority of PCR

methods use thermal cycling, i.e., alternately heating and cooling of the DNA sample based on apredefined series of temperature steps.

A thermal cycler is an automated instrument specifically designed for this purpose. A typicaldevice consists of a metal block with holes where plastic vials holding the PCR reaction mixtures

are inserted. The instrument has an integrated heating/cooling unit that is used to systematically

raise and lower the temperature of the block.


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Chapter 8.

References

Www.Nextreme.com Www. Howstuffworks.com Www.Wikipedia.com

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