chipscale review vol14,no5,sept-oct 2010

September-October 2010September-October 2010September-October 2010Volume 14, Number 5Volume 14, Number 5Volume 14, Number 5

The International Magazine for the Semiconductor Packaging IndustryThe International Magazine for the Semiconductor Packaging Industry

Aerosol Jet InterconnectAerosol Jet InterconnectFlip Chip Die Bonding for 3D ICsFlip Chip Die Bonding for 3D ICsWLCSP Drop Test Reliability and DesignWLCSP Drop Test Reliability and DesignThe Ever Changing Photovoltaic LandscapeThe Ever Changing Photovoltaic LandscapeInternational Directory of Wafer Scribing and Dicing SystemsInternational Directory of Wafer Scribing and Dicing Systems


http://www.newport.com/bond1

CONTENTS

Sept-Oct 2010 Volume 14, Number 5 The International Magazine for Device and Wafer-level Test, Assembly, and Packaging

Addressing High-density Interconnection of Microelectronic IC's including 3D packages, MEMS,MOEMS, RF/Wireless, Optoelectronic and Other Wafer-fabricated Devices for the 21st Century.

This edition’s cover features an inside view of SET’sFC300 Automated High Force Die / Flip Chip Bonder forautomated handling of chips and substrates up to 100 mmfrom waffle packs. With ± 0.5 μm post bond accuracy and

20 μradians leveling, the SET FC300 offers the latestevolutions in bonding techniques. The article “Flip ChipDie Bonding for 3D IC Integration”explores some of the

new challenges, advantages, and options.

Courtesy of Smart Equipment Technology SAS,Saint Jeoire - France.

September-October 2010September-October 2010September-October 2010Volume 14, Number 5Volume 14, Number 5Volume 14, Number 5

The International Magazine for the Semiconductor Packaging IndustryThe International Magazine for the Semiconductor Packaging Industry



FEATURE ARTICLESFlip Chip Die Bonding for 3D IC IntegrationKeith A. Cooper, Michael D. Stead SET-North America,Gilbert Lecarpentier, Jean-Stephane Mottet, SET-SAS

Jetting Your Way to Fine-pitch 3D InterconnectsMike O’ Reilly, Optomec, Inc., Jeff Leal, Vertical Circuits Inc.

Drop Test Reliability and Design of Wafer-Level Chip Scale PackagesYong Liu, Stephen Martin, Fairchild Semiconductor Corp, Luke England,Micron Technology

3D IC Integration with TSV Interposers for High Performance ApplicationsJohn H. Lau, ITRI, and Y. S. Chan and S. W. Ricky Hong Kong University ofScience and Technology

Wafer Scribing & Dicing ... Which Method? Equipment?Gil Olachea, Az Tech Direct, LLC

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Chip Scale Review. Sept/Oct 2010. [ChipScaleReview.com] 1

http://www.microcontrol.com

Chip Scale Review. Sept/Oct 2010. [ChipScaleReview.com]2

http://www.ssecusa.com


http://www.ssecusa.com


http://www.vitechnology.com


CONTENTS

FEATURE ARTICLES

DEPARTMENTS

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The Ever Changing PV Landscape An overview of worldwide PV production, new technologies and market demand.Bob Klenke, ITM Marketing

From the Publisher Forecasting ... We all do it! Year End 2010 and Forecasting into 2011...Kim Newman, Chip Scale Review

Editor's Outlook 1 + 1 = 3Ron Edgar, Technical Editor, Chip Scale Review

Industry News

2010 International Directory of Wafer Scribing and Dicing SystemsRon Molnar Az Tech Direct

Emerging Trends A Good Place to Place Your Bets (in ICs)Sandra Winkler, Senior Analyst New Venture Research

What’s New!

Market Forecast Walker’s September Forecast: Recovery, Boom, Growth, What’s Next?Françoise von Trapp, Contributing Editor, 3D InCites Group, LLC

Product Showcase

Advertiser Index, Advertising Sales, Calendar

http://www.hcdcorp.com


FRFRFRFRFROM OM OM OM OM THE PUBLISHERTHE PUBLISHERTHE PUBLISHERTHE PUBLISHERTHE PUBLISHER

STAFF

Kim Newman [email protected] Michaels Managing [email protected] Edgar Technical [email protected]çoise von Trapp Contributing [email protected] Winkler Contributing [email protected]. Tom Di Stefano Contributing [email protected] M. Sakamoto Contributing Editor [email protected] Mirabito Contributing Legal [email protected] Peters Contributing Legal [email protected]

SUBSCRIPTION--INQUIRIES

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EDITORIAL ADVISORS

Dr. Thomas Di Stefano Centipede SystemsRon Molnar Az Tech Direct, LLC.Dr. Andy Mackie Indium Corp. of AmericaDr. Thorsten Teutsch Pac Tech USACharles Harper Technology SeminarsDr. Guna Selvaduray San Jose State UniversityProf. C.P. Wong Georgia TechDr. Ephraim Suhir ERS CompanyNick Leonardi Premier Semiconductor Services

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The International Magazine for Device and Wafer-levelTest, Assembly, and Packaging Addressing

High-density Interconnection of Microelectronic IC'sincluding 3D packages, MEMS, MOEMS, RF/Wireless, Optoelectronic and Other Wafer-

fabricated Devices for the 21st Century.

VOLUME 14, NUMBER 5

ositive and optimistic industry trends were evident at SEMICON West 2010,with these trends visible as well in our July/August issue of Chip Scale Review

(CSR). Both the editorial content and corporate advertising were expanded in theissue, as progressive companies took action to capitalize on the upturn and promotetheir products, services, and new technologies. SEMICON West 2010 and corporate3rd Quarter, 2010 financial reports are history. Let’s look to the future.

This is the time of year when industry experts and amateurs alike look back andthen forward attempting to forecast the 2011 industry trends. Forecast information,regardless of its in-house or industry source, drives all levels of corporate resourceplanning, capital equipment procurement, and marketing budgets. Following thesignificant 2009 industry downturn and somewhat amazing 2010 upturn, forecastsare exhibiting much broader variability than in recent years. This wide range of forecastestimates may actually lead to “corporate indecision” regarding the 2011 outlook andslow down the positive industry momentum.

Decisions for 2011 will be critical, and although CSR isn’t in the business ofprofessional forecasting, nor is my phone ringing off the hook with execs solicitingmy advice, I’m happy to share my perspective of the industry with you based on mydiscussions with a significant number of industry professionals. One thing is certain- corporate productivity is at or near a record level in 2010! Companies have increasedtheir sales and bottom lines by doing more with fewer people. They have been slow toresume hiring in 2010 following their 2008 and 2009 reductions in staff. A majordecision facing many companies is whether to increase staffing or continue to “stretch”their resources further in 2011.

Global economics, inventory levels, buying trends, and many other important factorsinfluence the forecast accuracy of future performance. Market forecasting may not beone of your job responsibilities, however, I venture to say it enters into many of yourdaily decisions. Let me give you a few data points to help you with some of yourdecision-making: (1) Both MEPTEC and SMTA report increased advance registrationfor their Medical Electronics Symposium in September, (2) SMTA and CSR staffboth see increased attendee and exhibitor registrations for their International Wafer-Level Packaging Conference (IWLPC) in October, and (3) exceptional editorial contentand comprehensive supplier directories in CSR continue to attract new advertisers.

I appreciate that you have taken the time to read this letter, as it offers me theopportunity to convey my personal take on the health of our industry. There’s still onemore quarter remaining before we “close the books” on 2010. Information to review!Meetings to attend! Decisions to make! Give me a call if you can use my insight(advice at no charge) as we all strive to make our numbers and await the final accountingreports on our sales and earnings figures for the year.

I look forward to meeting many of you at the upcoming IWLPC event in SantaClara, CA where we can discuss each other’s views of the industry forecasts. We haveone more issue to publish before year end, so I’d appreciate any comments andfeedback you have regarding the publication.

Forecasting ... We all do it!Year End 2010 and Forecasting into 2011...

Kim NewmanPublisher

P


http://www.plastronicsusa.com


EDITOR'S OUTLOOK

admit it _ I’ve finally lost mymarbles! How can one plus oneequal three? According to the

rules of arithmetic, that is just notpossible. How can the result be greaterthan the sum of the parts? New math?Fuzzy logic? Or just plain wrong? Noneof the above, and here’s why.

The simple truth is, sometimes we haveto break the rules. Suppose I want to builda better mousetrap. I disappear into mylab and a long time later I emerge with anew device. But no one can mass-producethe materials, the device is too costly tobuild, and someone else has already madesomething better. But if I had got togetherwith some like-minded people, we couldhave cooperated on the design. Afterbasic agreement on the device, we couldeach use our specialties to develop a pieceof the device. We could agree onstandards to make the device and, in theend, we produce a product that is wellmade, can be manufactured costeffectively, and fills a major need. Socooperation plus standardization = wellmade, cost effective, and wide appeal; or1 + 1 = 3.

An interesting example comes in a2008 article by Professor Ruth Taplin ofthe London School of Economics whereshe is the Director of the Centre forJapanese and East Asian Studies. Herarticle, The Taiwan Model for PatentingNanotechnology, discusses how theTaiwanese government is pouring moneyinto basic research on next-generation ICmemory. “This funding will be sharedbetween the basic research supervisorNational Science Council (NSC),including the Nano Device Laboratory

1 + 1 = 3By Ron Edgar [[email protected]]

I (NDL) and the Industrial TechnologyResearch Institute (ITRI).” She goes onto say, “ITRI’s research funding will befocused on industrialization oftechnology. The institute is developingnanotechnology platforms to producehigh standard results through cooperationbetween related industries, academics andresearch centres.” Again, 1 + 1 = 3.

The costs associated with cutting-edgetechnology development is astronomic.Frequently this cost is much more thanany single company can afford. Also, therange of skills required is so diverse thatit is unlikely to live under one roof. Thecost effective answer? Cooperation andstandardization.

Industry organizations such as IPC andJEDEC are the core of globalstandardization. IPC “is a Global tradeassociation dedicated to the competitiveexcellence and financial success of its2,700 member companies whichrepresent all facets of the electronicinterconnect industry, including design,printed circuit board manufacturing, andelectronics assembly. IPC is an ANSI-accredited standards developer (whichbrings us to ANSI, another huge sourceof standardization). JEDEC, JointElectron Devices Engineering Council,now known as JEDEC Solid StateTechnology Association, is an independentsemiconductor engineering tradeorganization and standardization bodywith over 300 members, including someof the world’s largest companies. It isassociated with Electronic IndustriesAlliance (EIA) another trade organizationthat represents all areas of the electronicsindustry in the USA. The Global

Semiconductor Alliance (GSA)’s statedmission is “to accelerate the growth andincrease the return on invested capital ofthe global semiconductor industry byfostering a more effective fablessecosystem through collaboration,integration and innovation.”

The cooperation, standardization, andcommunication fostered by these andother industry groups are the nuts andbolts that hold together a substantialportion of our industry. They ensure thata wafer made in one place can beprocessed in another. They ensure thatcomponents made all over the world canbe brought together and successfullyassembled into a product. They ensurethat different products can “talk” toeach other.

One might think that sharing ideas isbad for the bottom line. Quite theopposite. Industry cooperation andstandardization has led to better products,lower cost, faster time to market, andbetter ROI. True, your special piece ofIP that differentiates your product andallows you to compete is critical, but forthe most part, the bulk of all products arebuilt with standard parts to standardspecifications. Truly, the result is greaterthan the sum of the parts; 1 + 1 = 3.

International Wafer-Level PackagingConference (IWLPC) is almost with us(October 11-14, 2010, Santa ClaraMarriott Hotel, Santa Clara, CA, USA.IWLPC is jointly sponsored by SMTAand this magazine and “explores cuttingedge topics in wafer-level packaging andIC/MEMS/MOEMS packaging, including3D/Stacked/CSP/SiP/SoP and mixedtechnology packages.” In his message,


Andrew Strandjord of Pac Tech USA,Conference General Chair, says, “Theobjective of the IWLPC is to provide aunique venue that brings togetherscientists, engineers, academia,manufacturing, and business people fromaround the world to present and debatesome of the latest and hottest packagingtechnologies.” Be sure to go towww.iwlpc.com for more information onhow to attend and what is offered in themany presentation sessions. IWLPC hasbecome one of the premier venues in ourindustry and a unique opportunity to rubshoulders with the movers and shakersfrom the thinkers and imagineers (thankyou Disney) to the companies that makethe dreams come true.

This edition we have another directoryfor you. Our previous offerings haveproven hugely popular and useful and wehope you find this likewise. Ron Molnar,Az Tech Direct, has prepared our 2010International Directory of Wafer Scribingand Dicing Systems.

We have a fine set of articles thisedition. Jetting Your Way to Fine-pitch3D Interconnects is a fascinating look atthe current state of TSV, wire-bond, and,yes, aerosol jet printing. Check it out!This is really interesting stuff from MikeO’Reilley of Optomec, Inc., and Jeff Lealof Vertical Circuits, Inc. A studiousreview of Flip-Chip Die Bonding for 3DIC Integration with focus on “technicallyeffective and manufacturable processes”is presented by Keith Cooper and MichaelStead of SET-North America and GilbertLecarpentier and Jean-Stephane Mottetof SET-SAS. There is a lot of good detailin this article and well worth wadingthrough. A collaborative article betweenYong Liu and Stephen Martin of FairchildSemiconductor and Luke England ofMicron explores the DropTest Reliabilityand Design of Wafer-Level Chip-ScalePackages. The results of this study arepresented showing corroboration betweenthe modeling and the actual drop tests.Our business article, written by long-timefriend and contributor Bob Klenke ofITM Marketing looks at The Ever

Changing Photovoltaic Landscape andis an overview of the worldwide PVproduction, new technologies, and marketdemand. Sandra Winkler, in her regularcolumn, Emerging Trends, is looking forA Good Place to Place Your Bets (in ICs).

We have our regular columns, What’sNew and an expanded Industry News.We hope everyone finds somethinginteresting and useful in this edition.‘Till we meet again. Oh, don’t forget,1 + 1 = 3.

http://www.evgroup.com


2010 Semiconductor Forecasts-

Updated Outlook

31.0% Future Horizons (May 10)

29.8% Semico Research (May 10)

27.0% IC Insights (May 10)

25.0% VLSI Research (May 10)

27.1% Gartner (Jun 10)

28.4% SIA (Jun 10)

0% 5% 10% 15% 20% 25% 30% 35%Source: SEMI

28.6% WSTS (Jun 10)

32.7% Henderson Ventures (Jun 10)

INDUSTRY NEWS

2010 Semiconductor Forecast outlooks as of July,2010. (Source: SEMI)

From SEMICON West: A PositiveOutlook

“This is an exciting time as the industrybegins its recovery,” noted SEMI’sJonathan Davis in his opening remarksat SEMICON West’s annual pressconference in July. “I want to savor thismoment, I don’t know how many timesI’ll get to stand up here and say the marketis going to double this year.”

Stan Myers, president and CEO ofSEMI offered equally encouraging news,noting that the latest versions ofsemiconductor forecaster reports indicatean average expected growth rate of 38.7%(Figure 1). Offering as a reference point,the January 2010 forecast of 14.9%growth, Myers said the recent predictionsare “fairly impressive” and expect to seebigger numbers moving forward.“Growth has been consistently positivesince April of 2009,” said Myers,“demand for semiconductors has clearlyrecovered from recent market declines.”

Myers cited market drivers such as on-going recovery in economy, (althoughconcerns with debt, unemployment andeconomic growth in the second half of2010 remain), the electronics marketgrowth, improved fab utilization and firmaverage selling prices. He also pointedto 11 months of book-to-bill ratio beingabove parity as another positive indicator.Japan is experiencing similar growth inthe semiconductor equipment market.“Recovery is active in all majorsemiconductor manufacturing markets; thedifference is to what degree,” said Myers.

Amidst all the celebrating, Myers didexpress some concern about investment

in innovation, which he says is neededfor continued growth. His concern is thatthere isn’t enough investment to maintaininnovative approaches, although NorthAmerica continues to invest in advancedtechnologies, and in Europe, a reported$5B per year will be spent onsemiconductor equipment and materialsin both 2010 and 2011.

With regard to SEMICON West itself,event organizers reported an increase injust about everything over 2009. The finalcombined attendance (visitors andexhibitors) for SEMICON West andIntersolar North America grew 17% to29,423, with verified visitors rising 9%to 19,423. Visitor interest between theshows was 68% for both SEMICON Westand Intersolar, 16% for SEMICON-only,and 16% for Intersolar-only. Technicalsessions at the TechSITE, TechXPOT,and Extreme Electronics show floorstages, as well as main stage keynotes andexecutive panel sessions were reportedto be standing-room only. Additionally,the premiere of Virtual SEMICON Westonline companion event reportedlyattracted nearly 700 “virtual” attendeesas of August 24, most of whom were notable to attend the live show.

SEMI Reorganizes, Makes ManagementChanges

In August, SEMI announced areorganization into three dedicatedbusiness units for IC manufacturing,photovoltaic (PV), and Emerging andAdjacent Markets. As part of this, KarenSavala succeeds Jonathan Davis aspresident of SEMI North America, andDavis will assume the new position,president of the Semiconductor ICBusiness Unit.

The reorganization is the result of ayear-long review and analysis by SEMI’sboard of directors to achieve betteraccountability and improved memberservice in the primary market areas ofsemiconductor ICs, PV solar, and relatedmarkets such as high-brightness LEDs,MEMS/MST, and printed and flexibleelectronics. The three new business units

will be responsible for developing anddelivering member services on a globalbasis through SEMI regional officesbased in China, Europe, India, Japan,Korea, North America, Russia, Taiwanand Singapore.

“While all these areas share a commonprocess technology base and need foreffective supply chain collaboration,these changes are intended to enable moreresponsive and specialized products,services and leadership in the multipleindustries that SEMI members nowserve.” said Stanley Myers, president andCEO of SEMI.

In addition to Davis and Savala’schanging roles, Tom Morrow will directthe activities of the Emerging and AdjacentMarkets Business Unit, in addition to hisduties as V.P. of Global Expositions andchief marketing officer. Dan Martin willcontinue to lead the PV Group, nowrecognized as a dedicated SEMI businessunit, assisted by Bettina Weiss who willtake on new global responsibilities asexecutive director, PV Group.

SEMICON Europa 2010 to focus onNano Innovations

SEMI’s lineup of keynote speakers andprogram highlights for SEMICONEuropa 2010, October 19-21, Dresden,Germany will feature all European fabsincluding GLOBALFOUNDRIES,Infineon, Intel, STMicroelectronics andX-Fab, as well as leading R&Dorganizations in SEMICON SciencePark. Key market segments to beaddressed include: semiconductor front-and back-end, MEMS/MST, secondaryequipment and advanced packaging.

“SEMICON Europa offers a widerange of programs that address Europe’smanufacturing issues and opportunities,”said Heinz Kundert, president of SEMIEurope. “This year’s event continues thetransformation of SEMICON into amanufacturing communication platformthrough programs put together bycommittees of industry experts.”

In addition to the events’ technologyconferences, courses, free technology and


standardization sessions, executive andnetworking events, this year SEMI hasexpanded co-location opportunities toinclude the Plastics ElectronicsConference, covering topics such asorganic electronics, displays, organicphotovoltaics, and lighting; The 12thEuropean Manufacturing Test Conference(EMTC); the Advanced PackagingConference; and the International MEMS/MST Industry Forum.

For more detailed information aboutkeynote speaker addresses, technicalprograms and short courses, or to registerto attend the exposition, please visitwww.semiconeuropa.org.

SEMATECH Completes 300mm Linefor Via-Mid 3D ICS

As part of its workin 3D IC integration,SEMATECH’s 3DInterconnect programannounced that its300mm 3D IC pilotline is complete andoperating at the

College of Nanoscale Sc ience andEngineering’s (CNSE) Albany NanoTechComplex. Dedicated to via-mid 3Dapplications, this development andexploratory platform reportedly includesall processes and test vehicles necessaryto demonstrate the viability of via-midtechnology in conjunction with advancedCMOS.

Based on 5 x 50μm TSVs, theprocesses include TSV formation andmetallization, wafer and die alignment,bonding, thinning, and the necessarymetrology for these integration sequences.Supported by the conventional CMOSprocessing capabilities of CNSE,SEMATECH researchers are workingjointly with chipmakers, equipment andmaterials suppliers, and universities ondevice interactions for fabrication at the65nm node for planar and future scalingto 30nm for planar and non-planar CMOStechnologies.

“Our program provides our memberswith access to complete 300mm R&D

capability in 3D, allowing them to evaluatetools, process modules and evenintegration sequences in a realistic setting,”explained said Sitaram Arkalgud directorof 3D Interconnect at SEMATECH,

adding that the organization plays astrategic role, working with the industryto drive manufacturability and forgeconsensus on technology options,standards, and cost modeling.

http://www.dltechnology.com


According to Richard Brilla, vicepresident of strategy, alliances andconsortia at CNSE, the integration of this3D IC pilot line enhances the research anddevelopment capabilities at the UAlbanyNanoCollege. “This marks anothercritical step forward in acceleratingadvanced manufacturing for innovativenanoelectronics technologies.” he said.

Kulicke & Soffa CEO, Scott KulickeRetires, Bruno Guilmart Takes the Helm

Effective September 30, 2010, ScottKulicke, officially hands over the reinsof Kulicke & Soffa (K&S) to BrunoGuilmart, who was elected president andCEO of the company in the wake of theannouncement of Kulicke’s plannedretirement. Kulicke will also retire fromthe Company's Board of Directors and theBoard has elected Guilmart to fill his seat.MacDonell Roehm, an independentdirector, will remain non-executiveChairman of the Board of Directors.

Late last year, Kulicke, CEO since1979, announced his intention to retireno later than June. “Leaving will bedifficult. Besides the host of ongoingprojects and programs that will makeK&S an even better company, I’ll missthe talented and dedicated team of K&Semployees around the world who havemade the company so successful,” saidKulicke, in a statement to the press. “TheBoard conducted a comprehensive searchfor my successor, considering many strongcandidates, both internal and external.Bruno is a great choice. Given his industryexperience, his drive and his technologyexpertise, I am confident in his ability tolead K&S into the future.”

According to Roehm, Guilmart has astrong industry track record as CEO,

Bruno Guilmart Scott Kulicke

leading companies in the USA and Asiaincluding Lattice Semiconductor, UnisemGroup, and Advanced InterconnectTechnologies. “He is uniquely positionedto build on Scott’s legacy and extendK&S’s leadership position in ourindustry,” he said, adding that he’sobserved K&S’s evolution underKulicke’s leadership over the past 25years. “The industry in general and K&Sin particular will miss Scott’s knowledgebase and wisdom,” said Roehm. “We wishhim well during his retirement.”

Kulicke will stay with K&S in anadvisory capacity to ensure a smoothmanagement transition. Guilmart will residein Singapore, the center of the K&S’ globaloperations. Other headquarter functionswill migrate to Singapore in fiscal 2011.

Heraeus Doubles PV Staff; IntroducesPastes Targeting PV

In response to recent success of its frontand back side silver pastes for crystalline Sisolar cells, Heraeus has recently takenmeasures to further increase its presence inthe photovoltaics market. Over the past fewmonths, the company has announcedcapacity expansion at its Photovoltaic (PV)business unit, and more recently doubled itstechnology staff at the US facility in WestConshohocken, PA. In addition, the PVbusiness unit introduced a new line of frontside silver pastes, the SOL9400 Series thatreportedly offer improved performance overthe company’s current product offering.

“The new staff has excellent knowledgeof material science, and solid experiencein the PV industry. They brought not onlynew energy but also new ideas to the team.These important additions to our staff willhelp us expand our product portfolio andgrow our technology advantage in the PVpaste market.” said Dr. Weiming Zhang,VP of technology for PhotovoltaicBusiness Unit. He said the initial feedbackfrom key customers for the SOL9400 hasbeen positive, and that they are particularlyimpressed with its improved efficiency andfaster throughput than its predecessor.

“We continue to innovate, develop newproducts and customize them for specific

production requirements. As the globalsolar market continues its rapid growthwe believe solar manufacturers willincreasingly turn to Heraeus,” said AndyLondon, Global Business Unit Leader forHeraeus PV.

DB Design Announces ManagementBuy-Out

The management team of Fremont CAbased DB Design, supplier of testhardware and interface products,announced it has purchased the companyfrom WELLS-CTI, Inc. The acquisitionwill reportedly allow the company to focuson its unique market while servicing newand existing customers. Rennie Bowerswill focus on operations and engineering,and Mark Stenholm will take charge ofsales, marketing and product development.

“We are very excited about theopportunity to bring our vision to DB Designas the new leadership team,” notes Stenholm.“After working at DB since the very earlydays, Rennie and I believe that we canenhance our customer satisfaction whilecontinuing to explore new markets.” AddsBowers: “Purchasing DB Design ensures ourcontinued quality and world-class service.”

Serving a broad customer base thatincludes top semiconductor manufacturers,DB Design specializes in innovative testinterface solutions including change kits,stiffeners, docking systems andmanipulators. The company will continueits operations in Silicon Valley.

“WELLS-CTI has decided to focus on ourcore, high growth areas including advancedthermal management,” said Matt BergeronWELLS-CTI CEO. “We wish the new DBteam the best of luck and look forward toworking with them on future projects.”

Rudolph Expands Presence inSemiconductor Process Control

In a move to expand its presence insemiconductor process control, RudolphTechnologies, Inc. has acquired selectedassets and IP of the Yield Dynamicssoftware business from MKS Instruments,related to yield management software usedby semiconductor manufacturers and


fabless semiconductor suppliers. As partof the acquisition, approximately 35engineering and applications personnel,most of whom are based in Tianjin, China,will join Rudolph’s Data Analysis andReview Business Unit.

As processes become more challenging,manufacturers are becoming more dependenton data management systems to deliverprocess information analysis designed toautomate decision-making and optimizeyield. The Yield Dynamics packagereportedly includes Genesis? Enterprisesoftware, a fabwide yield managementsolution that combines parametric and yieldoptimization in a unified platform with datamining and workflow development acrossall data sources.

“The products and technology includepatented analytical techniques for yieldimprovement that are complementary toour existing yield management andprocess control portfolio,” stated MikePlisinski, Rudolph’s vice president andgeneral manager, Data Analysis andReview Business Unit. “In addition to thetechnology, we welcome the Chinapersonnel to our growing applications andproduct development team.”

BITS Workshop 2011: Call for Papers

Planning for the Twelfth Annual Burn-in & Test Socket Workshop (BiTS) is wellunderway. Organizers of the event,scheduled to take place March 6-9, 2011,at the Hilton Phoenix East in Mesa, AZ,are seeking presentation and posterproposals on a broad range of Test & Burn-in topics to build a strong technicalprogram. Some topic ideas includetechniques and technologies that addresselectrical and mechanical challenges, PCBdesign and manufacturing challenges,advanced packaging technologies and testprocess and operational challenges. For afull list of suggested topics visitwww.bitsworkshop.org.

Presenting a paper at BiTS is a greatopportunity to share your latest work withyour industry colleagues and to helpadvance socketing & related industries.

Submit a 250 to 500 word abstract of youroriginal, previously unpublished,technical presentation by October 15.to:[email protected].

http://www.pactech-usa.com


Flip Chip Die Bonding for 3D IC IntegrationBy Keith A. Cooper, Michael D. Stead [SET-North America] and Gilbert Lecarpentier, Jean-Stephane Mottet [SET-SAS,]

D integration has emerged as aprime route to providing higherelectrical functionality within

smaller spaces. A key attraction for thismethodology is shorter interconnectionpaths by means of chip stacking, creatingnew types of vertical interconnects thatprovide direct circuit paths from one chipto another.1 These direct connectionsprovide higher operating speeds withreduced power consumption and loweroverall costs than competing methods.According to market research firm, YoleDéveloppement, 3D integration usingthrough-silicon vias (TSVs) is expectedto provide a major growth opportunity forthe semiconductor industry (Figure 1).

Of course, 3D integration has createda new set of challenges, though many ofits core elements and processing steps arebased on established front-end unitprocesses such as lithography, etching,depositions, and the use of variousmaterials and combinations. This articleexplores solutions in two particular areas:the removal of oxides prior to metal-metalbonding, and the proposal of a collectivehybrid bonding method to optimize accuracyand throughput between chip-level or wafer-level bonding methodologies.

3

Oxide removal prior to bondingAfter TSVs are etched, they are filled

with a conductive material such as copperor one of its alloys. After the dielectricand metal patterns have been formed,substrates are thinned to some fraction oftheir original thickness, then thesubstrates are bonded together to formone electrical entity.

Many papers have cited the advantagesof Cu-based systems, which include easeand familiarity of processing, mechanicaland electrical integrity, and scalability.2-6

For these and other reasons, Cu hasbecome a major focus as an interconnectmaterial for 3D integration. A representativeTSV structure for 3D chip stacking isshown in Figure 2.

To vertically join circuits, the exposedCu surfaces are bondedtogether using eitherdie-to-die (D2D), die-to-wafer (D2W), orw a f e r - t o - w a f e r(W2W) bond ing .Regardless of themethod used, the Cusurfaces are likely tohave oxides presentthat compromise resultsof thermocompressionbonding.

M e t a l s u r f a c eoxidation is a persistentproblem in devicebonding . Becauseoxides generally adherepoorly to other metals

or oxides, the bonding forcemust penetrate the oxide,literally breaking through it toachieve metal-to-metal cohesion.Not only does this increasethe required bonding force,but the presence of oxidesmay also raise the electricalresistance of the joint. Evenafter the device has beenbonded, existing oxides may

provide a convenient site for furtheroxidation, leading to reliability andperformance problems.4 For this reason,high-quality and reliable bonding benefitsfrom a controlled environment to eitherprevent oxide formation during thebonding sequence or to remove previouslyformed oxides. The requirements for anoxide removal process include:

Fast, effective removal of oxides Inert to other surfaces Minimal or non-existent residue EHS compliant Sufficient duration of effect Cost-effective

Historical methods for removing orinhibiting oxides include mechanicalscrubbing during the bonding process, usingan acid dip prior to bonding, or using oxide-reducing flux. Though these methods haveworked for larger feature sizes, they cancreate misalignments, add processing steps,or in the case of flux, can lead to reliabilityor performance problems if flux residuesare not completely removed.

However, a novel oxide removalmethod exists involving a localconfinement chamber built into thebonding tool that uses reducing gasses,such as forming gas or formic acid vapor,to safely reduce the oxides immediatelyprior to bonding. The confinementchamber is created by using a non-contactvirtual seal between the bonding head andthe substrate chuck, ensuring gascollection and preventing oxygenintrusion. This setup enables gasconfinement for D2D or D2W bonding

FFFFFigure 2.igure 2.igure 2.igure 2.igure 2. Schematic drawing of 3D stacking of the Si chip/Sicarrier with TSV (not to scale). (courtesy of A. Yu of IME Singapore)

FFFFFigure 1.igure 1.igure 1.igure 1.igure 1. TSV market forecast histogram (courtesy of Yole Dé veloppement,)


under controlled atmosphere whilepreserving the alignment of the devicewith respect to its substrate.

The process gas is injected throughhorizontal nozzles aimed at the devicebeing bonded (Figure 3). An exhaust ringremoves the process gas from the micro-chamber and sends it into the gas exhaustline, keeping the gas out of the machineand the clean room. A nitrogen curtain isformed around the exhaust, ensuring thatambient air is not entrained into the micro-chamber by the Venturi effect, while acover attached to the bond head createsthe confined micro-chamber (Figure 4).This configuration operates with eitherinert gasses to prevent oxide formation onbonding surfaces during the bondingsequence, or with reducing gasses such asforming gas to remove and prevent oxides.

Figure 5 shows a second confinementchamber configuration that is suited for

D2W bonding. Similar to the D2Dversion, hardware for this design providesthe oxide reduction capability to the chipand only to selected areas of the waferbeing populated. When the chip has beenaligned to its bonding site, the bondingarm lowers the chip very close to, but notyet in contact with the wafer. In thisposition, the chamber hardware on thearm forms a virtual seal to the wafer. Asmall gap between chamber and the wafersurface is maintained to avoid possiblecontamination or misalignment betweenchip and wafer.

To qualify the confinement chamber’sperformance, a chip with copper testpatterns was heated in a test apparatus to350 °C for 30 seconds while formic acidvapor flowed into the chamber at 8 SLPM(Figure 6). All oxides were presumablyremoved and the copper surface washighly reflective.

Next, formic acid vapor flow wasterminated, and the copper surfacesoxidized rapidly at 350 °C with ambientair, producing a mottled appearance in lessthan 5 seconds. Following this, the formicacid vapor was reinstated and the copperreturned to its reflective state within a fewseconds, indicating that oxide removal waseffective and rapid. Quantitative tests withelectrical and/or bonding data are ongoingand are positive, showing effectiveremoval of oxides at 250-350 °C. Figure7 indicates the testing of the copper couponas described.

The confinement chambers have beenimplemented in either configuration onSET device bonders. Materials andapplications explored and qualifiedinclude Cu-Cu for 3D integration, AuSnfor optoelectronics, and In for infraredfocal plane arrays. This setup may use anyinert or reducing gas, but formic acidvapor is in favor over forming gas due tosafety concerns and process efficacy.

Collective hybrid bondingWhen considering which of the three

methodologies (D2D, D2W or W2W) touse, many issues must be weighed andconsidered, including:

CTE mismatch between materials Die size Yield and use of known-good-die

(KGD) Overall cost

D2D bonding effectively addresses theissues of CTE mismatch between substratetypes, the potential mismatch in die sizebetween device types, and also offers theadvantage of bonding only good die. It hasbeen in use for many years for high-performance chips such as infraredimaging devices. Because of the highresolution imaging requirements, these

FFFFFigure 3.igure 3.igure 3.igure 3.igure 3. Schematic of local confinement chamber for D2D bonding

FFFFFigure 4.igure 4.igure 4.igure 4.igure 4. Photos of the confinement hardware looking down at the bonding chuck (a) or up at the bondinghead (b)

(a) (b)

FFFFFigure 5.igure 5.igure 5.igure 5.igure 5. Schematic of local confinement chamber for D2W bonding FFFFFigure 6.igure 6.igure 6.igure 6.igure 6. Test apparatus for formic acid chamber


imaging devices have extremely highbump counts (> 10 million), necessitatingthe use of very precise and often time-consuming bonding processes. ThoughD2D will continue to play a role in certainmarkets, it is a slow and thereforeexpensive methodology that will likely berelegated to low-volume applications.

Developed and used extensively forMEMS processes where a cap wafer wasrequired, W2W bonding has also been inuse for some time. More recently, it hasbeen applied to 3D integration due to itsinherent high throughput and processsimplicity. But since 3D integration isspecifically intended to bond variousdevice types of widely different sizes andmaterials, W2W bonding may beattractive only when joining smaller,higher-yielding devices, and where dieand wafers are equally sized.

D2W bonding is a promising assemblystrategy that may capture the best of the

two previous methodologies, but longbonding processes can also limit its cost-effectiveness. It offers high yield due tousing only KGD, high flexibility allowingheterogeneous integration, and highaccuracy placement potential by means ofthe flip chip device bonding technique.This method might suffer from potentiallylower throughput since each die is alignedand bonded or placed individually.However, this drawback is offset by thebenefit of bonding only KGD to known-good bonding sites of the wafer, increasingthe final yield andtherefore cost-effect iveness .D2W bonding isalso compatiblewith multiplebonding processf l o w s a n dm e t a l l u rg i e s ,including reflow,

thermocompression of copper and othermetals, thermosonic bonding, andadhesive and fusion bonding, (Figure 8).The roadmap for 3D integration calls forincreasing density of TSVs and relatedelements, necessitating ever-tighteralignment and control, and driving a movetoward D2W bonding.7-8

A new method has been developed, inwhich singulated die are initially bondedor tacked to a wafer in D2W fashion, thenthe bonding process is completed in awafer bonder tool. Intended to addressthe issues of CTE mismatch and bondingKGD of various sizes, yet with the costeffectiveness and throughput of a W2Wscheme, this method has been referred toas collective hybrid bonding (Figure 9).

In one application of this collectivehybrid bonding strategy, a patterneddielectric adhesive was used to populatea wafer in D2W fashion.9 The authornotes the inherent flexibility of D2W for3D integration, particularly forheterogeneous integration, as it allowsvarying die sizes and is compatible withthe selection of KGD. Following theD2W placement step, the populated waferwas further bonded in a two-step processin a wafer bonder wherein reflow of thepolymer pulled the Cu TSVs intomechanical and electrical contact with theCu landing pads. For this process, 2different polymers were used; electricalresults are shown in Figure 10 andindicate yields of 80+% for daisy chainsup to 1000 TSVs in length.

In another study, test die with Cu-Cu andCu-Sn TSV’s of 10μm and 40μm pitch,respectively, were tacked with high accuracyonto a 300mm landing wafer using a similarpolymer. After tacking, final bonding wasperformed in a wafer bonder. Electrical teststructures indicated all sites aligned to withinabout 1.5μm, with maximum die rotation of0.03 degrees observed.

FFFFFigure 8.igure 8.igure 8.igure 8.igure 8. Matrix of chip bonding processes

FFFFFigure 7.igure 7.igure 7.igure 7.igure 7. Copper patterns on test chip (a) after 30 seconds of formic acid vapor, (b) after a few seconds ofatmospheric ambient, and (c) after formic acid flow is reinstated, showing the rapid reduction of the oxides

FFFFFigure 9.igure 9.igure 9.igure 9.igure 9. In collective hybrid bonding, accurate placement of TSV die is followedby gang bonding of all dice to complete the bonding process. (Courtesy of Anne

Jourdain IMEC)


ConclusionsTwo key areas of 3D integration were

discussed, namely the removal of metaloxides prior to bonding, and the use ofcollective hybrid bonding to optimizeaccuracy and throughput. Solutions havebeen integrated using a flip chip bonderplatform, with a view toward creatingtechnically effective and manufacturableprocesses. Hardware and methodologyhave been successfully installed andimplemented at customer sites, with plansin place to apply and optimize these

solutions in new andexisting productlines.

References1. Dorota Temple,et al., “Bonding for3-D Integration ofH e t e r o g e n e o u sTechnologies andMaterials,” ECSTransactions 16, p.3-8, 2008.2. Aiban Yu, et al.,

“Three Dimensional Interconnects withHigh Aspect Ratio TSV’s and Fine PitchSolder Microbumps,” Proc. of 59th ECTC,2009.3. Rahul Agarwal, et al., “High DensityCu-Sn TLP Bonding for 3D Integration,Proceedings of 59th ECTC, 2009.4. John Lannon Jr., et al. “High DensityCu-Cu Interconnect Bonding for 3DIntegration” Proc. of 59th ECTC, May 2009.5. Bart Swinnen, et al., “3D Integrationby Cu-Cu Thermo-compression Bondingof Extremely Thinned Bulk-Si Die

Containing 10μm Pitch Through-SiVias,” Proc. International ElectronDevices Meeting, Dec 2006, pp. 1-4.6. Pierric Gueguen, et al. “3D Verticalinterconnects by Copper Direct Bonding”,MRS fall (2008).7. Gilbert Lecarpentier, et al., “WaferLevel Packaging Chip to Wafer approachusing Flux Less Soldering and featuringHermetic Seal Capability”, 4th AnnualIMAPS Conference on Device Packaging,Scottsdale, Arizona, March 2008.8. Leo DiCioccio, et al., “An InnovativeDie to Wafer 3D Integration Scheme: Dieto Wafer Oxide or Copper Direct Bondingwith planarized oxide Inter-Die Filling”,Proceedings of IEEE InternationalConference on 3D Systems Integration,October 2009.9. Anne Jourdain, et al., “ElectricallyYielding Hybrid Bonding for 3D Stackingof IC’s”, Proc. of 49th ECTC, 200910. Gilbert Lecarpentier, et al., “Die-to-Wafer bonding of thin dies using a 2-Stepapproach; High Accuracy Placement,then Gang Bonding”, Proc. of IMAPSDevice Packaging Conference, 2010

FFFFFigure 10.igure 10.igure 10.igure 10.igure 10. Electrical yield on 1000 TSV daisy chain structures with collectivehybrid bonding method. (Courtesy of Anne Jourdain, IMEC)

http://www.protoselectronics.com


n insatiable consumerappetite for instant accessto exponential functionality

at reduced cost is powering the smartphone and intelligent tablet devicemarkets. The question is: why?Goldman Sachs uses the 5C’s todescribe the attraction of these devices:consumption, content, connected,constant-on and commerce. While theywere referring to the Apple iPad, the5C’s can be applied to the continuouspush by “smart” device manufacturersto meet consumers’ ongoing thirst forinstant access to electronic contentregardless of how it is supplied. Thesesmart devices are finding their way intoa wide range of markets such asautomotive (smart cars); appliances(catch the latest episode of FoodNetwork right on your refrigerator);search the web, check out a book fromthe library, watch that latest on-demandmovie while downloading the latestexercise video _ all controlled througha Wii multi-media console.

So how do manufacturers deliver acompelling product that fits withinincreasingly smaller packages andsupports streaming audio, video, fastsearch/download, and touch screencommerce, all at attractive prices? Isthrough silicon via (TSV) the onlypackaging solution?

Challenges abound with the TSVapproach, although the majority can besolved with time and money. The mostchallenging obstacles are 3D infrastructureand the associated supply chain toenable broad adoption of 3D ICs. 3DTSV interconnects have many possibleimplementation scenarios ranging fromwhen in the process flow (first, middle,or last) the via is formed, to whichprocess is used in its creation (e.g.front, or back-side). Another keychallenge is I/O standardizationbetween memory and applicationlayers. Lastly, as package complexity

Jetting Your Way to Fine-pitch 3D InterconnectsBy Mike O’Reilly [Optomec, Inc.] and Jeff Leal [Vertical Circuits Inc.]

A increases, thermal management maybecome a troublesome issue. Yes, TSVholds lots of promise, but the factremains: manufacturing challenges areyet to be fully addressed.

Can wire-bond solutions continue tomeet system-in-package (SiP) scalingdemands? While wire bonding attemptsto address growing interconnect densitychallenges _ the overall diameter ofthe bonding wire is <35μm andequipment placement accuracy isimproving _ the sheer number ofinterconnects between memory stacked8-16 chips high present both performanceand manufacturing challenges. Issues,such as signal integrity, become realshow stoppers as customers pushperformance goals of these devices. Thechallenge is exacerbated when stackingsophisticated multi-chip packages thatintegrate processors. While wire-bondtechnology remains viable for themajority of today’s semiconductorinterconnect applications, it may bereaching an inflection point as 3Dpackaging demands push thefunctionality envelope.

Is there another way to meet theseadvanced packaging challenges withouthaving to completely reinvent manufacturingprocesses and technologies?

Replacing traditional wire bonds withfully printed conformal interconnectsusing evolutionary packaging steps maybe the answer to these complex issues.A proprietary aerosol jet technology hasbeen used in a variety ofprinting applicationsranging from crystallinesilicon solar wafers andnext-generation touchscreen displays, to fullyprinted transistors. Theability of this technologyto print a variety ofmaterials onto a widearray of substrates atfeature sizes as small as

10μm makes it a logical choice foraddressing fine-pitch semiconductorpackaging requirements.

Aerosol Jet Process - How it WorksAerosol jet1 printing begins with

atomization of an ink, which can beheated up to 80°C, producing dropletson the order of one to two microns indiameter. The atomized droplets areentrained in a gas stream and deliveredto the print head, which also can beheated to 80°C. Here, an annular flowof clean gas is introduced around theaerosol stream to focus the droplets intoa tightly collimated beam of materialthat also serves to eliminate nozzleclogging. The combined gas streamsexit the print head through a convergingnozzle that compresses the aerosolstream to a diameter as small as 10μm.The jet of droplets exits the print headat high velocity (~50 m/s) and impingesupon the substrate. Electrical interconnectsare formed by moving the print head,equipped with a mechanical stop/startshutter, relative to the substrate. Allprinting occurs without the use ofvacuum or pressure chambers and atroom temperature.

The high velocity of the jet enables arelatively large separation between theprint head and the substrate, typically 2-5mm (Figure 1). The droplets remaintightly focused over this distance,resulting in the ability to print conformalpatterns over three dimensional

FFFFFigure 1.igure 1.igure 1.igure 1.igure 1. Aerosol jet print head


substrates such as stacked die. Despitethe high velocity, the printing process isgentle; substrate damage does not occurand there is generally no splatter oroverspray from the droplets.

Once patterning is complete, theprinted ink typically requires post-treatment to attain final electrical andmechanical properties. Post-treatmentis driven more by the specific ink andsubstrate combination than by theprinting process.

The atomization step is very flexiblecompared to inkjet. Particulatesuspensions are easily atomized,although as a general rule, suspendedparticles should be on the order of 0.5μmor less. Ink viscosity may be in the rangeof 1-1000 cP, although it may benecessary to optimize the viscosity for aparticular application. The materialsused to construct the printing systemhardware are generally not susceptibleto degradation by the ink solvents,allowing a wide range of solventvehicles to be used in the process.

Direct Write of InterconnectsThe relatively large working distance

(the distance from the print tip to thesubstrate) of the aerosol jet print headenables conformal printing alongstacked dies of 2mm or less in totalheight without having to adjust Z-heightpositioning. Typical interconnects are25-30μm wide by >5μm in height. Totallength of the interconnects are typically1.5mm long with throughput for a singlenozzle reaching up to 5,000interconnects per hour (Figure 2). Theaerosol jet print head is highly scalable,

supporting 2, 3, 5,or more nozzles ata t ime, enablingprojected throughputsof > 20,000 or moreinterconnects perhour. The print headcan handle extendedprint runtimes oftwelve hours ormore before inkrefill is required.An automated inkrefill system thatwill extend inkruntime to twenty-four hours or moreis under development.

Automation IntegrationThe aerosol jet print engine has been

integrated into an electronics automationsupplier’s production proven platform(Figure 3). The automation platformaccommodates the print engineincluding the atomizer and print head,heater, shutter, and process controls.Additionally, the automation platform isequipped with auto-fiducial synching;shutter cleaning station; motion controlwith +/- 5μm of accuracy; heated platento 150° C; auto board load and unload;and GUI driven interface with on boardsystem diagnostics. The platform ishighly scalable and capable ofsupporting evolving semiconductorpackaging form factors.

A Working ProcessThis novel solution is suited for

printing fine featured interconnects andother materialsmeeting demandingm a n u f a c t u r i n gs p e c i f i c a t i o n s .However, printingis only one step inthe manufacturingof fully functioningSiP’s using thevertical interconnectpillar (VIP) process.2In addition to industrystandard packagemanufacturing steps,five additional steps

(Figure 4) that fully enable theimplementation of fine-pitch verticalinterconnect printing are necessary andinclude surface fillet, parylene coating,laser ablation, surface treatment, and fine-pitch vertical interconnect.

Typical print inks tend to flowdownhill regardless of their viscosity.The surface fillet (Figure 4) is used tocreate a gentle sloped surface on thestacked die, typically creating 45-60°inclines, which prevent the materialfrom free flow at steep angles. Theparylene coating is applied to the entirestack and then an excimer laser is usedto open specific pads on the dies andsubstrate where an electrical connectionis required. A surface treatment is usedto clean away ablated material andchange the surface tension to enableprinting of fine-pitch vertical interconnectswithout shorting between parallel lines onthe stacked die over 3D topology.

Using inks that meet both mechanicaland electrical requirements is key to thefine-pitch interconnect process. These

FFFFFigure 2.igure 2.igure 2.igure 2.igure 2. Vertical interconnect package

FFFFFigure 3.igure 3.igure 3.igure 3.igure 3. Integrated aerosol jet print solution

FFFFFigure 4.igure 4.igure 4.igure 4.igure 4. Vertical interconnect pillar (ViP) process

FFFFFigure 5.igure 5.igure 5.igure 5.igure 5. Aerosol jet printed interconnect


inks must be capable of extended 8+hour production runs without anychanges in output rates or electricalcharacteristics. They need to stackproperly without overspray or satellites,maintaining mechanical dimensionsthroughout the course of amanufacturing shift. As direct-writeprinted electronic applications continueto grow, a new class of nanoparticleelectrically conductive materials (inks)

has found its way into the market, fullymeeting manufacturing specifications.

As interconnects are printed fromboard connectors along the die stack,they come into contact with the laserablated (exposed) pads and createelectrical connections. A single printedinterconnect may connect with openingson several die, thereby creating a morecompact electrical connection andefficient circuit (Figure 5).

With wire bond, interconnects extendfrom one pad to another, requiring theneed for multiple physical wires to createa complete pad-to-pad circuit. Aspackage densities increase the numberof wire-bond connections increase,creating the potential for cross talk and/or signal integrity challenges within SiPpackages. This may force a vendor toslow the operational efficiency of thecircuit and limit full device functionality.

Validating the processThe steps in the ViP process have

been optimized over the past twelvemonths. Each process step has beenfully analyzed and optimized for SiPpackages. Actual boards filled withfunctioning SiP’s have gone throughthe proprietary process s teps,including the aerosol jet fine lineinterconnect print step with printedconformal interconnects of 25-30μmwide by > μm high, and ful lyfunct ioning parts have beenmanufactured.

Any product that will be commerciallysold needs to pass industry standardreliability testing (Figure 6). Completeproduct qualification tests are underwaythat will re-validate the process andproduct by Q3 of 2010. Pilot productionsites are due online before the end of2010, with full, high-volume productionsystems available by Q1 2011.

Expanding CapabilitiesFine line printing for SiP technology

is just at the beginning of its life cycle.When direct write ViP technology wasintroduced more than two years ago,the minimum line width was 100μm,with a pitch of 200μm. With theintroduct ion of the aerosol je ttechnology, line widths of 25-30μm arebeing achieved with pitches of <65μm. With further refinement of thetechnology, line widths as small as 10-15μm at 25μm pitch are expected tobe possible.

Aerosol jet technology also has theadded benefit of printing a wide arrayof materials. Investigation is underwayfor utilizing the process to print adielectric material coating to selectivelyinsulate pads. The benefit of this

http://www.aztechdirect.com


FFFFFigure 6.igure 6.igure 6.igure 6.igure 6. VCI reliability test criteria

Moisture Resist

Test:

Biased-HAST:

Autoclave/PCT:

High Temp

Storage:

Temp Cycle:

Card Tests:

(DBT/Insert/Salt)

VCI DRAM

(BGA)

Pass ServerLevel Reliability

JEDEC Level 3 @260oC

Bias 3.6V, 130oC,85% RH, 144

hours

Unbiased, 121oC,2atm, 100%RH,

96 hours

150oC,1000 hours

-55/+125oC,1000 cycles (B)

N/A

VCI FLASH

(LGA)

PASS


Bias 3.6V, 130oC,85% RH, 96

hours


96 hours

150oC,1000 hours

-55/+125oC,1000 cycles (B)

N/A

VCI SiP

(BGA)

Under Qual


Bias 3.6V, 130oC,85% RH, 96

hours


96 hours

150oC,1000 hours

-55/+125oC,1000 cycles (B)

N/A

VCI FLASH

(µSD)

PASS


Bias 3.6V, 130oC,85% RH, 96

hours

NO

150oC,1000 hours

-55/+125oC,1000 cycles (B)

SDI Spec.

approach is further reduction in process and equipment costs.Other areas, such as surface fillet printing and printingredistribution layers (RDLs) with this process are also beingexplored.

Viable Interconnect AlternativeWire-bond solutions will not just fade away and TSV is

emerging as the solution for the most complex packagingchallenges. However there is the middle ground where 3Dprinted interconnects can provide real cost and functionalbenefits for the production of multi-chip stacked die in SiPapplications. Aerosol jet’s fine line printing capabilities enablesignificant pitch reductions, thereby increasing interconnectdensities and affording greater semiconductor packagingfunctionality at a fraction of the cost of TSV technology. Withits ability to use off-the-shelf materials and print in normalatmospheric conditions, equipment and maintenance costs aregreatly reduced. This multi-function platform is clearly poisedto enable high density interconnect solutions for a range ofadvanced 3D semiconductor packaging applications.

References1. Aerosol Jet is a trademark of Optomec, Inc.2. Vertical Interconnect Pillar process is a trademark of VerticalCircuits, Inc.

For questions concerning the Aerosol Jet print solution, emailthe company at [email protected] processes described in this article are the subject matterof a number of granted patents and pending patent applications.Vertical Circuits offers licenses to those wishing to practice thistechnology. Contact VCI at (831) 438-3887ext. 102, or [email protected] for more information.

http://www.craneae.com


and 1mm distance left from each of thesix packages.

Figure 1b shows the finite elementmodel of the cross section ofthe corner joint for a WLCSPstructure. The basic settingincludes a 2.7μm thickaluminum pad, 2μm thickUBM with 0.5μm Au and0.2μm Cu, and a 0.9μm thickpassivation that covers 5μmof the edge of the aluminumpad. A 10μm thick polyimidelayer is above the passivationand the aluminum pad. Thereis a 200μm diameter viaopen in the polyimide layer;

T he trends in next generationwafer-level chip-scalepackages (WLCSPs) are

toward thinner and finer pitches withmicrobumps. The mechanical shockresulting from mishandling duringtransportation or customer usage maycause WLCSP package solder jointfailures.1 Since the board-level drop testis a key qualification test for portableelectronic products, it is becoming atopic of great interest for manyresearchers.2-4 Most of the drop test andmodeling works focus on the failuremodes of solder joints. The impact ofother aspects of WLCSP design has notyet been fully investigated. Thiscomprehensive study, with modelingand testing, investigates the WLCSPdesign and its drop test reliability. Theresults of varying WLCSP designparameters such as under-bumpmetallization (UBM) geometry,polyimide side wall angle andthickness, metal stack thickness, andsolder joint height are documented.

WLCSP Drop Test and Model Set UpThe drop test set up is based on

JEDEC standard JESD22-B111.5 Theboard, with a dimension of 132 x 77 x1.0mm, accommodates 15 componentsof the same type in a three-row-by-five-column format. Due to the symmetry, aquarter finite element model (66 x 38.5x 1mm) of a JEDEC board with WLCSPchips is selected. Figure 2 shows afinite element model of the lower leftquarter of the test board with sixcomponents (U1, U2, U3, U6, U7, U8)that are numbered according to theJEDEC standard. The line AB in Figure1a is defined across the board at adistance of 1mm from the edges ofcomponents U1, U2, and U3. There aresix corner points on the PCB defined1mm below each of the six packages

Drop Test Reliability and Design of Wafer-LevelChip-Scale PackagesBy Yong Liu, Stephen Martin [Fairchild Semiconductor Corp], and Luke England [Micron Technology]

FFFFFigure 1a.igure 1a.igure 1a.igure 1a.igure 1a. Finite element model of quarter PCBwith chip units (U1, U2, U3, U6, U7, U8)

FFFFFigure 1bigure 1bigure 1bigure 1bigure 1b..... Finite element model of the crosssection

its side wall angle (between its slope andthe bottom surface) is 60 degrees. TheUBM connects to the aluminum padthrough the via. The solder is placed onthe UBM and connects to the copperpost on the PCB board.

Table 1 defines the elastic modulus,Poisson ratio, and density of eachmaterial. The silicon, passivation,polyimide, PCB, and UBM areconsidered as linear elastic materials,while the solder ball, aluminum pad,and PCB copper pad are considered ashaving non-linear material properties.

TTTTTableableableableable 11111..... Elastic modulus, Poisson ratio, and densityof each material

TTTTTableableableableable 22222..... Rate-dependent Peirce model of solderSAC405

Modulus(Gpa)13126.383143.5Ex=Ey=25.42Ez=11Gxz=Gyz=4.91Gxy=11.4511768.9196

SiliconSolderPassivationPolyimide

PCB

Cu PADAl PADUBM

PoissonRatio0.2780.40.330.35Nuxy=0.11Nuxz=Nuyz=0.39

0.330.330.304

Density(g/cm3)2.337.52.991.47

1.92

8.942.79.7

Yield stress (Mpa)41.85Solder

(SAC405)

γ0.00011

m0.0953

FFFFFigure 2.igure 2.igure 2.igure 2.igure 2. Comparison of maximum peeling stress at U1 withdifferent polyimide side wall angles


Table 2 gives the non-linear propertiesfor solder SAC405 and is consideredas a rate-dependent Peirce model. Thedata was obtained through theHopkinson dynamic material highspeed impact test.

Impact of Polyimide Side Wall AngleThe polyimide layer connects both

the aluminum pad and UBM (Figure1b). Figure 2 shows the maximumpeeling stress comparison of the solder,copper pad, and aluminum pad withdifferent polyimide side wall angles atlocation U1.

The stresses in the copper pad,aluminum pad and solder interfaceconnected to the copper pad show thatthere is no significant difference withdifferent polyimide side wall angles.However, there is an impact on the solderjoint interface that adheres to the UBM.

Impact of Polyimide ThicknessThe polyimide thickness is selected to

be 5μm, 10μm, and 15μm respectively.

Figure 3 shows the peeling stress for thesolder, copper pad, and aluminum padwith different polyimide thickness atlocation U1.

The peeling stress on the aluminumpad increases as the polyimidethickness increases from 5μm to 15μm.The solder stress at the interface withthe UBM decreases as the polyimidethickness increases from 5μm to 10μm.However, after 10μm there is nosignificant difference.

Impact of the UBM StructureA copper UBM structure is designed

to compare with the existing 2μm nickelstandard UBM having 0.5μm Au and0.2μm Cu. The thickness of the copperUBM is 8μm. Figure 4 shows thepeeling stress comparison for the solderjoint, copper pad, and aluminum padwith copper UBM and with the standardUBM of the package at location U1.From Figure 4 it can be seen that thepeeling stress on the solder jointinterface attached to the standard UBM

is greater than that attached to thecopper UBM. However, the peelingstress on the Al pad with copper UBMis greater than the standard UBM.

Impact of Aluminum Pad ThicknessDifferent aluminum pad thicknesses

(0.8μm, 2μm, 2.7μm, 4μm) aresimulated.

Figure 5 gives the polyimide stressesversus the Al pad thickness and itscorrelation with the drop test life (blackdotted line). There is an optimal Althickness from both modeling and droptest results.

Impact of Solder Joint HeightDifferent solder joint heights (50μm,

100μm, 200μm, 300μm) are considered.Figure 6 gives the trends of solder jointplastic energy density with differentheights.

In all three package locations, highersolder joints result in less plastic energydensity. This indicates that a highersolder joint can help to improve the

FFFFFigure 3.igure 3.igure 3.igure 3.igure 3. Comparison of maximum peeling stress at U1 for different polyimidethicknesses

FFFFFigure 4.igure 4.igure 4.igure 4.igure 4. Comparison of maximum peeling stress at U1 with two differentUBM designs

FFFFFigure 5.igure 5.igure 5.igure 5.igure 5. PI stress versus Al pad thickness FFFFFigure 6.igure 6.igure 6.igure 6.igure 6. Plastic energy density of solder joint (MPa)


FFFFFigure 7.igure 7.igure 7.igure 7.igure 7. Drop test result FFFFFigure 8.igure 8.igure 8.igure 8.igure 8. Drop test failure mode

WLCSP drop test dynamic plasticenergy performance.

Drop TestThe drop test condition is 1500g with

half sine wave in 0.5ms. Drop count is1000. A total of 90 units are investigatedand mounted on eight JEDEC PCBs intwo groups, one with vias and the other

without vias under the copper pads. Thedrop test results are shown in Figure 7and Figure 8. From Figure 7 it can beseen that most of the drop failures appearat the corner locations U5, U11, and U15.Figure 8 shows the copper pad/crackwhich occurs at the interface of the solderand copper at the PCB. The test resultscorrelate with the simulation result that

the maximum first principal strainappears at the location of U1 which hasthe same behavior as U5, U11, and U15due to the model’s symmetry. Figure 9gives the first principal strain curves atthe interface of the copper pad, solder,and PCB with the package locations U1,U3, and U8. The failure rank isU1>U3>U8. When the dynamic first

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FFFFFigure 9.igure 9.igure 9.igure 9.igure 9. First principal strains of the copper pad at the interface of the solder,copper pad, and PCB for package locations U1, U3, and U8

principal strain reaches the failure strain,the copper pad/trace will break/crack.

ConclusionThis WLCSP design variable modeling

and test study investigate the dynamicbehavior of WLCSPs subjected to dropimpact by varying the following designparameters: polyimide side wall angle andthickness, UBM geometry, aluminummetal stack thickness, and solder joint

height. Both thedrop test andmodeling resultsshow that thecorner joints ofeach WLCSP chip(U1, U5, U11,U15) near the PCBscrew holes failfirst as compared tothe chips at otherlocations. Next tofail are the cornersolder joints of chiplocations U3 andU13, followed by

the U8 chip (center) and the rest of thechips. The failure mode is shown to becracking at the interface betweenSAC405 solder and the copper pad/trace,as well as cracking of the copper trace. Thetest results correlated with the simulationfor the failure modes and the PI stress trendswith different Al pad thickness. In addition,the solder joint height can significantlyimprove the drop test dynamic plasticenergy performance of WLCSPs.

AcknowledgmentsThe authors wish to thank the support

of Fairchild Semiconductor and especiallythe Package Development Group in SouthPortland, ME, and Bucheon, Korea.

References1. Lai, Y.S., Yang, P.C., Yeh, C.L.,“Effects of Different Drop TestConditions on Board-level Reliability ofChip-scale Packages,” MicroelectronicsReliabilityl, Vol. 48, 2008.2. Luan, J.E., Tee, T.Y., “Drop ImpactSimulation Using Implicit Input-GMethod,” 5th ANSYS Asian Conf., 20053. Dhiman, H.S., Fan, X.J., and Zhou, T.,JEDEC Board Drop Test Simulation forWafer Level Packages (WLPs), ECTC59,20094. Ranouta, A.,S., Fan, X.J. and Han Q.,Shock Performance Study of SolderJoints in Wafer Level Packages, ICEPTConference Proc., 2009, China.5. JEDEC standard JESD22-B111:Board Level Drop Test Method ofComponents for Handheld ElectronicProducts, 2003.

http://www.arieselec.com


M oore’s law has been themost powerful driver forthe development of the

microelectronics industry. This lawemphasizes lithography scaling andintegration (in 2D) of all functions on asingle chip, perhaps through system-on-chip (SoC). On the other hand, theintegration of all these functions can beachieved through 3D IC integrationsystem-in-package (SiP), (Figure 1).1-8

As Moore predicted in 1965, siliconchips are getting larger while incorporatinga higher pin-count and finer pad-pitch.3-7

Unfortunately, conventional substrateswith build-up layers made by organicmaterials, such as bismaleimide triazine(BT), are facing great challenges insupporting this. To address these issues,silicon interposers with high-densitythrough silicon vias (TSVs), redistributionlayers (RDLs), and integrated passivedevices (IPDs) have emerged as a viablesolution to provide high wiring densityredistribution and interconnection.1-5

TSVs are the heart of 3D ICs, and inaddition to being used for stackingmemory chips, they can be used in apassive interposer to support ultra-fine

3D IC Integration with TSV Interposers for High-Performance ApplicationsBy John H. Lau, [Electronics & Optoelectronics Labs (EOL), Industrial Technology Research Institute (ITRI)],and Y. S. Chan and S. W. Ricky [Hong Kong University of Science and Technology]

pitch, high pin-count, high-power, andhigh-density IC chips; and in activeinterposers such as logic, microprocessors,and high-bandwidth memories.3-7 Forexample, Figure 2a shows a conventionalface-down plastic ball grid array (PBGA)package, in which the chip is supportedby a high-density BT-substrate with build-up layers connected through microvias.9

As the chip gets bigger and its pitch getssmaller, the BT substrate can no longersupport it.9 Hence, an intermediatesubstrate is needed (e.g., the passive TSV/RDL/IPD interposer) to redistribute thearray of fine-pitch pads on the chip tofewer and relatively larger pitch pads ona simpler and thinner BT substratewithout any build-up layers (Figure 2b)to achieve a smaller footprint with betterperformance. The packaging system inFigure 1b is called the 2.5D ICintegration SiP.

Figure 3 demonstrates the ultimategoal of a high-power, high pin-count, andfine-pitch CPU and memory chipsstacked together to address the memorybandwidth challenge. In this case, theCPU acts like an active TSV interposer.However, due to the very high device

density and the complexity of the circuitson the CPU and memory, finding places/spaces to “drill” holes (TSVs) is verydifficult, as shown in Figure 4. Besidesthe tiny devices such as transistors (whichcannot be seen in this SEM image), thereare many tiny vias (< 0.1μm) on a chip.They are connected to devices (e.g., 4 tinyvias for each transistor) to build the firstmetal (M1) layer. Today for many chips,the number of these tiny vias alreadyexceeds the world population of over 7billion. One of the core competences andmajor businesses of foundries is to makethese tiny vias. They are not the same TSVfor 3D IC integration.

Additionally, the CPU and memorychip sizes and number of pin-outs maydiffer. Forcing them to attach reducesdesign freedom and could compromisefunctionality. Longer routings may beneeded in the TSV CPU and memorychip, which affects performance. Mostimportantly, the required TSVmanufacturing yield is too high(>99.99%) for the TSV CPU to bearadditional costs due to yield loss.10 Thus,a passive TSV interposer connecting theCPU and memory in certain 3D

FFFFFigure 1.igure 1.igure 1.igure 1.igure 1. Moore’S law vs. more-than-MooreFFFFFigure 2.igure 2.igure 2.igure 2.igure 2. (a) Conventional face-down PBGA. (b) Face-down PBGA with a passive TSV

interposer (2.5D IC integration)


FFFFFigure 3.igure 3.igure 3.igure 3.igure 3. CPU/logic as an active TSV interposer to support a memory/logic (3DIC integration)

FFFFFigure 4.igure 4.igure 4.igure 4.igure 4. Vias (not TSVs for 3D IC integration) in a chip

FFFFFigure 5.igure 5.igure 5.igure 5.igure 5. Thermal-enhanced and cost-effective 3D IC integration SiP (withoutTSVs on active chips) supported by a passive TSV interposer with RDL and IPD

configurations could be effective inresolving these issues.

Thermal management is critical to 3DIC integration because 3D circuitsincrease total power generated per unitsurface area; chips in the 3D stack mayoverheat if proper and adequate coolingis not provided; the space between the 3Dstack may be too small for coolingchannels; and thin chips may createextreme conditions for on-chip hot spots.Thus, low-cost and effective thermalmanagement solutions are desperatelyneeded for widespread use of 3D ICintegration SiPs. 11, 12

Design PhilosophyThis design addresses the electronic

packaging of 3D IC integration with apassive TSV interposer for high-power,high-performance, high pin-count, ultrafine-pitch, small real estate, and low-costapplications. To achieve this, the designuses chip-to-chip interconnectionsthrough a passive TSV interposer in a 3DIC integration SiP format with excellentthermal management. Rather than“digging holes” (TSVs) on active

(devices) chips,existing dies with apassive TSV interposerare used to:a) Provide verticalelectrical feed throughinterconnections.b) Perform redistributions (to fan out highpin-out and ultra fine-pitch circuitries).c) Provide decoupling (to enhance theelectrical performance).d) Connect to the next level of interconnects(e.g., the package substrate with fewer pin-outs and coarse pitches).e) Construct a cost-effective thermalmanagement system (e.g., heat spreader/sink).

Why not dig holes on the active chipsnow? Besides the technology issuesmentioned earlier, electronic designautomation (EDA) tools for 3D IC, arenot ready. Because the ecosystem (e.g.,infrastructures and standards) of 3D ICdoes not yet exist, this area cannot beworked on seriously and with full-force.

The New DesignThis 3D IC integration SiP (Figure 5)

features a siliconinterposer with high-density TSVs, RDLs,and IPDs that connectvarious chips withpads that have differentpitches, sizes, andlocations. A simple,organic substratewith standard (insize and pitch) solderballs for PCBassembly supports thepassive interposer.

All the high-power chips _ such as themicro-processor unit (MPU), graphicprocessor unit (GPU), applicationspecific IC (ASIC), digital signalprocessor (DSP), micro-controller unit(MCU), radio frequency (RF), and high-power memory chips, (Figure 6) _ areon top of the TSV interposer in a flip-chip format so that the backside of thesechips can be attached to a heat spreadervia a thermal interface material (TIM).In this case, most of the heat from thehigh-power chips can be dissipatedthrough the heat spreader (with a heat sinkif it is necessary). All low-power chips_ MEMS, OMEMS, CMOS imagesensors, and memory chips (Figure 6) _are at the bottom-side of the interposerwith either flip-chip or wire-bond formatsor both. A ring-stiffener connecting theorganic substrate and the heat spreaderprovides adequate standoff for 3D ICintegration with the passive interposerand to support the heat spreader with orwithout the heat sink. Underfillencapsulants are needed between the TSVinterposer and the high- and low-power flipchips, and between the TSV interposer andthe BT substrate. However, underfill is notneeded between the 3D IC integration SiPand the PCB. For wire bonding chips,encapsulants may be needed.

This proposed 3D IC integration SiPis very attractive to integrated devicemanufactures (IDMs), original equipmentmanufacturers (OEMs), and electronics


FFFFFigure 6.igure 6.igure 6.igure 6.igure 6. The passive TSV interposer with RDL and IPD supporting high-powerchips on the top and low-power chips at its bottom

Low-power chips at the bottom-side (showing face up) of the passiveinterposer

FFFFFigure 7.igure 7.igure 7.igure 7.igure 7. Dimensions of the passive TSV interposer with 4 high-power flip chips on its top and 16 low-power flip chips at its bottom (the gist of the 3D IC integration SiP.)

manufacturing services (EMS) because itis a standard face-down PBGA packageand has been used by the electronicindustry for more than 15 years.13 It’s notonly effective in thermal management, butits solder joints are very reliable.14, 15

Therefore, in conjunction with the properdesign of the high-power and low-powerchips above/below the passive TSV/RDL/IPD interposer inside the package, a cost-effective, 3D IC integration SiP that displayshigh electrical and thermal performance canbe achieved and manufactured.

The thickness of the proposed TSV/RDL/IPD passive interposer should be<200μm, the thinner the better. Thus thin-wafer handling methods are required forthe passivation, metallization and/orwafer bumping processes. Fortunately, byusing the passive interposer, thin-waferhandling is not necessary for the TSV-less high- and low-power chips.

A 3D IC Integration SiP Design ExampleFigures 7 and 8 show a design example

for detailed analysis of a 3D IC integrationSiP that consists of 4 identical high-powerchips (e.g., microprocessors) uniformlydistributed on the top-side of a TSV/RDL/IPD interposer and 16 identical low-powerchips (e.g., memories) uniformly distributedat the bottom-side. (This design can bedegenerated for the case shown in Figure3.) The dimensions of the high-power chipsare 10mm x 10mm x 200μm, the low-power chips are 5mm x 5mm x 200μm,and the interposer’s dimensions are 35mmx 35mm x 200μm. There are 1600 identicalTSVs with 20μm diameter and 850μm

pitch. The backsidesof the high-powerchips are attached toa heat spreaderthrough a 100μm TIM.An aluminum heatsink with 21 uniformlydistributed fins isattached to the back ofthe heat spreader.Special underfill isused between the TSVinterposer and thehigh- and low-powerflip chips.Ordinaryunderfill is usedbetween the TSV

interposer and the organic substrate.Encapsulant is needed for the wirebondingmemory stack.

The 3D IC integration SiP mentionedin Figure 8 is attached (with ordinarysolder bumps) to a BT-substrate (44mm x44mm x 0.8mm with a cavity of 33mm x33mm x 0.8mm.) The substrate is alsoconnected to the heat spreader with theheat sink through an aluminum ring-stiffener as shown in Figure 8. Then, thesubstrate is lead-free (SnAgCu) solderedon a FR-4 PCB (50mm x 50mm x 2.5mm).Nonlinear finite element modeling andanalyses of the temperature distributionsand creep strain energy density pertemperature cycle have been reported andshows that with proper selection of the heatsink and underfills, the micro-bumps andsolder joints are reliable for most of theoperation conditions.16

Summary and RecommendationsA generic, low-cost and thermal-

enhanced 3D IC integration SiP has beenproposed for high performance applications.Also, a special design has been providedfor demonstration. Here is a summary ofthe important results and somerecommendations.(1) The TSV/RDL/IPD passive interposer,which supports the high-power chips on topand low-power chips at its bottom, is thegut and workhorse of the current design.(2) With the passive interposer, it is notnecessary to ‘dig’ holes on the active chips.In fact, try to avoid making TSVs in theactive chips.(3) Using a passive interposer allows forflexible coupling of available and/ornecessary chips, enhances functionality,and shortens routing.(4) Current TSV manufacturing yield lossmakes it cost prohibitive to put TSVs inactive chips. Using a passive interposeris a cost-effective alternative.(5) Wafer thinning and thin-wafer handlingcosts (for the interposer) are lower becausethese are not needed for the active chipsand thus adds no additional cost due toyield loss.(6) With the current designs, all the chipsare bare; the packaging cost for individualchips is eliminated.(7) More than 90% of heat from the 3DIC integration SiP is dissipated from theback-side of high-power chips using aTIM and heat spreader/sink.(8) The appearance and footprint ofcurrent 3D IC integration SiP designs are


FFFFFigure 8.igure 8.igure 8.igure 8.igure 8. Overall dimensions of the 3D IC integration SiP with heat spreader and sink

very attractive to IDMs, OEMs, and EMSbecause they are standard packages.(9) Underfills between the copper-filledTSV interposer and the high- and low-power chips are recommended to reducecreep damage of the lead-free micro-bump joints and prolong their lives.(10) The industry should build anecosystem incorporating standards andinfrastructure for 3D IC integration sothat EDA vendors can create the softwarefor design, simulation, analysis andverification, manufacturing preparation,and test of 3D IC integration SiP.(11) IC integration SiP.(12) A roadmap for heterogeneous 3D ICintegration that integrates passive andactive interposers (not including memorystacks) has been established. (Figure 9).

AcknowledgementThe author (JL) would like to thank

HKUST fo r the fund : DAG08/09.EG12. He also would like to thankDr. Ian Yi-Jen Chan of Electronics

& Optoelectronics Labs of ITRI forhis strong support.

References1. Lau, J. H., “State-of-the-art and Trendsin 3D Integration”, Chip Scale Review,March/April, 2010, pp. 22-28.2. Andry, P. S., Tsang, C. K., Webb, B.C., Sprogis E. J., Wright S. L., Bang, B.,Manzer, D. G., “Fabrication andcharacterization of robust through-siliconvias for silicon-carrier applications,” IBMJournal of Research and Development,,Vol. 52, No. 6, 2008, pp. 571-581.3. Lau, J. H., Reliability of RoHSCompliant 2D & 3D IC Interconnects, tobe published by McGraw-Hill.4. Lau, J. H., C. K. Lee, C. S. Premachandran,A. Yu, Advanced MEMS Packaging,McGraw-Hill, New York, NY, 2010.5. Lau, J. H., “Critical Issues of 3D ICIntegrations”, Proceedings of IMAPSInternational Symposium on Microelectronics,San Jose, CA, November 2009, pp. 585-592. and IMAPS Transactions, Journal of

Microelectronics andElectronic Packaging,First Qusrter Issue,2010, pp. 35-43.6. Lau, J. H “Designand Process of 3DMEMS Packaging”,Proceedings ofIMAPS InternationalS y m p o s i u m o nMicroelectronics, SanJose, CA, November2009, pp. 1-9. and

IMAPS Transactions, Journal ofMicroelectronics and Electronic Packaging,First Qusrter Issue, 2010, pp. 10-15.7. Lau, J. H., Lee, R., Yuen, M., and Chan,P., “3D LED and IC Wafer LevelPackaging”, Journal of MicroelectronicsInternational, Vol. 27, No. 2, 2010, pp.98-105.8. Hu, G., Kalyanam, H., Krishnamoorthy,S., and Polka, L. “Package technology toaddress the memory bandwidth challengefor tera-scale computing.” Intel TechnologyJournal, Vol. 11, 2007, pp. 197-206.9. Lau, J. H., and R. S. W. Lee, Microviasfor Low Cost, High Density Interconnects,McGraw-Hill, New York, NY, 2001.10. Lau, J. H., “TSV Manufacturing Yieldand Hidden Costs for 3D IC Integration”,IEEE Proceedings of Electronic,Components & Technology Conference,Las Vegas, NV, June 2010, pp. 1031-1041.11. Yu, A., N. Khan, G. Archit, D. Pinjalal,K. Toh, V. Kripesh, S. Yoon, and J. H. Lau,“Development of silicon carriers withembedded thermal solutions for highpower 3-D package.” IEEE Transactionson Components and PackagingTechnology, Vol. 32, No. 3, September2009, pp. 566-571.12. Tang, G., O. Navas, D. Pinjala, J. H.Lau, A. Yu, and V. Kripesh, “IntegratedLiquid Cooling Systems for 3-D StackedTSV Modules”, IEEE Transactions onComponents and Packaging Technologies,Vol. 33, Issue 1, 2010, pp. 184-195.13. Lau, J. H., Ball Grid Array Technology,McGraw-Hill, New York, NY, 1995.14. Lau, J. H., T. Chen, and R. Lee,“Effect of Heat Spreader Sizes on theThermal Performance of Large Cavity-Down Plastic Ball Grid Array Packages”,ASME Transactions, Journal ofElectronic Packaging, Vol. 121, No. 4,1999, pp. 242-248.15. Lau, J. H., with R. Lee, “SolderJoint Reliability of Cavity-DownPlastic Ball Grid Array Assemblies”,Journal of Soldering & Surface MountTechnology, Vol. 10, No. 1, February1998, pp. 26-31.16. Lau, J. H., Y. Chan, and R. Lee,“Thermal-Enhanced and Cost-Effective3D IC Integration with TSV (Through-Silicon Via) Interposers for High-Performance Applications”, ASME Paperno. IMECE 2010-40975.


Wafer Scribing & Dicing...Which Method? Equipment?By Gil Olachea [Az Tech Direct, LLC, [email protected]]

O kay, what’s your preferredmethod for singulatingwafers into die? Sawing?

Laser cutting? Laser or mechanicalscribing and breaking? Do you reallycare? If you’re an OEM, does it matter?If you’re in the assembling/packagingend of the business, is this your issue?Ever see a flow chart or generic processspec on how and what happens with thewafer when it is received by thepackaging foundry? Most of thesedocuments simply state wafers are tobe singulated ... some documents willsplit-out wafer taping, however theydon’t precisely identify sawing, scribe/break, laser or another dicing processto be employed.

Now, let’s re-think the question, “...does it really matter what singulationprocess is chosen?” If you produce III-V semiconductors, MEMS, RFID’s,ultra-thin (25-50um) wafers, small die(<1x1mm2) you now do care! Why?Because conventional sawing or

scribing may introduce other issuesrelative to the yield, cost, performanceor reliability of the semiconductordevices downstream.

This article will introduce you tothe International Directory of WaferScribing and Dicing Systems ... acomprehensive supplier listing offully or semi-automated equipmentused in s ingula t ing wafers in toindividual die, or in some casessingulating individual I.C. packagesfrom molded package arrays.

The greatest market for semiconductorsingulation equipment is in diepreparation for package assembly.Industry estimates fluctuate between 70to 80% in favor of wafer singulation vs.package singulation, so let’s focus onwafer singulation. “DISCO’s marketsplit is about 70% in semiconductorsand the remaining balance in othermarkets, including medical, automotive,hi-brightness LEDs, and MEMs,”shares Devin Martin of DISCO Hi-Tec America.

The majority of wafer singulation isperformed by way of sawing. For manyyears this has been a stable, reliable andlow-cost process. It continues toaddress wafer advances of decreasingwafer thickness, denser dice, complexmetal interconnects, new dielectrics,back-metal systems, and so-forth.Improvements in saw blades and sawhardware/software continue to marvelus in their ability to keep pace with semiadvancements.

I attempted to obtain roadmaps forwhere the market is proceeding in saw,scribe, laser; i t was virtuallyimpossible. Even the internal maps are

imprecise. Since the semi market is sodiverse, the equipment guys have adifficult time keeping pace.

“Consider the current challenges indicing: 300mm wafers, low-k dielectrics,copper interconnect, Gallium-anything(III-V materials), sensors, MEMS, sub-30μm street-width, back metals, CSPwith very dense bump fields, 3-D,thinner wafers, and so-on,” states HenryDeJonge, ALSI’s Director of NorthAmerican Sales. “Now couple theseissues with the ever-present demand onthe engineering talent required to stayahead of the tech-curve of process-related improvements needed to delivera clean die. It keeps me VERY busy!”

After-all . . . there’ve been no‘revolutionary’ developments that haveshifted the manner in which wafers are

DISCO’s Model DFL7161 fully auto-matic ablationlaser saw. (source: DISCO Hi-Tec America)

ALSI’s Model ICA1204 multi-beam, fully automatic,laser grooving system integrates cleaning/coating

stations, accepts 300mm wafers and offers a single-pass cutting process. (source: ALSI)


singulated into die. What’s that, yousay? “What about laser? That’srevolutionary!” I’ll argue the move tolaser technology is evolutionary _ ause of another method to accomplishthe same outcome.

Laser technology is a paradigm shiftfrom the conventional dicing processesand equipment _ predominantly saw/blade or scribe/break. A tremendousinvestment already exists with theseconventional forms of singulating diefrom wafers. Most packaging foundriesare very hesitant in replacing goodequipment with long service livesremaining. Squinting-eyed CFO’scarefully watch the profit line and ROI(return-on-investment) to assure capitaldollars are properly placed andredeemed. Advances in dicing sawequipment and consumables continue tokeep pace with the demand for narrower

street widths, which reduces the waferfab cost per die by yielding more diceper wafer, but more importantly extendsthe life of the capital investment in theconventional saw equipment.

So, selecting a laser dicing technologywould require additional or incrementalcapital. The other side of this view andfueling the laser choice are semiadvancements challenging conventionalsingulation processes. These are low-k dielectrics, narrowing streets, exoticsemi materials, and thinner wafers(<50um) to name a few. However, fewlaser solutions offer the throughputefficiency of a single-pass cut. Mostsolutions utilize a laser for a first-passshallow cut/scribe followed by either aconventional saw cut or breaking. Thiswill reduce productivity causing thatsquinty-eyed CFO to become evenmore critical and disjointed.

Additionally, lasers have introduceda few issues of their own ... the ablationlaser process leaves Si ‘slag’ on the diewalls thereby causing the die to ‘hinge’.Furthermore, the heat generated by thelaser (some are low power beam and/or water-cooled) can cause brittlenessnear the cut.

A couple of interesting technologiesto keep watch on are:1. “stealth” laser - a sub-surface cut usinga laser to avoid disturbing sensitivepatterns or metals in the streets;2. multi-beam lasers _ enabling single-pass cutting (a few exist today);3. Plasma etching _ very pricey, beingstaged to address the 450mm waferevolution.

So, what’s the answer? ... establishyour requirements, contact the suppliersin the following Directory, andcarefully assess your options!

http://www.contechsolutions.com


INTERNATIONAL DIRECTORY OF WAFER SCRIBING & DICING SYSTEMS

CompanyStreet AddressCity, State, CountryTelephoneWebsite

Note: CM = Contact Manufacturer

Advanced Dicing Technologies Ltd.Advanced Technology CenterHaifa 31095, IsraelTel: +972-4-854-5222www.adt-co.com

Advanced Laser Separation International N.V.Platinawerf 20-G6641 TL Beuningen (Gld), The NetherlandsTel: +31-24-678-2888www.alsi-international.com

Aremco Products, Inc.P.O. Box 517, 707-B Executive Blvd.Valley Cottage, NY 10989Tel: +1-845-268-0039www.aremco.com

Disco Corporation13-11 Omori-kita, 2-chome, Ota-kuTokyo 143-8580, JapanTel: +81-3-4590-1100www.disco.co.jp

Dynatex International5577 Skylane Blvd.Santa Rosa, CA 95403Tel: +1-707-542-4227www.dynatex.com

Electro Scientific Industries, Inc. (ESI)13900 NW Science Park DrivePortland, OR 97229Tel: +1-503-641-4141www.esi.com

EO Technics Co., Ltd.864-4 Kwanyang 2 Dong Dongan-ku, Anyang, KoreaTel: +82-31-422-2501www.eotechnics.com

Fonon Display & Semiconductor Systems400 Rinehart Road, Suite 1000Lake Mary, FL 32746Tel: +1-407-829-2613www.fonondss.com

Method L - Laser, M - Mechanical P - Plasma, S - Saw

Automation LU - Loading & Unloading WA - Wafer Alignment CD - Cleaning & Drying

Specifications (Max.) WD - Wafer Diameter FR - Feed Rate / Speed

Models (Qty)

Method: LaserAutomation: LU, WAWD: 300 mmFR: 1,000 mm/sModels (2)

Method: MechanicalAutomation: CMWD: 200 mmFR: 100 mm/sModels (1)

Method: LaserAutomation: LU, WA, CMWD: 100 mmFR: CMModels (4)




Models (Qty)

Method: SawAutomation: LU, WA, CDWD: 300 mmFR: 700 mm/sModels (3)

Method: SawAutomation: WAWD: 150 mmFR: CMModels (2)

Method: SawAutomation: LU, WA, CDWD: 300 mmFR: 1,000 mm/sModels (14)




Models (Qty)

Method: LaserAutomation: LU, WA, CDWD: 300 mmFR: 500 mm/sModels (3)

Method: LaserAutomation: LU, WA, CDWD: 300 mmFR: 1,000 mm/sModels (1)

Method: LaserAutomation: CMWD: CMFR: CMModels (1)


Method: LaserAutomation: WA, CMWD: 300 mmFR: 500 mm/sModels (1)

COMPANYHEADQUARTERS

WAFER SCRIBINGSYSTEMS

SAW DICINGSYSTEMS

LASER DICINGSYSTEMS

Compiled by Az Tech Direct, LLC � www.AzTechDirect.com � Direct all inquiries and updates to [email protected] data has been compiled from company inputs and/or website search and may not be current or all-inclusive as of the date of publication.

Advertisers are listed in Boldface type. Refer to our Editorial Calendar for upcoming Directories.





Hanmi Semiconductor Co., Ltd.532-2 Gajwa-Dong, Seo-GuIncheon, South KoreaTel: +82-32-571-9100www.hanmisemi.com

Jenoptik AGCarl-Zeiss-Strasse 107739 Jena, GermanyTel: +49-3641-65-1000www.jenoptik.us

Joyo Engineering Co., Ltd.1-5-12 Edanishi, Aoba-ku, Yokohama-shiKanagawa 225-0014, JapanTel: +81-45-912-4411www.joyo-eng.co.jp

J. P. Sercel Associates220 Hackett Hill RoadManchester, NH 03102Tel: +1-603-518-3200www.jpsalaser.com

Loadpoint Ltd.Chelworth Industrial Estate, CrickladeSwindon, Wilts. SN6 6HE, EnglandTel: +44-1793-751160www.loadpoint.co.uk

Loomis Industries, Inc.1204 Church StreetSt. Helena, CA 94574Tel: +1-707-963-4111www.loomisinc.com

Micro Processing Technology, Inc. (MPT)936 Dewing Avenue, Suite BLafayette, CA 94549Tel: +1-925-299-8940www.microptech.com

NPOS Technologies Inc.1922 Santa Rosa AvenuePasadena, CA 91104Tel: +1-626-398-0327www.npos-usa.com




Models (Qty)

Method: MechanicalAutomation: WA, CMWD: 150 mmFR: CMModels (2)

Method: LaserAutomation: WA, CMWD: CMFR: CMModels (1)

Method: MechanicalAutomation: WAWD: 150 mmFR: CMModels (1)

Method: MechanicalAutomation: CMWD: 200 mmFR: 1,000 mm/sModels (1)

Method: MechanicalAutomation: CMWD: 200 mmFR: 100 mm/sModels (3)




Models (Qty)

Method: SawAutomation: WA, CMWD: 300 mmFR: 500 mm/sModels (3)




Models (Qty)

Method: LaserAutomation: CMWD: 300 mmFR: CMModels (1)

Method: LaserAutomation: LU, WA, CMWD: 300 mmFR: 1,000 mm/sModels (1)

Method: LaserAutomation: LU, WA, CMWD: 300 mmFR: CMModels (2)

COMPANYHEADQUARTERS


SAW DICINGSYSTEMS

LASER DICINGSYSTEMS







Opto System Co., Ltd.100 Nogami, Miyamaki, Kyotanabe CityKyoto 610-0313, JapanTel: +81-774-68-4440www.opto-system.co.jp

Panasonic Factory Solutions Co., Ltd.2-7, Matsubo-cho, KadomaOsaka 571-8502, JapanTel: +81-6-6905-5535www.industrial.panasonic.com

Panasonic Welding Systems Co., Ltd.3-1-1, Inazu-cho, Toyonaka-cityOsaka 561-0854, JapanTel: +81-6-6862-1121www.industrial.panasonic.com

Planar Corporation2 Partizansky Ave.Minsk 220033, Republic of BelarusTel: +375-17-223-7211www.planar.by

Shibuya Kogyo Co., Ltd.Ko-58 Mameda-Honmachi, KanazawaIshikawa 920-8681, JapanTel: +81-76-262-1200www.shibuya.co.jp

Synova SAChemin de la Dent d'OcheCH-1024 Ecublens, SwitzerlandTel: +41-21-694-3500www.synova.ch

Thermocarbon Inc.391 Melody LaneCasselberry, FL 32707Tel: +1-407-834-7800www.dicing.com

Tokyo Seimitsu Co., Ltd.2968-2 Ishikawa-machi, Hachioji-shiTokyo 192-8515, JapanTel: +81-42-642-1701www.accretech.jp




Models (Qty)

Method: Laser, MechanicalAutomation: LU, WAWD: 100 mmFR: 50 mm/sModels (1 each)


Method: LaserAutomation: CMWD: 150 mmFR: 600 mm/sModels (3)

Method: LaserAutomation: CMWD: 200 mmFR: 300 mm/sModels (2)




Models (Qty)

Method: SawAutomation: LU, WA, CDWD: 300 mmFR: 600 mm/sModels (3)

Method: Saw + Laser/WaterAutomation: LU, WA, CDWD: 300 mmFR: 600 mm/sModels (1)

Method: SawAutomation: CMWD: CMFR: CMModels (1)

Method: SawAutomation: CD, CMWD: 300 mmFR: 1,000 mm/sModels (6)




Models (Qty)

Method: PlasmaAutomation: CMWD: 300 mmFR: CMModels (1)

Method: Laser/WaterAutomation: CMWD: CMFR: CMModels (1)

Method: Laser/WaterAutomation: LU, WA, CDWD: 300 mmFR: 1,000 mm/sModels (4)

COMPANYHEADQUARTERS


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http://www.advanced.com


The Ever Changing PV LandscapeAn overview of worldwide PV production,new technologies and market demand.By Bob Klenke [ITM Marketing]

A s the classic expression goesnothing is more constantthan change. This could welldefine the dynamics that

have impacted the photovoltaic (PV)industry during the past several years.Changes in production capacity,implementation of new technologies,and supply chain partnerships, as wellas alterations in market demand, haveall had a profound effect on theworldwide solar industry.

A common issue driving the upwardgrowth of the PV industry is the needto meet increasing worldwide demandfor energy, especially from developingcountries and emerging markets such asBrazil, China, India and Russia. Forexample, China brings one coal-firedelectric generating plant online perweek to meet its growing energydemand due to ever increasing volumesof manufacturing. It is interesting tonote that China will surpass the UnitedStates as the world’s largest energyconsumer measured in quadrillionBTUs per year. China’s boomingeconomy combined with an improvedstandard of l iving means theirinsatiable appetite for energy willexceed even that of the land of gasguzzling SUV’s by 2015.

Alternative energy sources includingnuclear, hydroelectric and biomass havebeen successfully implemented but havereached a plateau in long-termapplication due to regulatory concernsand/or supply limitations. Electricitygenerated by solar power, solar thermalheating and wind generated electricitypresent the greatest alternatives in terms

of fulfilling thedominant worldwideenergy requirements.

Historically, theprincipal marketdriver for PV growthhas been geopoliticalfactors such as theearly adoption ofincentives by Japanin the mid 1990’sfollowed by widespreadfeed-in-tariff (FIT)programs in Germany,Spain, Greece ando t h e r E u r o p e a ncountries. Rollbacks in some of theseFIT programs could shift PV demandto other regions of the world. At thesame time, the Asia solar marketexperienced a significant growth ‘spurt’beginning in the 2005-2006 time periodlead primarily by China’s efforts to‘green’ their negative image as one ofthe world’s leading polluters due totheir reliance on aforementioned coal-fired electric generation.

Production CapacityFor the past several years the

worldwide solar industry operated underthe premise that they could sell whateverthey produced. This belief changeddrastically at the end of 2008 because ofthe global economic downturn. Thedramatic increase in domestic Chinesesolar production combined with the 2008-2009 global economic contractioncreated a short-term overcapacity ofpolysilicon on the order of 2.5-3 times‘normal’ demand, resulting in downward

pricing that is expected to last throughthe end of 2011. This oversupply conditionalso applies to the solar cell market, whichis almost 3 times ‘normal’ demand, andcould potentially last until 2012 whendemand is expected to slowly approximatesupply needs. For all these reasons, thecurrent worldwide solar utilization rate ofproduction vs. capacity is at anapproximately 66% level (Figure 1).

This production-to-capacity utilizationrate is expected to increase toapproximately 75% beginning in 2012and remain there through 2014.Additionally, this dramatic change inthe market environment has resulted inapproximately a 30-50% drop in theaverage selling price (ASP) of solarpanels since mid-2008 with pricingexpected to remain low until demandcatches up with supply.

Supply Chain ImplicationsIn 2008, China was the preeminent

world leader in production, producing

FFFFFigure 1.igure 1.igure 1.igure 1.igure 1. Projected worldwide photovoltaic capacity and production levels(Source: European Photovoltaic Industry Association)

Production

0

5

10

15

20

25

30

35

40

45

2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014

Gig

awat

t/Yr

(GW

p)

Capacity


26% of all solar cells followed byGermany and Japan at 18% each,and the United States with 15%.Taiwan accounted for 13% of allglobal production, while the rest ofEurope accounted for 7% with theremaining 3% scattered across therest of the world.

Despite the projected return indemand forecasted for 2010, the 2008-2009 price erosion continues toconstrict PV earnings. Some estimatespersist that the recent decrease in PVpricing represents a permanentratcheting down of price structures thatcould transform the PV industry into amore competitive marketplace with thiscollapse in demand likely to shiftmarket share among the world’s leadingsolar producers (Table 1).

This shift in market share was mostevident when Germany’s largest solarmanufacturer, Q-Cells was directlyaffected by the Spanish government’sdecision that it could no longer afford

2009

Rank

2008

Rank

Company Headquarters 2009 Production

(MW)

2009 Growth

(%)

Market Share

(%)

1 3 First Solar USA 1,100 MW +54.2% 12.1%

2 2 Suntech China 704 MW +24.7% 7.8%

3 4 Sharp Japan 595 MW +20.5% 6.6%

4 1 Q-Cells Germany 586 MW -3.4% 6.5%

5 7 Yingli China 525 MW +46.5% 5.8%

6 5 JA Solar China 520 MW +42.3% 5.7%

7 6 Kyocera Japan 400 MW +27.5% 4.4%

8 11 Trina Solar China 399 MW +47.3% 4.4%

9 9 SunPower Philippines 397 MW +40.3% 4.3%

10 12 Gintech Taiwan 368 MW +51.1% 4.0%

11 8 Motech Taiwan 296 MW +8.7% 3.2%

12 13 Ningbo Solar China 260 MW +32.6% 2.8%

13 10 Sanyo Japan 260 MW +17.3% 2.8%

14 15 E-Ton Solar Taiwan 220 MW +55.9% 2.4%

15 14 Schott Solar Germany 218 MW +36.7% 2.3%

Subtotal top 15 6,848 MW +34.6% 75.1%

Others 2,282 MW +21.3% 24.9%

Total market 9,130 MW +29.2% 100.0%

TTTTTable 1.able 1.able 1.able 1.able 1. Top 15 photovoltaic manufacturing companies 2009 production volume (Source: PhotonInternational)Photovoltaic Industry Association)

2009

Rank

2008

Rank

Company Headquarters 2009 Revenue

($M)

2009 Growth

(%)

Market Share

(%)

1 1 Intel Corporation USA $32,410 -4.0% 14.1%

2 2 Samsung Electronics South Korea $17,496 +3.5% 7.6%

3 3 Toshiba Semiconductors Japan $10,319 -6.9% 4.5%

4 4 Texas Instruments USA $9,617 -12.6% 4.2%

5 5 STMicroelectronics France $8,510 -17.6% 3.7%

6 8 Qualcomm USA $6,409 -1.0% 2.8%

7 9 Hynix South Korea $6,246 +3.7% 2.7%

8 12 AMD USA $5,207 -4.6% 2.3%

9 6 Renesas Technology Japan $5,153 -26.6% 2.2%

10 7 Sony Japan $4,468 -35.7% 1.9%

11 10 Infineon Technologies Germany $4,456 -25.2% 1.9%

12 11 NEC Semiconductors Japan $4,384 -24.8% 1.9%

13 16 Micron Technology USA $4,293 -3.2% 1.9%

14 14 Broadcom USA $4,278 -7.9% 1.9%

15 19 Elpida Memory Japan $3,948 +9.7% 1.7%

Subtotal top 15 $127,194 -10.4% 55.3%

Others $102,723 -14.2% 44.7%

Total market $229,917 -11.7% 100.0%

TTTTTable 2.able 2.able 2.able 2.able 2. Top 15 semiconductor manufacturing companies 2009 revenue (Source: Gartner Dataquest)

to subsidize 500 megawatts (MW) ofsolar power installations in 2009. Theresul t ing impact was immediatelayoffs and cutbacks in European-based manufacturing plants with acorresponding shift by Q-Cells to anew factory in Malaysia in an effortto reduce manufacturing costs.

Even with these shifts in marketshare, the top 15 PV manufacturerscontrol approximately 75% of thetotal available market with this highermarket concentration equating tolower price competition. Contrastthis with the semiconductor marketwhere the top 15 semiconductormanufacturers control only 55% ofthe total available market resulting inincreased price competition amongsuppliers (Table 2).

There are also distinct differencesbetween the PV and semiconductorindustries’ manufacturing value chains.Whether carried out by integrateddevice manufacturers (IDM) orsemiconductor assembly and testservice (SATS) providers, typical


Base Technology Share Sub-Category Technology Share

Single and Multicrystalline silicon (Si) 71% Single and Multi crystalline silicon (Si) 71%

Non - Standard Crystalline silicon (Si) 10% Hetero - junction with intrinsic ( HIT) 4%

“ Inverted metamorphic multi - junction (IMM) 3%

“ String ribbon/edge - defined film (SR/EFG) 2%

“ Organic photovoltaics (OPV ) 1%

Thin Film 1 9% Cadmium telluride ( CdT e) 11%

“ Amorphous silicon ( a - Si) 6%

“ Copper indium gallium selenide ( CIGS) 2%

TTTTTable 3.able 3.able 3.able 3.able 3. 2009 photovoltaic cell technology production share by type (Source: Yano Research Institute)

semiconductor manufacturing processesconsisting of wafer fabrication,packaging assembly and test generallyrepresents about 95% of the total valuechain. In contrast PV manufacturingprocesses that generally encompasspolysilicon wafer production, waferfabrication, cell fabrication and moduleassembly account for less than 53% ofthe total PV value chain. The remaining47% entails PV system assemblyconsisting of cables, chargers, mountingsystems, tracking systems and integratedbuilding solutions.

Market DriversThe cost of electrical power

generated using solar technology is acomplicated function of the PV systemcost, the cost of grid purchased power,the average hours of available sunshine,and capital costs. In almost all geographiclocations PV power generation is not yetcompetitive with grid purchased power.PV systems are on a long-term priceexperience curve based on a declining 7%compound annual growth rate (CAGR)where increases in module efficiency,capacity expansion and reduction inmanufacturing materials and processcosts will result in long-term parity withgrid purchased power.

Traditionally, the majority of PVapplications have been distributed on-grid installations due mainly togovernment incentives and regulations.Residential applications, including non-distributed off-grid and other consumertype applications, are expected toincrease as economics reach closer togrid parity pricing. Since attainingparity with grid purchased power is the‘silver bullet’ for economic justificationof residential-based PV installations,which are generally excluded frommajor government stimulus plans, itshould be noted that country-to-countrycost variation has a significant impactupon non-commercial solar applications.For example, the average 2009residential price of grid purchasedelectrical power in the United States

was $0.1165/kilowatt hour, which issignificantly lower than countries withregulated cost structures such asGermany and other European countrieswhere grid purchased power isapproximately the equivalent of $0.20-0.25/kilowatt hour. Obviously thesehigher cost countries help the economicjustification of residential-based PVinstallations which are often aided byhighly popular geopolitical-basedincentive programs.

New TechnologiesVarious emerging technologies are

under development to increaseconversion efficiency and/or lowermaterial and manufacturing costs.Examples of these are multi-junctionmonolithic cells and organic-basedcells. Multi-junction monolithic cellsexhibit a high conversion efficiency of25-40% compared to polysilicon-basedcells at 18%. Organic-based cells aresignificantly less efficient at 6-10% butexhibit greatly reduced material cost.

When all crystalline-based celltechnologies are considered,approximately 81% of all PV cellsmanufactured worldwide are based onsilicon wafers. While thin fi lmtechnologies currently comprise only19% of total PV, they retain the fastestgrowth rate due to the ability to reducematerial costs as well as increaseeconomy-of-scale with advancedfactory automation techniques.

Previous estimates that thin filmtechnology including various competingtechnologies such as cadmium telluride(CdTe), amorphous silicon (a-Si) andcopper indium gallium selenide (CIGS)would grow from a historic rate of 10%to 25-30% of total PV production hasnot proven to hold true. Advances intechnology notwithstanding, thewidespread conversion to thin filmtechnology has been slowed by theshort-term oversupply of polysiliconwhich has depressed the pricing ofcrystalline-based PV cells and thereforemade the conversation to thin film lessfinancially attractive (Table 3).

It has been expressed that a ‘wildwest mentality’ exists within the PVindustry. To this extent, industrystandards and production guidelines arebeing developed to address tabbing,stringing and glass-to-foil lamination toensure solar cell product reliability.The IPC’s Solar Standards Committeehas standards under development inseven key areas. Principle among theseis E-12 that will set acceptancestandards for the lamination of glass-to-foil solar modules and E-14providing standards for the tabbing andstringing of silicon solar cells.

Energy Consumption PatternsPer capita energy consumption on a

global basis is the result of a complexset of factors including supplyavailability, government policy and


0%

10%

20%

30%

40%

50%

60%

Germany Spain Japan US India China Italy ROW

GDP (% )

PV Consumption (% ) Populat ion (% )

FFFFFigure 2.igure 2.igure 2.igure 2.igure 2. Photovoltaic consumption versus population and GDP (Source:Navigant Consulting, CIA World Factbook)

market pressures. The consumption ofoil, natural gas and biomass as well aselectricity generated from coal, nuclearpower and hydroelectric sources varywidely. Electricity generated by solarand wind power represents the fastestgrowing segment of the world’s totalenergy portfolio.

Solar farms for example, also referredto as solar power plants, are becomingabundant in many countries around theworld as a direct result of governmentplanning as well as direct or indirectfunding. Many utility companies acrossEurope and the United States arebecoming increasingly interested inprocuring PV power generating systemsas one of the leading technologies fornear-term renewable energy sources.Approximately 75% of German utilitiescurrently use PV as part of their energyresource portfolio and close to 50% ofUS-based utility companies have PVresources in place or plan to implementthem within the next five years.

Market DemandDue primarily to current incentive

programs, Germany and Spain are theleading consumers of PV modulesfollowed by Japan and the UnitedStates. Besides the indication that solarconsumption is not a direct product ofpopulation density or gross domesticproduct (GDP), the graph belowreinforces the expansion opportunity

for increases in solar consumption incountries such as Brazil, China, Indiaand Russia (Figure 2). The growth ofPV installations in 2010 will be led bya re-energized German market that hasfrom a sluggish first-half of 2009. Butthis continued growth could stall if FITprograms are scaled back. Indicationspersist that this trend might continue aspotential cuts in FIT programs couldaffect Germany and Italy in combinationwith budget concerns in Greece and Spainresulting in a shift of PV demand to otherregions of the world.

By 2014, China is expected to be theworld’s largest PV market, surpassingboth the United States and Germany,estimated to be the second and thirdlargest markets by that timeframe.China will become a dominant force inboth the supply of solar cells and PVmodules as well as leading the demandfor PV systems with utility scale solarpower plants spearheading thecountry’s PV market growth.

Recently China undertook asignificant electrification program forrural communities inland from coastalpopulation centers to offset the growingtrend in urbanization. In lieu of relianceon sluggish, unprofitable, state-ownedfirms managed by the communist Chinacentral planning system to accomplishthis undertaking, an ambitious programof regional solar power plants were, andstill are, being constructed. Despite

China being thew o r l d l a r g e s timporter of aluminumand copper on anu n p r e c e d e n t e dglobal scale as wellas the leadingrecycler of scrapmetal, the scarcityof copper andaluminum created ashortage of electricaltransmission linecapability therebyincreasing the‘regional izat ion’

of China’s solar industry.

Future OutlookIn addition to traditional crystalline

cells and thin film technology, othertechnologies are emerging on the PVscene. Organic PVs (OPV) and dye-sensi t ized solar cel ls (DSC) arecoming to the forefront. DSCs showparticular promise since they generateelectricity through sensitizer-addednanoporous semiconductor electrodesthat convert light energy into electricalenergy with low material cost andsignificantly do not require the use ofsilicon-based materials.

While not as dramatic as thedownturn in 2008-2009, it is projectedthat quarterly PV shipments will looksimilar in 2010 with demand remainingslow through the first half of 2011 andthen rebounding to previous highgrowth levels beginning in the secondhalf of 2011. Additions in capacityplanned by several leading and costcompetitive PV manufacturers couldpotent ial ly resul t in a r isk ofoversupply therefore driving down PVprice points.

Equally dramatic will be the shift inmarket demand to alternative regionsof the world other than today’sdominant PV consumers wherecountries totaling 12% of the world’spopulation account for 95% of totalPV consumption. Developed PVmarkets such as Germany, Spain,Japan, Italy and the United States willbe surpassed by developing countriesand emerging markets includingBrazil, China, India and Russia. Afitting example of this trend is the factthat the world’s largest solar powerplant is being constructed by a US-based PV supplier _ in InnerMongolia.

B o b K l e n k e i s t h e m a n a g i n gdirector of ITM Marketing, a fulls e r v i c e m a r k e t r e s e a r c h a n dtechnical marketing firm and is astaff member of ITM Consulting.[[email protected]].


http://www.iwlpc.com


EMERGING TRENDS

T

A Good Place to Place Your Bets (in ICs)By Sandra Winkler, Senior Analyst [New Venture Research, www.newventureresearch.com]

he semiconductor industrytook a beating in early2009, but sprang back

sooner than many to end the year inbetter shape than initially anticipated.Small, handheld, always connecteddevices sold well even in the depths ofthe recession. Items priced under $300,even $400, still sold. Smart phones wereall the rage. PCs shrank to the smaller,more portable notebooks, which, in turn,shrank even further to the netbook. E-readers and other handheld consumeritems gained market acceptance. We dolove our gadgets.

Going into the future, what wouldbe good markets for a semiconductorcompany to be in? Areas that offer oneor more of the following:

High product volumes High, or reasonable, growth

potential High volume of ICs per

individual productThere are many ICs that fit within

these categories: MPUs Standard cell / PLD DRAM Flash Analog _ communications Analog _ voltage regulators Special purpose logic chips of

all types, including consumer,computer, communications, andautomotive

Package SolutionsWith so many products being

wireless, baseband products willcontinue to be in demand. They arebeing included in stacked options suchas package-on-package (PoP) inincreasing numbers. Memory,included in this list, is also beingplaced in both die stack and PoPoptions in large numbers. Even PLDscan be found in stacked solutions. Andlogic devices have been included inPoP solutions from the inception ofpackage-on-package.

Many companies are looking atthrough-silicon vias (TSVs) as aninterconnection method for deviceswithin stacked packages, and as a wayto increase performance, improvesignal integrity, and reduce parasitics.Elpida Memory is an early adopter ofthis technology and has a number ofmemory products in production, ashave severa l o ther memorycompanies. IBM is planning onmoving the SRAM off the MPU andconnecting it in a stack with TSVs.QUALCOMM is taking a seriouslook at this technology. PLDcompanies are reviewing thistechnology to place their devices ina homogeneous stack.

Most stacked package options arefitting within the FBGA outline,although QFN options are gainingacceptance.

QFN as a package solution has beengaining in popularity for some time,extremely popular for analog andsimple logic chips, of which there aremany. Coming onto the market is anew twist for this package, and that isto have inner leads on the leadframeto create a perimeter array pattern onthe leads, thus allowing this packagesolution to reach into higher I/Ocounts. This would allow it tocomplete with low-cost FBGApackages, to provide an even lowercost option, as leadframes are lessexpensive than substrates.

The same goes for WLPs, giving thepackage a new twist to reach intohigher I/O counts by creating theovermold WLP, in which the backsideis coated with overmold to create alarger surface on the face in which toplace the electrical traces.

Not that there is a shortage of a needfor packages in the low I/O ranges.Indeed, most analog and simple logicchips are of low I/O, and they areplentiful. SO and SOT solutions arestill in demand, especially for voltageregulators, which are in all electronicdevices.

What is being conveyed here is thatboth older and newer forms ofpackages are in demand, and newtwists are giving new life to existingpackage solutions. Being diversifiedis a safe bet.


WHAT'S NEW!X-ray Inspection System

Nordson DAGE announced that it willshowcase its XD7600NT100HP X-rayinspection system at this year’s SMTAInternational Electronics Exhibition andConference, Oct. 26 - 27th in Orlando,Florida. The XD7600NT100HP offers100 nm (0.1μm) feature recognition forfinite analysis of challenging inspectionapplications. Due to its 2.0M pixeldigital imaging system, oblique angleviewing of up to 70° around any pointof a 16" x 18" (407 x 458mm) inspectionarea is possible without compromisingmagnification.

The XD7600NT100HP combines digitalacquisition technology of the XiDAT 3.0imaging system with the company’sproprietary ImageWizard software, and isconfigured with dual monitors. This allowsoperators to view X-ray images on one 24"widescreen LCD monitor whilesimultaneously providing the fault locationsin a detailed X-ray navigation map on thesecond LCD display. The system isavailable with a high-power NT tube thatis able to retain sub-micron featurerecognition at full power.

Additionally, the system can be equippedwith computerized tomography (CT) optionproviding 3D modeling and volumetricmeasurement of solder joints suited foranalysis of solder interconnections for criticalapplications such as stacked die, MEMS,package-in-package (PiP) and package-on-package (PoP). [www.nordsondage.com]

Thermal Interface PadsKeratherm U 90 and U 80 silicone-free

thermal interface materials (TIMs) fromMH&W International provide high thermalconductivity where contamination threats

prevent the use of silicone-based thermalpads. U 90 is a ceramic-filled polyurethanefilm that has a thermal conductivity of 6.0W/mK and thermal impedance of 0.05Kin2/W. U 80 is the lower cost version, alsosilicone-free, which provides 1.8 W/mK ofthermal conductivity and 0.11 Kin2/W ofthermal impedance.

Both TIMs are available with a lighttack adhesive to keep them in placeduring assembly or pre-attached to heatsinks. The light tack adhesive can becompared with adhesives used onrepositionable notes. The TIM pads won’tbe damaged when removed from mountingsurfaces, which is a common problemwhen stronger adhesives are used. Typicalapplications these TIMs include medicaldevices, laser equipment, LED lighting,solar energy, disk drives and automotiveelectronics. [www.mhw.intl.com]

Wafer Backside Coating for StackedPackages

With the introduction of Ablestik WBC-8901UV, Henkel extends its wafer backsidecoating (WBC) portfolio to stacked diepackages, addressing the demandingrequirements of multiple die stackapplications for the memory market segment,including packages such as TSOPs, MCPsand FMCs (Flash Memory Cards).

Applied via a spray coating methodfollowing the wafer thinning process,Ablestik WBC-8901UV is preciselydeposited across the back of the siliconwafer following which the material is B-staged using a UV irradiation process.After this step, dicing tape is laminated tothe wafer, backgrinding tape is removed,and the wafer is diced in preparation fordie pick-up and placement.

The unique formulation of the WBCoffers an alternative to current film-basedsolutions for stacked die packages, witha reported 30-50% total cost ofownership. Additionally, processflexibility is affected because it allows forpackaging specialists to adjust die attachthickness based on specific manufacturing

requirements and use their dicing tape-of-choice, rather than be limited by thepre-determined thickness of filmmaterials that incorporate dicing tape.Henkel reports it is currently partneringwith spray technology and backgrindingequipment manufacturers to deliver anintegrated, in-line process solution for thisunique WBC advance. [www.henkel.com/electronics]

Fine Pitch Bump AdaptersAs part of the Correct-A-Chip series,

Aries Electronics’ Fine Pitch BumpAdapters were developed to allow higherpitch devices to be used on smaller pitchboards. The adapter tops have landing padsthat can be designed to accept any deviceon any pitch and settle into fine-pitchfootprints including thin-shrink smalloutline packages (TSSOP) and quad flatpackages (QFP) with pitches down to0.40mm. In addition, the adapter bottomhas raised connection pads up to 0.010"(0.25 mm) that provide easy mounting ofthe adapter to the target board.

Reclaimed adapter board space allowsfor manufacturers to add components tothe design at minimal cost. Additionally,the Fine Pitch Bump Adapters allow forBGA device integration in boards withsmaller pitches that previously could notbe used together.

Fine Pitch Bump Adapters areavailable in panelized form, as an adapteronly, or as a turn-key solution withdevices mounted. The boards are 0.062"


(1.57mm) thick FR4 or Rogers 370 HR,with 1oz. copper traces on both sides. Thenon-solder mask defined (NSMD) padsare finished with electroless nickelimmersion gold (ENIG). The apparatuscan operate up to 221°F (105°C) for FR4and 266°F (130°C) for lead-free. Thenew adapters are available in tape and reelfor high speed SMT assembly and can bemanufactured for RoHS compliance.[www.arieselec.com]

Stamped Spring Pin SocketIronwood Electronics introduces the

CBT-QFN-7002, a stamped spring pinsocket that addresses high performancerequirements for testing UART serial toparallel data convertors. The contactor isa stamped spring pin with 26g actuationforce per ball and cycle life of 500,000insertions. The self-inductance of thecontactor is 0.88 nH, insertion loss < 1dB at 15.7 GHz and capacitance 0.097pF.The current capacity of each contactor is4 amps at 80°C temperature rise. Sockettemperature range is -55 to +180°C.

The socket also features a low profilesnap lid and has a wave spring with swivelcompression plate for vertical forcewithout distorting device position. TheCBT-QFN-7002 is specifically configuredto test 7 x 7mm, 0.5mm pitch, QFNpackages that have 48 positions with centerground pad. The socket is mounted usingsupplied hardware on the target PCB with

no soldering, and is said to require thesmallest footprint in the industry. Thisallows inductors, resistors and decouplingcapacitors to be placed very close to thedevice for impedance tuning. This socketcan be used for quick device screening anddata conversion functional test applicationsthat have the most stringent requirements.[www.ironwoodelectronics.com]

Low Current Land Grid Array FuseAVX Corporation has expanded its

Accu-Guard Low Current Series with theaddition of a low-current, UL E141069approved, RoHS compliant 0402 fuse.This miniature fuse utilizes thin film andland grid array (LGA) technology toprovide an accurate 125mA current ratingin a small package. The thin-filmtechnology allows for precise control ofthe component electrical and physicalcharacteristics that is not possible withstandard fuse technologies, forcing end-device manufacturers to choose betweensize and current rating.

Reportedly the lowest current fuseavailable today, it is suited for use inhandheld devices like cell phones, PDAs,two-way radios, and video and digitalcameras, in addition to hard disk drives(HDD), LCD screens, computerinstrumentation, battery chargers andrechargeable battery packs. [www.avx.com]

BGA Clamshell SocketsE-Tec Interconnect’s “economy”

ClamShell sockets for BGA, LGA &QFN chips feature a locking system thatallows for controlled distribution oflocking forces with 1 or 3 locking pegsdepending on pincount.

The sockets feature an open topretainer for improved heat dissipation andaccess to die. Pressdown forces can bepre-set with a stopper screw and re-

adjusted manually, and the easy open/close method requires no screws or tools.

The small body size makes thesesockets ideal for use on high-densityPCBs, requiring little board space. Theyare available in SMT, thru-hole andsolderless compression type for eitherlow or high pin count configurations; withraised SMT pins to lift socket abovecomponents on board; and with probe pinand elastomer sockets. [www.e-tec.com]

Worldwide IC Packaging MarketReport

Now available from New VentureResearch, The Worldwide IC PackagingMarket, 2010 Edition, offers an in-depthlook at the worldwide integrated circuit(IC) packaging market.

Individual IC device market forecastsare provided for units, revenue, and ASP,from 2008 through 2014. The packagesolutions for each of these markets arethen forecast, broken down into I/Oranges. In a separate chapter, packagetypes are rolled up to deliver an overallworldwide forecast divided into 12different package families plus bare diesolutions. Additionally, forecasts for diemounted using direct chip attach (DCA)methods were developed.

This report is intended to aid companiesassociated with the IC packaging marketin forecasting demand for their ownproducts. [www.newventureresearch.com]


W hile macroeconomicscontinues to improve,questions still pop up

about the strength of this recovery. AtMEPTEC’s annual September ForecastLuncheon, Sept. 9, 2010 at DobsonRanch Inn in Mesa AZ, GartnerDataquest’s Jim Walker offered bothexplanation on the recovery thus far,while offering his predictions andreasoning for what’s to come in the nextfew years.

Economy at a GlanceGiving a broad view of the world

economy, Walker explained that whileIndia, China, and Southeast Asia areseeing strong growth, the US andEurope are still lagging, putting a dragon worldwide growth. As China’smiddle class continues to grow, thecountry has become the largest buyerof consumer electronics while in the USand Europe consumer spending andsentiment is stall ing as concerncontinues around unemployment, thereal estate market, consumer andcommercial debt.

Basically, we’re dealing with a mixedbag resulting in confused signals withinthe industry. On one hand, Walkernoted, current market data indicatesstrength, while on the otherannouncements and anecdotes are causefor concern. It appears that the industryis approaching a revenue peak, thequestion is, notes Walker, will theinevitable slowdown cause a revenueadjustment?

Walker’s September Forecast:Recovery, Boom, Growth, What’s Next?By Françoise von Trapp, Contributing Editor [3D InCites]

Market OverviewSummarizing the overall semiconductor

device and applications market, Walkerpredicts revenue is still poised to hitrecord highs in 2010 reaching 31.5%growth driven by the PC, cell phone andLED markets, although he doesn’t ruleout a downturn scenario. While the PCsupply chain is expected to experiencea correction, DRAM will be the fastestgrowing device type in 2010. Therewill also be a “modest chip correction”in the second half of 2010 assemiconductor growth aligns withsystem growth.

Walker says there’s strong growthacross the board in capital spending,with mostly foundriesspending on capacitybuys. According toGartner data, the top5 capital spenders in2010 are Samsung,TSMC, Intel, Global-Foundries and Hynix.And for the first timeever, two packagingcompanies, ASE andSPIL, made the top20. “It’s a milestone,in my opinion, thatthe packaging guysare starting to spendon capex.” saidWalker, saying thatit’s due largely to thetransition from goldto copper wirebonding.

Growth in PackagingAfter 3 years of market declines,

Walker says that the back-endequipment market is expected to surgewith better than 130% growth. He saysgrowth for advanced package toolingwill be solid, and memory ATE andcopper wire bonders will be topperformers. However, 2011 could beimpacted by uncertainty of marketconditions. Q4 2010 will provide cluesto strength of 2011.

Technology buys and foundry andmemory capacity buys are what’sdriving equipment spending. Walkerpredicts that while fab growth willcontinue, it will begin to slow down in

MARKET FORECAST

FFFFFigure 1.igure 1.igure 1.igure 1.igure 1. SATS Market quarterly revenue scenarios


2011 and 2012 due to ordering in2010. Memory will experience anover-investment through 2012 and willdrive a 2013 downcycle. Walkersuggests that key questions to payattention to moving forward: Is thecurrent surge in chip demandsustainable in the near term? Will chipmanufacturers respond to any kind ofnegative economic news with capexpushouts? Which chip manufacturerswill be able to invest, and which willgo fabless/asset “lite”?

“The packaging va lue of theindustry is going up because we arethe enabler of Moore’s Law,”notedWalker. “Most of the integration in acell phone, because time-to-market isso short, is via packaging.”He addedthat des ign wins of SOC-typeproducts have gone down, and withthat the value of the back-end canincrease in a five year period. Front-end equipment manufacturers areseeing this opportunity to serve theback-end needs in wafer- leve lpackaging and TSV. “Value-addappears to be growing in the back-end,” he said.

However he doesn’t see that the TSVmarket has driven equipment buys forcompanies like TSMC or Elpida,regardless of their announcements ofoutfitting 300mm TSV lines. “Elpidaannounced they’d begin production onTSV in June 2010, but I still haven’tseen anything on that yet.” He said,adding that it will be the middle ofnext year before we see any TSVproduction, and that will be in pilotlines only. Walker expects there won’tbe any measurable volume of TSVdevices for several years.

Addressing the outsourcedsemiconductor assembly and test(OSAT) market, based on quarterlyrevenue forecast scenarios, Walkerpredicts an expansion of 37% this yearand eventually will have 50% of thepackaging and test market (Figure 1).

SATS vendors are focusing onadvanced packaging and copperbonding capacity; the latter because ofthe increase price of gold. Memoryassembly and test capacity is beingexpanded.

The top 5 SATS vendors are currentlyASE, Amkor, SPIL, STATS ChipPAC,and Powertech Technologies. “The onethat has grown the fastest over the past5-10 years is Powertech Technology,”says Walker. He said the company only

handles memory package and test, andhas weathered the storm using financialacumen, understanding the market, andhaving a guaranteed customer to supplythrough the downturn. He noted thatASE has taken market share from SPIL,most likely because SPIL didn’t investin copper wire bonders and ASE wasaggressive. “They’re all experiencingnice growth in the marketplace.” hesaid, thanks to good strategies and goodrelationships with their customers.

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CALENDAROctober 11-14, 2010IWLPC _ International Wafer-Level Packaging ConferenceSanta Clara, CA USAhttp://iwlpc.com/October 19-21, 2010SEMICON Europa Dresden, Germanyhttp://www.semiconeuropa.orgOctober 24-28, 2010SMTA InternationalOrlando, FL USAhttp://smta.org/smtai/index.cfmOctober 28-29, 2010KGD WorkshopSanta Clara, CA USAhttp://www.semi.org/en/eventstradeshows/ctr_028107October 31, 2010 November 4, 2010IMAPSRaleigh, NC USAhttp://www.imaps.org/imaps2010/index.htmNovember 2-4, 2010ITC _ International Test ConferenceAustin, TX USAhttp://www.itctestweek.org/November 10, 2010MEPTEC Q4 Semiconductor Roadmaps:Santa Clara, CA USAhttp://meptec.org/meptecroadmaps20.htmlDecember 1-2, 2010SEMICON JapanChiba, Japanhttp://www.semiconjapan.org

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chipscale review vol14,no5,sept-oct 2010

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