cicc 05 slides
TRANSCRIPT
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Algorithmic Design Methodologies and
Design Porting of Wireline TransceiverIC Building Blocks Between Technology
Nodes
S.P. Voinigescu1, T.O. Dickson1, T. Chalvatzis1, A.Hazneci1, E. Laskin1,
R. Beerkens2, and I. Khalid2
1) University of Toronto2) STMicroelectronics, Ottawa, Canada
CICC, San Diego, Sept.19, 2005
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Outline
Introduction
Low-noise broadband inputcomparators
Mm-wave VCOs
High-speed logic gates
Circuits beyond 40 Gb/s
Summary
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Si(Ge Bi)CMOS speed is free ... if you canafford the mask costs!
MOS-HBT(BiCMOS)Cascode
MAG > 8 dB @ 65 GHz in HBTs and MOSFETs
HBT-based cascodes have highest gain
Benefits of the MOS cascode questionable at 65 GHz
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Fundamental limitationsof dynamic range
Noise
floor
Breakdown voltage
Dynamic Range
Voltage
Bandwidth
Dynamic range
compressed as data
rates increase
Emphasizes need for low-noise design
methodologies
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Power dissipation a major limitation incircuits beyond 40 Gb/s
Bipolar only implementations suffer from
VCC >= 3.3V
40 GHz latch consumes more than 50 mW
CMOS has lower supply voltage and lower powerdissipation but
40 GHz latch has yet to be demonstrated
- must design in 90/65 nm with first pass success
Emphasizes need for new low-voltage, high-speedlogic topologies and robust design methodologies
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Goal of this presentation
Prove that algorithmic design methodologies existfor optimal solutions for all wireline building blocks
Broadband input amplifiers
VCOs
(Bi)MOS-CML logic gates
Prove that CMOS implementations are portable
between technology nodes and foundries
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Key enablers
Invariance of characteristic current densities inMOSFETs
Low-noise broadband matching, biasing, and sizing
Low-voltage (Bi)CMOS topologies
Small footprint (less than 20 mm per side) inductors
with SRF> 100 GHz
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MOSFET characteristic current densitiesMOSFET characteristic current densitiesinvariant across nodes & foundriesinvariant across nodes & foundries
Peak fT
@ 0.3 mA/mm Peak fMAX
@ 0.2 mA/mm NFMIN
@ 0.15 mA/mm
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Characteristic MOSFET current densitiesinvariant over CS and cascode topologies
The peak fTcurrent
density of a MOSFETcascode stage remains0.3 mA/mm
Cascode stage can betreated as a compositetransistorin circuit
design (fT, fMAX, NFMIN)
fTof MOSFET cascode
is < 60% of MOSFET fT
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Vertically stacked, multi-metalinductors for CML logic
Q is not important
Size is important
Maximize L*SRFto
trade-off tail current for
bandwidth
Use 3-7 metals
T. Dickson et al. IMS-2004
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Low-noise broadband amplifiers
RCZ0
L0
LC
RE
Q1
VOUT
IN
VCC
Z0
L0
RC
LC
Q2
VOUTV
IN
VCC
Q1 V
OUT
VCC
RF
LF
RC
LC
Q2
VIN
Q1
RC
VDD = 1.2 V
LC
M1
IT
Z0
L0
200 Ohm 600 pH
W = 20 um
W = 40 um
W = 40 um
VDD = 1.2 V
180 pH
W = 60 um
W = 120 um
W = 40 um
180 pH
200 Ohm 650 pH
W = 40 um
3mA
VDD = 1.2 V
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Transistor low-noise design(S. Voinigescu et al., BCTM 1996)
Lowest noise achieved when transistor biased at JOPT (0.15mA/mm).
Transistor noise parameters scale with emitter length/ gate width.RN = R/LE GN = G
2LE GCOR = GC2LE BCOR = BLE
RN
= R/W GN = G2W GCOR = GC
2W BCOR = BW
Optimal biasing and sizing of transistor @ BW3dB is key to low noise design.
JOPT JOPT
HBT 130nm MOSFET
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Sizing SiGe HBT TIA & INV designs for noisematching
lEOPT
TIA requires much smaller
transistor size:Higher bandwidth
Broadband input match
Lower power consumption
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Broadband CMOS LNA topology scaling
Biased at 0.15 mA/mm
W, IDS do not change withnodes
NF50and BW3dB
improve
as technology scales
RC
VDD = 1.2 V
LC
M1
IT
Z0
L0
200 Ohm 600 pH
W = 20 um
W = 40 um
W = 40 um
VDD = 1.2 V
180 pH
W = 60 um
W = 120 um
W = 40 um
180 pH
200 Ohm 650 pH
W = 40 um
3mA
VDD = 1.2 V
Al ith i d i th d l f
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Algorithmic design methodology forbroadband low-noise TIAs
1. Bias HBT(MOSFET) at optimal noise current densityJOPT (0.15 mA/mm) at 3dB frequency
2. Choose the DC voltage drop across RC for linearity
requirements. This fixes the loop gain T = gmRC (=gm*ro)
3. Set the feedback resistance RF for 50 input match.
4. Size the emitter length (gate width) of Q1 for low-noise, such that the TIA noise impedance is 50 .
5. Add inductors to extend bandwidth and filter high-frequency noise.
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Measured single-ended 50-Ohm noise figure
Differential versions of three
circuits implemented
Measured single-ended noisefigure in 50 Ohm
TIA has low noise over entiremeasured bandwidth
RCZ0
L0
LC
RE
Q1
VOUT
IN
VCC
Z0
L0
RC
LC
Q2
VOUTV
IN
VCC
Q1 V
OUT
VCC
RF
LF
RC
LC
Q2
VIN
Q1
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40-Gb/s eye diagrams
Eye quality better for TIA (7.0) than EF-INV (5.8)
20-mV single-ended input (10-mV per side)
TIAEF-INV
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90-nm SOI TIA
8-dB noise figure 1V supply
6 mW
p-MOS load
40mm
10 Gb/s
15 Gb/s
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VCOs
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Differential Colpitts topology
HBT VCOs
1 2
2Neg. Res. m
b
gR
C C= -
1 2
1 2
1
2,
osc EQ
B EQ
C Cf C
C CL C= =
+
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SiGe HBT oscillator measurements
Impact of: 1. base (tank) inductor
2. inductive emitter degeneration (LE)
C. Lee et al. CSICS-2004
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Vop
2L
Von
Q2
Q1
VDD
= 1 V
ISS
Vop
LL
Von
Q2
Q1
VDD
= 1 V
ISS
C C
CMOS VCOs
osc ,CMOS23
g 'mQeff
C 'gs4C 'gdC 'dbCL
W
osc ,nMOSg 'mQeff
C 'gs4C 'gdC 'dbCL
W
WnMOS ,cross1
osc
2L [C '
gs4C '
gdC '
db]
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Colpitts CMOS/BiCMOS VCOs
RSS
C2
C1
LT
Vop
C2
C1
LT
LS
VCON
LS
LD
LD
Von
Q2
Q1
30x1mmx65nm30x1mmx65nm
40 .. 80 fF 40 .. 80 fF
40 fF 40 fF
200 pH
100 pH
80 pH80 pH
VDD
= 1 V
LSS
200 pH
200 pH
CSS
=0.5 pF
100 pH
RSS
C2
C1
LT
Vop
C2
C1
LT
LS
VCON
LS
LD
LD
Von
Q2
Q1
33x1mmx130nm33x1mmx130nm
230 fF 230 fF
30 fF 30 fF
415 pH
200 pH
100 pH100 pH VDD = 2.5 V
415 pH
CSS =1 pF
200 pH
3x9mm 3x9mmQ4 Q3
WnMOS ,Colpitts1
osc2 L [C 'gsC 'sb
C 'gsC 'sbk C 'gd]
AE ,HBT ,Colpitts
1
osc2
L [CjbA
CvarAE
C 'jbACvarAE
k CjcA ]Colpitts has higherfOSC
and
built-in buffering over X-coupled
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BiCMOS cascode oscillator measurements
Measured phase noise at 35 GHz and simulated
NFMIN
of SiGe MOS-HBT cascode stage as a
function of gate voltage
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VCO design methodology
VCOs treated as LNAs matched to the source impedance
Rp. This is generally not possible in cross-coupled VCOs! VCO topology (CS/CE or cascode) biased at optimum
NFMIN
current density (0.15 mA/mm in FETs)
Vosc
must be set close to VMAX
to minimize phase noise
Lower inductance, higher bias current, better L(fm)
HBT-VCOs have 6..10 dB better phase noise due to largerV
MAX
L fm=
In2
Vosc
2
1
fm
2
1
C1
2 C1C2
12
C2
C1
L
RS
V1
VOSC
R
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High-Speed Logic
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Logic families
Unlike conventional CMOS, gate & subthreshold
leakage is not a problem in MOS-CML
In MOS-CML low-VT is desirable
MOS-CML with peaking is > 3x faster than CMOS
Fig. 9. Inverters in various CMOS and SiGe BiCMOS logic families.
Wn
Wp
kWn
kWp
DV
DV
IT
RL
DV
DV
RL
IT
IT
INN
INP
OUTP OUTN
RL
RL
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MOS/BiCMOS CML device sizing & biasing
For a given speed and technology there is a maximum realizable Lpmax
Speed improvement as CMOS scales is due solely to Veff
(DV) scaling.
250
VDD
= 1.8 V
1 nH
IT
Q1
Q2
Q3 Q
4
1 nH
250
CLK
DATA
OUT
330
VDD
= 1.8 V
1 nH
IT
Q1
Q2
Q3 Q
4
1 nH
330
CLK
DATA
OUT
CLK
DATA
OUT
W=IT
1.5 JpeakfMAX=
IT
0.3mA /m; AE=
IT
1.5JpeakfMAX
Lp=CLRL
2
3.1BW3dB=
1.6IT
2VCLITmin=V
CL3.1Lpmax
Lp=C
L3.1
V2
IT2
2VeffV2Veff scales with L
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BiCMOS ECL latches (> 49 GHz)
BiCMOS cascode with EF (SF)
EF vs. SF:
higher gain, lower E-S capacitance
VBE > VGS
2.5 V supply, IT=2 .. 4mA 3.3 V supply, I
T=2 .. 4mA
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Evolution to 1-V, 40-GHz latch
330
VDD
= 1 V
1 nH
Q1
Q2
Q3 Q
4
1 nH
330
CLK
DATA
OUT
HVTHVT
LVTLVT
S D1 S D2 S D2 S D1 S
G
1
Dum
my
Dum
my
G
1
G
2
G
2
G
2
G
2
G
1
G
1
S D1 S D2 S D2 S D1 S
G1
Dummy
Dummy
G1
G2
G2
G2
G2
G1
G1
S D1 S D2 S D2 S D1 S
G1
Dummy
Dummy
G1
G2
G2
G2
G2
G1
G1
DUMMY DUMMY
HVT Pair
LVT QUAD
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Wireline circuits beyond 40 Gb/s
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2.5-V, Broadband 49-GHz MS DFF2.5-V, Broadband 49-GHz MS DFF
45 GbsD QTransimpedance
Preamplifier50- Output
Driver
BiCMOSD-Flip Flop
CLKBuffer
CLK
Data
In
Data
Out
12 Gb/s 40 Gb/s
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2.5-V, 80-GHz driver with pre-emphasis and2.5-V, 80-GHz driver with pre-emphasis andgain controlgain control
Vop V
onQ2
Q1 33x2mmx130nm
125 pH
50 pH
VDD
= 2.5 V
55
4x4.8mm
Q4
Q3
50 pH
27.5
2x4.8mm3x4.8mm
10 mA 10 mA
10 mA
10 mA 10 mA 10 mA
20 mA
2x4.8mm
23.5
3x4.8mm
Adjustable gain with peaking
Gain > 0 dB @ 94 GHz
S22
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80-Gbs SiGe BiCMOS 280-Gbs SiGe BiCMOS 23131-1 PRBS Generator-1 PRBS Generator
T. Dickson et al. ISSCC-2005
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Selector: BiCMOS 80-Gb/s
RLRLLP1 LP1 LP2
LP2D1D2
CLK
VGTAIL
VCC = 3.3V
DOUT
EF2 & series-shunt peaking for
highest speed3-D stacked inductor for reducedarea and high SRF
D1
D2
CLK
DOUT
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40-Gb/s Feed Forward Equalizer40-Gb/s Feed Forward Equalizer
core of each gain stageis a Gilbert cell
tail current of the
differential pair controlsthe tap weight (GAINpad)
SP/N pads control thetap sign
A. Hazneci et al. CSICS-2004
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40 Gb/s over 9-ft SMA cable + 3dB attn.40 Gb/s over 9-ft SMA cable + 3dB attn.
input output
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10 Gb/s equalization over 24-ft SMA cable +6dB attn.10 Gb/s equalization over 24-ft SMA cable +6dB attn.
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100-Gb/s transmission over 5cm of on-chip100-Gb/s transmission over 5cm of on-chipinterconnect possible in 90nm SiGe BiCMOSinterconnect possible in 90nm SiGe BiCMOS
Model extracted from
meas. on 3.6-mm long line 7-tap FFE equalizer
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Summary
Key design ideas:
Optimal solutions exist for LNA, TIA, VCO, (Bi)CMOS-CML gate topologies
Biasing at minimum noise figure current density
Matching noise impedance to signal source (tank)impedance
Key MOSFET circuit scaling ideas
FETs should be biased at constant current density
Circuit size and bias current invariant over nodes
while performance improves with scaling Circuits in the 50-80 GHz range
Sub-3W, 100 Gb/s Ethernet transceiver possible in 250-GHz, 90-nm SiGe BiCMOS technology
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Acknowledgments
Bernard Sautreuil for his support over many years
STMicroelectronics for fabrication
Micronet, NSERC, Gennum Corporation andSTMicroelectronics for financial support
OIT and CFI for equipment grant
CMC for CAD licenses
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Backup
I t f li i d b i
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Impact of scaling in deep-submicronMOSFETs (500nm to 50nm)
As a result of the constant-field scaling rules beingapplied to every new CMOS technology node:
Voltages scale by factorS
Vertical & lateral electric fields remain constant
Charge per unit gate width and current per unit gatewidth remain constant
The classical MOSFET I-Vsquare law remains validonly at very low V
effbeyond which it becomes linear
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Mobility degradation
Mobility degradation due to the
vertical gate field dominatesbehaviour (based on Intel data, S.Thompson, IEDM'99 Short Course).
The lateral field (due to VDS
bias) is about 50 times smallerthan the vertical field
ac[ cm2
Vs ]330Eeff1/3[ MVcm ]sr
[
cm2
Vs
]1450Eeff
2.9
[
MV
cm
]
eff=acsr
acsr
M d f & b h h ld
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Measured transfer & subthresholdcharacteristics in 90-nm n-MOSFETS
Meas red small signal g C C
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Measured small signal gm, C
gs, C
gd
characteristics in 90-nm n-MOSFETS
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Si vs. III-V FETs: fT, f
MAX
peak fT: 0.3 mA/mm
peak fMAX: 0.2 mA/mm
S. Voinigescu et al. JHSES,March 2003
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Consequences of constant-field scalingin 500 nm to 50 nm MOSFET channels:
C'gs,C'gd, C'db constant over nodes down to 130 nmthen decreasing as scaling oft
OXstopped at 1.2 nm
g'm, g'ds, fT, fMAX increase
FMIN, Rn decrease RF & high-speed performance (except output
swing) improves with scaling
Constant current density biasing ensures design
robustness over bias current, VT, process variation,nodes & foundries
Scaling is good for high-speed digital/wireline
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Slide 49
60-GHz, single metal inductor for VCOs
Planar spiral inductor:
Diameter = 27 mm
Turns = 1 S = 2 mm, W = 2.5 mm
C. Lee et al. CSICS-2004
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Applying negative feedback for noisematching
Negative feedback has similar impact on noise andinput impedance
Use Y-matrix to analyze noise params of:
Multifinger MOSFETs
CMOS inverter topology
Parallel (transimpedance) feedback circuits
Use Z-matrix to analyze noise params of:
Differential stage Series feedback circuits:
Tuned LNA with L (xfmr) degeneration
EF input
Inverter with resistive degeneration
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Series feedback for noise matching
zSOP=rSOPA2 rNF
gNA2rCORAZ11F
2Z11FzCORFZ11F
2gNF
gNAj[XSOPZ11F]
FMIN=12gNA [rCORArSOPZ11 F]
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Parallel feedback for noise matching
YSOP=GSOPA2 GNFRNA
2GCORAY11F2Y11F
YCORFY11F2
RNF
RNAj[BSOPY11F
FMIN=12RNA [GCORAGSOPY11F]
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Inverter noise matching
FZo=11
1L0Z0
2Z0
RN
YCOR
2
Z0
2
GN
lEWOPT=
1
2
Z0
1
GRGC2B2
TIA noise matching
FZo=1RNA Z0YCORA1
Z0
1
RF
1j0
102
2
Z0 GNAZ0
RF
1
102
lEWOPT=1
1
Z0
1
RF
1
102
2
1
RF
0
102
2
1
GRGC
2B2
RF > Z0 for 50match, resulting in lower noise & smaller transistor
size than low-noise INV design
ZIN=RF
1RC IT
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CMOS topology
In 90-nm CMOS, the p-MOSFET is low-noise andfast enough for most applications up to 40 Gb/s
Use CMOS inverter to improve gm/I, Rn to savecurrent over NMOS-only implementations
Si CMOS SiGe BiCMOS InP low noiseSi CMOS SiGe BiCMOS InP low noise
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Si CMOS, SiGe BiCMOS, InP low-noiseSi CMOS, SiGe BiCMOS, InP low-noisebroadband preampsbroadband preamps
OUT+
OUT-
IN+
IN-
IN
OUT+
OUT+
Low noise broadband preamps: InP vs SiGeLow noise broadband preamps: InP vs SiGe
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Low-noise broadband preamps: InP vs. SiGeLow-noise broadband preamps: InP vs. SiGeBiCMOSBiCMOS
(H. Tran et al. GaAs IC Symp. 2003 for InP TIA)(H. Tran et al. GaAs IC Symp. 2003 for InP TIA)
InP: 40 Gbs
NF at 10 Ghz Data Rate Sensitivity
CMOS 16.5 dB 20 Gb/s 20 mVpp
SiGe-HBT 10 dB 40 Gb/s 20 mVpp
InP-HBT 11.5 dB 40 Gb/s 8 mVpp
SiGe: 40 Gbs
Push-Push VCO measurements (cont)
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Slide 57
Push-Push VCO measurements (con t)
Tuning characteristics:
Tuning: 10 GHz
(10.2%)
Tuning: 15 GHz
(21%)
C. Lee et al. CSICS-2004
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CMOS VCO design scaling and porting
As technology scales to next node, g'm increases butV
MAXdecreases,
Ideally Wand IDS are fixed to maintain VOSC
In reality Wand IDS
must be reduced in sync with VMAX
maximum fOSC increases hence largerCvarcan be used
Scaling allows for smallerIDS&Wbut not necessarily better
L(fm)
Hi h S d L i F M
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High-Speed Logic FoM:CML Gate Delay
SLHBT=ICpeakfT
CbcCcsSLFET=
IDpeakfT
CgdCdb
HBTV CbcCcsIT
kRb
RL V C1AVCbc
IT
FETV
CgdCdb
IT
k
Rg
RL
V
Cgs1AVCgd
IT
BiCMOSVC
Ccs
ITkRgRL V
CgsCgdIT
Scaling of MOS/BiCMOS CML logic
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Scaling of MOS/BiCMOS CML logic
Assumes maximum inductor SRF of 80 GHz*nH andSRF=2*Bitrate
Numbers in brackets include emitter(source) followers
Table 1: fanout-of-1 latches ideal i.e. no parasitics, *) measured
Latch Family Rate:Gbs VDD (V) DV (V) IT(mA) P D(mW) Ind (nH)
130nm MOSCML 40 1.8 0.5 1.5(2.4) 2.7 2
130nm BiCMOSCML
40 1.8 0.2 0.83 (1.6) 1.5 (2.9) 1
130nm BiCMOSCML *)
12 2.5 0.2 1 2.5 0
130nm BiCMOSECL *) 50 2.5 0.25 7.5(12.5) 18(30) 0.25
90nm MOSCML 40 1.2 0.38 1.8 2.2 0.5
90nm BiCMOSCML
40 1.5 0.2 1 1.5 0.5
90nm BiCMOS
CML extracted
30 1.5 0.2 1 1.5 0.5
65-nm MOSCML 60 1 0.35 2.5 2.5 0.5
49 Gb/ 6 ft bl49 Gb/ 6 ft bl
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49 Gb/s over 6-ft cable49 Gb/s over 6-ft cable
49 Gbs
43 Gbs