ElectronicsCircuit Designer's Casebook

Published by Electronics -1221 Avenue of the Americas, New York, N.Y. 10020

McGraw-Hill Books for Electronics Engineers

CHARACTERIZATION OF

SEMICONDUCTOR MATERIALS

By PHILIP F. KANE, Director, andGRAYDON F. LARRABEE, Manager, CompositionalMethods Branch, both of Central Analysis & CharacterizationLaboratory, Texas Instruments, Inc.333 pages, 221 illustrations

Requiring no special knowledge of semiconductor technology,this comprehensive one -of -a -kind volume brings you a wealthof practical information for the evaluation and applicationof semiconductor materials and characterization techniques.Geared to meet the needs of all professionals, this uniqueguide provides a brief account of semiconductor develop-ment, then presents a concise nonmathematical analysis ofthe band theory. Semiconductor principles, bulk materialcharacterization, single -crystal growth, chemical and physicalimperfections in single crystals, epitaxial films, diffusion, andthin films are among other topics discussed.

THE NEW ELECTRONICS

By BRUCE SHORE, Administrator of Scientific Information,Radio Corporation of America254 pages, 85 photographs

Today's solid-state revolution-from the discovery of thetransistor in 1948 - is discussed in this "how -it -works -and -where -it -came -from" guide. It takes you into the laboratorieswhere the great discoveries were and are being made, andexplains in everyday language exactly what is happening.Completely up to date, the book offers you a rapid under-standing of solid-state electronics and the phenomena asso-ciated with it - shown not only in all their beauty and spiritof adventure, but in their growing centrality to industrial andindividual life. Illustrated with scores of photographs, thebook offers full historical background from the ancientGreeks to the dedicated men and women involved in thefield today.

AN ILLUSTRATED GUIDE

TO LINEAR PROGRAMMING

By SAUL I. GASS, Vice President, World SystemsLaboratories, inc.224 pages, with charts, graphs, and drawingsIn this excellent nontechnical introduction to an importantnew tool for solving business problems, the author draws ona wide variety of actual situations to show you just exactlywhat linear programming is, what it can do, how it is applied,and what kinds of problems it can handle for you. The searchfor the best solution - the optimum solution - has intriguedman throughout the ages, and this new, completely authorita-tive but thoroughly entertaining new book offers you allessentials of a key element in management today. Movinglogically from the simple (getting dressed each day) to themost sophisticated levels of linear programming, the bookis an admirable springboard for more advanced work andstudy in the entire fascinating field.

SOLID-STATE ELECTRONICS

A Basic Course for Engineers and TechniciansBy ROBERT G. HIBBERD, Serniconductor-ComponentsDivision, Texas Instruments Incorporated164 pages, 7 x 10, 90 illustrationsThis unique work presents the principles of semicon-ductors in an unusual way. It starts with a descriptionof semiconductors and their properties, the p -n junctionand the junction transistors, and the characteristics oftransistors and basic transistor amplifier circuits. It thendescribes the manufacture of transistors and other semi-conductor materials and devices. The book also discussesthe whole family of semiconductor devices and examinesthe applications of integrated circuits. Down to earth inpresentation, it can be used by non -technical readers toobtain a working familiarity with the subject.

SOURCEBOOK OF ELECTRONIC CIRCUITSBy JOHN MARKUS, Manager, Information Research,McGraw-Hill Inc.896 pages, 81/4 x 11, over 3000 illustrationsA virtual desk -top retrieval center for engineers, designers,and technicians in all areas of electronics, this first bookof its kind contains over 3,000 electronic circuits, completewith values of all components. A distillation of circuitknowledge for the past ten years, it brings together ma-terial from many diverse sources. The majority of circuitsshown are recent semiconductor designs, but importantelectron -tube circuits are 41equately represented. Includedwith each circuit is a concise description of its significantfeatures, performance data, and operating characteristicsso you can find the circuit that most closely meets yourneeds in any practical, on-the-job situation. It also tellsyou where to get further information on each circuit.

HANDBOOK OF SEMICONDUCTOR

ELECTRONICS, Third EditionEdited by LLOYD P. HUNTER, Professor of ElectricalEngineering, University of Rochester, and prepared by17 top specialists1,100 pages, 963 illustrations and tablesEverything you need to know about semiconductor circuitryis clearly explained and illustrated in this practical book. Anow -famous work, it brings you step-by-step guidance indevice physics, fabrication techniques, evaluation methods,and circuit design techniques in a single volume. Writtenby specialists who were chosen for their proven knowledge,ability, and experience, the book includes all recent advancesto keep you abreast of today's rapidly developing integratedcircuit techniques. In this new edition, a section has beenadded on the design of integrated operational amplifiers, andalso a section dealing with the utilization of computers. Pageafter page of illustrations and tables offer visual clarity toevery key aspect of semiconductor circuitry, and the entirebook has been completely expanded, updated and revised.

INTEGRATED CIRCUITSDesign Principles and Application

Prepared by THE ENGINEERING STAFF,MOTOROLA, INC., Semiconductor -Products Division385 pages, 71/4 x 97/s, 298 illustrations

With the help of this authoritative guide you can easilyapply the valuable know-how of over twenty outstandingcircuit design engineers to your own daily design problems.It gives a unified treatment to all phases of integrated cir-cuits, clearly and precisely defining every important pointfrom initial material processing to device packaging andreliability testing. You'll find in it detailed information onsuch subjects as acceptor doping . . . hole -electron spinassymmetry ... recombination and generation ... the gaus-sian distribution . . . diffusion time . . . sheet resistance... and much more.

HANDBOOK OF THIN FILM TECHNOLOGYEdited by LEON I. MAISSEL, Manager, Thin Film BasicStudies, and REINHARD CLANG, Manager, DeviceProcess Studies, both IBM Components Division,East Fishkill, New York1,216 pages, 887 illustrations plus charts and tables

This all-inclusive reference work offers you today's latest andmost dependable source of guidance on thin film theory andpractice. The volume serves both as an introduction to thefield and a practical day-to-day guide for scientists engagedin thin film work. Profusely illustrated, it gives you easyaccess to all information you need, helping you to catch upwith the fast-moving field. Each of the 23 detailed sectionshas been written by a recognized authority who covers thesubject areas he knows best. Divided into four sections: Prep-aration of Thin Films, The Nature of Thin Films, Propertiesof Thin Films, and Applications of Thin Films (this lattersection with particular emphasis on thin films in the elec-tronics industry).

See additional titles and ordering information on back cover

Electronics.Circuit Designer'sCasebookPublished by

ElectronicsA McGraw-Hill Publication

Price $4.00, Printed in U.S.A.

All material copyrighted byElectronicsMcGraw-Hill, Inc.1221 Avenue of the Americas,New York, New York 10020

Table of ContentsMEASUREMENTNomograph determines aperture time error 1

Differentiate and count to find frequency error 14Logic system checks out analog -to -digital converter 38Logic probe with LED display checks ECL circuits. 46Converter for oscilloscope provides four -channel

displays 46TTL gates speed up pulse -height analysis 50Feedback linearizes resistance bridge 64Soldering iron converts to constant -temperature

probe 65Precision auto tachometer squelches point bounce 76

POWER SUPPLIESStable voltage reference uses single power supply 16Filament transformer output drops cost of 400 -Hz

supply 24Regulating high -voltage with low -voltage transistors 25Pulsed standby battery saves MOS memory data 28Four -ampere power supply costs just $13 to build 74

FILTERSTunable active filter has controllable high Q 7Wien bridge in notch filter gives 60 dB rejection 54Active filter has separate band and frequency

controls 57Voltage -tuned filter varies center frequency linearly 69Active resonators save steps in designing active

filters 90Active filters get more of the action 95Tables shorten design time for active filters 113

GENERATIONMOSFET network minimizes audio oscillator

distortionBootstrapped capacitor stabilizes UJT oscillatorOp amps generate precision staircaseStable square -wave generator provides broad

bandwidthECL gates stretch oscillator rangeTriangular -wave generator spans eight decadesOutput comparator enhances versatility of one-shotThumbwheel switches set synthesizer output

frequencyDouble -duty multivibrator gives complementary

outputsPreset generator produces desired number of

pulsesPulse generator accuracy is immune to agingMultivibrator clock obeys digital commandsGenerator independently varies pulse rate and

widthExclusive -OR gate makes bidirectional one-shot.C-MOS sums up tones for electronic organStaircase generator resists output driftBinary division produces harmonic frequencies..One-shot timing performance: don't take it for

grantedThe integrated Schmitt trigger: a versatile design

component

AMPLIFIERSTransducer preamplifier conserves quiescent power

348

10183031

34

39

424555

61

66707374

87

101

13

Series -connected op amps null offset voltageOp amps multiply RC time constantsControlling op -amp gain with one potentiometerOp amp with feedback makes full -wave rectifierComplementary output stage improves op -amp

responseApproximating true log output at high frequenciesDoubling op amp summing powerInstrumentation amplifier conditions computer

inputsDynamic zero -correction method suppresses

offset error in op amps

CONTROLSCR reset for integrator provides high speedFeedback current switch divides rf inputs by 20Fast -switching modulator reverses uhf signal phaseLinear signal limiting with feedback multiplierHeight -to -width converter digitizes analog samplesControl one-shot divides frequency by up to 30Series resistance improves potentiometer linearityAmplitude modulator is highly linearFETs remove transients from audio squelch circuitDiode plus low-cost op amp makes accurate

thermostatBroadband cutoff limiter is phase -transparentFrequency doubler accepts any waveshapeOp amp cancels video switching transientsPrecision integrator resets as it samplesLogic circuit converts synchronous motor to

stepperQuasi -matched MOSFETs form filterless squaring

circuitGated MOSFET acts as multiplexing switchStepper drive circuit boosts motor torqueTemperature -stable decoder for modulated pulse

widthsElectronic fuel injection reduces automotive

pollution

COMPARATORS AND DETECTORSVSWR detector protects class C rf amplifiersOne-shot/flip-flop pairs detect frequency bandsAnalog voltage sensor controls LED thresholdPhotodetector senses motion in noisy surroundingsAgc rf threshold detector provides fast slewingPhase comparator for servo loops

LOGICSchottky diodes eliminate two -level NAND gatingTwo adders form BCD subtractorFeedback latch reduces memory recovery timeSimple logic circuits compare binary numbersUnclocked logic element makes quick decisionsCircumventing BCD addition in digital

phase -locked loopsSchmitt trigger prevents clock train overlapLogic driving gates double as d -a converter

switchesWired -OR gates increase multiplexer input capacityGray -code generator avoids output glitchesRing counter eliminates false gating signalsTransistor gating circuit cuts signal delay to 100 psDiode switching matrices make a comebackTake a bit of advice: use 16 -bit converters carefully

21

254856

6081

84

119

123

26

16192328323536

3741

434452

58

636768

70

104

11

2751

627778

911

152022

3340

495256587279

109

COMPUTER -AIDED DESIGNBrief Fortran program for active low-pass filters 4Programs in Getel speak test engineer's language 125Sceptre rules benevolently over computer -aided

design 130Optinet guides electronic products from design

through marketing 136Program calculates load effects of high-speed

digital circuits 143Computer helps design of complementary MOS

logic 147Aedcap: the circuit designer's computer -assisted

slide rule 152Easy -to -use Hypi program makes possible transition

from nonlinear to linear transistor model 157

ForewordAsk any electronics engineer if he could use another filterto work with and, after mentally ticking off such types asconstant -k, m -derived, Chebyshev, Butterworth, active, L -C,and a host of others, he'd probably say: "Thanks, but nothanks. I have enough problems building the ones I knowabout." But there is another kind of filter every engineerneeds desperately-an information filter.

Probably no one works closer to ground zero in the in-formation explosion than the electronics engineer. Howcan he recognize and save the published material that'sof lasting value, but only note and then discard the currentnews information that has a built-in obsolescence factor?Making these evaluations under the real-time pressures ofcompleting a design project isn't easy.

Books like this one, we feel, will help him assemble areadily accessible storehouse of design information witha long shelf life. In this case, we have done the filtering.

This book is a collection of recently published basic,how-to articles from the technical article section of Elec-tronics, combined with brief circuit ideas from the De-signer's Casebook section. It can be used both as anup-to-date practical design textbook and as an idea book.

The editors of Electronics

Nomograph determinesaperture time errorby Stephen MuthILC Data Device Corp., Hicksville, N.Y.

A simple nomograph does away with the tedium of cal-culating the error due to aperture time for a sample -and -hold circuit. It can also be used to compute the con-version error of an analog -to -digital converter whichhas a varying dc signal or a low -frequency ac signal asits input.

Being a measure of the repeatability of the analogsampling switch characteristic, aperture time reflects theuncertainty of when exactly the switch opens. Errorsdue to it vary with the signal rate of change at thesample point. The voltage that is sampled and held canhave an error of:

E = (dv/dt)Twhere E is the voltage change or error, dv/dt the max-imum signal rate of change, and T the aperture time.

The nomograph shown is based on this relationship,and assumes a full-scale input voltage swing at the fre-quency of interest. If the signal is less than full scale, theerror will be smaller. When the only limit on the inputsignal rate of change is slew rate limiting, dv/dt is easilycomputed and the nomograph is not necessary.

As an example, suppose the maximum allowable er-ror for aperture time is 0.5% and the upper frequencylimit is 2.6 megahertz. Use a straight -edge to intersectthe frequency axis on the bottom and the error axis inthe center. Maximum permissible aperture time is readfrom the top axis -300 picoseconds. (The present limitfor aperture time in high -accuracy -0.1% linearity-sample-and-hold modules is about 100 ps.)

To find the error of an a/d converter with a conver-sion time of 22 microseconds and a dc input varying at20 hertz maximum, treat conversion time as aperturetime and signal rate variation as frequency. Use ofstraight -edge and nomograph shows the maximum er-ror to be 0.3%. It should be noted that the error of thea/d converter can be reduced by two orders of magni-tude by employing a sample -and -hold module to keepthe converter's input constant for its full 22-µs conver-sion time.

Computation aid. Nomograph solves equation for percent -of -full-scale error dye to aperture time of sample -and -hold circuit. Error, E, canbe written in terms of signal rate, dv/dt, and aperture time, T: E = (dv/dt)T. Using straight -edge to intersect all three axes gives theanswer.(Signal rate is represented by frequency axis.) Conversion error of a/d convertor can also be found by using the same technique.

CI -0.5 pF

_L.0.01 pF

TEXAS7 INSTRUMENTS 12

SN76001 4

3

82 pF

25 A+ F

1 k23N128

1N914

100 k2

+6V

100 S2

25µF _ 100 p F

- 0.05 p F

R2 3.3 ki2

- 100 p F

ADJUST FOR DESIREDOUTPUT LEVEL

OUTPUT2 V PK-PK

SCR reset for integratorprovides high speedby Marshall W. WilliamsUniversity of Georgia, Athens, Ga.

A fast -switching three -gate reset circuit allows steady orvarying dc voltage to be converted into TTL-compatiblepulses for driving counters or other data storage or dataprocessing devices. The circuit, actually a digitizing in-tegrator, performs short-term integration on the inputvoltage. Each time an SCR conducts, the integrator sec-tion is reset, and a pulse output is obtained.

Because of its fast reset action, the circuit exhibitsgood linearity and accuracy. An output pulse rate of10,000 counts per second injects an error of only 1%,which decreases to 0.001% at 10 counts per second (cor-responding to a 25 -millivolt input to the integrator.) Er-ror, in this case, refers to the deviation from linearity ofinput voltage versus output frequency.

To avoid elaborate isolation circuitry, the SCR'S cath-ode is connected to the integrator's summing point, per-mitting the integrator to accept only negative voltages.Positive voltages can be accommodated by precedingthe integrator with an inverter stage.

The reset circuit consists of cross -coupled NAND gatesthat form an R -S flip-flop and another NAND gate, con-nected in a 1 -microsecond -delay inverter configuration,that keeps the flip-flop's Q output normally low. The in-tegrator output is fed through a forward -biased diode tothe base of a transistor, allowing the transistor to turnon only when the integrator output reaches approxi-mately 1.4 volts.

When the transistor conducts, its collector goes low,applying a negative -going transition to the flip-flop's Sinput. The Q output of the flip-flop now goes high, turn-ing on the SCR gate and producing a negative -goingTrL-compatible pulse at the flip-flop's 45 output.

As the Q output goes high, a delayed positive pulse isfed to the inverter gate, causing its output to go to logic0 and resetting the flip-flop. The integrating capacitor isdischarged to approximately 0.7 v (the turn-off voltageof the scR) to initiate the next integration period.

With the input resistor values shown, integrator resetrate may be adjusted to around 0.25 millisecond when-10 v is applied to the input; lower input voltages giveproportionately longer integration periods. A chopper -type operational amplifier is indicated in the diagram,but almost any op amp will work if larger drift errorscan be tolerated.

Digitizing integrator. Dc input voltage is integrated and 'converted into TTL-compatible pulses by reset circuit that switches SCR to dis-charge integrating capacitor. When integrator output turns on transistor, CI output of flip-flop (cross -coupled gates) goes high, switching on

SCR. Logic output pulse at flip-flop's CI output is terminated when inverter gate resets flip-flop and SCR turns off.

1 MS2

DC

0 TO 470 IcS2

- 10 V MAX

2

MOSFET network minimizesaudio oscillator distortionby Glen CoersTexas Instruments Incorporated, Dallas, Texas

Because a MOSFET feedback control keeps the outputlevel constant and prevents limiting, a low -distortionaudio oscillator can deliver several volts into a 50 -ohmload. The circuit uses a 1 -watt audio amplifier as bothan oscillating element and a power amplifier, and pro-vides a total harmonic distortion of less than 1%. More-over, it operates from a single supply, and holds outputlevel change below 0.2 decibels if the supply voltagechanges by 6 volts.

The oscillator circuit is a Wien -bridge type, in whichresistors R1 and R2, and capacitors Cl and C2 functionas frequency determining elements. First, R1 is chosenbetween 100 ohms and 1 kilohm. Then C1 = 1/2/rfoR1,where fo is circuit resonant frequency. The values of R2

and C2 are directly proportional to R1 and C1, respec-tively: R2 = 10R1 and C2 = C1/10.

An automatic gain control network at the negativefeedback terminal of the audio amplifier assures a low -distortion sine -wave output. The MOSFET acts as a vari-able resistor. Its resistance is set so that the gain of theamplifier and the loss of the frequency determining net-work are equal when the desired output is reached.

Negative half cycles of the output are rectified by adiode and filtered by capacitor C3. Resistor R3 providesa slight discharge path so that the peak level of the rec-tified voltage is maintained at the gate of the MOSFET,keeping output level constant.

If amplifier gain increases and output amplitude alsorises, more negative bias is applied to the MOSFET'Sgate, increasing MOSFET resistance to reduce amplifiergain and output amplitude. If the amplitude decreases,the MOSFET becomes biased in the forward direction sothat its resistance is lowered, and both gain and amp-litude are increased.

The audio amplifier used has an open -loop gain of 70dB. Attenuation of the frequency determining networkis 26 dB.

Power audio oscillator. MOSFET acts as variable resistor to control gain of audio amplifier, which functions as both oscillating element andpower amplifier. If output amplitude becomes larger than desired, MOSFET is back -biased, increasing its resistance and lowering amplifiergain. When amplitude falls below desired level, MOSFET is forward -biased to decrease its resistance and increase amplifier gain.

APERTURE TIME

10 ps 100 ps 1 ns 10 ns 100 ns 1 10 ps 100 msI I 1 1 1 Ilf 1 1 1 1111 1 1 111111 I II I 111 I I 1 1 1111 I I I IIII1 I 1 I 1 1111

0.01 %

ERROR

0.1% 1% 10%

I IIH1111j I I MN I I +MINI

1 1 11111

1 Hz

FREQUENCY

10 Hz

1 1 111111

100 Hz

1 11111111 kHz

I 1 111111

10 kHz

1 1 1 11111

100 kHz

1 1 1 11111

1 MHz

I 111111110 MHz

3

Bootstrapped capacitorstabilizes UJT oscillatorby Michael J. DebronskyKDI Labtron Corp., Dayton, Ohio

A highly accurate low -frequency relaxation oscillatorcan be built by making the circuit independent of theunijunction transistor's interbase resistance. Simplybootstrapping the voltage of the charging capacitorthrough a temperature -compensated zener diode backto the UJT's base2 does the job. Good frequency stabilitycan be attained -0.05% over a 0°C -55°C temperaturerange and 0.5% for a 100% change in the supply.

There are certain circuit conditions that must be ob-served, however, for good stability. The value of timingcapacitor C1 must be much greater than that of bypasscapacitor C2. The latter bypasses any zener noise toavoid output jitter. Moreover, current through timingresistor R1 must be more than Qi's base current, andthe UJT's voltage must be larger than the zener's.

Ci is discharged by the UJT when its voltage is:V, = 11V,(1-71)

where n is the intrinsic standoff ratio of the UJT, and Vzis zener voltage. Usually, the base -emitter voltages ofQi and Q2 are small compared to Vz. Then:

Va = Clf i(t) dt = VA/RIC'

And output pulse duration becomes:t = 1/f = 11RiC1/(1-71)

For 60 -Hz operation, R1 ranges from 10 to 50 kilohms,and C1 must be greater than 0.001 microfarad.

R1

Tightening frequency stability. Low -frequency oscillator providesfrequency stability of 0.05% over a temperature range of 0°C to55°C. Bootstrapping voltage of timing capacitor C1 back to base2 ofunijunction frees oscillator circuit from dependence on UJT's inter -base resistance, the usual cause of .nstability. Temperature -com-pensated zener and bypass capacitor C2 are also used.

Brief Fdrtran program foractive low-pass filtersby Irvine P. Stapp, Jr.University of Kentucky, Lexington, Ky.

A short computer program, written in 1130/1800 For-tran, makes it possible to design three -pole active low-pass Butterworth filters with gains between 1.00 and2.00. What's more, the program can be easily translatedinto Basic computer language.

Unlike previous programs, the one shown in (a) uses

a simple iterative procedure to converge on normalizedelement values, instead of solving for the roots of a cu-bic equation. This technique simplifies calculating gainsother than unity. Finding capacitor values that are ac-curate to one part in 107 (0.1 ppm) requires about 30traversals of the iteration loop.

A filter designed with the program shown in (b) pro-vides a 15 -hertz cutoff frequency and a gain of 1.20. Thefilter is intended to drive a multiplexer input networkwith a gain of 1/1.20.

If a small amount of gain is included in an active fil-ter, many scaling amplifiers frequently can be elimi-nated from a multiplexed analog -to -digital systemwhere over-all gain must be maintained at some estab-lished value. For example, certain process control corn -

4

R1

puters, like the IBM 1800, require multiplexer inputpoints to be preloaded with low impedances, in the or-der of 1 kilohm shunted by 0.05 microfarad. Only a fewoperational amplifiers can tolerate this much capaci-tance with a tight feedback loop. But many will functionproperly if decoupled from the capacitive load by about100 ohms.

A sample of the program's output, also included in(b), shows the design solution: K is the number of itera-tions required to reach desired accuracy; L, M, and Nare normalized capacitor values in farads for a 3 -decibel

(a)

WRITE (4,21)21 FORMAT('IELLMEN7 VALUES FOR 3 -POLE LOW PASS BUTTERWORTH FILTER WIT

1H PREASSIGNED GAIN OETWEEN 1.00 AND 2.00.1//' K IS LOOP INDEX WHEN2 SOLUTION CONVERGED TO 0.1 PPM.'//' L,M,N ARE CAPACITOR VALUES IN3FARAOS, NORMALIZED TO 1 OHM, 1 RADIAN/SECOND.')READ (3,20) NRUN

20 FORMAT (12)

DO 88 J=1,NRUNREAD (3,23) F,R,G

23 FORMAT (T1,E13.6,T15,E13.6,730,E13.6)AM =1.AN = 1.

AL . 1.

C=G -1.

DO 200 K=1,99BM=AMBN=AN8L.AL

AL=2.-3../1111+2..AM.E

AN.(2.+4.M.AL.E)/(2.(AL.AM))AM.1./(AL.AN)IF CAL*AM+AN-1.E-04) 250,250,260

point of 1 radian per second. Besides capacitor values,the program finds the values for R1 and R2 that yieldoptimum filter gain.

Other common low-pass filtering functions can be re-alized with the program by modifying the iterativeequations. A data card is needed to indicate the numberof runs, followed by cards specifying, for each run, thedesired cutoff frequency in hertz, the resistance level inohms, and amplifier gain. Program statement 23 pointsout where the data should be placed on the card. Theprogram is easily adapted for remote terminals.

26C IF CABS(GL-AE.)AGS(BN-AN).,ABS(BM-AM)-1.E-07) 300,100,20025C E.F.11-052E0 CONTINUE

300 WRITE (4,22) K,AL,AM,AN ,G22 FORMAT(101,11, K=',I3 ,T21,11.=',E13.6,138,111=1,113.6,756,'N=1,E

113.6,174,1G=1,11/.6 )Q. 159154.9/(F.R)CI.ALNC2=AM'QC3RK:114-1(1Q.E-03

R1.3..0.40(

R2.RI/E

NRITE(4,24) G,RK,F,C1,C2,C3 ,R1,R224 FORMAT ('0','F00 GAIN OF',F6.2,' AND RESISTORS OF',F6.2,' KILOHMS

1 A CUTOFF FREQUENCY OF',F9..' HERTZ REQUIRES'/I' ','Cl.',10.6,38

2,'C2=',F9.6,3X,'C3.',F9.6,1X,'MICROFARADS. OPTIMUM GAIN -SETTING RE3SISTORS ARE 7/",'R1=',01.4,38,'R:=',F9.4,1X,'XILOHMS'///' '.1194(18.))

88 CONTINUE

CALL EXIT

END

(b)

20 kS2

INPUT C,

R2

360 k52

20 02 20 1(12

I-

200S2

1 KE2 0.05µFTO

MULTIPLEXER

ELEMENT VALUES FOR 3 -POLE LOW PASS BUTTERWORTH FILTER WITH PREASSIGNED GAIN BETWEEN 1.00 AND 2.00.

K IS LOOP INDEX WHEN SOLUTION CONVERGED TO 0.1 PPM.

L,M,N ARE CAPACITOR VALUES IN FARADS, NORMALIZED TO 1 OHM, 1 RADIAN/SECOND.

K= 29 L= 0.150211E 01 M= 0.169718E 01 f1= 0.392253E 00 G= 0.120000E 01

FOR GAIN OF 1.20 AND RESISTORS OF 20.00 KILOHMS A CUTOFF FREQUENCY OF 15.00 HERTZ REQUIRES

Cl' 0.796896 C2= 0.900386 C3= 0.208096 MICROFARADS. OPTIMUM GAIN -SETTING RESISTORS ARE

R1= 71.9999 R2= 360.0000 KILOHMS

Filter design. Fortran listing (a) eases design of three -pole active low-pass Butterworth filters. Program finds capacitor values and optimum -gain resistors. Filter gain is preset between 1.00 and 2.00; the value of ladder resistors is also fixed. Program uses iteration for extremely ac-curate capacitor determination. Design example for 15 -hertz filter and sample of program output are given in (b).

5

Feedback current switchdivides rf inputs by 20by Roland J. TurnerRCA Corp., Missile and Surface Radar division, Moorestown, N.J.

In a ripple -carry binary feedback counter, countingdown to 20:1 requires five binary stages, and the time ittakes for the signal to pass through all five stages limitscounting speed. But an analog counter that employspositive feedback around a single current switch stagerequires only one transition period to establish thecount. This current switch, which has a transition timein the order of 1 nanosecond, counts a 1-gigahertz sig-nal down to 50 megahertz in one stage. Two switches incascade, then, provide a 400:1 countdown.

The usefulness of the counter lies in its ability to pro-vide a low -frequency sync signal that is locked to an rfcarrier, so that full advantage can be taken of an oscil-loscope's vertical bandwidth. The detailed character-istics of each rf cycle of the signal may then be observedon a scope with a low -frequency sync capability.

When an rf signal at the base of transistor Qi goes

positive, the base of transistor Q2 is driven negative,turning Q2 off. As the emitter current of Q2 changes, theemitter current of transistor Q3 is forced to increase, andstarts positive feedback action through capacitor CI tothe base of Q2. Additional positive feedback is fed fromthe collector of Q2 to the base of Q3 through C2.

During the recovery period of Q2, the current switchformed by Q2 and Q3 acts as a high-speed comparator,while the base voltage of Q2 decreases toward ground.As soon as the most positive swing of the input signalexceeds the VD bias at the base of Q3, positive feedbackbegins again, and the switch automatically resets itselfto the initial state. Transistor Q4 serves as an outputbuffer to drive another analog stage. The output is asquare wave with a 2.2 -volt peak -to -peak amplitude.

Potentiometers R1 and R2 control the initial bias con-dition of Q2 and Q3, respectively. And the collector biasof both Q2 and Q3 is well above their saturation voltage.Moreover, when one of these transistors is in cutoff, itstill has a 1 -milliampere idling current to assure that itmaintains a high fT.

The countdown of the circuit can be altered by re-turning R2 to a different supply voltage.

Divide -by -20 counter. Analog circuit counts down rf signal in one transition. For positive input, 02 turns off and Q3 turns on, causing

positive feedback to Q2's base. While 02's base voltage approaches ground, 02 and 03 perform as high-speed comparator. When rf input

exceeds 03's base bias, positive feedback resets 02 and 03 to their initial state. at is buffer stage for output square wave.

5.1 kS2

e,

1300 MHz) 0.001

5.1 kS2

20 kS2

1 k2

1µH

2N5841 47 pF

-22 V

5 kS2

C1

I

160 pF

R1

+22 V

910 2 20 kS2

220 S2

C2

0.1 ;IF

I220 2

1N4376

100 pF

22 k 2

160 pF

022N5841

Q3

2N5841

1N4376}41

1N4376

1N4376

1.8 kS2 22 k2

-22 V

VD

042N5841

680 S2

(15 MHz)

6

Tunable active filterhas controllable highby Max ArtusyStanford Electronics Laboratories, Stanford, Calif.

A tunable variable -Q active narrowband filter can bebuilt from a slightly modified Wien -bridge oscillatorwith a net loop gain of less than unity. Not only can Qbe independently controlled, but stable single -fre-quency Qs as high as 2,000 can be realized. A gain of600 is achieved with a Q of 2,000. Gain becomes ap-proximately 140 when Q is 30, and Q remains constantwithin ±10% over a 10 -to -1 tuning range. (Gain, in thiscase, refers to signal gain, from input to output, ratherthan amplifier or loop gain.)

Although it is generally known that the effective Q ofan oscillating tuned circuit is infinite, it is often forgot-ten that stable finite Qs can be obtained by reducing the

net loop gain below unity. In the conventional Wien -bridge oscillator, the gain of the amplifier looking intoits non -inverting input is maintained at 3, and the cir-cuit oscillates. For the modified oscillator, however, am-plifier gain is less than 3, allowing the Q of the sur-rounding RC network to be increased. And, as can beseen from the diagram, the value of resistor R1 is thesame as that for resistor R2, and the value of capacitorC1 is identical to the value of capacitor C2.

Signal current is introduced into the negative feed-back loop by R3, which also determines input imped-ance and circuit Q. For oscillation to occur:

1 + Ri/(R3+ Rs) must be less than 3.where Its is the source impedance. Resonant frequencybecomes:

fo = 1/27(RiR2C1C2)1/2Circuit components should be selected carefully for

best tuning range and constant Q. In particular, well -

matched wirewound potentiometers help maintain uni-form Q with changing frequency. All capacitors shouldbe Mylar. Nominal component values shown result in atuning range of 160 hertz to 1.6 kilohertz for the circuit.

Adjustable 0. Active filter offers Q of up to 2,000 that is stable to within ±10% for moderate Os over 10 -to -1 tuned frequency range. Actuallya modified Wien -bridge oscillator, the circuit operates with a net loop gain of less than 1 so that Q of RC network can be increased. Poten-tiometers RI and R2 and capacitors CI and C2 determine filter resonant frequency, while potentiometer R3 is an independent Q adjustment.

c,0.05 pF

82

20 k.0.

,11

TUNE+ 15 V

C = 0 05 pF20 k0.

Rs

741

15V

R4 10k12

101(00 SETHE LIPOT

OUTPUT

7

Op amps generateprecision staircaseby Jerald GraemeBurr -Brown Research Corp., Tucson, Ariz.

A staircase generator with adequate precision for se-quential control and multiple -level testing produces astaircase output by differentiating and then integratingonly the negative transitions of a square wave. Al-though a staircase waveform can be generated preciselyby a digital -to -analog converter driven by a clock -con-trolled counter, a simpler, but sufficient, circuit ap-proach is to use operational amplifiers.

Amplifier Al differentiates and rectifies input squarewave ei, which is applied to capacitor C1 through re-sistor R1. For positive input transitions, transistors Qiand Q2 are off, and diode D1 conducts; for negativetransitions, Qi and Q2 conduct. From this rectification,only negative -going transitions are transferred to the

Stepping up. Staircase generator first differentiates and then integratesdifferentiation, and 0, and 0 rectify all negative -going inputs, passing tnegative input steps up the output until 03-04 reset clamp triggers when

second amplifier through Q1 and Q2. Transistor biasingis implemented by connecting one input of Al belowground through resistors R2 and R3.

The staircase output is produced by amplifier A2,which integrates, through capacitor C2, the current sup-plied by Qi and Q2. The change in output voltage (Deg)becomes:

Pe, =C2

f i(dt)

where:i = Cide,/dt

Or, whenever input voltage change (fie;) is less than 0:Aeo = -C10ei/C2Each negative transition of the input square wave

creates a step in the output voltage, generating a stair-case waveform. This stepping continues until the outputvoltage reaches the trigger level of the reset clampformed by transistors Q3 and Q4.

The clamp triggers when the emitter -base junction ofQ4 breaks down, limiting the output to a peak voltage(Vp) of:

Vp = VCB - BVEB VHE - Vf

input square wave to supply precise stepped output. A, performs thehem on to integrator A2. Positive input transitions are not used. Every04's emitter -base junction breaks down.

3

where VCB is Q4's collector -base voltage, BVEB is Q4'semitter -base breakdown voltage, VBE is Q3's base -emit-ter voltage, and Vf is the voltage across diode D2. Be-cause the collector -base junction of inverted transistorQ4 is forward -biased, its voltage drop is around that ofthe diode, and:

Vert - Vf = 0-so that Vp is approximately equal to 7 volts:

Vp = VBE - BVEBSince the thermal variations of VBE and BVEB approxi-mately cancel, Vp is quite stable, with a temperaturecoefficient of around 0.01%/°C.

With Q4's breakdown, base current through Q3 acti-vates the positive feedback loop formed by Q3 and in-verted transistor Q4. Capacitor C2 is then dischargeduntil its voltage reaches VBE, the cutoff for clamp con-duction. Once output voltage returns to 0 v, the clampturns off, and a new staircase begins.

Gain error and nonlinearity for this staircase gener-ator vary with operating frequency and componentcharacteristics. Operational amplifier input currents re-move some of the derivative current pulses, and theyalso create output sag by discharging capacitor C2. Toprevent severe error from being introduced by these opamp input currents, amplifier input protection circuitrymust be avoided since such circuitry will draw high cur-rent during an input overload.

Slewing rate and overload recovery limit the gener-ator's operating frequency range. Another currenttransfer error results from the finite betas of transistorsQi and Q2. However, for the Darlington pair used, theloss is only about 0.002%. Resistors R4 and R5 are in-cluded to reduce an output nonlinearity that is intro-duced by leakage of the reset clamp. Circuit gain erroris typically about 0.05%, and nonlinearity is commonlyaround 0.1%.

Schottky diodes eliminatetwo -level NAND gatingby Charles J. Huber,Westinghouse Electric Corp., Systems Development division, Baltimore, Md.

To eliminate the need for two -level gating with NANDgates, a pull-up resistor and Schottky diodes can per-form the AND function at the input of a low -power TELgate. NAND gating causes an unwanted increase inpower consumption and delay time. The diode circuitcan be used for decoding sequence -generator outputs,encoding digital signals, and implementing the ANDfunction in counter designs.

Conventional pn junction diodes are not suitable foruse with low -power TEL gates since diode forward volt-age drop is comparable to the maximum allowablelogic 0 gate input voltage-around 0.7 volt. ButSchottky -barrier diodes exhibit only half the voltagedrop of pn junction diodes, permitting them to satisfythe TTL logic 0 condition.

Moreover, the dynamic change from logic 1 to logic 0at the output of a TEL gate is limited, since the common -base input stage is not rapidly cut off. Gate responsecan be improved considerably by placing a resistor fromthe supply line to the gate's input pin.

The test results in the table show that the worst -casedegradation of gate response time from no diodes tothree diodes is 35 nanoseconds for five-TTL loads. Sincethis time factor is comparable to the propagation delayof only one TEL gate, an entire gate delay is saved andthe power consumption is due principally to the pull-upresistor. When three diodes are used, the dc level at thediode -resistor junction is approximately 0.5 v.

Designer's casebook is a regular feature in Electronics. We invite readers to submit originaland unpublished circuit ideas and solutions to design problems. Explain briefly but thor-oughly the circuit's operating principle and purpose. We'll pay S50 tor each item published.

Diode gating. Pull-up resistor and Schottky diodes replace NANDgates at input of low -power TTL circuits, improving gate responsetime and decreasing power consumption. Since Schottky diode dropis only half that of pn junction diodes, Schottky diodes are compa-tible with logic 0 condition of TTL gates. Pull-up resistor decreasesgate response time by connecting gate input directly to supply.

MOTOROLA3- MM80 - 101

SCHOTTKY DIODES

50 kS2

4.9 V

TTL. LOAD

TEXAS INSTRUMENTSSN 74L00N

OUTPUT

DIODESTTL

LOADSRESISTOR

I kS2)

DELAY TIME(INPUT TO OUTPUT)

RISING EDGEIns)

FALLING EDGEIns)

0 1 75 70

0 5 ,,0 75 70

1 1 .. 70 110

1 50 80 65

2 1 50 85 65

3 1 50 80 65

3 2 50 80 80

3 3 50 80 95

3 4 50 85 105

3 5 50 85 105

9

Stable square -wave generatorprovides broad bandwidthby William StandkeHoneywell Inc., Corporate Research Center, Hopkins, Minn.

A high-speed analog comparator and a linear currentsource are the key elements in a stable square -wavegenerator that can oscillate from a few hertz up to sev-eral megahertz. The generator circumvents two com-mon sources of stability error-a nonlinear capacitor -charging current and limited op amp bandwidth.

Current source Q1 linearly charges capacitor C1 untilcapacitor voltage exceeds the reference zener voltage onone of the comparator inputs. The normally high outputof the NAND gate then goes low, starting the one-shottiming cycle. As the output of the one-shot goes high,Q2 turns on and sinks the current from Qi so that C1 isquickly discharged. When the one-shot finishes its tim-

ing cycle, its output goes low, Q2 turns off, and C1 be-gins to charge for the next cycle. Circuit oscillation pe-riod is approximately:

T = 3.3C1R1/0.7 + one-shot widthOne-shot output pulse width should be as narrow as

possible for width stability, but wide enough to dis-charge fully the timing capacitor. Resistor R2 slowsdown this discharge. Although R2 can be eliminated forsmall values of capacitance, it must be included forlarge capacitances to protect Q2 from excessive currents.

The generator's gate input line allows it to be startedand stopped with a digital signal. It should be notedthat the generator always starts in the same phase, andits initial cycle has the same period as the subsequentones. If the gating feature is not wanted, the gate lineshould be connected to a positive supply voltage (Vcc)In addition, the generator can be used as a voltage -con-trolled oscillator by replacing the zener with a controlvoltage or by controlling the base voltage of Qi.

The silicon transistors and switching diodes selected,as well as capacitor C1, depend on the operating fre-quency desired.

Controlled pulses. Square -wave generator offers stability and wide operating frequency range. C1 accepts linear charge from Q1 until itsvoltage reaches that of zener. Comparator then switches, starting one-shot and turning on 02, which discharges C1. When one-shot timingcycle is complete, 02 goes off, and C1 charges again. Gate input permits generator to be controlled digitally.

10

Two adders formBCD subtractorby Peter K. BiceHewlett-Packard Co., Microwave Division, Palo Alto, Calif.

Engineers often avoid using binary -coded -decimal(BCD) designs because the arithmetic involved seems tobe formidable. But BCD arithmetic can be almost as

simple as binary arithmetic. The circuit shown, for in-stance, does BCD parallel subtraction. All that is neededfor each digit is two four -bit adders and four inverters.

The first adder does the actual arithmetic, subtractingone digit from the other. The second adder converts thisdifference to BCD form and, if necessary, generates a"borrow" for a subsequent stage. The CARRY OUT is al-ways logic 1 unless a "borrow" is being generated. Thelast subtractor stage will have a logic 1 CARRY OUT ifthe difference between the two numbers is positive,or ifthe difference is zero.

The diagram shows one digit of a parallel subtractor.The stages can be cascaded, or one stage can service aserial shift register. BCD addition, it should be noted,cannot be implemented as easily as BCD subtractionsince more hardware is required.,

TEXASINSTRUMENTSSN74042

LOGIC 1

CARRY OUT

N2

1 8 10 16 4 7 11

4 4 -BIT ADDER

15 2 9

1 3 8 10 16 4 1 11

431T ADDER is

15 2

13CARRY IN

(LOGICFOR FIRSTSTAGE)

TEXASINSTRUMENTSSN7483

LOGIC 1

BCD OUTPUTIN, -N21

Digital arithmetic. A couple of four -bit adders and four inverters areall of the hardware required to build a BCD parallel subtraction cir-cuit. Top adder takes actual difference between input numbers N1and N2. Second adder then forms BCD number of this difference.Both "borrow" and CARRY OUT lines are included for use withother stages. Subtractors can be cascaded.

VSWR detector protectsclass C rf amplifiersby Frederick A. Warren, Jr.Harris-Inlertype Corp., Radiation Systems division, Melbourne, Fla.

An inexpensive protection circuit against open -circuitdamage to class C rf amplifiers senses and detects volt-age standing wave ratio with a single -turn transformer.In addition, the circuit removes drive from high -powerstages, has low insertion loss, and suppresses secondharmonics with a notch filter.

Any class C rf power amplifier must be operated witha load, once supply voltage and an rf signal are applied.If the load is removed, a high VSWR is created, and rfpower is reflected back to the output transistor's collec-tor. The resulting rf voltage swing can exceed the tran-sistor's collector -base breakdown voltage, causing col-lector current to increase in an avalanche manner sothat the base -collector or base -emitter junction opens.Risking this destruction is normally unavoidable, unlessthe designer is willing to accept a significant insertionloss or pay a high price for protection.

Figure (a) shows a block diagram of a high -powerclass C vhf amplifier-consisting of transistors Qi, Q2and Q3-externally connected to the protection- circuit.When the amplifier drives a properly matched load, aquiescent rf voltage develops across transformer T1.

This voltage is then rectified by hot -carrier diode D1,producing a negative voltage at the junction of resistorsR1, R2, and R3. The values of R2 and R4 force transis-tors Q4 and Q5 into saturation, creating a short circuitbetween Q4's collector and ground that allows Qi to op-erate normally, relatively insensitive to load phase.

If the amplifier load is removed or shorted, a highVSWR results, and the rf voltage across T1 increases. Therectified voltage at the resistor junction then becomesmore negative and pulls the base voltage of transistorQ5 down, driving both Q4 and Q5 into cutoff. Now, Qi'semitter opens, removing. the drive to transistor Q3 andtherefore shutting off the amplifier.

For adequate circuit reaction time, the R1C1 timeconstant should be less than one period of the ampli-fier's operating frequency. Resistor R3 sets the quiescentbase current of Q5. And the Q4 -Q5 Darlington pair op-erates with only a small drive voltage differential be-tween transistor cutoff and saturation regions.

The protection circuit also offers the advantage ofsecond harmonic suppression (the second harmonic ofan amplifier must be below some maximum powerlevel). Because a class C amplifier is usually operated ina saturated condition, it often generates high-level har-monics that require additional filtering after the outputstage, thereby creating undesirable insertion loss orcomplexity. But the protection circuit provides an in-tegral notch filter whenever its transformer's secondarywinding and capacitor C2 are tuned to the second har-monic of the amplifier's fundamental frequency. AndVSWR detection by the protection circuit suffers only

11

negligible degradation because of the filter.Graph (b) depicts the voltage levels at the base of

transistor Q5 when the amplifier output is loaded,opened. or shorted. The saturation and cutoff voltagesshown are those needed for the Darlington circuit. Theymust be less than the loaded voltage but greater thanthe open -circuit and short-circuit voltages. Graph (c),which shows amplitude -versus -frequency curves for theamplifier with and without the protection circuit, re-flects the amount of insertion loss. From 170 to 230megahertz, worst -case insertion loss is 0.15 decibel.

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Load watchdog. Output of class C rf amplifier (a) goes to protectioncircuit that shuts off amplifier when VSWR exceeds safe operatinglimit. Transformer T1 performs as VSWR sensing and detection ele-ment. Removing or shorting load pulls down Q5's base voltage, cut-ting off 04-05 Darlington pair and opening Q1's emitter to turn offamplifier. Plots (b) and (c) illustrate amplifier performance.

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Transducer preamplifierconserves quiescent powerby Robert F. DownsOcean & Atmospheric Science Inc., Santa Ana, Calif.

A low -voltage micropower preamplifier holds powerdissipation to approximately 13 microwatts because ofthe low bias current of its two -transistor impedance con-verter output stage. The preamplifier, which is intendedfor use with a capacitive transducer, operates at a quies-cent current of 10 microamperes with a supply voltageof only 1.35 volts.

The gate of field-effect transistor Qi is essentiallybiased at 0 v through resistor R1. Negative feedback,provided by resistor R2, maintains Qi's gate -to -sourcevoltage at approximately -0.4 v, forcing its drain cur-rent to less than 4p.A. Resistor R2, therefore, contributessignificantly to Qi's bias stability.

Preamplifier input impedance depends on both R1and the voltage gain of the field-effect transistor stage.Actual FET intrinsic input impedance can be ignoredsince it is orders of magnitude larger than R1.

If ei denotes input signal voltage, the voltage acrossR1 can be expressed as e1(1 + Kv), where lc is thestage's voltage gain. Since current through R1 is in-

creased by a factor of 1 + K, the apparent input im-pedance is RI/(1 +K,.).

On a small -signal basis, then, the preamplifier's inputstage is equivalent to a common -source configuration,while the bias arrangement is that of a source -follower.For the over-all circuit, the dc input impedance isaround 1.5 megohms, while the ac input impedance isabout 300 kilohms.

The FET selected for this circuit should have a lowpinch -off voltage (Vp) and a low drain current (Inns)when the gate -source junction is shorted. For the deviceused, Vp is about 0.1 v and IDas approximately 100 µA.Because a FET'S transconductance (gm) depends ondrain current, Qi's gm is only around 50 micromhos.

Since the FET'S output conductance is negligible, itsoutput impedance, like that of a common -source stage,essentially equals R2. Because this is a high resistancevalue, two bipolar transistors, Q2 and Q3, are used as animpedance converter.

This converter stage operates like a pnp emitter -fol-lower, providing very high values of current gain andinput impedance. Moreover, it realizes greater bias volt-age compatibility between the FET and bipolar stagesthan a conventional Darlington pair could. Converterbias current is about 6 µA, input impedance exceeds 2megohms, and output impedance is about 4 kilohms.

For the preamplifier, equivalent input broadbandnoise is relatively low, about 33 ay from 140 hertz to 20kilohertz. And voltage gain is nominally 5 (14 decibels).

Power pincher. Preamplifier for capacitive transducer input dissipates only 13 microwatts and operates from 1.35 -volt supply. Bias currentof impedance converter, composed of bipolar transistors 02 and 03, is only 6 microamperes, keeping total circuit current drain to only 10µR.FET input stage has source -follower bias arrangement but provides voltage gain of common -source configuration.

0.33nF

TRANSDUCER 0(5000 pF)

,1 35 Vdc

5 kS2MINIMUM

13

Differentiate and countto find frequency errorby Robert C. RogersTexas A&M University, College Station, Texas -

By counting differential pulse transitions for a knownperiod, a simple error -detection circuit measures the fre-quency difference between a variable square wave andreference square wave. Usually, frequency error is

found by counting both signals for some fixed periodand then comparing the resultant values, or by mixingthe signals and then counting the beat frequency. Thefirst method often requires a considerable amount ofdigital logic if high -frequency signals are involved,while the second method is generally limited by thepassband of the beat -frequency detector.

The frequency error detector shown requires inputsignals that are compatible with logic circuits. (A zerocrossover detector could be used initially to prepare theinputs.) The reference square wave is differentiated and

applied to the strobe input of a latch, and the variablesquare wave is applied to the data input of the latch.

How many positive or negative transitions the latchoutput makes in a given period represents the numberof times the variable frequency has gained or lost a fullcycle relative to the reference. Counting these transi-tions for a known period, then, yields the total fre-quency error during that period. A high-level output in-dicates that the variable is within the limit.

The time -base input signal sets the latch to a logic 1 ifthe four -bit counter does not reach a value of 10 in thepreceding 0.1 -second timing interval. This signal is alsoused to reset the counter for the next counting period,which begins when the reset pulse returns to zero.

There are two drawbacks that should be remem-bered. The detector fails if the variable frequency be-comes identical to the reference in both frequency andphase, and it becomes ambiguous when the variablefrequency is either a higher or lower harmonic of thereference. However, even with these limitations, the de-tector is useful and reliable over the reference range of 5to 20 megahertz. Error limit for the circuit shown is-±100 hertz and can be changed by altering the numberdetected by the counter gate.

Frequency error detector. Differentiated reference square wave drives latch strobe input; variable square wave feeds latch data input.Counter logs either positive or negative transitions of latch output for specific period to total frequency error between inputs. High circuit out-put indicates error is within desired limit. Time -base signal sets latch and resets counter. Detector range is 5 to 20 MHz for ±100 Hz.

VARIABLEINPUT

rutREFERENCEINPUT

an_TIMEBASEINPUT(0.1 Si

1

123 S2

Nt

- 10 pF

100 S2

100 pF

FAIRCHILD

TEXASINSTRUMENTS

SN7493COUNTER

OUTPUT

14

Feedback latch reducesmemory recovery timeby Joseph McDowell and William MossMonolithic Memories Inc., Sunnyvale, Calif.

The cycle time of wire-oRed semiconductor memoriescan be improved with the addition of a feedback gate toa NAND gate latch. The resulting three -gate configura-tion, which also includes a diode and a resistor, provideslatched data outputs from open -collector memory pack-ages with significantly reduced turn-off delay.

For open -collector devices, like S1 through SN in thediagram, the common problem is choosing a pull-up re-sistor that is small enough for fast turnoff and largeenough for the current sinking capability of the pack-age's open -collector driver. Turn -on speed is not usuallya problem, since capacitors C1 through CN are drivenfrom a low -impedance saturated transistor.

However, turn-off speed or recovery time is deter-mined by the RC time constant at the wire-oRed node. Ifmany memory outputs turn on at once (for examplewhen all low -logic signals are stored in a 72 -bit memoryword), the change in the power supply load (about 1

ampere in 10 nanoseconds for 15 -milliampere open -col-lector drivers) may require a large pull-up resistor tokeep voltage noise within specifications at the expenseof turn-off speed.

The illustrated latch employs the common cross -couple gate arrangement of G1 and G2. A feedbackgate, G3 actively pulls up the wire-oRed line (like a tri-state gate) after the cross -coupled gates latch. Diode D1isolates G3 from node A, allowing low-level signals tobe sensed at this point. To avoid transistor -transistorlogic high-level signal problems at node A, D1 shouldhave a low forward -voltage drop.

Resistor R1 is used to limit the current from gate G3to the open -collector outputs of memories S1 throughSN. The value of R1 must be small enough to provide anacceptably low signal level at the latch input. Only theoutput leakage of the wire-oRed memories and the in-put leakage of the feedback latch determine the max-imum value of pull-up resistor R2. Recommended val-ues for resistor R2 range from 1 to 10 kilohms,depending on power supply load considerations.

For 16 wire-oRed memory packages and a 4.7-kilohmpull-up resistor, the feedback latch can reduce turn-offtime from 70 to 10 nanoseconds.

Speeding up wire -oiled memories. Cross -coupled gates G1 and G2, along with feedback gate G3, trim turn-off delay for array of wire-oRedmemories (S1 through SN). Three -gate feedback latch uses diode to isolate G3 so that low-level signals can be detected at wire-oRed node A.

Resistor RE prevents surge currents from G3. Maximum value of pull-up resistor R2 is determined by leakage currents.

DATA OUTVcc

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15

Stable voltage referenceuses single power supplyby Mahendra J. ShahUniversity of Wisconsin, Madison, Wis.

When an integrated circuit differential operational am-plifier is used in a voltage reference source, two suppliesusually are needed-both positive and negative. More-over, additional circuitry is generally required to estab-lish output polarity. But if one supply line is grounded,only one supply becomes necessary-the one that givesthe desired output polarity.

So long as the non -inverting input of the operationalamplifier is maintained at some positive potential, evena tiny one, the output of the reference source will alsobe positive. Similarly, small negative potentials at thenon -inverting input will result in negative outputs.

The voltage reference source shown employs a single15 -volt supply to give a positive output. To produce anegative output voltage, the positive supply line isgrounded, the negative supply line is run to -15 v, and

Zener diode Dz establishes the reference voltage (Vz)and the reference current (Iz) for the circuit so that aconstant -current source is provided by resistor R1 andthe buffering action of the op amp. Zener current is:

Iz = VzR2/R1113Due to the configuration of the op amp's output

stage, circuit output voltage (E0) will always be greaterthan 0.5 V when a positive 15-v supply is applied andthe negative supply line is grounded. Therefore, a fewtens of millivolts will always appear at the op amp'snon -inverting input, making the output positive:

E. = Vz(1 +R2/R3)With the positive supply line grounded and -15 v at

the negative supply input, E. will always be less than

Eliminating dual supplies. Voltage reference source has eitherpositive or negative output, depending on polarity of supply used tobias op amp. Positive supply results in positive voltage at op amp'snon -inverting input and, therefore, positive output. Negative supplyproduces negative output. In either case, final output voltage is

about 10 volts. Zener diode acts as reference.

-0.5 v. The negative voltage at the op amp's noninvert-ing input causes a negative output:

E, = -Vz(I + R2/R3)The reference zener voltage of 6.4 v yields a zener

current of about 2 milliamperes. For a positive supply,output voltage is 9.547 v; temperature coefficient, 1.9parts per million/°C; voltage stability, 9.5 ppm/v; andoutput impedance, 53 milliohms. For a negative supply,temperature coefficient remains the same; but outputvoltage becomes -9.560 v; voltage stability, 2.6 ppm/v;and output impedance, 21 milliohms.

Fast -switching modulatorreverses uhf signal phaseby R.N. AssalyMassachusetts Institute of Technology, Lexington, Mass.

In just a few nanoseconds, a modulator for shapingtransmitted ultrahigh -frequency radar signals canswitch a signal through three states. The signal can be

turned on or off, and while it is on, the phase can be re-versed between 0° and 180°. An off signal is attenuatedby at least 35 decibels.

The modulator (a) consists of a tri-state driver and adouble -balanced mixer, which allows the rf signal to becontrolled by video commands. Three values of controlcurrent- -30 milliamperes, 0 mA, and 30 mA- are gen-erated by the driver for the three modulator states- 0°phase, off, and 180° phase, respectively.

The transition times of the two input logic signals,designated as code Q and gate P, are enhanced by adual four -input AND gate. (The gate -P input turns the rf

16

signal on and off, performing a gating function; thecode -Q input reverses the phase of an on signal, therebycoding signal phase.) A line driver then produces theoutputs labeled A and B:

A = PQ and B = PQAt the tri-state driver output, a difference signal, B -A, isused to provide the three desired states, as shown in thetruth table.

To obtain this difference signal, transistor Qi invertsthe A output of the line driver to produce signal C. Andoutput B passes through transistor Q2 without inversion,keeping the circuit balanced and resulting in signal D.A resistor network averages signals C and D, which arethen applied to output transistors Q3 and Q4 that drivethe double -balanced mixer.

Since Q3 and Q4 do not conduct if their base voltageis less than 0.6 volt, the resistor network holds bias volt-age to about 0.5 v during the off state to reduce any de-lay during driver state transitions. Also, because a largebase voltage must be applied either to Q3 or Q4 for con-duction to occur, mixer current can be held to a verylow value. If mixer current increases, to even just a fewmicroamperes, the attenuation of an off signal becomesless than the desired 35 dB. For instance, attenuationdegrades to about 30 dB when mixer current becomesapproximately 10 microamperes.

Inductors and capacitors in the circuit are simplyused to speed up state transitions. The turn -on of a 430-

megahertz signal is illustrated in (b), while (c) shows aphase reversal. These transitions took less than 10 ns.

Uhf modulation. Three -state modulator (a) turns off uhf signals or reverses their phase between 0° and 180°. AND gate improves input sig--el transitions. To balance circuit, line driver output A is inverted by 01, while B passes through 02 without inversion. Transistors 03 and 04drive mixer with difference signal of B -A. Turn -on (b) and phase reversal (c) traces are for 430 -megahertz signal.

+6V

CODE

GATE P

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a

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500.01 pF

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14

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12

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10012

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1600°

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15 pF

1100 pF

1 k2 1130 pF

100 2 100 Cl

100

1 0.1 pF03

2812222

4 68 0

2N2901

( a )P 0 A B

0 0 1 1 0

0 1 1 1 0

1 0 1 0 -11 1 0 1 1

b

GATE P

CODE 0

I 15mE

i 0 1 pF

OUTPUT

TO DOUBLE -BALANCEDMIXERLORCH

ELECTRONICS,MODEL

OUTPUT r -L,

L

17

ECL gates stretchoscillator rangeby William BloodMotorola Semiconductor Prou,icts inc., Phoenix, Ariz.

The frequency range of crystal -controlled oscillators canbe extended easily with emitter -coupled logic gates. Se-lecting the proper crystal and the right number of fre-quency doublers results in accurate frequency signalsover the range of 150 to 250 megahertz. Standard crys-tals are normally limited to less than 150 MHz becauseof the number of crystal overtones required to achievehigher frequencies.

A 200 -MHz crystal -controlled oscillator that is builtwith only two integrated circuit packages is shown inthe diagram. Two types of ECL gates, one with a propa-gation delay of I nanosecond and the other with a 2-nsdelay, are used for best performance.

In the oscillating section of the circuit, the crystal is inseries with a feedback loop from the NOR output of a

2-ns gate, G1. The LC tank circuit tunes the 100 -MHzcrystal overtone, and also acts as a fine -tuner. Another2-ns gate, G2, from the OR output of G1, buffers the os-cillating section and provides a complementary output.

The frequency doubler section of the circuit consistsof two 2-ns gates (03 and G4) performing as phaseshifters, and two high-speed 1-ns NOR gates (G5 andG6) operating as summers. For a 50% output duty cycle,the complementary 100 -MHz signals should be delayedone-fourth of a cycle, or 2.5 ns. This may be done pre-cisely with delay lines, or approximated with gates G5and G6, as shown. The gating method is easier to imple-ment and causes only a slight offset in output dutycycle. Gates G5 and G6 combine the four -phase 100 -MHz signals, yielding a 200 -MHz output frequency,when their outputs are wired -OR.

A third 1-ns gate G7 is used as a bias generator forthe crystal oscillating section. Tying the output of thisNOR gate back to its input assures that the oscillatingsection remains biased in the center of its linear regionover wide temperature and power supply extremes.

Speeding up crystal oscillators. Emitter -coupled logic gates can increase the frequency output of crystal -controlled oscillators to 250megahertz. For 200 -MHz output, LC tank tunes 100 -MHz overtone of crystal, while gate G2 forms complementary 100 -MHz signals. Phaseshifters G3 and G4 and wired -OR summers G5 and G6 then delay and double these signals. Gate G7 provides buffered bias supply for gate GI.

b

100 MHz CRYSTAL

OSCILLATOR

RP

If

0.15pH

G1

'4(000101MOTOROLA//

7 35 pF G2

',,MC10101MOTOROLA

G7

".iMC1662MOTOROLA

0.001 µF

T

OUTPUT(200 MHz)

FREQUENCY DOUBLER

G6

C 1662MOTOROLA

G3

%MC 1 0101MOTOROLA

(IOM CI 0101MOTOROLA

G

Rp: TYPICALLY 510 52 TO VE E OR 5052 TO -2 VDC

1

18

Linear signal limitingwith feedback multiplierby R.J. KarwoskiRaytheon Co.. Equipment division. Sudbury, Mass

A signal can he linearly compressed or limited over awide dynamic range by using a four -quadrant analogmultiplier as a feedback element. Particularly useful foraudio applications, this linear limiting technique doesaway with the signal distortion that occurs with non-linear methods. Also, the linear limiter does not requirethe careful calibration and many trial -and -error adjust-ments needed for a nonlinear limiter.

The control section of the linear limiter consists ofthree operational amplifiers and a multiplier. Op ampAl is the throughput amplifier with local feedbackthrough resistors RI:. R1. and R2. When RF is shorted,the control circuitry is bypassed, and the circuit be-comes a linear voltage -follower:

e = e1(1 + RF/ER R.,/( R, + RA)The fundamental feedback equation for the limiter is

based on amplifier A1:e = Aei/( I + A/3)

where gain A is determined by A1's local feedback ar-rangement of RF and R1 in parallel with R.,. Feedbackfactor /I depends on the control section, whose oper-ating function resembles the basic feedback equation.The relationship between multiplier input ey and multi-plier input ex becomes:

ey = ex/( I +ex)For small values of ex, this equation degenerates to:

ey = exwhich is a linear function representing a 1:I compres-sion ratio between e and e,. For large values of ex, thefunction becomes asymptotically limiting:

ey = ex/ex = 1Over-all limiter transfer function can be written as:e 1-1-lir/[111R0/(R1-i-11.2)]-ei 1 f-410

Multiplier output exey/10 and the product of gains ofamplifiers A2, A3, and A4 are represented by the factor410(O11k. where (ei)pli is the peak input signal ampli-tude. Resistor RF controls both circuit gain and com-pression. However, for any single value of e1, the limitercan be set to provide a gain of unity, regardless of RF'sresistance and how much or how little limiting isneeded. Additional over-all gain adjustments are thenunnecessary, even if the compression ratio must bechanged.

With a 100 -millivolt input, the circuit illustrated sup-plies a 100-mv output, no matter what the setting of RF.

For any value of RF, resistor R1 is selected to keep:I + RF/RIR2/(R1 + R2)] = 1 + 410RF(100mv)/R2

Circuit compression ratio can be varied by changing thevalue of RF, but circuit gain remains unity for e, = e =100 my.

The performance curves show the limiter's transferfunction for three compression ratios with circuit unity -gain point at 100 my -1:1 (no compression, RF = 0),8: I (maximum compression, RF = 25 kilohms), and 3:1(midrange compression).

Variable linear limiter. Compression ratio can be varied by adjusting resistor Rj: without changing circuit gain-limiter's unity -gain point re-mains e, = e = 100 millivolts. Amplifier Al is controlled by local feedback through resistors RI:, R1, and R., and by additional feedback frommultiplier and amplifiers A2, Al, and A, When Rp = 0. compression ratio is 1:1, when RF = 25 kilohms, compression is 8:1.

47 k1

330 S

Al74 1

COMPRESSIONAND GAINADJUSTMENT

ex

MULTIPLEXER-exey

10

1N4606A2

74 1 01

0.01 pF7.5kS2135 V)

TELEDYNE/PHILBRICK4452

125

> 100E

A 750--- 50

25

0

C(J%S, I A',+PL I UDEREGION

1 I COMP RATIO

8 13 1

I I I I I

25 50 75 100 125

mV

19

Simple logic circuitscompare binary numbersby Edward J. MurrayInter -Computer Electronics Inc., Lansdale, Pa.

In real-time data acquisition applications, determiningthe relative magnitude of two binary numbers withhardware, rather than software, now requires only threelogic modules if data is being transferred serially. Pre-viously, rather complex circuitry was needed.

Only the most -significant difference between twocoincident serial data streams defines their relativemagnitude. If the least -significant bit is transmittedfirst, the last difference between coincident word bitsdetermines which is the largest word. When the most -significant bit is the first transmitted, the first differenceestablishes relative magnitude, and all other differencescan be ignored.

Six logic gates (a) can compare two words when theleast -significant bit is the initial input. Eight logic gates(b) are needed when the most -significant bit arrivesfirst. The heart of both schemes is a three -state latchthat provides three comparisons for input words A andB: A is greater than B, A equals B, and A is less than B.

The timing diagrams in (a) and (b) illustrate circuitoperation when input A is octal number 25 (binary010101) and input B is octal number 15 (binary001101). Signals A and B are not limited to a fixednumber of bits per word. Any variable word size can beused if the results are interrogated after the word hasbeen transmitted and a reset pulse precedes the wordbeing interrogated.

This type of binary comparator is useful in prelimi-nary data sorting and number ranging prior to softwareprocessing for multi -channel data acquisition. In thetiming diagram, the "result available" waveform indi-cates the best interrogation periods.

Checking number size. To find relative magnitude of serial words A and B, only most -significant differences between coincident data bitsmust be considered. Transmitting least -significant bit first (a) requires six gates for comparison. Two additional gates are needed (b) if most -

significant bit is transmitted first. In timing diagrams, octal 25 (binary 010101) is compared to octal 15 (binary 001101).

TEXASINSTRUMENTS

LEAST SIGNIFICANTBIT

A = 258

= 158I

A B

0

SN7410N_J

RESET

MOST SIGNIFICANT

0

0 1

A >

A - B

A < B

0 11- - - -

0 0

A=B

A B I

Fir

n

L SN7486NB

TEXASINSTRUMENTS

RESET

RESULTAVAILABLE

WORD N-1 WORD N WORD N+1

' SN'7400ft_

r

RESET

MOST- SIGNIFICANT LEAST- SIGNIFICANTBIT BIT

A 2

B = 15

A > B

A=8

A < B

4

i_

d1

i

i-

o 11-1 o U1 1,1

-41.......1

f

1.4L

rt---ir--1,

ir

1

WORD N-1 WORD N

20

Series -connected op ampsnull offset voltageby Lawrence ChoiceBurr -Brown Research Corp., Tucson, Ariz.

The input offset voltage and offset voltage drift of a dif-ferential operational amplifier can be held essentially tozero by connecting a second amplifier at the invertinginput of the first. This auxiliary op amp must have anoffset voltage and drift that are matched to the primaryop amp. The additional amplifier will then act as a

floating voltage source, canceling any offset voltage.As shown in (a). unity -feedback amplifier Al is con-

nected to the inverting input of amplifier A.,. providinga floating offset voltage source between A2's non -invert-ing input and its output. (If Ai's offset characteristicswere matched with opposite polarity to those' of A2.then Al could be placed at A2's non -inverting input.)Letting V represent the input offset voltage of A2, V.the voltage across AI, A the open -loop gain of A". andE1 and E2 the two input signals, then output voltage E,,can be written as:

E0 = - Ao(VAI-Vos)If VAI = Vs. then:

E =The composite amplifier consisting of AI and A2 can

Getting rid of offset voltage. Letting amplifier AI act as floating voltage source (a) effectively eliminates offset voltage and offset voltage driftof amplifier A2. As long as AI and A2 are matched, their offset voltages cancel, keeping offset of composite amplifier at zero. Composite am-plifier of (a) can be used as conventional single operational amplifier for either inverting (b) or non -inverting (c) applications.

E21

COMPOSITE AMPLIFIER

(a)

500 - 2 000 pF

(c)

BURR BROWN3500 MP

Ell

E - E,

BURR BROWN3500 MP

lie used as a very -low -drift inverting amplifier, like theone illustrated in (b). Resistors RI, R2, and R.3 areadded to decrease the effects of amplifier bias currenton total offset voltage and drift. This particular unity -gain composite amplifier configuration will be stable incircuits having feedback factors as large as 50%.

When used as a unity -gain non -inverting buffer, thecomposite amplifier should be compensated as indi-cated in (c). The compensation does not reduce ampli-fier small -signal bandwidth.

21

Unclocked logic elementmakes quick decisionsby Leslie K. TorokUniversity of Toronto, Toronto, Ont., Canada

A new kind of logic element can make logic decisionswithout requiring a clock for synchronization. CalledJade, this asynchronous decision element can operate atspeeds as high as clocked logic blocks, offers easy de-bugging, and allows sequential logic systems to bemechanized directly from flow charts. Moreover, Jadewill operate in clocked as well as unclocked systems.

A control signal, DO, functions much like the clock insynchronous logic, while input signal X represents thelogic condition that must be decided and acted upon.The Jade element has two states-a quiescent statewhen signal DO is logic 0 and a decision state when DOis logic 1. There are four possible outputs: XTRUE (X istrue), XTRUE (not XTRUE), XFALSE (X is false), andXFALSE (not XFALSE).

When the Jade is in its quiescent state (DO = 0),XTRUE = XFALSE = 0 and XTRUE = XFALSE = 1. Forthe decision state (DO = 1), Jade makes an exclusiveand singular decision at the rising edge of signal DO -XTRUE = 1 and XTRUE = 0 if X = 1, or XFALSE = 1and XFALSE = 0 if X = 0. The output decision then ac-tivates the appropriate task logic.

As long as DO = 1, further changes in X do not affectthe output. Returning DO to logic 0 clears the decision,causing Jade to assume its quiescent state. It should benoted that XTRUE = XFALSE only in the quiescent state.For the decision state, XTRUE = XFALSE and XTRUE =XFALSE, since the outputs are exclusive. Those outputsthat are not selected remain quiescent.

As X drops to logic 0 and DO rises, a spike may ap-pear at the output of gate G1 when the propagation de-lay of gate G2 to a logic 1 is less than the propagationdelay of gate G3 to a logic 0. If the spike is wider thanthe minimum hold time of gate 04, a double decision ismade. To prevent this, two inverters can be placed be-tween Gi and G4 to integrate the spike.

Jade can sort decisions at speeds of at least 10megahertz, with signals X and DO having pulse widthsof about 30 nanoseconds.

Decisions, decisions. Asynchronous decision element named Jade uses control signal DO instead of clock to gate information signal X.When DO is logic 0, circuit is in quiescent state; when DO is logic 1 , circuit is in decision state and provides single exclusive output out of fourpossibilities. Inverters can be added to avoid switching spike that causes erroneous double decision. Truth table shows logic characteristic.

00

X

ALL GATES:TEXASINSTRUMENTSTYPE SN7410

P.. )0o `'So

X TRUE

X TRUE

00

XTRUE

X TRUE

FALSE

X FALSE

INPUTX

DECISION STATE, DO = 1 QUIESCENT STATE, DO = 0

X FALSE X TRUE X FALSEii.

X TRUE.X FALSE X TRUE X FALSE X TRUE

0

1

1

0

0

1

0

1

1

0

0

0

1

1

0

0

1

1

22

Height -to -width converterdigitizes analog samplesby Roland J. TurnerRCA Corp., Missile and Surface Radar division, Moorestown, N.J.

By controlling the charge on a storage capacitor, a tem-perature -stabilized height -to -width converter can pro-duce a gray code output from an analog input sample.The copverter uses a differential diode -transistor ar-rangement to operate over a temperature range of-55°C to +65°C, and its conversion error is less than0.15 microsecond for a full-scale output pulse width of3.25 ,us.

During the first half of the input sample, a clear pulseremoves all charge from storage capacitor C1. Duringthe second half, a charge proportional to the sampledanalog signal is placed on this same capacitor throughtransistors Qi and Q2.

Current source Q3 keeps diode D1 forward -biasedand transistor Q4 fully on during the sample time. Onthe trailing edge of the analog sample, DI becomes re-

verse -biased by a voltage level equal to the amplitudeof the analog sample before its termination. TransistorQ4 is then cut off, and for a period of time that is pro-portional to the stored analog sample amplitude, a cur-rent source formed by Q3 and the slope -control poten-tiomteter linearly discharges capacitor C1.

During the time that Q4 is off, the converter generatesa pulse that has a width proportional to the amplitudeof the analog sample. When the stored charge goes tozero, diode DI and transistor Q4 are again turned on bythe current source. After Q4 conducts, a new samplemay be processed. Transistors Q6, Q7, and Q8 act aspulse shapers to yield the desired output.

Diodes DI and D2 and transistors Q4 and Q5 are con-nected in a differential configuration to keep Q4's con-duction interval independent of temperature variations.The voltage drops of DI and D2 and the base -emittervoltage drops of Q4 and Q5 track each other as tempera-ture varies.

The converter in the diagram is designed to operatewith a peak -to -peak video input level of 6.5 volts. Max-imum output pulse width is determined by the slope ad-justment, which is set to provide a pulse width of 3.25 usfor a an input video level of 6.5 v. The waveformsshown represent the maximum level of the gray code. 0

Compensating for temperature. Differential hook-up of transistors al and 05 and diodes D1 and D2 maintainstemperature stability of height -

to -width converter. Amplitude of analog input sample is converted to gray code output. Second half of input sample charges capacitor C1,

then linear current ramp through transistor 03 discharges C1. During discharge time, D1 and Q. are off, and output pulse is produced.

INPUTSAMPLE

a(A)

2N338

22 Idt

--1 0 lips I.-65

{A1\I

0V

2N706

-12 V

ANALOGSAMPLE

-010- 0 2 ps-

(B) CLEAR-8V

0 VC)

+(0)8 V-1.5 V

11V

0V

0 V(F)

V

SLOPEADJUSTMENT

C,

270 pF151914

100 pF

j_ I

rd--- 3.25 ps

rOUTPUT

100 kil

2.2 at2N1118

(D)

1N995

CLEAR

(B)1.2 kS1

0.01µF

04

2N706

-12 V

4.7 kl?.

+12 V 15914

25706

+12 V-12 V

1 kS-1.

10 kS2 251118

tEl

3 kS2

-12 V

F--200 pf

25706

1N914

1 kS.2

+12 V

-12 V-12 V

(F)

OUTPUT

0 V

--11 V

23

Filament transformer outputdrops cost of 400 -Hz supplyby Glen CoersTexas Instruments, Components Group, Dallas, Texas

Power supplies with a 400 -hertz output are oftenneeded in testing servo systems and aircraft equipment,but they can be expensive to build when their outputvoltage must be on the order of 115 volts, root meansquare. This being the equivalent of a peak -to -peakvoltage of 325 v, the circuit transistors would have tohave very high operating voltage ratings, and sincethere are no integrated amplifiers that can handle± 160 v, a discrete amplifier would be required.

Alternatively, the number of parts and componentcosts can both be considerably reduced by generatingthe 400 -Hz sine wave at some low voltage level and thenstepping it up with a transformer. This approach allowslow-cost transistors and integrated circuit operationalamplifiers to be used, yet it produces enough outputpower to operate small motors, servos, resolvers, andsynchros. Larger output transistors and a larger trans-former will, of course, increase output power.

The audio oscillator of (a) provides the sine -wave in-put for the amplifier of (b). The frequency -determiningcomponents for the oscillator are resistors R1 and R2and capacitors C1 and C2. These are returned to thenon -inverting input of an op amp that functions as thecircuit's oscillating element.

Voltage gain for the amplifier is supplied by an opamp, while discrete transistors supply current gain. Theinput sine -wave frequency can vary from 60 to 400 Hz

when a conventional filament transformer is used at theoutput. With the components shown, an output currentof about 250 milliamperes is obtainable.

The amplitude of the input sine wave depends on theamount of feedback in the amplifier network. If thefeedback factor is low, a small signal can drive the am-plifier, but the output driving impedance becomes high,possibly causing current limiting in the output stage andtherefore poor voltage regulation. If the feedback ishigh, a higher level of input voltage will be required,but the output driving impedance becomes lower andregulation is improved.

Here, op -amp closed -loop gain (A,,) is 10, makingthe required drive voltage around 1 v rms. The value offeedback resistor 1Zr is determined by:

Rf = Rs(A-1) = 9 kilohmswhere Rs is source resistance. Feedback factor /3 is setby Rf and Rs:

= Rs/(Rs+Rf) = 0.1while closed -loop output resistance Rout becomes:

Rout = Ro/A4 = 0.01 ohmswhen open -loop output resistance Ro equals 50 ohms,and open -loop gain A, is 50,000. This last equation in-dicates that circuit regulation should be adequate be-cause the effective driving impedance is much lowerthan the load impedance.

The output transistors are connected in a bootstraparrangement, eliminating two base -emitter voltagedrops and allowing more ac voltage to be developed. ADarlington configuration could be substituted, but therewould be a 5% drop in the available output voltage. Ad-justing the 400 -Hz drive voltage varies output voltagebetween 0 and 144 v rms.

Servo supply. Amplifying low-level high -frequency sine -wave input cuts parts and price of 400 -hertz 115 -volt rms power supply. Audio os-cillator (a) provides 1-V rms sine wave for amplifier (b). Standard filament transformer delivers output currents of up to 250 milliamperes andvoltages as high as 144 V rms. Bootstrap arrangement of amplifier's output transistors optimizes available output voltage.

1 MS2

01_0.04pF

2N3819

F

1pF

1.8 kS?.

10 k(l

68 812

vw-

910 S2

18 kS2

1N914

+15 V

-15 V

0.004 pF 100 812

(a)

6.8 812

SINE WAVEOUTPUT

1 kS2 1400 Hz)

-.-

(b)

+15V

R

9.1 k

150 S2(v. W)

TIP 34

TIP 29

1 kS2

W)

1 l(S2

SINE WAVEINPUT(0 -10 V rms,400 Hz)

Us WI

2

SN72 41 6

3

(1/4W)

TRANSISTORS AND OP AMPS: TEXAS INSTRUMENTS

680 St

(% WI

TIP 30

FILAMENTTRANSFORMER

150 sa(14W)

6.3 Vrms

TIP 33

-15 V

OUTPUT(115 V rms,400 Hz)

24

Regulating high voltage withlow -voltage transistorsby Mahendra J. ShahUniversity of Wisconsin, Madison, Wis.

High -voltage regulation usually calls for high -voltagetransistors. But, by absorbing the bulk of the outputvoltage with a zener diode, only relatively low -voltagedevices are needed. The circuit illustrated regulates 250volts with a 90-v transistor; however, the same conceptcan be applied to regulating voltages in the kilovoltrange.

Transistor Qi operates as a shunt regulator, monitor-ing the output voltage, eo, across the load. Without ze-ner diode D1, Qi would be subjected to nearly all theoutput voltage. But Di absorbs a good part of this volt-

age because it is in series with the collector of Qi. Thisallows Qi to operate at the difference voltage betweene0 and the voltage across the zener.

The output voltage is divided by resistors Ri and R2and applied to the non -inverting input of an oper-ational amplifier, which functions as a comparator. Theop amp compares el with e2, and maintains output volt-age eo so that ei = e2. Regulated output is a function ofthe comparator's inverting input voltage, e2, and the re-sistors of the voltage divider:

eD = e2(1 +R2/Ri)Another diode, D2, protects Qi's base -emitter junc-

tion from reverse breakdown. During normal operation,D1 is forward -biased, allowing Qi to receive base drivefor proper regulation.

For the component values shown, voltage regulationfrom no load to full load (25 milliamperes) is less than0.04%. Unregulated voltage is 330 v, and the voltageacross Qi's collector -emitter junction is approximately40 v. 0

Putting a zener to work. Zener diode D1 handles most of 250 -volt regulated output, permitting a mere 90-V transistor to be used. Transistor01 acts as conventional shunt regulator for load resistance. Op -amp comparator maintains output voltage to keep its inputs el and e2 equal,thereby providing proper base drive for 01. Regulated output voltage is: e0 = e2(1 + R2/R1). Unregulated output of 330 V is also available.

+15 V

1N4736r

§ 4.7 kL22

UNREGULATEDOUTPUT (330 V)

3 kS1

1 ME20.0022 µ F

500 S2 1 (50 V)

100 kE2

2 8

+15 V

MOTOROLA 7MC 1439G

43

-15 V

D2

10i

1N4245

20 kE-2

DI

(200 V)

0,

40409(90 V)

2722

'LOAD

e0

(250 V)

LOAD10 kS7

Op amps multiplyRC time constantsby Quentin BristowGeological Survey of Canada, Ottawa, Ont., Canada

Unusually long time constants can be generated withconsiderable accuracy by combining readily availablelow -value resistors and capacitors with a couple of gen-eral-purpose operational amplifiers. Besides being phys-ically smaller than their higher -value counterparts, low -value components offer tighter value tolerances and donot have leakage or polarity problems. Furthermore,when high -value resistors are used, field-effect-transis-

25

tor -input op amps must be employed. They are moreexpensive than general-purpose op amps and do notprovide as good input offset and temperature drift spec-ifications.

A number of instrumentation applications requiretime constants in the order of seconds or minutes. Cir-cuit (a), for instance, can be used to stretch one-shotoutput pulses, or as a low-pass insertion filter for moni-toring slowly changing meteorological, oceanographic,or other geoscientific phenomena where low -frequencynoise is undesirable. This network can multiply a basicRC time constant by a factor as large as 10,000. (For ex-ample, a 100 -second time constant can be realized withR = 100 kilohms and C = 0.1 microfarad.)

When V, is a step input, output voltages E1 and E2rise exponentially to final values -V, and + Vi, respec-tively, with a time constant (taken at 63% of the finallevel) of (N + 2)RC.

E2 = -E1 = - exp(-t/(N + 2)RC)]The actual values of resistors R1 and R2 are not criticalbecause the time constant is determined by ratio N andthe values chosen for R and C. The components indi-cated provide a time constant of 50 seconds.

The drift and noise of either output referred to theoriginal input V, will be the same as that obtained whenamplifier Al is operated at a closed -loop gain of N+ 1,modified of course, by the filtering effect of the timeconstant generated. After capacitor C is removed, thecircuit can be seen to be an op amp (A1) connected for a

closed -loop gain of N+ 1, since amplifier A2 is simply aunity -gain inverter.

The offset null trimmer permits the E1 output to beset initially to zero for a zero input. Generally, the trim-mer can be omitted for values of N less than 50. Toavoid a tedious time lag in circuit output response whenmaking this adjustment, one end of the capacitor shouldbe disconnected temporarily.

Gains other than plus or minus unity can be obtainedat outputs E1 and E2 by making the input attenuationand feedback ratios unequal; they are both 1/(N+ 1)for circuit (a). Also, the inverting gain of amplifier A2can be other than unity. As shown in circuit (b), inputattenuation can be controlled by ratio a, feedback byratio y, and inverting gain by ratio /3. The two outputsbecome:

El = -V,(7 + 1)[1 - exp(-01/(,8 + ORC))/(a + 1)/3E2 = Vi(y+ 1)[1 - exp(-t/34/3+ y + 1)RC)[/(a + 1)In applications where desired drift and noise specifi-

cations cannot be met by a 747 -type op amp, amplifierAl can be stabilized with a temperature -controlled dif-ferential preamplifier, such as Fairchild's AA727B. Thisintegrated circuit has an on -chip proportional tempera-ture regulator, affording tight control of chip tempera-ture at about 100°C. The 727 -plus -747 combination pro-vides excellent dc stability at high closed -loop gains andcan be treated circuitwise as a single op amp. If apreamplifier is added, the null offset trimmer is nolonger effective.

Extending RC time constants. Low -value resistors and capacitors and two op amps can generate time constants that are several minuteslong. Output voltages E1 and E2 exponentially approach level of step input Vi. Time constant, which is 50 seconds for circuit (a), primarily de-pends on R, C, and ratio N. For circuit (b), there are three controlling ratios: a for input attenutation, y for feedback, and /3 for gain.

C

(a)

R)

26

One-shot/flip-flop pairsdetect frequency bandsby Edward E. PearsonOpelousas, La.

A retriggerable monostable multivibrator and a type Dflip-flop can form a simple reliable frequency compara-tor that senses if an input frequency is greater than orless than a predetermined reference. Connecting addi-tional comparators in parallel, together with AND logic,permits the detection of input frequencies that fallwithin selected bands.

Both the one-shot and the flip-flop are wired for posi-tive edge triggering. Each input pulse causes the monos-table's output to go high for the period of its preset tim-ing interval. The flip-flop is triggered simultaneously,but its output is determined by the state of its D input atthe time of trigger threshold.

If the period of the input frequency is shorter thanthe preset timing of the monostable, a constant highlevel will be present at the D input, forcing the flip-flop's Q output to remain high. If the input frequencyperiod becomes greater than that of the monostable, theD input will go low prior to the next incoming trigger.The flip-flop's Q output then goes low and remains low

until the input period becomes shorter than that of themonostable.

To determine whether an input frequency (f) falls be-tween two known frequencies, f1 and f2, two one-shot/flip-flop combinations are required, as shown. Thetop pair of devices detects an input greater or less thanf1, while the bottom pair detects an input greater or lessthan f2. The AND gate provides a high output when theinput frequency lies inside the preset band (less thanor greater than f2, if f1 is greater than f2). This detectionscheme can be expanded to include any desired numberof segments within the operating passband.

The frequency band detector also has an inherentmemory function that could be particularly useful incontrol applications. When the input signal terminates,for example, with a tone burst, no trigger is available tothe flip-flops, and all outputs remain static until the in-put signal returns.

Although the detector responds only to the period ofthe input signal and does not require the input to main-tain a specific duty cycle, input pulses must have a rapidrise time. All trigger thresholds must be reached withinan interval that is appreciably less than the mono -stable's propagation delay time. Circuit speed is limitedonly by the setup and hold performance of the compo-nents being used.

Sensing frequency. Retriggerable one-shot and flip-flop compare frequency of input to preset reference frequency. To form frequency -banddetector, two frequency comparators and AND gate are needed. Depending on period of input pulse train, each one-shot output is high orlow. Each flip-flop triggers to level seen by its D input prior to trigger threshold. AND gate output goes high when f falls between fi and f2.

INPUT

SET FORf1 PERIOD -

71 r2

OONL

SHOT

13

CP

FLIP-FLOP

JULnIf Hz)

3

1SETf2

FORPERIOD

ti

V

10O D N

ONE- FLIPSHOT FLOP

9 CP 0

y

TO ADDITIONAL SECTIONS(FOR 13, fa, ... fN

TEXAS INSTRUMENTSSN74123 SN7474

f < f2

27

Control one-shot dividesfrequency by up to 30by Jerome SnaperLeach Corp., Controls Div., Azusa, Calif.

A three -gate control allows precision frequency divi-sions of up to 30 merely by changing a resistance. Acrystal oscillator acts as the frequency source so that allsubharmonics of the reference frequency have crystalstability.

NAND gates G1 and G2 and the crystal comprise theoscillator that generates the reference frequency. Theone-shot, consisting of NAND gates G3 and G4, controls

gate G5, which is synchronized by the oscillator.After one pulse of the reference frequency passes to

the output, the one-shot locks out gate G5 for a periodof time determined by the setting of potentiometer Rt.When the one-shot resets, another single pulse reachesthe output, and the cycle repeats.

The input frequency, fln, is simply a multiple of theoutput frequency, fout:

fin = Nfoutwhere N is the division factor. N can have any integralvalue between 2 and 30. The circuit shown divides a1.1 -megahertz reference frequency by 11 to yield anoutput frequency of 100 kilohertz.

Additional versatility is possible by substituting afield-effect transistor or voltage -variable resistor for thepotentiometer. Then, frequency divisions can be elec-tronically swept over a wide range.

Precision division. Crystal oscillator supplies reference frequency for three -gate divider scheme. NAND gates G3 and G4 form one-shot thatcontrols gate G5. After G5 passes single reference pulse, one-shot inhibits this gate for period selected by adjustment of potentiometer R.When one-shot resets, another reference pulse passes to output. Crystal frequency can be divided by up to 30 without loss of stability.

560 E2

cs0.01 pF

(fIN =1.1 MHz)11111111111

Cl 1.1 MHz

8 - 50 pF

22 pF

(four = 100 kHz)

I

N = 11

0ALL GATES: 7400

0.01 mF -p.1.5 kit

Pulsed standby batterysaves MOS memory databy K. C. HerrickFisher Berkeley Corp., Emeryville, Calif.

A simple pulsed battery supply can reduce standbypower necessary for mos random-access memories to

one -thousandth of the operational requirement. Inmany systems, this power -saving scheme allows inex-pensive batteries to be used with essentially shelf -lifelongevity. In some cases, merely a capacitor can supplyenough standby power to sustain memory until an aux-iliary power source can come on-line.

A typical RAM cell consists of a cross -coupled multi -

vibrator with active mos transistor loads. When there isa power failure, the potential across the multivibratordeclines toward zero. As long as its inputs are kept off,the cell is isolated from external influence, except for

28

leakages, when the mos transistors cease conducting.The charges remaining on the gates of the cross -

coupled transistors then begin to leak off exponentially.If power is reapplied within a short period of time, how-ever, sufficient differential charge levels remain on thegates to re-establish flip-flop conduction in the samestate as when power failed.

It is this cell characteristic that can be exploited tosave standby power. The potential across the multi -vibrator must be reapplied periodically, at a rate fastenough to replenish the MOS gate charges before theydecline below threshold levels and for long enough tore-establish fully the charge levels. Usually, a sufficientrate is 1,000 hertz with a pulse width of 1 microsecond.For any given type of memory and upper temperaturelimit (leakages increase with temperature), the requiredduty cycle may vary.

Of course, the potential needed must be reappliedwithin the maximum period of time that is allowable(for example, 1 millisecond). The little -used series mul-tivibrator and a 14 -volt battery (a) will do the job. Thenominal memory cell potential is 15 v, less one diodedrop, or about 14.3 v.

When power fails, diode D1 disconnects the RAM'SVDD line from the main supply. The memory potentialof Vcc - VDD declines in magnitude until the voltage of14 -(Vcc - VDD) is large enough to start the series multi -vibrator. Oscillations usually begin when the voltageacross the multivibrator becomes about 0.75 v. Thecomponents shown yield a pulse width of about 1 psand a pulse interval of about 500 As.

If a rechargeable battery is used, the diode and re-sistor connected with dashed lines may be added to al-low the battery to charge while the main power is ap-

plied. The memory's peripheral -circuit supply voltageVD can become zero and remain zero during the loss ofmain power, without any effect on data retention.

While the memory supply voltage is decreasing, thememory's chip -select input must be held FALSE at theVcc ( + 5 v) potential. rrL devices or other elementsdriving this line may change state erratically when the5-v logic supply loses voltage. The presence of thesestray signals may cause a RAM cell to change state.

A circuit for maintaining the chip -select line at the in-stantaneous Vcc level is shown in (b). Since the 14-v (inthis case) semi -regulated supply is the power source forthe 5-v regulated logic supply, in the event of powerfailure the 14-v source will lose voltage before the logicsupply.

Transistor Qi is normally kept on by base currentfrom the 14-v supply via zener diode Di. Collector cur-rent from Qi biases Q2 on. Base current from Q2 causesonly a negligible drop below 5 v in the FALSE voltagelevel of the memory chip -select line, due to the high re-sistance ratio of R1 to R2. Whenever a zero chip -selectvoltage is applied to Q2's collector from the controllogic, Q2 conducts, and its emitter voltage changes tothe TRUE level (0 v).

Upon power failure, the 14-v and 10-v supplies beginto lose voltage. Transistor Qi's base current will becomezero when resistor R3's voltage drops below about 0.7 v.At this time, voltage V equals 10.7 v-20.7 v above-10 v or 5.7 v more positive than Vcc-a value that stillmaintains the 5-v Vcc level. When Qi stops conducting,Q2 is cut off, and the memory's chip -select input line isconnected only to Vcc via resistor R2. Therefore, even ifVcc decreases in value, the chip -select line remains atthe Vcc potential.

Preserving memory contents. Series multivibrator and battery (a) allow MOS random-access memory to retain data when power fails. Cir-cuit takes advantage of MOS charge retention property so that pulsed voltage is sufficient to refresh memory. Dashed components let batteryrecharge when main power is restored. Protection circuit (b) for chip -select line prevents erratic logic signals from changing memory state.

+5V

10V

Vcc

IC MEMORY(RAM)

- ---D,

X 1N4001

VD D

- - 0.01 µF

14V

68 kS1t

105210 St

2N4141

2N3645

68 kft

1N4001

CHIP SELECTTO RAM

(b)27 kf2

-10V

- 0.01 F

CHIP SELECT FROM LOGIC(0 V, TRUE)

V

(+14 V)

29

Triangular -wave generatorspans eight decadesby William S. ShawUniversity of Texas, Applied Research Laboratories, Austin, Texas.

Because of its nonsaturating design, a triangular -wavegenerator can cover eight decades of frequency-from0.01 hertz to 2 megahertz. Lower and upper frequencylimits are set by resistance adjustment. Circuit layout isnot critical, and complementary circuitry assures outputsymmetry and amplitude stability, as well as the ab-sence of dc offset. By decreasing output voltage swingand increasing current, the generator's frequency rangecan be made to span 1 to 20 MHz.

Transistors Qi and Q2 are constant -current sourceswhose outputs are switched to produce the charging anddischarging currents for the output capacitor. Transistorpairs Q3 -Q4 and Q5 -Q6 are differential amplifiers thatfunction as comparators; Q3 and Q6 conduct wheneverQ4 and Q5 switch off, and vice versa.

The series string of diodes D1 and D2 and resistorsR1, R2, R3, and R4 set comparator voltages Vi and V2.Diodes D1 through D4 compensate the four -transistorintegrated -circuit array so that the generator maintainsits frequency stability with changing temperature. Com-parator input and output currents are:

i1 = 28.7R1/(Ri + R2 +11,3 ±R4)R5i2 = R7i1/R6When Q4 and Q5 are on, Q3 and Q6 are off, and out-

put capacitor C1 charges at a constant rate (since i2 is a

constant) until the upper trigger level (Vu) is reached:Vu = VE1 VBE1 VD5

where VE1 is the voltage at Qi's emitter, VBE1 is Q1'5base -emitter voltage, and VD5 is the voltage acrossdiode D5. Once output voltage equals Vu, transistor Qiconducts and Q2 switches off, turning Q3 and Q6 on.Since R7 is larger than R6, Q4 and Q5 will switch off.

Due to the symmetry of the circuit, capacitor Ci isdischarged by transistor Q6 at the same constant rate asit was charged and by the same current, i2. The capaci-tor discharges to the lower trigger level (VL):

VL = VE2 - VBE2 - VD6where VE2 is Q2's emitter voltage, VBE2 is Q2's base -emitter voltage, and VD6 is the voltage across diode D6.When VL is reached, Qi turns off, Q2 turns on, and V2becomes larger than V4. This switches on Q4 and Q5,causing Q3 and Q6 to switch off by feedback through ca-pacitor C2. The cycle can now repeat.

Diodes D5 and D6 allow the output to slew above andbelow the limits imposed by the emitter -base break-down voltage (about 6 v) of Qi and Q2. The generatorwill oscillate without latch -up as long as VE1 is less thanV1 and VE2 is greater than V2.

For a 20-v peak -to -peak output, the frequency is:fout = 0.0425i1/C1

Capacitor C1 determines nominal output frequency,while resistor 113 sets the lower frequency limit and po-tentiometer R2 sets the upper limit in addition to pro-viding a linear frequency span of 20:1. When R2 = 500kilohms and C1 = 1,000 microfarads, foot = 0.01 Hz;when R2 = 0 and C1 = 100 picofarads, fout = 2 MHz.

High -frequency triangles. Complementary nonsaturating circuitry permits triangular -wave generator to provide 20 -volt output at fre-quencies as high as 2 megahertz. Output triangle is obtained by charging and discharging C1. Current from 02 charges C1 until output volt-age reaches threshold Vu, then 03-04 and 05-06 comparators switch, and 01 supplies discharge current until threshold VL is reached.

10 kS-2,

3.3kt2

0.1µF

C31MPS918

+15V

Ri4.1 kit

D5

1N914

MPS 3640D6

Q2

0.1 p F

3.3 kS2

0.001 µF

C2

1N914

R2

500 kS2

27 kS2 R3

1N914

D2

V2

R

4.1

-15V

1 kl-2

D3

1NI914

V3

OUTPUT

VL --+ 20 V

CI

100 pF -1,000 Ai F

ALL TRANSISTORS: MOTOROLA

30

Output comparator enhancesversatility of one-shotby Harvey J. Scherr*Westinghouse Corp., Systems Development Div., Baltimore, Md.

If an operational amplifier is used as an output com-parator, a monostable multivibrator can provide wideand accurate output pulses over a broad temperaturerange. The one-shot is also retriggerable-that is, its out-put pulse duration can be extended by reapplying theinput pulse. In addition, this multivibrator can be resetto accept a new trigger input within its timing period.

Each time an input pulse occurs, timing capacitor Ctis discharged by field-effect transistor Qi, and compara-tor Al switches off. In the absence of a trigger input, Ccaccepts charge from Qi, and the comparator is turnedon. Switching takes place when Al's input voltages, eland e2, are equal. Because the comparator is off duringthe timing interval, there are no output errors intro-duced by op -amp input offset current.

Output pulse width, T, is determined by the supplyvoltage, VDD, reference voltage, VR, and the timingcomponents, Rt and Q. At the comparator's input:

el = e2 = VDDexp(-t/RtCt)which can be rewritten as:

exp(-t/RtCt) = Voo/el = VDD/[VRR2/(R1 + R2)]Output pulse width becomes:

T = RtCt[In(VDD) - ln(VRR2/(Rl +R2))]'Now with Stereo Equipment Sales Inc., Baltimore, Md.

IfVDD = VR and R1 = R2, this equation reduces to:T = RtCtln(2) = 0.694RtCtThe timing equations illustrate that output pulse

width is completely independent of any transistor junc-tion voltage and therefore is independent of junctiontemperature dependence. Op -amp offset voltage driftprincipally determines the one -shot's temperature per-formance. And since offset drift is typically as low as 10microvolts/°C, total variation in the multivibrator's tim-ing interval is only about 0.002%/°C.

Unusually large time constants can be achieved be-cause the primary restriction on the value of timing re-sistor Rt is op -amp bias current. Rt must be smallenough to allow the voltage developed at Ai's invertinginput to turn the comparator on. Since op -amp bias cur-rent generally ranges between 0.25 and 0.5 micro-amperes, resistor Rt can be as large as 10 megohms(when VDD = 10 volts and el = -5 v).

As illustrated in the timing diagram, the multivibra-tor can be re -initiated during its timing interval tostretch output pulse width. This is possible becausetransistor Qi discharges capacitor Q every time an in-put pulse occurs. By adding transistor Q2, capacitor C1,and resistor R3, the circuit can be reset by restoring it toits stable state. A fixed -width reset pulse cancels the re-maining portion of the output pulse.

Substituting a resistor for capacitor C2 alters the mul-tivibrator's timing-a time out then occurs with the ab-sence of a negative voltage from the input terminal. Cir-cuit output polarity is easily reversed by interchangingthe connections to the comparator's inverting and non -inverting inputs. The active devices used determinecomponent values.

Retriggerable monostable. Input trigger causes Oi to discharge capacitor Ct, turning off comparator Al and producing output. Before tim-ing period is over, new trigger can be applied to extend output duration. Reset pulse through 02 can terminate output during any part of tim-ing interval. Output comparator maintains one-shot temperature stability and permits unusually large time constant to be used.

31

Series resistance improvespotentiometer linearityby Harry H. SchwartzElectrodesign Ltd., Ville Lasalle, Otiebee, Canada

Adding a series resistance to one end of a loaded linearpotentiometer can reduce loading error by a factor offive or more. The price for this gain in linearity is a volt-age loss across the pot. But losses in amplification ordrive in the order of 3 to 4 decibels can usually be toler-ated in view of the marked improvement in linearity.

As shown in (a), voltage Ei is applied to potentiome-ter Rp and series resistor Rs. The load resistor is R., theoutput voltage is E0, and 0 is the per -unit variation ofthe pot wiper. Letting:

Yo = E)/Ei, P. = R./Rp, and Ps = Rs /Rpthe voltage transfer function can be expressed as:

Yo = OP. /(P. Ps + P. + OPs +0-62)If Yo = Yo when 0 = 0 and Yi = Yo when 0 = 1, thenoutput impedance ratio Z0 is:

Zd = Ye/Y1 = 041 - (1 - 0)(Ps - 0)/(P. +Ps + P.P.)]

For three points of this equation, the values of Z0 and 0are the same; or, since there is no linearity error, thenZe = O. These points occur at 0 = 0, B = 1, and 0 = Ps.

The well-known curve (b) for a loaded potentiometercan be written in terms of 0 and P.:

Zo = 041 + 0(1 - 0)/P.]When the load resistance is very high, P. approachesinfinity, and the pot output is the straight black line. Forfinite values of Pm, the nonlinear colored curve is ob-tained. As P. becomes smaller, linearity error grows.

A short computer program (c) that solves the generalequation for impedance ratio Zo can be used to deter-mine the effect of series resistance ratio Ps for variousvalues of load resistance ratio Pm. Generally, the largerthe magnitude of Ps, the greater is the error reduction.The program varies Ps from 0 to 2 in steps of 0.1 and 0from 0 to 1 in steps of 0.05 for P. values of 1, 2, 5, 10,20, and 50.

The plot of (d) shows that output linearity for P. = 1is improved by a factor of five when Ps is increasedfrom 0 to 0.6. In (e), linearity error is plotted against 0for P. = 5 and P. = 10 for Ps values between 0 and0.6. Again, linearity is greatly improved. Values of Psshould be held to 0.5 or less so that the series voltageloss is tolerable.

Reducing loading effects. Output of loaded potentiometer (a) becomes nonlinear, as shown by graph (b), with smaller load resistance ratio(Pm = Rm/Rp). Increasing series resistance ratio (P. R./Flp) decreases loading error and improves linearity. Computer program (c) findsoutput impedance ratio Za for several values of Pm, P,, and wiper position 0. Graphs (d) and (e) show effect of P. on 4 and linearity error.

(a) (b(

READYPLIST10 DATA 1, 2, 5, 10, 20, 5030 READ P140 FOR P2=0 TO 2 STEP .145 PRINT" PM="P1," PS="P246 PRINT47 PRINT " A","Z"48 PRINT50 FOR A=0 TO 1 STEP 5.0 0 0 0 0 E-0 260 LET Z=A/(1 - -A) (P2-A))/(P1 + P2 + P1 P2))70 PRINT A, Z80 NEXT A85 PRINT86 PRINT90 NEXT P295 PRINT96 PRINT100 GOTO 30110 END

READY(c) RUN

(dl

(e)

c, 0.02

cc0

t 0.04

0.02

0

-0.02

0.2 0.4 0.6 0.8

5

0.04 PS -0P, = 0.2

P5 = 0.4

PrIl 10

Ps = 0.6

P, = 0 Ps = 0.2Ps = 0.4

Ps = 0.6

0-0.2 0.4 0.6 0.8 1.2 v

32

Circumventing BCD additionin digital phase -locked loopsby Larry MartinHewlett-Packard Co., Palo Alto, Calif

Many of the applications for a digital divide -by -Nphase -locked loop require the locked oscillator to beoffset by a fixed frequency. Usually, the first stage of theprogramable binary -coded -decimal divider circuit addsthe input frequency to the desired offset frequency. ThisBCD addition, however, can be eliminated by detectingthe proper number at the output of the counter dividerchain.

If a receiver is tuned to 118.15 megahertz, and its in-termediate -frequency stage is at 10.7 MHz, the local os-cillator must then operate at 128.85 wiz. A standard di-vide -by -N circuit (a) adds the i-f frequency to the inputfrequency, takes the BCD nines complement of the sum,and then loads the result into a programable counterdivider chain. Detection occurs when the counter out-puts are all nines. The input number is then reloaded on

the next clock pulse and the process repeats.Let N be the input number; in this case, N = 11815

and the desired offset is 1070. The number at the out-puts of the BCD adders is N + 1070, which becomes19999 -(N + 1070) at the outputs of the complementingcircuits. Therefore, the number of counts that occurs be-fore the divider resets is the divider state that is sensed.Or, the input frequency is divided by:

19999 -[19999 -(N + 1070] = N + 1070which can be rewritten as:

19999 + 1070 -(19999 - N) = N + 1070, or21069 -(19999 - N) = N + 1070By counting to 21069, instead of 19999, the proper

number of counts still occurs before the divider resets.The BCD adders, then, can be removed simply by de-tecting a different output state of the counter, as shownin (b).

Since the divider is an up -counter, detection of thedesired output state should be done when the properoutputs are ones. Because there are only six ones in21069, as opposed to nine in 19999, one fewer outputgate is needed.

Frequency offsetting. Standard divide -by -N circuit (a) sums input fr.equency (118.15 MHz) with offset frequency (10.7 MHz), takes ninescomplement of sum, and then detects signal when counter outputs are all nines. BCD adders and one output gate can be omitted, as in (b),by detecting sum of nines complement and offset frequency (19999 + 1070 = 21069). Correct count is still reached before divider 'esets

(a)

2

INPUT

COMPLEMENTINGCIRCUITS

BCDADDERS

8

0= B

7 =C

DIVIDERCHAIN

Di

Ci

0 B,

A,

L Cp Ao

Di

C.

8,

A,I Cp A0

STATE DETECTINGAND

LOAD CIRCUITS

Di Do

C,

81

AL,

C

DiDo

- Ci- Bi- AL,

Cp-Di Do

Ci

Bi

A,

Cp

CLOCK IN

tout

I b

COMPLEMENTINGCIRCUITS

128.85 MHz

S

OUTPUT

LOAD

ALL LOGIC: TYPE 7400

DIVIDERCHAIN

Di

C,

13,

L Cp

Pi 0oCi

Bi

Ai AaL Cp

Di

C,

B,

AL,

Cp

.1111.1M.

Di

Ci

B,

A,

L Cp

9

STATE DETECTINGAND

LOAD CIRCUITS

CLOCK IN

tout128.85 MHz

LOAD

33

Thumbwheel switches setsynthesizer output frequencyby Jerrold L. FooteUniversity of Utah College of Medicine, Salt Lake City, Utah

Two binary-coded thumbwheel switches can set the out-put of a two -decade frequency synthesizer that in-cludes the two switches, a single crystal oscillator, andtwo decade counters. Synthesizer output accuracy andlong-term frequency stability are the same as that of thecrystal used as the reference frequency source. What-ever pulse -to -pulse time variation occurs is minimizedto an acceptable level by a chain of binary counters.

The synthesis technique involves generating a seriesof pulses and blank spaces, divided by as many binarycounters (N) as needed to yield the desired output fre-quency (f0). The frequency -selection circuit consists ofthumbwheel switches, S1 and S2, two banks of diodes

and their corresponding decade counters, and a flip-flopformed by gates G1 and G2. More decades of frequencycontrol can be added easily.

The number of oscillator pulses passed by the flip-flop -controlled NOR gate, G3, is determined by thethumbwheel switch setting (S). Blank spaces occur whilethe decade counters are counting beyond the switch set-ting. When these counters reach their maximum count(M), the flip-flop resets, and the oscillator pulses passthrough gate G3 to the binary countdown string. Theoutput frequency is given by:

f0 = f,S/MNwhere f, is the crystal frequency.

The output of gate G3 is a train of pulses and blankspaces that must be time -averaged to reduce the pulse -to -pulse time variation (AT) in the output frequency.This time -averaging is performed by the binary count-down string. The closer the tolerance that must be heldon AT, the larger is the number of binary counters re-quired. Maximum pulse -to -pulse time variation is:

AT = S/f0NCrystal frequency can be as high as 10 megahertz.

Dialing frequency. Thumbwheel switches determine number of output decades for frequency synthesizer. Single crystal oscillator serves asfrequency source. Decade counters generate pulse train that is divided by binary counter chain to obtain frequency set by switches. Whenswitch -fixed decade count is reached, flip-flop formed by gates G1 and G2 resets, enabling gate G3 so that pulses pass to binary counters.

MC 780 P

MC 780 P

CRYSTALOSCILLATOR

Vcc

W0 w< H

Zw D00 4

2

1N277 (ALL)

4.7 k2

s,

LU CC'Li 2

zp0 4

14

1N277

ALL CIRCUITS: MOTOROLA

S2

TO ADDITIONAL DECADES

Y.MC724P

BINARYCOUNTER

MC 777 P

BINARYCOUNTER

OUTPUT

BINARYCOUNTER

MC 777 P MC 777 P

34

15 k12

(A)

MODULATIONINPUT (Wm)1

10 kS2

+10 Vdc

-10 Vdc

82012

R(C)

5.6 kS2

R5

15 kS2

2N2222

R6

R4

Cl 39 pF

(B)

a2 6.8 kS-2 1N772

- 2N2222

CARRIERINPUT (c..)c)

(E)

15 kS2

5.6 kS2 (

820 S2

131

D3

2N2222

C2 39 pF

R2 D2

6.8 kS2 1N772

MODULATEDOUTPUT(mac ± wc)

Splitting and chopping. Highly linear amplitude modulator theoretically can operate at half the carrier frequency. Transistor 01 splits modu-lation input into two equal signals that are opposite in polarity and phase. Switch 02 passes positive half -cycles of square -wave carrier, whileswitch 03 passes negative half cycles. Chopped modulated signals (points C and D) are then summed by resistors R5 and R6.

Amplitude modulatoris highly linearby Donald DeKoldSanta Fe Junior College, Gainesville, Fla.

Besides offering good linearity, an amplitude -modu-lation circuit can operate at modulation signal fre-quencies ranging from dc to half of the carrier fre-quency. At modulation levels as high as 97.5%, thecircuit retains its linearity. All signals are directlycoupled without inductive or large capacitive elements.

Transistor Qi performs as a phase splitter for themodulation signal, which appears at Qi's emitter with00 phase shift and somewhat attenuated from its inputlevel. The dc level of the modulation is approximately-5 v dc at Qi's emitter and +5 v dc at the collector,where the signal is 180° out of phase with the input.

Transistors Q2 and Q3 are high-speed switches, drivenalternately from saturation to cutoff by the carrier in-put. This signal, preferably a square wave, is applied tothe bases of Q2 and Q3 through resistors R1 and R2 anddiodes D1 and D2, respectively. The diodes protect thetransistors from excessive reverse base -emitter voltagegenerated by possible overdrive from the carrier signal.Capacitors C1 and C2 speed up Q2 -Q3 switching times.

The collectors of Q2 and Q3 are coupled to the twooutputs of phase-splitter Qi through resistors R3 andR4. These isolate the modulation frequency portion ofthe circuit from the carrier frequency portion.

The modulation signal appearing at Qi's collector isswitched from its average 5-v dc level to ground by Q2on each positive half -cycle of the carrier. A choppedversion of the modulation signal then appears at Q2'scollector. Similarly, the modulation signal at Qi's emit-ter is chopped by Q3; Q3's cutoff -to -saturation transition

occurs at each negative half -cycle of the carrier.Positive and negative chopped modulation signals are

then combined by a simple summing network com-posed of resistors R5 and R6. Signal components of thechopped outputs that occur at modulation frequenciesare summed to zero. Therefore, under perfectly bal-anced conditions, the modulated output is spectrally de-void of modulation -frequency components but, ofcourse, contains the modulation sidebands. Theoret-ically, this permits modulating to an upper frequencylimit of one-half the carrier frequency without trouble-some filtering problems. The modulation envelope, inthis case, is 180° out of phase with the input modulationsignal.

The circuit's output is an amplitude -modulatedsquare wave containing harmonics principally at oddmultiples of the carrier frequency. (Spectral content isnw, ± (Om, where co, = carrier frequency, Wm = modu-lation frequency, and n = 1, 3, 5, . . . .) If a sinusoidalcarrier is wanted, the output must be filtered. Sincemodulation frequency components are absent from theoutput spectrum, a low-pass filter can be employed toselect the fundamental carrier frequency and its side -

bands. However, a bandpass filter must be used if theoutput is to be some multiple of wc.

Modulator high -frequency performance dependslargely on the speed of the switching transistors. For thetransistors shown, useful modulated output extends to 1megahertz. The modulator itself is essentially flat andlinear to 250 kilohertz, with visually apparent distortionoccurring in the modulation envelope above this fre-quency. At a carrier frequency of 100 kHz and modu-lation frequency of 1 kHz, good linear modulation canbe obtained to a modulation depth of 95%.

For a modulation input signal of 14 v peak -to -peak,the maximum modulated output level will be 7.4 vpeak -to -peak into an open circuit. The minimum carrierinput level for a square -wave drive is 2.8 v peak -to -peak. And overdriving does not produce any unde-

35

sirable effects. The modulation can be any waveform.A sine wave can be used as the carrier input, but

chopping action will not be as good. Minimum sine-wave drive level is 4 v pk-pk. A linear modulationdepth of 97.5% can be obtained at a carrier frequency of10 kHz and a modulation input level of 14 v pk-pk.

Minimum carrier input drive levels remain essentiallyunchanged at a lower carrier frequency. Modulator per-formance, however, degrades somewhat at higher out-put frequencies-maximum linear modulation becomesonly 94% at 500 kHz and 88% at 1 MHz. Output level

also drops at higher frequencies, but can be improvedby using faster switching transistors and lower imped-ance levels throughout the circuit.

Higher supply voltages offer an alternate method forimproving circuit output level. The saturation voltage ofthe chopping transistors represents the theoretical limitof maximum modulation depth; this voltage becomesless significant when higher supply levels are used. Fur-thermore, using precision resistor pairs (R3 -R4, R5-14,and R7 -R8) assures that positive and negative peakmodulation signals are identical at the output.

FETs remove transientsfrom audio squelch circuitby Glen CoersTexas Instruments Components Group, Dallas, Texas

Using field-effect transistors instead of bipolar transis-tors for an audio squelch circuit eliminates switchingtransients without sacrificing switching time. Moreover,because there are no transients, the circuit's frequencyresponse can be as low as desired.

In a typical audio squelch circuit (a), bipolar transis-tor Qi acts as the control device for bipolar transistorQ2, which serves as the amplifier. When Qi turns off Q2,the base voltage of Q2 switches from a dc level (in thiscase, 2.8 volts) to ground, causing a large transient out-put voltage spike to be generated.

The problem can be minimized by slowing the

12V

AUDIO 10

IN 11µ

F

1 k1.2

CONTROLVOLTAGE

la I

AUDIOOUTPUT

switching speed of Qi or raising the low end of the am-plifier's frequency response. However, this method isnot practical in applications requiring a broad fre-quency response, such as high-fidelity audio equipment.

Building the circuit with FETs (b) provides a better so-lution. Again, transistor Qi is the control, while transis-tor Q2 is the amplifier. Only ac voltage is present at thegate of Q2; its dc level is at ground potential so thatthere is no transient generated when Q2 is switched off.

When ()I's gate is at zero volts, the device itself con-ducts, bypassing the audio signal to ground. TransistorQ1 and resistor R1 form a voltage divider that attenu-ates the signal by about 60 decibels. The "on" resistanceof the FET is approximately 100 ohms.

To pass the audio input, a negative voltage must beapplied to Qi's gate to turn the device off. The audiosignal at the gate of Q2 can then reach the output de-void of any switching transients.

12V

CONTROLVOLTAGE

AUDIOOUTPUT

FETs replace bipolars. In bipolar -transistor audio squelch circuit (a , large output transient is generated when Ch turns off, because dc volt-age at 02's base is grounded. Substituting FET circuit (b) eliminates transients without limiting switching speed. Control FET C), turns off fornegative gate voltage, allowing amplifier 02 to pass audio signal to output. Only ac voltage is present at 02's gate.

36

Diode plus low-cost op ampmakes accurate thermostatby Robert KossAdac Inc., Colchester, Vt.

Employing a silicon diode as the temperature -sensingelement allows an inexpensive operational amplifier tocontrol temperature to a variation of less than 005°C. Atype 1N4148 diode, for instance, has a typical tempera-ture coefficient of -2 millivolts/ °C.

The resistance bridge in the diagram sets the tem-perature that is sensed by diode D1 and that is main-tained by the heater element, resistor R1.

When temperature is too low, control voltage Vi goesnegative, limiting the op amp's output to 12-14 volts.Transistor Qi conducts and provides the necessary

heater current. When temperature is too high, diode D2prevents amplifier output voltage from going negative,and transistor Qi turns off. Average current then is al-ways positive and is controlled by the amplifier to com-pensate for changes in temperature.

Transistor Q2 and resistor R2 prevent the heater cur-rent from exceeding a specified limit. (For this circuit,maximum heater current is 375 mA.) If the voltage dropacross resistor R2 equals Q2's 0.6-v base -emitter voltage,transistor Q2 turns on, shorting the amplifier's current -limited output to ground, thus turning off transistor Qi.

The stability of the control loop depends on severalthermal time constants that are not easy to calculate.Computations can be reduced a little by using a rela-tively large time constant in the feed -forward directionfor R3C1 and keeping the remaining thermal lags assmall as possible. Sense diode D1 should make goodthermal contact with the object to be temperature -con-trolled. It should also be thermally insulated fromchanges in external conditions. El

Inexpensive thermostat. Tight temperature coefficient of silicon diode permits low-cost op amp to be used for controlling temperature towithin 0.05°C. Resistance bridge sets temperature of heater containing sense diode D1. For low temperatures, amplifier turns on transistor01, which supplies heater current. For high temperatures, amplifier output remains positive because of diode D2, but 01 stops conducting.

+15 V

12.1 kE2 15.8 kE2

1

500 E2

LTEMPERATURE

02 1N4148

33 pF

+24 V

HEATERr 1D,

1N4148

R332.4 kst

V,

CONTROL

'NAN32.4 kl2

_... 1µF

741

Q2

2N2369

(RESISTANCER,

88 0 1 WALIRLEdYjE451-,LIFF,I 19.4 12/FT)

1 k0Qi

2N40322

1 6 02 W)

37

Logic system checks outanalog -to -digital converterby Charles J. HuberWestinghouse Electric Corp., Systems Development Div., Baltimore, Md.

Testing the conversion accuracy of an analog -to -digitalconverter need not be a laborious and time-consumingtask. The test configuration shown can reduce the job toa go/no-go operation without undue expense (approxi-mately $36 for integrated circuits plus the cost of a digi-tal -to -analog converter).

This test system produces a 12 -bit digital ramp that isconverted (by the d -a converter) to a 4,096 -step analogramp. The analog ramp is applied to the a -d converterunder test, and the resulting output from the 10 -bit a -dconverter is compared to the 10 most significant bits ofthe 12 -bit digital ramp.

An input clock is applied simultaneously to a one-shot delay network and to a ripple -through counter con-sisting of three four -bit binary counters. The delayedclock becomes the input for six four -bit buffer latches.These accept and delay all 12 of the bit outputs fromthe counter to remove glitches from the digital ramp.The delayed clock now acts as the basic time reference.

The 10 most significant bits from the latches driveboth a d -a converter and a comparator formed by threequad exclusive -OR gates. These gates compare the bitsof the digital ramp to the output bits of the a -d con-verter, on an individual basis. The analog output of thed -a converter corresponds to the input digital codewithin ±'/8 the least significant bit.

The delayed clock pulse also passes through anotherone-shot delay network before reaching a sample cir-cuit, which strobes a second set of buffer latches. Forzero error at the buffer outputs, the minimum strobe de-lay equals the a -d conversion time. An interpolatingvoltage applied to the d -a permits continuous voltagecontrol of the a -d output over the 1/2 -bit range.

The test system can accurately determine conversiontimes of 2 microseconds for successive -approximationand variable -reference a -d converters. Additionally, thenature and position of other conversion errors can bedetermined by relating displayed error pulses to thedigital ramp. For example, small areas of the ramp canbe investigated by making constants of the 10 most sig-nificant bits of the digital input and using the eleventhand twelfth bits as variable controls.

More system flexibility can be obtained by using anup/down counter to eliminate the d -a converter's slewtime when the count changes from 111 . . . 1 to000 . . . 0. Replacing the counter with a pseudo -ran-dom generator allows testing for all input changes.

Verifying converter accuracy. A -d converter test system generates 12 -bit digital ramp with ripple -through binary counter. Buffer latchessmooth out any ramp glitches. D -a converter then develops analog input for a -d converter using only 10 most significant ramp bits. Exclusive -

OR gates compare a -d output with ramp. Errors pass to another buffer for comparison with appropriately delayed clock.

CLOCK DELAY

(ONE SN74123)

12 12 10

11 D -A

COUNTER

(THREESN74197)

3

BUFFERLATCHES

(SIXSN7475)

10 CONVERTER(ANALOGDEVICESDAC 12-O)

A- DCONVERTER

(10 BITS)2

COMPARATOR

(THREE SN7486)

BUFFER LATCHES

(SIX SN7475)

ALL ICs TEXAS INSTRUMENTS

SAMPLE

(ONE SN74123)

DELAY(ONE SN74123)

38

Double -duty multivibratorgives complementary outputsby Edward BeachNational Radio Institute, McGraw-Hill Inc., Washington, D.C.

Depending on its input signal period, a pulse generatoroperates as a one-shot or as a synchronous astable mul-tivibrator. In either mode, the circuit provides comple-mentary outputs. An ordinary grounding pushbuttonswitch can serve as the input device.

Gates G1 and G2 form a simple latch that preventsthe circuit from operating in the absence of an input(high). When the input goes low, the latch changesstate, allowing gate -G1 to act as an inverter. Gates G1,G3, and G4 are the pulse -generating portion of the cir-cuit.

If the input remains low for less than three generatortime constants, single complementary pulses are pro-duced by gates G1 and G4. The leading edge of eachoutput pulse coincides (neglecting gate delays) with theleading edge of each input pulse. The trailing edge ofthe output pulse (again, neglecting gate delays) resetsthe latch and disables the generator.

When the input signal remains low for longer than

tree time constants, at least two complete outputpulses with a period equal to approximately three gen-erator time constants are produced. In this case, thepulses begin and end synchronously. The first outputpulse coincides with the leading edge of the input, andthe last pulse is a full -width pulse, no matter when theinput is removed.

Resistor R can range in value from 330 ohms to 1.5kilohms, while capacitor C can be some value between0.001 microfarad and 1,000 µF. For example, whenR = 1,000 ohms and C = 100 [if', the circuit will pro-duce either a 100 -millisecond pulse or a 100 -ms pulsetrain with a repetition rate of about 3 pulses per second.

For critical timing applications, a nonpolarized ca-pacitor should be used when C is a high value; for less-critical applications, an ordinary electrolytic or tanta-lum capacitor will suffice. Since the reverse capacitorvoltage is only about -0.7 volts, an inexpensive capaci-tor can be used.

The circuit can also function as an inexpensive tran-sistor -transistor -logic clock simply by replacing gatesG1, G3, and G4 with half a type 7404 circuit. In addi-tion, gate G2 could be eliminated and an inverted ver-sion of the input signal applied directly to gate GI, butthis could shorten the last pulse in the pulse train.

Manual pulser. Pushbutton -operated pulse generator functions either as a monostable or astable multivibrator. Low input signal enables G1 -

G2 latch so that G1 becomes an inverter. Gates G1, G3, and G4 then generate complementary output pulses. When input is low for less thanthree RC time constants, circuit is a one-shot; when input period exceeds 3RC, circuit is a synchronous astable multivibrator.

R

+5V

INPUT

0 V -7IF

< 3 RC

INPUT

0V

OUTPUT A T = RC

0 V

OUTPUT B

0 V .11116

ALL GATES: TYPE 7400

T, , 3 RC

INPUT -I0 V -

OUTPUT A

0V-OUTPUT B

0 V --T= 3 RC -4.1

39

Schmitt trigger preventsclock train overlapby R.R. OsbornRoberts Enterprises, Flagstaff, Ariz.

Non -overlapping clock trains are often required in digi-tal systems, especially when transistor -transistor -logiccircuits must be interfaced with metal -oxide -semicon-ductor logic circuits. A single integrated Schmitt trigger,using only one RC time constant, can provide the ap-propriate delay between clock trains. Moreover, thetemperature stability of the IC Schmitt trigger assuresthat the separation between output clocks remains con-stant, despite changing temperature.

The Schmitt trigger delays the Q output of the flip-flop for the time fixed by resistor R and capacitor C; itdoes not delay the flip-flop's (5 output. The delayed andundelayed pulse trains then pass through a combinationof NAND gates, producing the two desired non -over-lapping output clocks.

Interclock intervals, which occur when both clockoutputs are high, are unequal if resistor R alone sets thedelay, because of the flip-flop's output levels and theSchmitt trigger's input current. Adding resistor R' andtwo diodes, as shown by the dashed lines, allows the in-terclock intervals to be made equal to each other. Thevalue of R' can range from 0 to 5 kilohms.

Capacitor C can vary from 0 to 1,000 microfarads,producing interclock intervals of 30 nanoseconds to 1

second. The time between input clock pulses must al-ways be greater than the output clock interval; inputclock frequency can be as high as 10 megahertz.

Staggering clock phase. Circuit produces two non -overlapping output clock trains from single input clock to flip-flop. Q output of flip-flop isdelayed by Schmitt trigger for one RC time constant. Delayed clock from Q and undelayed clock from 5 are combined by NAND gates to yieldseparate output clock trains. Adding dashed components yields equal interclock intervals. Clock speed can be as fast as 10 MHz.

CLOCKIN

FLIP-

FLOP7473

CLOCK IN

a

S

(7)

CLOCK 1

A.A.A,

2202

vs,

1N277

DELAY

S

Y, 7413

SCHMITTTRIGGER

INTERCLOCKINTERVAL

7400

r

CLOCK 2

QS

40

Broadband cutoff limiteris phase -transparentby Roland J. TurnerRCA Missile & Surface Radar Division, Moorestown, N.J.

When information is transmitted in the phase domain,the video or intermediate -frequency processor in a ra-dar or communications system frequently requires alimiter circuit that does not alter the zero crossings ofthe input signal.

By using current cutoff limiting, a broadband phase -transparent (zero phase -shift) limiter can be built thatmaintains input zero crossings within 14 picoseconds,while providing a gain of 20 decibels over its linearrange. This limiter, which operates from dc to 30 mega-hertz, can improve receiver sensitivity, allowing smallertargets to be resolved in a radar system or, in a commu-nications system, reducing level- and frequency -depen-dent phase noise so that phase -detection thresholds canbe lowered.

The limiter circuit uses microwave transistors thathave a unity -gain crossover frequency (fT) of greaterthan 1 gigahertz. The bandwidths of the transistorstages making up the limiter can then exceed 500 MHzto yield the limiter's over-all wideband performance byusing conventional microstrip techniques.

Exceptional signal control is realized by driving thetransistors into their cutoff regions to achieve limitingaction. Transistor cutoff parameters are more control-

lable and more clearly defined than transistor satura-tion parameters. And with cutoff signal limiting, thetransistors look like high impedances to low load im-pedances, thereby achieving fast limiting action withcontrolled passive elements.

Transistors Qi through Q4 perform the limiting func-tion, while transistors Q5 and Q5 operate as a unity -gainoutput driver. There are two limiting sections, one con-sisting of Qi and Q2, and the other of Q3 and Q4. Twotransistor stages, then, form each limiting section.

For one polarity of the input signal, one transistorstage operates as a low -gain broadband amplifier, whilethe other limits the section's output by performing as acutoff isolation amplifier. During the opposite polarityof the input signal, the transistor stages reverse roles.Each limiting section supplies a gain of 3.3. The outputlevel of each section is determined by its quiescent oper-ating point.

This limiting scheme provides extremely low carrieroutput phase shift for the full dynamic range of the in-put signal. Over a 40 -dB input range, from 100 milli-volts peak -to -peak to 10 volts pk-pk, the limiter circuitis phase -transparent within 0.25°. For example, the out-put is 1.2 v pk-pk for a 120-mv input. For frequenciesup to 20 MHz, the output impedance of the driver sec-tion is less than 5 ohms.

From dc to 20 MHz, the time displacement of adja-cent zero crossings of the output waveform are within14 picoseconds of the period established by the inputzero crossings. In the phase domain, this means that thephase of a 20 -MHz input will be shifted less than 0.1° atthe output, making the limiter phase -transparent for allpractical purposes. CI

Linear -phase signal limiting. Operating from dc to 30 megahertz, limiter circuit remains phase -transparent within 0.25° over 40 -decibel in-put dynamic range. Each limiting section contains two transistor stages. Depending on input signal polarity, one stage is low -gain broadbandamplifier, while the other acts as cutoff isolation amplifier. Optimum usage of transistor cutoff parameters achieves desired limiting action.

INPUT

3.48 kl2

3 3 mA

SUPPLY17 Vdc, 50 mA

0.001 1.1F-I1N936

2N285/2N285/

12.1 kE2

C

1µH

0.001 ,F

0.001 µF

Hf-L

1N936

2N2857

18 S2 12.1 k62

3.48 k62

12V

LIMITINGSECTION

0.001 µF

1+1

1.10 k62

-12 V

+12 V

68.1 S!

0 0010

HL

1N936

2N2857

0.001 µF

LIMITINGSECTION

18 62

10 mA

1.10 kS2

0.001 Pr0.001 /IF C: 1µF NON -POLARIZED

-12 V = MYLAR IN PARALLELWITH 1000-pF LOW -INDUCTANCE BYPASS

OUTPUTDRIVER

68.1 12 316 62

0.001 µF

L1N9 36

2N2857

12.1 kS2

2N2857

56212

-12 V

20 mA

68.1 13

j- C

2N5829

15 mA

51-E2LOAD

41

Preset generator producesdesired number of pulsesby Glen CoersTexas Instruments, Components Group, Dallas, Texas

Computer systems and medical instruments are likelyapplications for a digital pulse generator that will de-liver, on command, any desired number of full -widthpulses from 1 to 999. Three 10 -position switches set thenumber wanted.

Rotary switches Si, Sz, and S3 fix the number of out-put pulses. Si controls the most significant digit, whileS3 controls the least significant digit. For example, if Siis set to 3, S2 to 6, and S3 to 8, the number of outputpulses will be 368.

Gates G1 through 04 eliminate any count errorcaused by contact bounce from toggle switch S4. WhenS4 is placed in its count position, flip-flop FF1 inhibitsgate G4 until the trailing edge of S4's count pulse occurs,so that even the first output pulse is full width.

Placing S4 in its count position results in a high atboth inputs to G2, enabling this gate (its output goeslow) and resetting the decade counters to zero. Thecount command also causes one input of G1 to go low,making its output high. This clears flip-flop FF1 andkeeps its Q output low. The high from Gi also drives

FF1's preset function high, as well as one of the inputsto G4. The output from G5 is now low.

The first negative edge of a clock pulse triggers theflip-flop and makes Q go high. The output of G3 thengoes low, presetting the flip-flop to maintain Q in thehigh condition. When G3's output goes low, one inputto 04 also goes low, enabling this gate so that clockpulses are passed to its output.

The binary -coded -decimal count that is accumulatedin the divide -by -10 arrangement of decade counters istransferred to the BCD -to -decimal decoders. A de-coder output goes low when that decoder reaches thesetting of its associated rotary switch. When all threedecoder outputs are low, gate G5 is inhibited (its outputgoes high). This causes one input to G4 to go high, stop-ping the transfer of pulses.

Placing switch S4 in its reset position drives one inputto gate G2 low, making its output go high and operatingthe reset function of the decade counters. Both inputs ofGi are now high, while its output, the clear function ofthe flip-flop and one input to G3 are low. This clears Qto a low condition, causing Gi's output, FF1's presetfunction, and one input to G4 to go high. The circuit isnow ready to start a new count.

Adding more counters, decoders, and switches will, ofcourse, increase the number of pulses that can becounted. 0

Pulse counter. Three rotary switches control number of output pulses that can be generated; settings may range from 1 to 999. Flip-flop andgates G1 through G4 assure that all output pulses are full width. Toggling switch S4 to its count position allows gate G4 to transfer clock pulses

to divide -by -10 arrangement of decade counters. Each BCD -to -decimal decoder counts to setting of its rotary switch.

CLOCK

1/3 SN7427

SN7472

+5 V

CLEAR

CLOCK

PRESET

FF1

04

OUTPUT COUNTER

4.7 IcEl

1/4 SN7400

1/4 SN7400

S4 COUNT

TRESET

IIIb

1/4 SN7400

4 7 kS-2

ALL ICs: TEXAS INSTRUMENTS

+5 V

RO

BD SN7490

DCBA

I IDECODER

DCBASN7442

0123456789

3

181

lOs 100s

RO RO

BD SN7490 BD SN7490

.111DCBA DCBA

10 11111DCBA

SN7442

0123456789

DCBASN7442

0123456789

- s,

(6)

1,3 SN7427

S, -

(31

CLOCK

STOPCOUNT

Gi OUTPUT

G4 OUTPUTWHEN 5, =0, S2 = 0, S3 = 4

START COUNT

42

Frequency doubleraccepts any waveshapeby Donald DeKoldSanta Fe Junior College, Gainesville, Fla.

The frequency of nearly any waveform can be doubledby means of quadrature square waves that drive a bi-conditional logic circuit. Only two restrictions must beimposed on the input to this frequency doubler-thewave form must have a duty cycle of approximately50% and a peak -to -peak amplitude of at least 0.5 volt.

For the circuit shown, the input is a sine wave that

can vary in frequency from 40 to 600 kilohertz. The out-put is a square wave at twice the input frequency, hav-ing a duty cycle of about 38% for the lower -frequencyinputs to'around 65% for the higher -frequency inputs.

Comparator Ai operates in its noninverting mode, ac-cepting the input sine wave and producing a squarewave at its output. Capacitors Ci and C2 couple thissquare wave to a pair of complementary switches, tran-sistors Qi and Q2. The switches boost the amplitude ofthe square wave to 24-v pk-pk. Resistors Ri and R2 pre-vent the bases of Qi and Q2 from being clamped to dcvoltages that would drive them into cutoff.

Capacitor C3 is alternately charged and dischargedthrough resistor R3. When Qi is in saturation and Q2 incutoff, C3 exponentially charges towards 12 v dc; withQi cut off and Q2 saturated, C3 discharges towards

Frequency times two. Sine -wave input is converted into square wave by comparator Al. Emitter -followers OI and 02 charge and dischargecapacitor C3, producing triangular wave that drives comparator A2. Resulting square -wave output of A2 is in quadrature with square -waveoutput of Al. Switches 05 and 06 conduct only when comparator states are different, providing square wave that is twice input frequency.

+12 V dc

2N2222OUTPUT

68052 SQUARE2.4 k12 WAVEQ3

INPUTSINE WAVE(40 - 600 kHz)

012N3905 1N662 06

91052 0.22p F 04 2N2369A220 2

2CI-

0.1 p F R32 2N2222 2.41(2HI (C)

Al C4 A2(A) ( 8 )41-W0-1 kS2 3 ( Dl 1N662

C20.1 p F 91052 C3

2.4 k12 2N2369A22Q Sl 6.8 6.8

Q2 0.012µF "2 k,f2

2N2222R2

2.4 k2 2.2 k12 2.2 kl21N753A

1 kS2

COMPARATORS:FAIRCHILD pA710

-12 Vdc

INPUT 1 V pk-pk

(A)

(B)

3.2 V ---

-0.5 V -

12 V - -

-12 V ---

(C)

( DI

12 v ---OUTPUT 8.5 V

14 V pk-pkMAX AT 40 kHz

43

-12 v dc. When the charging or discharging interval isshort compared to the R3C3 time constant, the vim' ageacross capacitor C3 approximates a triangular wave thathas its peak value occurring 90° out of phase with thepeak amplitude of the input sine wave.

The triangular wave is applied to the noninverting in-put of comparator A2 through capacitor C4. The com-parator "squares" the triangular wave about its zerocrossings, producing a square wave that is 90° out ofphase with the output of the first comparator.

Transistors Q3 and Q4 are emitter -followers that actas buffer amplifiers for both comparators and drive aset of nonsaturating switches, transistors Q5 and Q6.When comparator states are the same, Q5 and Q6 areoff; when comparator states differ, Q5 or Q6 conducts.

The switching action of transistors Q5 and Q6 isequivalent to the biconditional logic function:

XY + XY = 1which has the effect of doubling the frequency ofquadrature square waves. A diode and resistor in each

transistor's base -emitter loop prevent false switchingwhen both comparators are in the same state, but mayhave different output levels.

A square wave with a 50% duty cycle can be realizedfor a nominal input frequency of 120 kHz. At lower fre-quencies, the duty cycle is smaller because the triangu-lar wave becomes exponentially rounded. At higher fre-quencies, the duty cycle is larger, since the amplitude ofthe triangular wave decreases, thereby shortening theduty cycle of the square wave at the output of the sec-ond comparator. Also, circuit delays become significantcompared to the period of high -frequency inputs.

The frequency doubler can operate below 40 kHz ifhigher capacitor values are used throughout the circuit.To operate at higher frequencies, faster switching de-vices must be used, and transistors Qi and Q2 must notbe allowed to saturate.

Since the maximum input voltage for the type p.A710comparator is ±7 v, the amplitude of the triangularwave must not exceed 14 v pk-pk.

Op amp cancels videoThe video gate basically consists of a switching field-

effect transistor (Q1), its associated TTL-compatibledriver (bipolar transistor Q2), and an output op amp.switching transients Transients are generated when the switching waveformedges pass through the FET'S gate -drain junction.

By adding a second FET (Q3) and its biasing resistors,the transients can be eliminated by forcing them to can-cel through the op amp. Since the transients from tran-

The common -mode rejection of an ordinary operational sistor Qi will be identical to those from transistor Q3,amplifier can help to minimize switching transients in the op -amp's common -mode rejection stops these un-low-level video gates. The transients are caused by the wanted spikes from reaching the output.leading and trailing edges of the switching waveform. Capacitor C1 helps maintain equal feedthrough char-

Transient-fres video gate. Leading and trailing edges of gating waveform create transients when passing through first FET, 01. Including asecond FET, 03, duplicates signal path of Oland permits op -amp common -mode rejection to cancel most transients. Capacitor C1 equalizesfeedthrough characteristics of the two FETs so that matched pair is not necessary. Bipolar transistor 02 makes circuit TTL-compatible.

by Steven E. HolzmanElectromagnetic Systems Laboratories, Sunnyvale, Calif.

VIDEO SIGNAL INPUT

-12 V

INHIBIT+5V

0 ON

GATING WAVEFORM

56 pF

4.7 kS2

0,2N4860

CI5 pF

1N4148

6.2 kS2

1

+5 V

032N4860

022N2907

RI

1

1 kS2

1 kS2

2 kS-2,

NATIONAL

GATEDVIDEOOUTPUT

44

acteristics for both Qi and Q3. This eliminates the needfor a matched pair of FErs. By simply adjusting resistorR1, nearly all of the transients can be cancelled.

In the circuit shown, the amplitude of the switchingtransients can be reduced to less than 1 millivolt over anoperating temperature range of -20 to + 60°C.

Pulse generator accuracyis immune to agingby Frank CicchielloDigilog Systems Inc., Willow Grove, Pa.

This pulse generator for driving digital circuits won'tchange frequency, even after its components have agedor are replaced. And pulse repetition rate remainsstable over a wide temperature range.

If any or all of its active devices are replaced or haveaged, the generator exhibits only a 1.5% worst -case vari-ation in rep rate. Replacing or aging any or all of thepassive components causes a worst -case change of 1%.Typically, rep rate varies merely 0.5% over a 50°C tem-perature range, and all variations amount to less than2% when taken collectively.

When the dc supply voltage (Vcc) is turned on, tim-ing capacitor C1 charges exponentially through resistorR1 until capacitor voltage reaches the threshold voltage(VT) of programable unijunction transistor (PUT) Qi.This triggering level is established by the voltage divi-der formed by resistors R2, R3, and R4. For optimumtemperature stability when the supply is greater than 10volts:

VT = 0.5VccPulse rep rate is determined by:

rep rate = 1/[0.78R1C1 + (0.5 x 10-12)R1C1]Once its triggering threshold is reached, the PUT

switches, causing its gate voltage to swing in the nega-tive direction. This produces a positive -going pulseacross cathode resistor R5, which turns on transistor Q2and discharges capacitor C1.

The function of Q2 is twofold. It rapidly discharges C1by passing the discharge current around the anode -cathode junction of the PUT. And it also effectively elim-inates the PUT's valley -current offset. This allows timingresistor R1 to have a value as low as 2 kilohms, ratherthan a value above 100 kilohms, as normally required.Output pulse rep rate can then vary over a 250:1 rangefor a given value of C1 (500 picofarads to 1 microfarad).Output frequency can be up to 1 megahertz.

PUT temperature stability is assured by diode -con-nected transistor Q3, which matches the temperaturecharacteristic of the Pur's anode -gate junction, even ifcurrent flow is in the microampere region. Althoughmost standard diodes cannot do this, almost any low -leakage diode -connected silicon transistor may be usedfor Q3.

Negative -going pulses from the PUT are directlycoupled to the base of transistor Q4 through transistorQ3; capacitor C2 provides ac coupling. If pulses shorterthan 4 to 5 microseconds (typical for this circuit) are re-quired, the R6C2 time constant of Q4's input couplingnetwork can be reduced to differentiate the input signaland produce narrower positive -going output pulses. Theoutput pulse train is compatible with both transistor -transistor and diode -transistor logic.

Stable pulse generator. Power supply charges capacitor C1 until threshold of programable unijunction transistor Q1 is reached, Qi thenswitches, turning on transistor 02, which discharges C1. Diode -connected transistor Q3 dc couples resulting pulse to output transistor Q..

Generator's repetition rate changes only 2% for worst -case variation of all its components, even if they age or are replaced.

(1% POLY -C1 = STYRENE

OR MYLAR)

Qi2N6027

2

85820 S2

Q3

20 kS2

"Ro1.15 kS2

R22.00 k,r2

1.15 kS2

C2

470 pF

R6

10 kSt2.2 kS2

04

02, 03, 04 PART OF RCA CA3018 '1% METAL FILM RESISTOR

Vcc

+5 V

PULSEOUTPUT

45

Logic probe with LED displaychecks ECL circuitsby William WilkeUniversity of Wisconsin, Madison, Wis.

A simple logic probe for testing emitter -coupled -logiccircuits identifies three input conditions-a logic high, alogic low, and an open circuit. The probe indicates alogic high (-0.75 volt) by lighting a red light -emittingdiode, a logic low (-1.5 v) by lighting an amber LED,and an open -circuit condition by lighting neither. Thecircuit costs about $4-$ 5 to build.

Input resistor R1 and diode D1 protect the circuitagainst positive voltages. When an open circuit exists atthe probe tip, resistors R2, R3, and R4 hold point A at alogic low so that gates 01 and G2 are disabled. Since theLEDs only light for a logic low excitation voltage, bothstay off regardless of the voltage level at point B.

When the probe tip is connected to a low or a highlogic level, point B is forced to that level (-1.5 or -0.75v) and point A is forced to a logic high level. Now gatesG1 and 02 are enabled and, depending on the level atB, either the red or the amber LED lights up.

Resistors R5 and R6 allow the quad ECL NAND gate toswitch up to 20 milliamperes through the LEDs for abrighter light output. The entire logic probe circuit canbe assembled inside an ordinary felt tip pen or othersmall container. 1=1

ECL logic probe. Red light -emitting diode lights up for logic high input, while amber LED indicates low input. Both LEDs are dark with opencircuit at probe tip. When low or high is present at input, gates G1 and G2 are enabled, point A goes high, and point Bgoes to logic level atinput, lighting proper LED. For open -circuit input, G1 and G2 are disabled and point A is low, keeping both LEDs off.

PROBETIP

R2 82 ks2

R1

1.3 kE2

20 - 80 µA it DI1N914

R3

33 kE2

4 33 kg2

MOTOROLAMC 1048

an D.

D.

R5 86r2 R6 86x2

(B)

REDLED MV 50

MONSANTO

j (A)AMBERL ED

-5 V1110 mA)

MV 1MONSANTO

Converter for oscilloscopeprovides four -channel displaysby Grady M. WoodHarris-Intertype Corp., Melbourne, Fla.

With the help of only two integrated circuits and ahandful of passive components, conventional single- ordual -channel oscilloscopes can be economically con-

verted to four -channel displays. The key element is afour -channel programable amplifier, the Harris typeHA -2405. This is an operational amplifier with fouridentical input stages, any one of which may be elec-tronically connected to the output stage by two binaryaddress inputs.

For the scope converter circuit, each amplifier iswired in its unity -gain inverting mode. High -value (2megohm) feedback resistors provide a high input im-pedance for each channel. All four non -inverting ampli-fier inputs go to a variable voltage source formed by a500-kilohm potentiometer that is between the ±15 -volt

46

power supplies. This arrangement provides an indepen-dent centering control for each channel. Any offset volt-age resulting from the large feedback resistors is not aproblem, since the centering control provides adequateamplifier adjustment range.

The scope's gate output is divided down by a dualJ -K flip-flop to supply binary channel selection signalsfor the integrated amplifier circuit. This gate signal issynchronized to the scope's sweep, so that there are notiming difficulties. After each trace is completed, thenegative -going gate signal selects the next channel. Theretrace time allows adequate time for channel selection.

The passive network at the input to the flip-flop-ca-pacitor Cl and resistors R1 and R2-extracts a trigger

pulse of approximately 5 v from the 30-v waveform ob-tained at the GATE OUT terminal of a Tektronix type545 scope. Other scopes may require a different passivenetwork.

Important circuit performance characteristics in-clude: a gain of 1, a bandwidth of dc to 5 megahertz, aslew rate of 15 v/microsecond, a maximum input volit-age of ± 10 v, an input impedance of 2 megohms, and acrosstalk figure of 80 decibels.

Circuit voltage range, bandwidth, and input imped-ance can be increased by adding op amps to buffer eachinput. Making the gain of each of these buffers indepen-dently variable further improves circuit versatility. Ap-proximate parts cost for the entire circuit is $25. 0

Scope converter. Monolithic quad operational amplifier provides inexpensive way to increase display capability of standard oscilloscope.Binary inputs drive IC op amp; dual flip-flop divides scope's gate output to obtain channel selection signals. All channels have centering con-trols for nulling offset voltage. Negative -going scope gate signal sernts next channel after each trace. Circuit operates out to 5 MHz.

CHANNELINPUT Fr- 2 MS2

1µF

2 ME2

1 µF11 biF

2 MSH.--MA-7

( 4 )

(31

( 1 )

1 µF( 2 )

2 MS2

0.001µF

FROM OSCILLOSCOPE GATE OUT-I

5 k.c).

1 Id -2

(2)

16

15

13 12 11

FLIP-FLOP

4 5

+5 V

TEXASINSTRUMENTSSN 7473

DECODECONTROL

13

OUTPUTAMP

HA -2405

12

11

10

15 pF

+15 V

TO SCOPE11, INPUT

2 MS2

2 MS2

2 MS2fvV\..2 MS2

(2)

500 kS2

500 kS2

500 ks2

(4)

500 ks2

CENTERINGCONTROL

15 V

47

Controlling op amp gainwith one potentiometerby T. Frank RitterSan Antonio, Texas

A single potentiometer and a few resistors can controlthe gain of an operational amplifier from a selectednegative value, through a null, to its positive open -loopgain. The variable -gain circuit, which is shown in (a),maintains a high input impedance, even at high ampli-fication. It makes a convenient wide -range voltage ref-erence for a voltage regulator because it eliminates theneed to switch the op amp's circuit for above- or below -reference operation.

A graph of voltage gain versus potentiometer rotationis also shown in (a). The equation for output voltagecan be written as:

= [EiRF/(R1+R1)IRRI/R2) -(Ri/RF)1

where R1 is the resistor at the op amp's noninvertinginput, and R1_ the resistor at the inverting input.Varying feedback resistor RF changes the magnitudes ofboth the positive and negative gains without changingthe appearance of the graph; varying resistance ratioRi+/ RI_ shifts the null point.

As resistor R1_ approaches infinity, op amp gainvaries from null to positive infinity only, as illustrated in(b). The equation for output voltage becomes:

E(, = [ERF/(Ri+ +RI)1[(RI /R2) + (RI/ROIAs can be seen from the figure, the gain curve for thiscircuit is nearly logarithmic.

For a potentiometer rotation of 10% to 90%, amplifiergain can be varied over four decades. The gain at 50%rotation is the ratio (Rt +R2)/(Ri+ +RI). Any general-purpose differential op amp can be used in the circuit.E

Wide -range gain adjustment. Potentiometer varies gain of operational amplifier (a) from chosen negative value to positive open -loop value.Null point can be shifted by changing resistance ratio of noninverting input resistor RI* to inverting input resistor R1+. Removing permitspositive gains to be controlled over wide range, as shown in (b). Circuit's input impedance remains high over full gain range.

40

30

20

10

z

0 0

-10

--20

NEGATIVE GAIN

RF

30 I

0 20 4C t i 60NULL

POSITIVE GAIN

J I

80 100

PERCENT ROTATION OF RT

40

20

-20

300

RF

POSITIVE GAIN

'lit20 40 60 80 100

PERCENT ROTATION Of RT

48

Logic driving gates doubleas d -a converter switchesby Amos WilnaiMonolithic Memories Inc., Sunnyvale, Calif.

The design of a weighted -resistor digital -to -analog con-verter can be simplified by using the gate that suppliesthe digital input data as a switch. This approach permitsa high -resolution converter to be built with standardopen -collector logic. With 1% resistors, five -bit resolu-tion is possible; tightening the tolerance to 0.1% canprovide seven -bit resolution on selected units.

A d -a converter (a) usually contains input switches, aresistor network, and an operational amplifier that pro-vides gain and a low -impedance analog voltage output.The digital input data is generally supplied at standardlogic levels-for example, at transistor -transistor -logiclevels or diode -transistor -logic levels. Logic gates driv-ing the converter can therefore be used as its inputswitches (b).

Individually packaged gates, however, limit outputword length to about two to three bits because of themarked gate -to -gate variation in logic low and logichigh output levels. A TIT high, for instance, is guaran-teed to be between 2.4 and 5 volts, while a low lies be-tween 0 and 0.4 V. Output resistance also varies consid-erably from unit to unit. Excellent voltage -level trackingcan, however, be obtained by using gates that share acommon substrate if they are operated under the sameload conditions. A five -bit converter (c) can be builtwith an open collector hex inverter performing the in-put switching function.

When the outputs of the open -collector gates are low,each gate has a load impedance of 500 ohms, and thecollector -emitter saturation voltages of the gate outputtransistors are within millivolts of each other. When theoutputs are high, each output transistor is off and theresistor network is referenced to supply voltage Vcc.

Longer output word lengths can be realized in thesame way by utilizing two hex inverter packages. Theremay be some variation between packages in the lowgate output voltage level, but this can be minimized byselecting the two packages from the same lot (by usingthe date code on the package).

Let gates do the switching. Basic digital -to -analog converter (a) requires input switching network to interface digital input data. Using indi-vidual logic gates (b) to drive and switch converter limits resolution. However, up to five -bit word lengths can be obtained with open -collectorhex inverter (c) as driving and switching network. Because inverters have common substrate, is good.

DIGITALDATA IN

(al

SWITCHES

HIGH LOW

REFERENCE VOLTAGES

DIGITALDATA IN

2

RESISTORNETWORK

GAIN ADJUST

ANALOGOUTPUT

ANALOGOUTPUT

DIGITALDATA IN

HIGH

L74051

-V

ALL RESISTORS: 1/4 W, 1",

ANALOGOUTPUT

49

TTL gates speed uppulse -height analysisby Joseph LaughterUniversity of Tennessee Medical Units, Memphis, Tenn.

Being used mainly for analyzing nuclear energy, deter-mining white -noise amplitude, or counting blood cells,pulse -height analyzers require high-speed performance.They are complicated to design with discrete transistors.But with transistor -transistor logic and integrated com-parators, fast operation can be realized at a fraction ofthe usual cost.

Positive dc voltage E1, is the lower limit for a pulsepassing from input to output, and positive dc voltage Euis its upper limit. At the instant the input pulse risesabove FL, lower -level comparator Al switches to zero,triggering monostable multivibrator OS1. The output ofOS1 returns to zero after about 300 nanoseconds andtriggers monostable OS2, sending a 60-ns pulse to theanti -conic gate. The anti -conic gate inverts the pulseand triggers the output pulse shaper (monostable OS3).

When input pulse height is greater than Eu, compara-tor Al is fired first, and then upper -level comparator A2is fired. Once A2 switches on, the pulse stretcher(monostable OS4) produces a positive pulse that turnsoff the anti -conic gate for 600 ns. Therefore, when thepulse from monostable OS2 appears several nanose-conds later, it is blocked by the anti -conic gate andthere is no output. Throwing the window switch to its"out" positioh disables the anti -conic gate, allowing apulse to reach the output each time the input pulse ex-ceeds the lower -level limit voltage.

This pulse -height analyzer can accept positive pulseshaving a maximum rise time of 250 ns and a maximumrepetition rate of 500,000 pulses per second. The repeti-tion rate can be increased by using lower -value timingcapacitors for delay line OS1, output pulse shaper OS3,and pulse stretcher OS4. However, input rise time re-quirements become more stringent.

The type CMP-01C comparators can be replaced bythe more popular type 710 comparators if the supplyvoltage is changed from ±15 volts to + 12 and -6 v. Al-though the type 710 is considerably cheaper, it does notperform as well in critical applications.

Timing curves show output wave forms for severalimportant points in the circuit. 0

Examining pulse height. Comparators AI and A2 set lower (EL) and upper (Eu) voltage limits. When pulse height exceeds EL, one -shots OS1and OS2 slow down pulse from Al and transmit it to anti -conic gate, which fires output pulse shaper OS3. When input exceeds Eu, AI and A2switch, causing pulse stretcher OS, to turn off gate so that pulse from OS2 cannot reach output. Window switch at "out" disablesgate.

PULSEINPUT

+5 VUPPER LEVEL COMPARATOR

100 NF.1 (10 VI

3.9 kS2Eu

820 pF

PRECISIONMONOLITHICSCMP-01C

INPUT

1.8 kS2

EL3.9 kr2

30 pFI I--15 V

4

s -tr*-+15 V

8 lJ7

ANTI -CONIC GATESHAPER

1.8 kS2 330 pF

STRETCHER

kS2 pFNI(007 WINDOW

SWITCH

11111 I T4 5 14 11 10 4 514 11 10

3 741210S4

6

73 741210S3 6

7400 OUTPUT

11wv.8kS2 H1,270 pF 8 kS2

PF

TT I iTi4 5

3OS,

14 11

74121

10

6

7

4

3

7

5 14 11

74121

10

6OS,

15 V

30 pF

LOWER LEVEL COMPARATOR

Eu- -- -EL EL < INPUT < Eu

A2

OS1

OS2

OS4

GATE

OUTPUT

0 200 400 600

TIME Ins)800 1,000

I

DELAY LINE

EllINPUT E, INPUT> EL, > EL

A, -1A2 -1OS1

OS,

0S4

GATE

OUTPUT

n

0 200 400 600 800 1,000TIME Ins)

50

Analog voltage sensorcontrols LED thresholdby Thomas MazurMotorola Semiconductor Products, Phoenix, Ariz.

Most light -emitting diodes are found in alphanumericdisplays and optically isolated circuits where they areusually controlled, either directly or indirectly, by dig-ital logic systems. Analog LED control circuits can alsobe useful, provided that distinct light/dark LED transi-tions can be obtained. The scanning circuit in the dia-gram employs silicon unilateral switches, which func-tion like four -layer diodes but have a gate control toproduce sharp LED transitions for voltage -level sensingapplications.

There are N circuit sections, depending on the num-ber of voltage levels to be sensed. Each section consistsof a LED, a silicon unilateral switch, a zener diode, abipolar transistor, and two biasing resistors. The unilat-eral switch begins to conduct when its terminal voltagereaches a critical level, nominally 8 volts. Once theswitch is turned on, its terminal voltage decreases to ap-proximately 1 V.

While switch voltage is increasing, the LED and thetransistor's base -emitter junction become forward -biased. LED current, which is limited by the emitter re-sistor, rises until the unilateral switch conducts. Sincethe transistor junction and the LED require around 2 vto be forward -biased, the LED shuts off when the switchvoltage drops to 1 v.

Whether the switches are on or off, the voltage across

the transistors continues to increase with rising inputvoltage. Because the transistors are separated by zenerdiodes, each succeeding section operates only after in-put voltage V1 increases by zener voltage Vz. Therefore,accurate LED turn -on levels (VD) can be set and, withthe switches providing an abrupt turnoff, incrementalcontrol of each LED can be achieved.

Assuming that all the zeners have identical voltageratings:

(Vi)mix = Vz1 + VEB1 VD1

(VI)MAX = NVZ VSwhere VEB is transistor emitter -base junction voltage,and Vs is the critical voltage level of the preceding uni-lateral switch.

The LEDS may be operated sequentially or in an over-lapping fashion by varying the type of zener used ineach section. For a sequential mode:

Vs is less than or equal to Vz + VEB VDFor an overlapping mode:

Vs is greater than or equal to Vz + VEB + VDIn addition, the level of Vs may be reduced by connect-ing a zener diode between a switch's gate and cathodeterminals.

The scanning circuit may be modified to providehighly discernible visual indication by replacing theemitter resistors by constant -current sources. This sup-plies the LEDs with uniform current pulses, allowingeach one to produce a constant light output. Anothermodification permits the circuit to serve as a data trans-fer mechanism-phototransistors can be inserted be-tween the LEDs and the emitter resistors so that theLEDs can be optically modulated.

LED scanning circuit. Silicon unilateral switches SI through SN require 8 volts to trigger, but only 1 V to stay on. Rising input voltage for-

ward -biases transistor 01 and light -emitting diode DI. LED emits light until switch SI conducts; it goes dark abruptly when switch voltagedrops to 1 V. Zener diodes Z1 through ZN establish voltage levels that are sensed by each section of scanning circuit.

10 kr2 2 10 kS2

O.

10kI

D,

A

D2 DNS2 SN

270 SZ 270 270 a

z, Z2

SILICON UNILATERAL SWITCH

ZN

ALL SEMICONDUCTORS MOTOROLA 01 - ON : MPS 6515

SI - SN : MUS 4987DI - Dry : MLED 55

51

Wired -OR DTL gates increasemultiplexer input capacityby Eric G. BreezeFairchild Semiconductor, Mountain View, Calif.

A 10 -input multiplexer can be built by adding only onediode -transistor -logic gate package to an eight -inputmultiplexer that has an open -collector output. Decademultiplexers are not currently available as standard in-tegrated circuits because of the lead constraints of con-ventional dual -in -line packages. Either an eight -inputmultiplexer in a 16 -lead DIP or a 16 -input multiplexer ina 24 -lead DIP can be purchased. And modifying the 16 -input unit is both an expensive and cumbersome way tobuild a decade multiplexer.

Only three DTL gates are needed to add two input bitsto an eight -input multiplexer, provided the multiplexerhas an open -collector output that can be wired -OR likeall standard DTL gates. The decade multiplexer illus-trated makes use of the OR tie facility of the 2 outputof Fairchild's type 9313 eight -input multiplexer.

The most significant bit of the binary -coded -decimalcontrol input is connected to the ENABLE (active low) in-put of the multiplexer and to the inputs of gates 01 andG2. When the most significant control bit is low (codevalue of 0 to 7), the multiplexer operates normally, ac-cepting input bits 0 through 7, and Gi and G2 are dis-abled (their outputs are high).

For BCD input selection codes of 8 or 9, the most sig-nificant control bit is high, the multiplexer is disabled,and input bits 8 and 9 can pass to the output, since bothG1 and 02 are enabled. Gate G3 performs as an in-verter for the least significant control bit into the multi -

LEASTSIGNIFICANTBIT

INPUT BITS

0 1

A II23 4 5 6 7 B9

o_ Ai

A2c0

A3-+

MOSTSIGNIFBIT

ENABLE 10 I, 12 13 14 15 16

SO

S

S2

9313EIGHT INPUT MULTIPLEXER

7

ED.

CD.

cs

ALL CIRCUITS: FAIRCHILD

TTLOUTPUT

WIRED -ORPOINTS

DTLOUTPUT

9962 OR 9963

Two more bits. Binary -coded -decimal input controls selection of in-put bits to decade multiplexer. When most significant bit A3 is low,gates G1 and G2 are disabled, and eight operatesnormally for input bits 0 through 7. For high A3 bit, eight -input multi-plexer is disabled, but G1 and G2 transfer input bits 8 and 9 to output.DTL gates and i output are wired -OR.

plexer to decode input selection code 8.The type 9313 multiplexer contains an inverter stage

after its 2 output, making both TRUE (Z, Tm-compat-ible) and ASSERTION (Z, Dm/TIT-compatible) outputsavailable. 0

Precision integratorresets as it samplesby Dennis J. KnowltonUniversity of Wyoming, Laramie, Wyo.

A circuit that continuously samples the integral of aninput and resets itself achieves an accuracy of within0.1%. Other integrators with this tight an accuracy canbe expensive and complicated because they do not inte-grate continuously but rather require some time tosample and reset.

The integrator shown uses two sample -and -hold cir-

cuits-while one is sampling, the other is holding theprevious integral value. Reset is also continuous-theprevious value of the integral is fed back so that the cir-cuit is continuously reset for the full integration timeperiod. In this way, integration precision is determinedprimarily by hardware and not by technique. Addingan offset adjustment to each of the operational ampli-fiers permits accuracy to be improved by at least an or-der of magnitude.

The integrating section is a simple integrator, com-posed of an op amp having a low input bias current anda feedback capacitor. The sample -and -hold section con-tains complementary MOSFETs. One portion of this sec-tion holds the integral, while the other follows (samples)the output from the integrating section. When the mos-PETS are switched, these roles are interchanged. The

52

741 -type op amps are used in voltage -follower configu-rations to isolate the integrating section from thesample -and -hold section.

The integrator is a true feedback system. If the inte-gration period is 1 second, the integral formed during a1 -second period is fed back to the input during the fol-lowing 1 -second period to reset the integrator. Mean-while, new data is being integrated. The output, then, isthe sum of the new integrated data, plus the old datathat has been integrated back to zero, which simply

yields the integral of the new data. Two timing dia-grams show the circuit's response to a pulse input and toa step input.

Calibration procedure for the integrator is straight-forward. After the feedback circuit is unhooked, resistorR1 is adjusted to obtain the desired slope from the inte-grating section (for example, 1 volt out per second pervolt in). The feedback circuit is then connected again,and resistor R2 is adjusted so that there is no overshootor undershoot to a step input.

Precision integration. Simple integrator can provide accuracy within 0.1% because it continuously integrates input. Output from integratingsection is sampled by one sample -and -hold circuit, while the other holds previous integral and uses it to reset integrator. ComplementaryMOSFETs do the switching. Sample -hold roles reverse every integration period.

INTEGRATING SECTION=NOM 41.

-t5 µF

INPUT II 180 ks2 40k1.2

(± 10 V)T-Alvv-r3180112

308

200 ka

R2

MIN iMM1 MOM 01111=

PULSEINPUT

(A)

OUTPUT

741

741

(A)

SAMPLE -AND HOLD SECTION

2N4351

SQUAREWAVE(0.5 Hz,1.15 V)

3µF

302

2N4352

L

2N4352

T3 µF

302

2N4351

1

J

ALL CAPACITORS: POLYCARBONATE

10STEP 10

-4425°' '-50°°-" INPUT

w 10

5 (A) < 5

4-0 0 0

10

OUTPUT55

0 0

0

TIME (s)

OUTPUT

TIME (s)

53

Wien bridge in notch filtergives 60 dB rejectionby Donald DeKoldUniversity of Florida, Gainesville, Fla.

A modified phase splitter and Wien bridge networkform a notch filter that is capable of providing 60 deci-bels of signal rejection. The bridge network, which con-sists of two capacitors and two resistors, makes this highrejection possible and allows the filter to be tuned withganged capacitors or resistors. The three -capacitor,three -resistor bridge ordinarily used for the twin -T vari-ety of notch filter is not as easy to null because morecomponents must be trimmed, and maximum notchdepth is usually about 45 dB.

Because of the wideband frequency response of itsmodified phase splitter, the filter (a) can operate fromsubaudio frequencies up to hundreds of kilohertz. Forvery -low -frequency performance, however, a direct cou-pling scheme must be worked out.

Unlike a unity -gain phase splitter, the filter's phasesplitter has a gain of approximately -2 at its collector. Ifcollector resistance is small with respect to resistor R ofthe bridge, the ac equivalent circuit of (b) can be drawn.

The voltage transfer function of the equivalent circuitis:

H(s) = Vo(s)/V,(s) = (s2c2R2+ 1)/(s2c2R2+3sCR + 1)where s = jw, with w representing frequency.

This transfer function has a transmission zero at w =1/RC, the center frequency of the notch. At frequenciesabove and below the notch frequency, H(s) approachesunity. Since every R is paired with a C in the expressionfor H(s), the shape of the transfer characteristic cannotbe changed by varying the ratio of R/C. The filter's Q,therefore, is constant for any value of R or C, or at anyfrequency for which the notch is designed.

A practical implementation of the filter is shown in(c), along with its frequency response. Instead of asingle collector resistor, a potentiometer and a series re-sistor are used so that the filter can be adjusted for max-imum signal rejection.

Employing a standard dual ganged variable capacitorfor the bridge capacitors allows the notch to be tunedfrom 8 to 200 kHz. Notch depth may vary because ofimperfect tracking of the capacitors, but will never dropbelow a minimum of 45 dB. Because the filter operatesat a high impedance level, it should be shielded to avoidnoise pickup at the output node.

Effective notch. Non -unity -gain phase splitter and four -element Wein bridge make up notch filter (a) capable of suppressing unwanted sig-nals by 60 decibels. Ganged variable components can be used for bridge R or C, allowing notch to be tuned over broad frequency range.Filter transfer function can be found from equivalent circuit (b). Practical filter (c) has adjustable collector resistance.

F-

(a)

Vi(s)

( b )

0.1 µF

(c)

FREQUENCY (Hz)

10 102 1030

0Z -20

I-

w -40

-60

fo = 174 Hz

104

54

Mu ltivibrator clockobeys digital commandsby Patrick L. McGuireGeneral Dynamics, Electrodynamic division, Pomona, Calif.

A simple variable -frequency multivibrator clock sourcecan be made data -dependent by controlling the currentinto the multivibrator's timing network. When timingresistor values are selected in increments of two (doubl-

ing the preceding value), the relationship between bi-nary input and frequency output is linear within 8%.

Inverters with open -collector outputs act as input buf-fers, providing the necessary pulldown of current fromthe timing resistors. Diodes are added to prevent signalinterference at the inverter outputs.

Circuit output is a square wave having a frequency ofhalf the pulse rate from the multivibrator. Output fre-quency depends on the value of timing capacitor C:

f = 0.049/Cwhere f is in kilohertz and C in microfarads.The graph shows the multiple of f determined by eachinput data word.

Programable clock. Controlling current through multivibrator enables binary input to determine frequency of output square wave. In-put/output relationship is practically linear because values of adjacent timing resistors differ by factor of two. Inverters buffer current fromtiming resistors, while diodes guard against signal interaction between bits. The flip-flop halves output pulse rate from the multivibrator.

LEASTSIGNIFICANTBIT 394(12

BINARYINPUT

MOSTSIGNIFICANTBIT

20 kE2 101<2 4.7 kS-2

2/3 SN7405

ALL ICs: TEXAS INSTRUMENTS

MULTI

Vcc

1N914(ALL)

15 14

1/2 SN74123

13

INPUTDATAWORD

OUTPUTFREQUENCY

0000 15f

0001 14f

0010 13f

0011 12f

0100 11f

0101 10f

0110 9f

0111 8f

1000 7f

1001 6f

1010 5f

1011 4f

1100 3f

1101 2f

1110 f

1111 0

f(in Hz) = 0.049/C On NF)

FLIPFLOP

1/2 SN74107

OUTPUTSQUAREWAVE

55

Op amp with feedbackmakes full -wave rectifierby Richard Knapp and Roger MelenStanford University, Palo Alto, Calif.

A feed -forward resistive element allows one operationalamplifier to do the job of two op amps-perform full -wave rectification of low-level signals. The resulting cir-cuit is useful for a wide variety of frequency -doublingand small -signal rectification applications, such as ac -to -dc converters, absolute -value detectors, and fre-quency multipliers.

For both positive and negative inputs, the op amp'sinverting input is always at virtual ground. And for ei-ther input polarity, output voltage is developed by inputcurrent flow through feedback resistor R1.

Diode D1 is forward -biased during positive inputs,while diode 132 remains off. Input current flows primar-ily through resistor Ri to the output. During negativeinputs, diode D2 conducts and diode D1 is off, main-

Full -wave rectifier. Inverting input of operational amplifier remainsat virtual ground for both positive and negative input voltages so that

output voltage is always developed by input current flow throughfeedback resistor R1. Diode DI conducts only during positive inputs,and diode D2 is on only for negative inputs. Normally, two amplifiersare required to perform full -wave rectification.

taining the op amp's inverting input at virtual ground.Circuit output impedance is approximately equal to

the resistance of diode DI for positive voltages and tothe sum of Ri + R2 for negative voltages.

Gray -code generatoravoids output glitchesby Carl MoserWestern Electric Co., Winston-Salem, N.C.

When binary signals are ANDed together, undesirableWitches can be generated at a circuit's output if one ormore signal transitions are simultaneous. A Gray -codegenerator can be built with six J -K flip-flops that are ar-ranged so that only one signal transition occurs at anyparticular time. Therefore, the four output signals form -

ing the Gray code can be ANDed without glitches.Flip-flops FF1 and FF2 are wired as a Johnson

counter. The Q output or FF1, which is 90° out of phasewith the Q output of FF2, provides the A Gray -codeoutput line. Flip-flop FF3 is toggled by the CT output ofFF2, causing it to produce the B Gray -code output line.

The other three flip-flops, FF4 through FF6, form amodified Johnson counter. FF5 and FF6 are toggledsimultaneously by the Q outputs (labeled X and Y inthe diagram) of FF2 and FF4. Output lines C and D aregenerated by FF5 and FF6, respectively.

Since the circuit is asynchronous, its maximum oper-ating frequency is limited by the delay of the flip-flops.For correct output code generation, all the flip-flopsmust be cleared initially.

OUTPUT GRAY CODE

A BCDI

-o

J

T FF,

K

Q

--c T FF2

K

CLOCK

IX)

CLOCKIIIIIIIIIIIIIIII 1

I (X)

(Y)

J Q JA

-C T F F5 -0 T FF6

K KB

C I I

0

J Q

T FF4

(Y)

FLIP -F LOPS: TEXAS INSTRUMENTS SN7473

J Q

T FE:

K

Stopping glitches. Output lines of Gray -code generator have no si-multaneous signal transitions, permitting them to be ANDed togetherwithout creating glitches. Six flip-flops comprise complete generator.FFi and FF2 are connected as Johnson counter, while FF5 and FF6form modified Johnson counter. FF3 supplies one of the output lines;FF4 is part of simultaneous toggling scheme for FF5 and FF6.

56

Active filter has separateband and frequency controlsby John JenkinsMontgomery, Ala.

The bandwidth and center frequency of an active band-pass filter can be controlled independently by two sepa-rate resistors. Moreover, the filter's gain remains atunity over its full tuning range. Filter Q range is 2 to200, while center frequency is 1 to 10 kilohertz.

The circuit shown in (a) has these properties, but itrequires a variable inductor, which is usually difficult totune, can be large, and cannot provide good tempera-ture stability. The transfer function for this LC filter is:

e0/e; = (s/ReCe)/(g2+s/ReCi + 1/LC1)Replacing the inductor with an active RC network, as

illustrated in (b), yields a temperature -stable circuit. Ifall the components are ideal and R2C2 = R3C3, theequivalent inductance can be expressed as:

Leg = R2C2Re henriesand the 3 -decibel bandwidth as:

BW = 1/(2.7111C1) hertzand the center frequency as:

fo = 1/[277(RfC1R2C2)1/2]HzA wide range of component values can be used in the

circuit, which is easy to design, once the desired filterspecifications are established. As an example, a filterwill be designed with a 5 -Hz bandwidth, a center fre-quency of 1 kHz, and a maximum output voltage of 1volt peak -to -peak. A few important operational ampli-fier specifications must also be known. Typically, inputresistance (Ri) is greater than 40 kilohms, output resis-

tance (R0) is less than 200 ohms, voltage gain (GO ismore than 10,000, and output voltage swing (V0s) ex-ceeds 20 v pk-pk.

To solve the design equations, let:K1 = (ReC1R2C41/2 = 1/(2.iff0) = 1.59 X 10-4K2 = R1C1 = 1/(2.7;BW) = 3.18 x 10-2K3 = (RfCl/R2C2)1/2

[(Vosileomax)2 1]1'2 = 19.98then the filter's time constants can be computed:

R1C1 = K2 = 3.18 x 10-2R2C2 = K1/K3 = 7.96 x 10-6RtC1 = K1K3 = 3.18 x 10-3Rf/Ri = K1K3/K2 = 0.1For most applications, a few simplified guidelines can

be followed to choose component values: resistor R1should be less than 400 kilohms, resistor R2 should liebetween R,2 (about 40 kilohms) and 1 kilohm, the loadresistance should be greater than 1 kilohm, and factor(1 - R3C3/R2C2) should range between 0 and resistanceratio (Re/Re) X 10-2.

This last constraint requires that time constant R2C2track R3C3 within +0% and -0.1%. Therefore, these re-sistors and capacitors must have closely matched tem-perature coefficients and operating temperatures.Metal -film resistors and NPO-type capacitors that aremounted close together can be used. (The R2C2 andR3C3 time constants can be aligned by first opening thefilter's input to obtain maximum Q, then increasing R3until oscillation occurs, and then decreasing R3 until os-cillation just stops.)

A set of typical component values is noted in (b). Asindicated, resistor R1 tunes filter bandwidth, while re-sistor Re adjusts center frequency. 0

Active circuit ousts variable Inductor. Bandpass fPter (a) offers independent center frequency and bandwidth adjustments. Hard -to -tunevariable inductor can be replaced by active circuit (b) that provides an equivalent inductance and better temperature stability. Fully active fil-ter is easy'to design and will operate over a broad range of component values. General-purpose amplifiers can be used.

BANDWIDTHADJUST

(a)

BANDWIDTHADJUST

R

318 kS2

i41

31.8 krz

0.001 p F

C2

FREQUENCYC, = ADJUST

0 1 pF

A2741

H2

7.96 kft

C3I 0.001 pF

7.96 kSl

57

Logic circuit convertssynchronous motor to stepperby Michael D. DoeringFood and Drug Administration, Bureau of Radiological Health, Rockville, Md.

A simple circuit that is compatible with transistor -tran-sistor -logic circuits can convert a two -coil synchronousmotor to a synchronous stepping motor. Since circuitsthat perform this conversion are not available commer-cially, the designer is usually forced to use relays orcome up with his own stepper control circuit.

The problem of conversion generally arises when avariable -speed synchronous motor is needed that is ca-pable of delivering up to 1,800 inch -ounces of torque, orwhen a variable -speed adaptor is required for a motorthat is already installed. The converter, therefore, mustbe a high -current, high -voltage, variable -frequency cir-cuit that can drive a two-phase 115 -volt ac motor.

A variable -frequency square wave, which can be sup-plied by Tri, integrated circuits, drives the converterand establishes motor stepping speed. Motor -speed ac-curacy depends on how accurate the input square -wavefrequency is. The size of the step and the maximumstepping speed are determined by the motor used.

Flip-flops FF1 and FF2 are connected as a repeatingtwo-bit counter, which has its output decoded by anAND -OR -INVERT circuit. This arrangement provides thefour states, which are noted as A, B, C, and D in thediagram, needed to make the motor step properly.

The position of the switch at the output of FF2 deter-mines the direction of rotation. As can be seen from thefigure, the D state simply represents the switch -selectedB or 5 states.

Output states C and D are fed to the inverting inputsof high -power comparators Al and A2, respectively. Thevoltage levels of these two states are then compared tothe reference voltage established by the 5-v supply andzener diode D1. Each comparator drives a separate mo-tor coil and can develop a 75-v 100 -watt output. 0

NUM.INPUTSQUAREWAVE

+5 V

ks2

Q

C FFi

K

7473

+5 V

+5 V

1 kS2 7473

+5 V

Q

FF2

B CCW

CW

7451

X AND -OR -

INVERT

C = A e

RCA HC -2000

+30V 22f2-1/V r--e_JYYY

9 10 10 pH4

Al 3

-30 V

+5V

25011

RCA HC -2000

-30V

A2 3

121.552v22)

49 10 100-I

+30V 22 f2

SUPERIORSS150 P1 RC

ADJUST COMPARATORSUPPLY VOLTAGE TOMATCH MOTOR

Stepping a synchronous motor. Logic circuit plus high -power cornparators step two-phase synchronous motor in clockwise or counterclockwise direction. Frequency of input square wave determinesmotor stepping speed. Two-bit counter formed by flip-flop pair andAND -OR -INVERT circuit produce four logic outputs (A, B, C, and D)that control motor. Each comparator output supplies one motor coil.

Ring counter eliminatesfalse gating signalsby Glen HamiltonDickson, Tenn.

A ring counter that performs reliably at speeds up to 7megahertz can be designed to prevent counting errorscaused by false gating signals. Besides being able to

clock in either direction (up or down), the counter canbe reset from any ring output without losing a clockpulse. Only five dual in -line integrated -circuit packagesare needed-a binary counter, a quad latch, a quadNAND gate, and two BCD -to -decimal decoders.

When the input clock pulse rises to logic 1, the binarycounter is incremented up or down, depending on theposition of switch S1. The unused clock input to the bi-nary counter must be held continuously at logic 1. Formost applications, switch S1 can be eliminated becauseonly one clock direction is required. To switch betweenthe two clock inputs, two gates must be added so that

58

the unused connection is always held at logic 1.With the transition of the input clock pulse from logic

1 to logic 0, the binary counter outputs are loaded intothe latches. The next clock pulse enables the NANDgates, allowing the .45 signals from the latches to pass tothe decoders, which then select the appropriate ringoutput to be enabled. Each succeeding clock pulse se-quentially steps and enables the decoder outputs.

The number of stages in the ring is determined by thering output at which switch S2 is placed to implementthe reset function. When the ring output tapped byswitch S2 is enabled, the binary counter is set to thenumber appearing at its preset input lines. These presetinputs can be either hardwired or made selectable.

For the wiring connections shown, the binary counterhas the binary number six continuously held at its pre-set inputs, and the ring counter's reset function is placedat the fourth output line of the second decoder. Thishookup resets the binary counter to six each time thetwelfth ring output is enabled, causing the ring counterto step sequentially from six to 12 and then repeat, as

indicated by the waveforms in the timing diagram.All ring outputs are disabled (in the logic I state)

when the input clock pulse is logic 0. During this time,the ring outputs are inhibited by the NAND gates to pre-vent false gating due to transients. Also, all ring outputsare always 180° out of phase with the input clock pulse,and a transition from logic 1 to logic 0 is required to re-set the ring counter. This means that the ring counterwill be reset only when the ring output selected byswitch S2 is enabled (in the logic 0 state).

The circuit can also be used as a frequency dividerthat has its output pulse frequency determined by thewidth of the input clock pulse. Any integral divisor,from 2 to 15, can easily be selected by switch S2. The di-vided frequency may be taken from any of the ring out-puts.

The binary counter is provided with CARRY TO andBORROW FROM pins, permitting counters to be cascadedfor generating more than 15 outputs. With two binarycounters, up to 256 outputs can be produced, as long asan appropriate number of decoders is used.

Sure -clocking ring counter. Input clock pulses sequentially step data through binary counter to latches (flip-flops) to NAND gates to BCD -to -decimal decoders. Switch S1 permits clocking up or down, while switch S2 selects number of stages in ring. S2 also carries reset signal that

sets binaiy counter to its preset input number. Counting proceeds only for clock transition from logic 0 to logic 1.

INPUT CLOCK PULSE

PRESETINPUTS

CLOCKPULSE

6

CLOCKDOWN

CLOCKUP

BINARYCOUNTER

B B

DM7563

DM7475

ALL ICs: NATIONAL SEMICONDUCTOR

DM7400

OC

CLEARLOAD(PRESET)

7 -1-19

10

11

12

120nsMIN

A

DECODER

0

1

2

3

4DM7442

6

7

8

RINGOUTPUTS

A 0

DECODER

B 3

DM7442

6

7

8

s,

59

Complementary output stageimproves op -amp responseby Robert Gagnon and Richard KarwoskiRaytheon Co., Equipment division, Sudbury, Mass.

The performance of a conventional 741 -type oper-ational amplifier can be considerably enhanced if it'sgiven a complementary -transistor output stage. The opamp's gain -bandwidth product is extended from itsnormal 1 megahertz to 7.5 MHz for a 250 -ohm load re-sistor, while slew rate is increased from 0.5 to 5 volts/microsecond. Similarly. the full -power bandwidthreaches 50 kilohertz, as opposed to 15 kHz, and thebandwidth at a voltage gain of -2 becomes 2.5 MHz,rather than 330 kHz.

The output stage (a), which contains transistors Qiand Q2, acts as a current buffer, providing extra loaddrive capability. It is basically a bootstrap configurationusing degenerative feedback. Transistor Q2 is the princi-pal source of load current, and the stage's dynamic in-put impedance is the product of the load resistance andthe current amplification factors of both Qi and Q2.

The two outboarded transistors form two comple-mentary pairs with the output transistors inside the opamp-outboarded transistor Qi complements internaltransistor Q3, while Q2 complements Q4. This configu-

ration (b) makes it possible to keep voltage gain inde-pendent of output load conditions and to be determinedby a resistance ratio:

eo/e, = R2/R1where R1 is the load resistance for the op amp, and R2 isthe input resistor to the output stage.

If R2/R1 = 10, the op amp output voltage swingneed only be ± 1 v to realize a circuit output voltageswing of ±-10 v. In practice, a resistance ratio of 6.7, withR1 = 270 ohms, yields the best over-all results becauseof how the op amp responds to this load resistancevalue.

For a load resistance of around 300 ohms, the opamp's maximum output voltage swing is reduced byabout 30%, but its slew rate remains approximately 0.5yips for small voltage excursions. By fixing the gain ofthe output stage at about 10, the slew rate of the over-all circuit is increased by a factor of 10, and the opamp's frequency response is extended.

Undesirable high -order effects of the 741 -type opamp are far enough beyond its nominal 1 -MHz cross-over frequency that instability due to the gain added bythe output stage is not a problem. A 100-kilohm cermetpotentiometer is included in the circuit to permit cancel-lation of crossover effects. It should be adjusted at thefull -power bandwidth limit -50 kHz and a maximumoutput voltage of 20 v peak -to -peak.

Boosting op amp performance. Output stage (a) multiplies op amp slew rate by 10 and extends crossover frequency to 7.5 megahertz. Asshown in (b), external Oi and Q2 complement internal transistors 03 and 04, respectively. Resistor R1 acts as op amp load resist-ance so that resistance ratio R2/R1 fixes overall circuit gain. Additional gain lets op amp operate at low output voltage.

18052

330 sz

500 S-2

ei-AAAi-=

1 al

18052

lal

072N2905

eo

01

2N2219

2.2 NF

2.2 NF

(b)

+v

z 6COMPENSATE0

NORMAL

0 1 1 10

FREQUENCY (MHz)

60

Generator independentlyvaries pulse rate and widthby Mahendra ShahUniv. of Wisconsin, Space Science and Engineering Center, Madison, Wis.

Capacitor charging current can be used to change theoutput frequency of a voltage -controlled pulse gener-ator that also offers an independent control over outputpulse width. The generator's output -pulse frequencycan range from 1 to 75 kilohertz and output pulse widthfrom 100 nanoseconds to 18 seconds. A dual retrig-gerable one-shot performs the actual pulse generation,while an operational amplifier and a couple of transis-tors convert the control voltage into a proportionalcharging current for the frequency timing capacitor.

The voltage divider created by resistors R1 and R2 de-termines the voltage level at the noninverting input ofthe op amp. Since the op amp and emitter -follower Qiform a unity -gain buffer having a high input imped-ance, the large open -loop gain of the op amp keeps thenoninverting input voltage (Vi) equal to the invertinginput voltage (V2):

V1 = V2 = [R2/(R1 + ROW;

and Qi's emitter current becomes:IE1 = V2/12.3

Both V1 and V2 can range between 0 and 2 volts.Transistor Qi has a minimum hFE of 250, making its

base current much smaller than its collector current sothat constant current Tel is maintained nearly equal toconstant current IE1. Because transistor Q2 is also alarge-hFE device, it draws very little base current and al-most all of Ici passes through resistor R4 and diode D1.

Furthermore, the base -emitter voltage of Q2 and theforward voltage drop of D1 are about the same, permit-ting voltage V3 to be written as:

V3 = R4IC1And the constant charging current, 1c2, for timing ca-pacitor C1 can be expressed in terms of voltage

1c2 = R4V1/R3R5One-shot OS1 can be retriggered during its on state

within 100 nanoseconds of the end of the timing period,fixed by its timing components. The positive trigger in-put of OS1 is connected to its Q terminal, and a small ca-pacitive load (C2) is added at the Q terminal to increasethe retriggering delay by about 20 ns.

At the end of OSi's timing cycle, its Q output makes ahigh -to -low transition, and its Q output makes a slightlydelayed low -to -high transition, retriggering OS1 backinto its on state for another timing period. This cycle re-peats at frequency f:

Voltage -variable rep rate. Input control voltage determines output frequency of pulse generator. Collector currents developed by transistorsQl and 02 are directly proportional to control voltage Vi. Constant current IC2 charges timing capacitor C1, controlling pulse frequency ofone-shot OS1, which is retriggered by its own 0 output. OS,'s 0 output triggers one-shot 0S2, which controls output pulse width.

+5 V PULSE -WIDTHCONTROL

0<C3< 1,000O<R6< 60

pF

1(12R4

820(±5%)

DlIN4148

12

R5

8201±5%)

D22N3251

1C2

12

C3

0.022(±10%)

R6100

F17

5.1

kS2

k.12

1900(±10%)

pFR1

10 kit(±1%)

µF

+3

a,2N2484

15 14. 16 6In

1 13 10

CDFAIRCHILDpA741

OS, 0S2-J

6

2-=" 22 12

R2CC 1k&2

(±1%) LC.1

R3

I

820 .12 C2 -330 pF

-5 V

TEXAS INSTRUMENTSSN74123N

OUTPUT

UTPUT

+4.5 VSL110 ..._.1 1.4_1 ps

61

f = 1/(T1 + 60 ns)where T1 is OS1's on -time. One-shot 0S2 is triggered bythe low -to -high transitions of OS1's Q output; thesetransitions generate positive -going pulses at OS2's Qoutput. The width of OS2's output pulses is controlledindependently by resistors R6 and R7 and capacitor C3.

Timing period T1, which is usually much greater than60 ns, is inversely proportional to voltage V1. The cir-cuit's output pulse frequency is almost linearly pro-portional to voltage V1 and, therefore, to control voltage

V1. The graph shows that the pulse generator's fre-quency is practically linear over the control voltagerange of 5 to 22 v (0.45 to 2 V for VI).

Generator frequency range can be extended to higheror lower frequencies by scaling the value of capacitorC1, but this capacitor's charging current, 1C2, should notbe made greater than a few milliamperes. Voltage con-trol of output pulse width can be obtained by replacingresistors 11'6 and R7 with a voltage -controlled constant -current source.

Photodetector senses motionin noisy surroundingsby Richard T. LaubachNational Cash Register Co., Cambridge, Ohio

A digital phototransistor amplifier, consisting of a fewreadily available inexpensive components, can detectslowly moving objects in an electrically noisy environ-ment. The circuit works reliably, even if long cables linkits optical sensing section to its amplifying section.

The circuit detects objects that break the light beambetween the light -emitting diode and the phototransis-tor. When the light beam is interrupted, transistor -out-put voltage V1 increases, causing the potential at pointA to rise until the threshold voltage (about 8 volts) ofinverter II is

Both inverters I1 and 12 then switch, and voltage V2jumps from 0 to 12 v. This voltage jump supplies addi-tional current at point A through feedback resistor Rf,reducing the pull-up resistance seen by the phototran-sistor so that voltage Vi jumps from 8.5 to 11 v when

voltage V2 makes its low -to -high transition.Besides protecting the input of inverter I1, diode D1

isolates point A, allowing the potential at this point torise to 12 v. Without the diode, point A would beclamped at Ifs threshold voltage of 8 v and voltage Viwould never reach 12 V.

Once the circuit is in its high state, transistor voltageVi must drop below 4 v to pull point A below Ifs thres-hold and to switch V2 back to ground. When V1 be-comes less than 4 v, the phototransistor's pull-up resist-ance increases and speeds up the rate of decline of V1.Feedback resistance Rf causes Vi's switching voltagelevels to be different-first 11 v, then 4v-thereby pro-viding 7 v of hysteresis and noise immunity.

Inverter 13 and diode D2 buffer voltage V2, convertingit to a 5-v transistor -transistor -logic signal. If desired,the 12-v output of V2 can be used directly as the logicinput voltage.

The circuit is operating successfully in an electrome-chanical printer where the cable from the phototransis-tor to the amplifier input is a twisted pair of wires 10feet long that run near solenoid driver cables. Movingprinted matter is detected by an existing circuit withoutany output -signal bounce, even though the edge of thematter momentarily stops as it breaks the light beam.

Optical detector. When object breaks LED light beam, phototransistor output voltage V1 increases, switching on inverters I, and 12. VoltageV1 then jumps up because additional current through resistor Fif to point A decreases phototransistor pullup resistance. Voltage V2 stays highuntil V1 drops to 4 V, increasing pullup resistance and causing V2 to return to ground. Inverter 13 converts V2 to TTL-compatible output.

+12 V

43 IcS2

PHOTOTRANSISTOR: TEXAS INSTRUMENTS LS600

LED: TEXAS INSTRUMENTS L23 12 V

11 12, 13: % FAIRCHILD 9109 V2 0

+5 V

62

Quasi -matched MOSFETs formfilterless squaring circuitby W.V. SubbaraoNorth Dakota State University, Fargo, N D

By compensating inexpensive dual -gate MOSFETs sothat they appear matched, a squaring and frequency -doubling circuit can be made to function reliably over abroad frequency range without the aid of a filter. Con-ventional filterless squaring circuits require costly high -quality matched components.

Biasing MOSFETs Qi and Q2 to operate in their deple-tion region causes MOSFET behavior to resemble that ofthe junction field-effect transistor. The drain current(ID) of either Qi or Q2 is given by:

ID = IDss(1 - V6s/Vp)2where IDss is the drain current with both gates shortedto the source terminal, VGs is the voltage betweenshorted gates and the source terminal, and Vp is thepinchoff voltage (the VGS value when ID = 0).

Since Qi and Q2 are not matched, they may, howeverhave about the same Vp value (approximately -1.5volts) but exhibit different IDss values. If Q2's IDss cur-rent is lower than that of Q1, say 3 milliamperes as com-pared to 4 mA, the control gate (G2) of Q2 can be drivenpositive, making Q2 more conductive so that its IDsscurrent is compensated to equal that of Qi. In this way,Qi and Q2 can be made to look matched with the sameIDss and Vp values. The transfer curves show how Q2'scharacteristic tracks Qi's characteristic.

Transistor Q3 functions as a unity -gain stage, trans-ferring input voltage V; to produce voltages Vi and V2,which are equal in magnitude to V, but 180° out ofphase with each other:

V1 = -V2 =Effectively, the input to the main gate (GO of transistorQi is V1, and the input to the main gate of transistor Q2IS -V1. Input voltage V, can then be considered as theVGs voltage for both Qi and Q2.

The MOSFET transfer characteristic can now be usedto solve for the drain current that flows in resistor Rn:

ID1,2 = ID1 1D2 = 2IDSS 2IDSS(Vi/VP)2The output signal voltage contribution can be separatedfrom the output dc offset voltage of 2RDIDss:

V. = 2RDIDss(Vi/Vp)2Letting K = 2RDIDss/Vp2 allows the output voltage tobe written as:

Vo = KVJ2,which is a squaring function.

The value of resistor RD is held to 1 kilohm to preventthe dc offset current of 2IDss from saturating the MOS-FETs when the circuit is operating. Also, peak outputvoltage swing is restricted to about 1 volt to keep fromdriving the MOSFETs away from their optimum mid-point bias condition.

For a sinusoidal input, V. is also a sinusoid at doublethe input frequency and with a voltage gain of approxi-mately 3.5. Resistors R1 and R2 are adjustable so thatthe Qi-Q2 match can be preserved for changing inputsignal conditions. This permits the circuit to operatefrom 200 hertz to 1 megahertz without any distortion. n

Compensated MOSFETs double frequency. Filterless squaring circuit works from 200 hertz to 1 megahertz. MOSFETs 01 and 02 are oper-ated in their depletion mode, causing them to square voltages applied to their main gates (GO. Adjusting control gate (G2) voltage forcesMOSFETs to simulate a matched pair. Unity -gain transistor 03 drives Oi and 02 with equal voltages of opposite polarity (V1 = -V2 - V1).

63

Feedback linearizesresistance bridgeby Robert D. GuytonMississippi State University, State College, Miss.

With the addition of a feedback circuit, the output volt-age of a standard resistance bridge can be made to varylinearly for a change in bridge resistance. The feedbackcircuit provides good sensitivity for a wide range ofbridge resistance variations, while maintaining the full-scale linearity of the bridge output voltage to within0.1%. Furthermore, either an ac or a dc voltage may beused to excite the bridge.

The output voltage of the standard bridge remainszero as long as its four resistance arms are equal to eachother, with a resistance value of R ohms. One arm of

the bridge is variable from this resistance null:= R + AR

where AR represents the change in bridge resistance.For the standard bridge:

V0' = V1(0R)/(2R +AR)This is not a linear relationship, since AR appears in thedenominator. The standard bridge, therefore, is usuallylimited to those applications that involve only small val-ues of AR.

The feedback circuit shown in the figure alters thebridge excitation voltage so that the relationship be-tween the output voltage and OR becomes linear:

Vo = (1 +2Rf/R)V(AR)/ 2RFeedback resistor Rf determines the circuit's sensitivityto the change in bridge resistance. Bridge excitationvoltage can be written as:

V1 = V + RVo/(R + 2Rf)when:

R1 = R2(R+2Rf)/RResistance R can vary from 0 to 2R.

Linearized resistance bridge. Adding feedback circuit to standard resistance bridge allows output voltage V. to be linearly related to vari-ations in bridge resistor Rx. Changes in bridge resistance produce output voltage that is linear to within 0.1%. Circuit sensitivity is set by valueof feedback resistor Pf. Amplifiers control bridge excitation voltage VI, which can be due to either ac or dc source.

R

2.2kI2

Rf

2.2ks-z

R2

lOkE2

301(f.-2

R,

R2

tokn Z 4.31(12

+6V

ALL RESISTORS: ±0.1%OP AMPS: BURR -BROWN 3024/15

5k1-2

5k fl

64

Soldering iron converts toconstant -temperature probeby Mahendra J. ShahUniv. of Wisconsin, Space Science an: Engineering Center, Madison, Wis.

Designing a circuit that has good temperature stabilityrequires pinpointing those components that are the ma-jor drift contributors. These components can then beproperly specified and compensated for temperaturedrift, if necessary. Unfortunately, the designer mustfrequently run temperature stability tests on the entirecircuit because he cannot heat individual componentsselectively. And employing a soldering iron as a selec-tive heat source does not produce precise temperaturetest results.

However, a conventional line -operated soldering ironcan be easily converted into a constant -temperatureprobe. Since most low -power circuits operate very nearambient room temperature and most circuit compo-nents have a low thermal resistance for efficient heattransfer, the device being heated by the probe will bewithin a few degrees of the probe temperature. The driftcontribution of the component can then be measured bynoting the change in the circuit parameter of interest.

The temperature -control circuit in the diagram regu-lates the voltage applied to the tip of a 115 -volt, 27 -watt

soldering iron, allowing tip temperature to be set fromnear room ambient to 125°C. A potentiometer permitsthe temperature setting to be varied continuously. Thetip -temperature -sensing element is a thermistor, whichis installed by drilling a small hole in the tip and thenepoxy -mounting the thermistor in place.

For best results, an isolation transformer should beplaced between the source of line power to the tip andthe triac at the output of the control circuit. The heattransfer of the probe can be improved by using siliconevacuum grease between the tip and the component un-der test.

Sometimes, testing component drift with a constant -temperature probe can reduce parts cost. For instance,suppose a regulated 600-v power supply that contains ahigh -stability zener reference costing about $24 is tested.When the temperature of the whole supply is increasedby approximately 50°C, the supply output drops around5 v.

A transistor junction is found, with the probe, to bethe principal cause of the drift. Substituting a general-purpose zener selling for about $1 for the high -stabilitydevice will decrease over-all supply drift. The tempera-ture -drift errors of the transistor junction and the low-cost zener almost cancel each other, since they haveabout the same magnitude but are of opposite polarity.

It is also possible to build a probe that lowers compo-nent temperature below room ambient by using athermoelectric cooling element in a temperature -controlloop. CI

Pinpointing component drift. Constant -temperature probe can be built by controlling power to tip of soldering iron. Control circuit maintainstip temperature within a few degrees of desired setting, from room ambient to 125°C. Thermistor located inside probe tip acts as the tempera-ture -sensing element. An isolation transformer (not shown) should be placed between the line input and circuit's output triac.

LINE

115/30Vrms

2A

THERMISTOR.F EN EWAL GA45J 1,

50 ka @ 23°C.

2k0

101(C2 TEMPERATUREADJUST

30kE1

320 I.LF

+ (20V)

100k12

10k12.

WI RAMPSLOPE

CONTROL

1.2k1

2N4852

125 pF

(25V)

470k12

2N3646

10052

410--vVV-411

3

14 RCA

9

"1--- 1.2 µ F

(25V1

CA3059

7

loon

4

1052

IN649

2N3646

10052

PROBE TIP

(115-V27-W

IRON)

*INSERT ISOLATION TRANSFORMER

RCA40724TRIAC

PULSE TRANSFORMER

65

Exclusive -OR gate makesbidirectional one-shotby Tim O'TooleTektronix Inc., Beaverton, Ore.

An exclusive -OR gate is an ideal device for building abidirectional one-shot by running the same signal intoboth gate inputs, but putting a time delay on one of theinputs. The gate will then produce a pulse for every ris-ing or falling edge of the input signal, and the width ofthe pulse is determined by the time delay.

In (a), the gate inputs are inverted with respect toeach other so that the gate output is in the high state foreither a high or low input signal. When the input signalswitches from high to low, both gate inputs are low untilthe inverter has a chance to change states. During thistime, the gate output goes low until the inverterswitches and causes the gate output to return to the highstate. This process repeats when the input signalswitches from low to high. Therefore, for every transi-tion of the input signal, the gate puts out a negative -go-ing pulse having a width equal to the delay time of theinverter.

Two inverters can also be used as the delay element,as shown in (b). Now the gate inputs have the same po-larity, causing the gate output to be low for either ahigh or low input signal. The output will be a train ofpositive pulses with a width equal to a single inverter'sdelay time. These output pulses may be easily extendedor stretched by inserting an RC timing network betweenthe two inverters.

Applying the operating principles of circuits (a) and(b) permits the realization of a bidirectional one-shot (c)that has an addressable output pulse polarity. Gates G1and G2 simply duplicate the one-shot of (a) and feedone of the inputs of the exclusive -OR output gate, G3. Aflip-flop, comprised of gates G4 and G5, drives G3'sother input. The polarity of the output pulses is now se-lectable, since the state of the flip-flop controls outputpulse polarity.

If longer or more accurate output pulse widths are re-quired, the delay element in any of the three one -shotscan be changed to a delay line, such as the ones nowavailable in 14- and 16 -pin dual -in -line packages. Thedelay device could even be a standard off -the -shelf one-shot, for example, Texas Instruments' SN74121 or Fair-child's 9601.

Selectable one-shot polarity. Either positive or negative output pulses can be generated by controlling high/low states of inputs to exclu-sive -OR gate. One-shot (a) uses time delay of single inverter to produce negative pulse train. One-shot (b) has additional inverter for positiveoutput pulse train. Bidirectional one-shot (c) has addressable output polarity, which is determined by state of G4 -G5 flip-flop.

lhl

J L

7400

G

1/6 7404

1/6 7404

1 t6 7404

1/4 7486

1

XL

SELECT

7400

G4 )D

G,

7400 1 05 )0

1/4 7486

1/4 7486

-LITT

Jt_f1-7

66

Gated MOSFET acts asmultiplexing switchby Glen CoersTexas Instruments, Dallas, Texas

A four -terminal MOSFET makes a handy series analoggate for time -multiplexing either ac or dc signals. An ar-ray of these MOSFETS can, for instance, be used to gate anumber of voltages that are being monitored period-ically by a chart recorder or a voltmeter, as shown in thefigure. Here, the BCD -to -decimal decoder switches oneMOSFET analog gate at a time for a given interval beforeswitching another.

The decoder outputs are high except for the output

number being decoded. An operational amplifier, con-nected as a comparator, is used to switch each MOSFETon and off. Each comparator's inverting input is set to adc reference voltage of approximately 1.6 volts.

When a logic 0 appears at the selected decoder out-put, the associated comparator's output goes to -14 v.The MOSFET that is tied to the comparator output thenconducts, gating the analog input voltage to the volt-meter or chart recorder. When the decoder output re-turns to logic 1, the comparator output switches to14 v, turning off the MOSFET.

Since MOSFETs are bilateral devices, they can handleboth positive and negative voltages. For this circuit, themaximum input voltage swing is ±-10 v, but can be ex-tended by raising the level of the positive and negativesupply voltages that bias the MOSFET's gate terminal.The multiplexer circuit has good isolation and leakageproperties.

MOSFET gate. Analog signals can be gated selectively by using a BCD -to -decimal decoder to switch array of MOSFETs. All decoder outputsare high, except for the one selected to be the output number. When selected decoder output goes low, output of associated comparatoralso goes low, turning on MOSFET and permitting analog input to pass to circuit's output. Both positive and negative inputs can be gated.

E,

E,

3N16O OR 3N161

3N160 OR 3N161

SN72741

15 V

SN72741

15 V

ALL ICs TEXAS INSTRUMENTS

271,1!

3.3 kl2

3.3k22

VOLT-METER

SN 1442

CHARTRECORDER

INPUTS

BCD -TO -DECIMALDECODER

TO OTHERANALOG GATES

67

Stepper drive circuitboosts motor torqueby E. WolfRedactron Corp., Hauppauge, N.Y.

The output power of a stepping motor can be boostedwhen it's stepping, while the dissipated power during itsdwell (holding) intervals is minimized, by effectivelydoubling the supply voltage of the motor -drive circuitwith capacitor charge. The boosted drive circuit shownis intended for four -phase 28 -volt motors.

During the dwell intervals, the drive circuit suppliesthe pair of motor coils that were energized during theprevious clockwise step. Transistor Qi is on, but con-ducts only leakage current because transistors Q2 andQ3 are off. This permits capacitor Ci to charge to thesupply voltage of 24 v. (Transistors Qi and Q2 form acomplementary Darlington transistor pair.)

The motor's advance sequence is dictated by a pulsestream that increments the motor's winding -sequencecounter and also triggers the monostable multivibratorat the input of the drive circuit. When the Q output ofthis one-shot goes low, its Q output goes high, turningoff transistor Qi and turning on transistors Q2 and Q3.

Since diode D1 is reverse -biased, the potential at Q2'scollector rises to about 24 v, and the capacitor is re-stricted to a discharge path through the motor windings.Therefore, the voltage available for the coil commonlead is nearly two times the supply voltage-or approxi-mately 48 v. With this boosted voltage, motor -windingcurrent rises rapidly to enhance available torque.

Once the current buildup time is over, the one-shotcompletes its timing cycle, turning off transistors Q2 andQ3, while turning on transistor Qi, which is current -lim-ited by resistor R1. Capacitor C1 recharges to the sup-ply -voltage level. This cycle repeats for every steppingpulse.

The timing of the one-shot is not critical. A reason-able timing period would be half of the shortest periodbetween advance pulses.

Stepping up torque. Drive circuit for stepping motor boosts available stepping power without increasing supply voltage. During motor dwell

time, capacitor C1 charges to 24 -volt supply level. When advance pulse triggers one-shot, transistor 01 turns off while transistors 02 and 03

turn on. Coil common voltage then builds to twice the supply level because 02's collector voltage rises by 24 V.

+5 V

470 SZ

1 kS2

4.7 kS2

+5 v 1 kn

+24 V

Q3

2N3566

MOTOROLA

02MJE 1091

CI

D1 I IN4003

COIL COMMON

1001.LF

(35 VI

470 52 0 V MOTOROLA

1 kS2

ADVANCEPULSES

ONE-SHOT

74121

CLOCKWISEENERGIZATION

SEQUENCE

QiMJE 1101

2.2 S2

MOTORCOILA

MOTORCOILB

MOTORCOILC

MOTOFCOILD

STANDARDDRIVE CIRCUIT 0 V

ADVANCE PULSES

ABBC

CDDA +48 V 1iMOTOR COMMON VOLTAGE +24 V fTh

68

Voltage -tuned filter variescenter frequency linearlyby Vassilios J. GeorgiouUniversity of Massachusetts, Amherst, Mass.

Although a voltage -tunable multiple -feedback activefilter generally offers constant gain and constant band-width throughout its tuning range, its tuning curve forcenter frequency versus control voltage is usually highlynonlinear for extended frequencies. This is due to thenonlinearity of the field-effect transistor, which is usedas a variable resistor, and because the center frequencyvaries inversely with the square root of the FET's drain-

source resistance. Employing feedback, therefore, tolinearize the FET'S behavior is not a solution.

Instead, a modified version of the diode function gen-erator can be used to drive the FET'S gate terminal. Forthe voltage -tunable bandpass filter shown, center fre-quency remains nearly linear for changing control volt-

age over a center -frequency range of 4.5:1.Resistor R1 and supply voltage VGG bias the FET at

-3 volts, thereby setting the filter's first breakpoint forVc = 0 at. 1,460 hertz. For negative values of controlvoltage, only diode D1 conducts, and the gain of theamplifier is determined by resistors R2 and R3.

For positive control voltages, diode D2 conducts, andamplifier gain is about half the value it is for negativecontrol voltages. As a result, the lower portion (right-hand side) of the filter's tuning curve tilts upward andaligns with the upper portion (left-hand side) to form alinear characteristic.

Diodes D3 and D4 define the second filter break-point-at Vc = 2.4 v-by further reducing amplifiergain and extending linear operation to 570 Hz. Prefera-bly, the germanium diodes, D1 and D2, should be gold -doped so that they have a low forward -voltage drop. 0

BIBLIOGRAPHYG. Deboo and R. Hedlund, -Automatically Tuned Filter Uses IC Op Amps," EDN/EEE,Feb. 1, 1972, p. 38.

Straight-line tuning. Modified diode function generator (in color) drives FET variable resistor for voltage -tunable bandpass filter, causingcenter frequency to vary linearly with control voltage over 4.5:1 frequency range. Gain of function -generator amplifier is reduced for poditivecontrol voltages to raise lower section of (uncompensated) tuning curve. Compensated filter remains nearly linear.

COMPENSATED

CONTROL VOLTAGE IV)-4 -3 -2 -1 0 1

1 I t 1 1 1 i

-2.5

2.0

-1.5

17;x - 1.0

- 0.5

UNCOMPENSATED

2 3

CONTROLVO1 TAGE V`

-1 -2 -3FET GATE VOLTAGE IV)

GERMANIUM

11.4 Ic12

DI 6.98 k12

6.2 kS1

-6 V

-4

1SIGNAL 6 kS2

VOLTAGE Nil -/%111---.

SILICONIN914

VGG

-7.4 V

R,

13.4 kS2

10 ki-2

:',1(),,),;(), A

OUTPUTVOLTAGE

Vo

69

Temperature -stable decoderfor modulated pulse widthsby H.R. BeurrierBell Telephone Laboratories, Murray Hill, N.J.

Besides offering exceptional temperature stability, apulse -width -modulation decoder for remote propor-tional radio control produces a presettable fail-safeanalog output when the input control signal is inter-rupted. The circuit converts a time -modulated pulse in-put to an analog output.

Transistors Qi and Q2 form a sawtooth generatorwith a ramp output that starts when the input controlsignal goes positive and that resets when the input goesnegative. The control signal switches Q2 alternately onand off.

When the base of Q2 is driven positive by the input,this transistor turns off and capacitor Ci charges withthe constant current supplied by transistor Qi. (Thelonger the input pulse duration, the higher Ci's rampvoltage and the resulting output voltage.) When Q2 isdriven negative, it conducts, pulling its emitter voltagein the negative direction and partially discharging ca-pacitor C1.

Emitter -follower Q3 acts as a peak -voltage detectorthat charges capacitor C2 positively when its base isdriven positive by the ramp voltage of capacitor C1. Ifthe voltage across C1 is too negative to forward -bias thebase -emitter junction of Q3, capacitor C2 dischargesthrough resistor R1. This portion of the circuit, there-fore, acts as a diode peak detector with power gain. Re-sistor R2 and capacitor C3 are connected as a simplefirst -order output filter.

Once the input signal is terminated, the base voltageof transistor Q2 settles to a level determined by the volt-age divider of resistors R3 and R4. This voltage level iscoupled to the output through transistors Q2 and Q3,which are connected as cascaded emitter -followers. Thecomplementary arrangement of Q2 and Q3 causes any

temperature -induced change in the base -emitter voltageof transistor Q2 to be cancelled by an equal -in -magni-tude, but opposite -in -polarity, change in the base -emit-ter voltage of transistor Q3.

The circuit's output voltage is referenced to the lowerpoint of capacitor Ci's charge/discharge cycle. Whenthe input is negative, diode D1 reverse -biases transistorQ2's collector so that capacitor C1 always discharges tothe same level. Diode D2 and resistors R5 and R6 clampthe capacitively coupled input control signal so thattransistor Q2's base is driven slightly negative. Diode D3simply fixes the base voltage of transistor Qi.

With the component values shown, the circuit willconvert a pulse width of 1.25 ±0.63 milliseconds to ananalog output of 2.4 ±0.6 volts dc. The 1-kilohm inputresistor simply reduces the loading on the drivingsource.

1

PULSEINPUT 47µF

+4.8 V

SILICON

ANALOGR2 OUTPUT

(+2.4 V)

3

4.7 /IF

PWM decoder. Circuit detects pulse -width -modulated signals, sup-plying dc analog output over wide operating temperature range. If in-put control signal is interrupted, decoder output goes to preset fail-safe level. Transistors ()land 02 and capacitor C1 make up sawtoothgenerator that drives. transistor 03, which acts as peak -voltage de-tector. 02 and 03 are cascaded complementary emitter-tollowers.

C-MOS sums up tonesfor electronic organby Robert WoodyHercules Inc., Radford, Va.

An electronic organ that produces a wide variety ofvoices, either singly or in combination, can be built withrelatively simple circuitry if complementary-mos logic

circuits and linear diode gates are used. The organ,which requires only one gate for each frequency, addstones to derive the harmonic content of each voice.Sound reproduction varies smoothly, too, so that thereare no unpleasing key clicks.

The circuit shown generates the eight frequencies ofnote A. Adjacent frequencies of the same note have 2:1ratios and are separated by an octave. Similar circuit ar-rangements generate frequencies for notes B through Gand five sharps, for a total of 12 notes. These 12 notes,each having eight frequencies, comprise the 96 fre-quencies in the organ. Individual frequencies are spaced

70

at 6% intervals, from 32.7 to 7,902 hertz.The eight square -wave outputs of the Hartley oscilla-

tor and the binary divider have precise frequencies, butare not musical because square waves contain only thefundamental frequency and odd (not even) harmonics.Furthermore, if these square -wave frequencies areturned on and off directly by key switches, the soundsbegin and end too abruptly to be musically pleasing,and key clicks will be heard.

A diode gating circuit, like the one consisting of diodeD1, resistor R1, and capacitor C1, is used to convert eachsquare wave to a sawtooth. This supplies the even har-monics and helps to turn the tones on and off graduallywithout clicks.

The square wave alternates between the supply volt-age and ground. While the square wave is at ground, D1is forward -biased by current flowing through R1, andthe gate output is also at ground. When the square wave

goes to the supply voltage level, D1 is back -biased sothat current through R1 charges C1, causing the gateoutput to have a rising slope. The capacitor dischargesquickly through the diode when the square wave re-turns to ground, and the cycle repeats.

Resistor R2 and capacitor C2 slow the application ofcurrent to resistor R1, permitting the gate to turn on andoff gradually without clicks. Since C1 charges for halfthe cycle of square -wave frequency f, time constantR1C1 is half the period off, or:

C1 =Values for capacitor C2 are selected to approximate theswitching times of organ pipes. Since the output of eachgate is linearly proportional to its dc biasing voltage, thetone amplitude needed can be metered out precisely.

To sum tones to create the desired organ voices,which comprise several harmonically related tones, eachgate output must be filtered to reduce its harmonics

C-MOS makes organ music. Complementary-MOS ICs add tones to produce eight frequencies that make up note A. Each of the remainingsix notes, B through G, plus five sharps, requires its own Hartley oscillator and binary divider network to generate all 96 organ frequencies.Diode gate at each divider output converts that square wave to a sawtooth to get the necessary even harmonics.

HARTLEYOSCILLATOR

RCA Y,CD4001AE

=JO (A8)

0.0047 pF

60-130 mH

MILLER#6324

10 k12

0.1 µF

RCA CD4004AE

1

12

BINARYDIVIDER

4

ALL DIODES: 1N3064Vim SUPPLY = 10 V

(A7)

(A2)

(AllD1

NW_CI

0 15 )IF

0-30 V KEY BUSES

C2

0.47 µF

Notef

(Hz)C1

(PHC2

(pH

Al 55 0.15 0.47A2 110 0.082 0.33A3 220 0.047 0.22A4 440 0.022 0.22A5 880 0.01 0.22A6 1,760 0.0047 0.22A7 3,520 0.0022 0.22A8 7,040 0.001 0.22

OUTPUT(Volpk-pk

0.082µF

_AAA_OUTPUT

131

56 IcS2

0.33 µF

R2

56 kS2

>):V8 ---0 t,

56 kE2

dc BIAS

164.8 Hz(E3)

AAAAII

ONOFF

dc BIAS

TO OTHER KEY SWITCHES

30 V

71

HARMONIC CONTENT OF SOME TYPICAL ORGAN VOICES

VOICE HARMONIC FREQUENCIES1 2 3 4 5 6 7 8 9 10 11 12

OPEN FLUTE I I m

OPEN FLUTE,OCTAVE HIGHER i

ABOVE FLUTESSOUNDED TOGETHER I a I a

TRUMPET !III'.FRENCH HORN I 1 I

VIOLIN III I I II III a a

STOPPED FLUTE I I I

CLARINET I I I . I . I .

down to the simplest voice produced in the organ,namely the flute. Since the eight frequencies of a noteare multiples or submultiples of each other, they can behandled by one low-pass filter. This means that only 12low-pass filters are needed for all 96 frequencies.

The diodes between the gates and the key switches-diode D2, for instance-allow a given tone to besounded by a number of different key switches. All ofthe key switches indicated are operated by the key fornote Al. The voltages (VI, V2, V3, . . .) on the key busesdetermine the amplitude at which the tones aresounded (V5 controls the fundamental frequency tone,V2 the second harmonic, V3 the third, . . .). The key busvoltages set the harmonic content and, therefore, thevoice of all the keys on the keyboard.

To conserve circuitry, the third harmonic, note A3.borrows a tone from the gate (not shown) used for noteE3. The resulting 0.2 -Hz frequency error cannot beheard.

Transistor gating circuitcuts signal delay to 100 psby Arthur J. MetzTektronix Inc., Beaverton, Ore.

Frequently in emitter -coupled -logic design, a high-speed data signal must be gated by a dc control signalthat is generated by a contact closure or a transistor -transistor -logic gate. When the propagation delay in thehigh-speed signal path must be held to a minimum, asimple transistor circuit can probably provide the fastestway to perform the gating function.

Propagation delay for the transistor gate is as low as100 picoseconds, compared to the I -nanosecond delaysof the fastest integrated -circuit gates presently avail-able. Moreover, the transistor gate consumes less powerand costs less than the lc gate, especially if an addi-tional Ic gate package is needed to perform the gatingfunction.

A typical application for the transistor gate is shownin the figure. Here, signal delay between the flip-flop's(5- output and its D input must be minimized to realizethe fastest possible toggle rate.

With switch Si open, the transistor's base -emitterjunction is reverse -biased. An internal pull -down re-,sistor of about 50 kilohms at the flip-flop's D inputholds all data inputs near ground potential, reverse -biasing the flip-flop's input stage (by more than 3 volts)and assuring the rejection of any signal that passesthrough the internal capacitance of the transistor. Whenthe switch is closed, the transistor saturates and pro-vides a low -impedance signal path. For rrL appli-cations, the function of switch Si is implemented by theappropriate TTL device.

The noise immunity of the gating circuit is main-tained by keeping the transistor's collector -emitter volt-age drop low. (With the type 2N2907A transistor, which

has excellent saturation characteristics, the VcE dropcan be held to approximately 10 millivolts by using aforced beta of 0.1.) Driving several high -impedance in-puts or perhaps one low -impedance input will causesome loss of noise immunity. Although driving a termi-nated line is not recommended, the gate may be drivenfrom a terminated line.

As with any ECL design, care must be taken in layingout the circuit to realize maximum performance. Sincethe fun logic -voltage swing appears at the transistor'sbase terminal, the base biasing resistor should be lo-cated close to that terminal to eliminate themission line effects of an interconnecting lead.

-

Gating ECL signals. Bipolar transistor gate cannals with propagation delay of as little as 100 picoseconds. Withswitch closed, transistor saturates and gates signals from flip-flop's10 output to its D input. When. switch is open, transistor is cut off,and strong reverse bias at D input rejects all unwanted stray signals.The switch can be a pair of contacts or a TTL device.

transfer logic sig-

72

Staircase generatorresists output driftby Maxwell StrangeNASA, Goddard Space Flight Center, Greenbelt, Md.

Tracking capacitors that mutually cancel temperaturedrift make a simple analog staircase generator, which isas accurate and stable as expensive circuits that employprecision digital -to -analog converters. Additionally, thestrictly analog circuitis easier to adjust for any numberof steps and to any step amplitude.

The generator essentially consists of two sections, aone-shot and an integrate -and -hold circuit. The one-shot, which drives the integrate -and -hold circuit, is trig-gered by an oscillator or system clock that determinesthe generator's stepping rate. During the high period(T) of the one -shot's output pulse, integrating capacitor

C1 is charged to produce an output voltage step:AV° = VREFT/RIC1

Between one-shot output pulses, transistor Qi is off, andthe integrator becomes a hold circuit and maintains theoutput constant.

Capacitors C1 and C2 are the two components withthe greatest effect on step height stability. If the sametype of capacitor is used in both the one-shot and theintegrator sections of the circuit, the temperature coeffi-cients of C1 and C2 will cancel. Staircase risetime is pro-portional to capacitor C2, while integrator slope is pro-portional to capacitor C1, so that step height isunaffected by a similar percentage change in both ca-pacitors. The period of the one -shot's output pulse isdirectly proportional to the ratio of C2/C1.

As for the output voltage droop that occurs duringthe integrator's hold mode, the value of C1 must bzlarge enough to keep it negligible over the staircasecycle. For the components shown, output droop is onlyabout 1 millivolt in 10 seconds, and step amplitude isstable within ±0.2% from 0°C to 50°C.

Stepping up. Staircase generator employs one-shot to drive integrate -and -hold circuit. During one-shot period, capacitor C1 charges andsteps up output voltage. When one-shot is off, integrator section holds step height constant. Output voltage droop is kept to 1 millivolt in 10seconds. Step amplitude drift is held to ±0.2% because temperature coefficients of same -type capacitors Ci and C2 cancel.

CLOCK

OVINPUT

0.5V MIN NATIONALLM201

h-T--2 32ms

OV

START/RESET

NATIONALLM208

0.001 NF(FREQUENCYCOMPENSATION/

STAIRCASEOUTPUT

vAv.= 0.500 V/STEP

'1% METAL FILM

"5% COMPOSITION

C, and C2: POLYCARBONATE OR MYLAR

73

Four -ampere power supplycosts just S13 to buildby Joseph EnnisAutomation Industries, Inc., Vitro Laboratories Division, Silver Spring, Md.

The cost of building a regulated power supply can belowered to around $13 if a large capacitor is used tostore energy at a higher voltage than is necessary. Un-der normal operating conditions, the supply, which isprimarily intended for powering a stereo amplifier, candeliver an output of 4 amperes at 20 volts with loadfluctuations down to 18 hertz and with regulation tobetter than 5%.

A high -value capacitor, one measuring tens of thou-sands of microfarads, stores cliarge so that only a smallamount of transformer iron is needed to produce the4-A operating current. The resulting higher -than -re-quired capacitor voltage is then dropped to the desired20-v level with a transistorized series regulator. More-over, two inexpensive incandescent lamp bulbs are usedfor short-circuit protection, rather than a more costlycurrent foldback technique.

With no load at the output, the transformer charges

the capacitor to about 39 v through the diode bridge.The transformer, which has a no-load secondary voltagerating of 28 v ac, can deliver the 4-A operating currentbut will not deliver this voltage under loading becauseof its core and copper losses. Although capacitor voltagemay drop to around 24 v during peak loading, the seriesregulator will continue to provide a smooth 20-v output.

A current of more than 4 A could be controlled by theregulator transistor with the appropriate heat sinking,but the heat sink would cost more than the transistor.The heat -sink area is designed to handle only normalworst -case operating conditions and does not allow forany current foldback dissipation.

Instead, this dissipation is provided by two replace-ment -type automobile lamp bulbs. Besides acting asfuses when there is a short circuit at the output, they re-duce the voltage drop across the regulator transistor,thereby decreasing the power it has to dissipate duringnormal supply operation.

To change the supply's output voltage to 15 v, the23-v zener is replaced by a 17-v one. If a 5-v supply isneeded, a transformer with a secondary voltage lowerthan 28 v should be selected to reduce the voltage dropthat the regulator must handle. A negative -voltage sup-ply can be constructed by substituting complementarytransistor types TIP30 and TIP32 for the type TIP29

and TIP31 transistors.

Economical regulated supply. Parts cost for power supply is pared to absolute minimum by storing energy in 33,000-microfarad capacitor

at higher -than -required voltage level. This allows a fairly lossy, and therefore inexpensive, transformer to be used. Incandescent lamp bulbs

serve as fuses in case of a short circuit and reduce voltage seen by series -regulator transistor. Output is 20 volts at 4 amperes.

TRIADMZ5

$4.35)

115Vac

DIODES: 100-V PI V, 6A(391 EACH)

28 V ac

TOTAL PARTS COST: $13.12

HEAT SINK(241)

33,000µF($2.64)

BULBS: GENERAL ELECTRIC1206 (201 EACH)

GENERALELECTRICZD23

23VIS1 20)

HEAT SINK($1.09)

TEXASINSTRUMENTSTIP29 1291)

TEXAS INSTRUMENTSTIP31 ($1.35)

20 V0-4A

Binary division producesharmonic frequenciesby Donald DeKoldSanta Fe Junior College, Gainesville, Fla.

Harmonically related frequencies-more specifically, afundamental frequency and its first nine overtones-canbe generated with binary division of a blanked pulse

train. The harmonic frequency generator, which consistsof a clock pulse generator, a decade counter, and a fewNOR gates and flip-flops, produces square -wave outputsat frequencies f. through 10f0.

The clock frequency must be 2n times faster than thefrequency of the highest harmonic of interest (n is thenumber of flip-flops used for the binary division).Therefore, to produce the highest harmonic, 10f0 in thiscase, the clock output is simply divided down by 2n. Forall harmonics but the fifth, however, the clock signalmust be properly gated before it can be divided.

To understand why this is so, consider what happens

74

with the ninth harmonic. The uppermost NOR gatepasses and inverts the first nine clock pulses to reach it.But the arrival of the tenth pulse coincides with the arri-val of a high from the decade counter. Since thecounter's output stays high for the full duration of thetenth clock pulse, the gate's output remains low, pre-venting the tenth pulse from propagating. This tenth -pulse rejection occurs every 2nfo times per second.

Clearly, the gate's output pulse frequency is nine -tenths that of the clock frequency, because one pulse isblanked for every ten delivered. The gate's outputwaveform may be regarded as the 2nth overtone of 9f0,but one that is badly distorted with respect to phase.The nine pulses making up a full period of this wave-form are cumulatively advanced in time from theirproper locations as they progress through one completeperiod of the binaryffiovertone of theffifundamental.

This phase distortion can be almost eliminated bysuccessively dividing the gate output by two with flip-flops, as shown in the timing diagram. Waveforms Athrough F illustrate how the blanked space can be madesmaller by flip-flop divisions of 2, 4, 8, and 16. Althoughonly 21/2 cycles of divided -by -16 waveform F are shown,

the reduction of phase distortion is still evident.The proper locations of this waveform's transitions-

those that a true square wave of frequency 9(2n-4)fowould produce if divided in the same way-are denotedby the colored dashed lines. The leftmost switchingedge, which exhibits the largest error, is advanced by18° from the true edge. At any stage of division, themaximum uncertainty in a transition will always be lessthan the period of the clock frequency.

Harmonic frequencies 6f0, 7f0, and 8f0 are developedin much the same way as 9fo. Two clock pulses must beblanked for 8fo, three for 7fo, and four for 6f0. To gener-ate harmonics 5f0, 4f0, 3f0, 2f0, and f0, binary divisions ofharmonics 10fo, 8f0, and 6f0 are performed as indicated.

Complementary-Mos integrated circuits can be usedto build this harmonic generator. If RCA's typeCD4017A decade counter is chosen, the maximumclock frequency is limited to 5 megahertz. (An unuseddual -input NOR gate in RCA'S type CD4001A packagecan be employed as the clock inverter.)

Harmonic generator. Single clock signal can be used to create fundamental frequency f° and its first nine harmonics. Clock frequency canbe divided directly for tenth and fifth harmonics, but other harmonics must be gated to produce appropriately blanked pulse train. (For in-stance, one clock pulse out of ten is blanked by top NOR gate for harmonic 9f..) Flip-flops then divide gated outputs.

CLOCKPULSEGENERATOR

fr1012")f(A)

RCA CD4000A

8

7

5

4

3

2

101

DIVIDE -8Y-2"n F LIP -F LCPS

DIVIDE -BY -2"n FLIP FLOPS

1 2 3 4 5 6 7 8 910

(CLOCK) MUIR If

(GATE) Mil11E11.11f if(÷2)

LE

(-81

(÷ 16)I

-RCA IhCD4002A

DIVIDE -BY -2"n FLIP-FLOPS

ICI

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75

Precision auto tachometersquelches point bounceby James B. YoungCanadian General Electric Ltd., Peterborough, Ont., Canada

A tachometer circuit for automobiles with capacitive -

discharge ignition systems suppresses point bouncewhile measuring motor rpm accurately to within 1%.The circuit, which has an operating temperature rangeof -20°F to 150°F, can also be used as a temperature -compensated ratemeter or to eliminate relay -contactbounce.

Many automobile tachometers do not work properlywith a capacitive -discharge ignition because this type ofsystem employs the breaker points only for triggeringan SCR. The voltage waveform across the breakerpoints, therefore, consists of a series of 14 -volt pulses,rather than the 200-v spikes that exist in the usual ket-tering ignition system.

The tachometer circuit shown is composed of threesections: a relaxation oscillator at the input for pointbounce suppression, a monostable multivibrator forpulse generation, and a buffer for driving a meter.

Unijunction transistor Qi is operated with an emittercurrent that is larger than its valley current so that itwill not turn off after triggering. When the points open,capacitor C1 charges through resistor R1 until Qi fires

(in 0.5 to 0.7 millisecond) and triggers the monostable.The current through R1 keeps Qi on and prevents Cifrom charging until the points close. If the pointsbounce upon closure, they will not be open long enoughto allow C1 to charge and fire Qi again.

For every point opening, the monostable produces apulse having a fixed width and amplitude. Normally,the output stage of the operational amplifier produces anegative saturation voltage. But when a positive triggerfrom the relaxation oscillator is applied through diodeD1, the op -amp's output switches to a positive satura-tion voltage, causing capacitor C2 to charge positivelythrough resistor R2. Capacitor C2 stores the charge untile- is greater than e+, and the op amp switches back toits stable state.

Diode D2 clamps the voltage across C2 to about-0.6 v, while diode D3 provides temperature compensa-tion for changes in D2's junction -voltage drop. Both ofthese diodes should be kept in thermal contact witheach other. Since the op amp is left floating so that itcan be operated from a car's single supply voltage, ithas a small positive output voltage when in its untrig-gered state, making capacitor C3 necessary to decouplethe meter.

Zener diode D4 and resistor R3 regulate the outputagainst supply voltage variations, and the thermistorcompensates for temperature variations in the base -emitter voltage of transitor Q2. If a meter with a full-scale current rating of less than 5 milliamperes is used,the thermistor, as well as transistor Q2 and resistor R.4,can be omitted. 0

Measuring rpm. Intended primarily for automobiles with capacitive -discharge ignitions, tachometer circuit accurate within 1% is immune tobreaker -point contact bounce. When points open, capacitor C1 charges until unijunction transistor 01 fires and triggers one-shot formed byop amp. Point bounce is suppressed because C1 takes 0.7 millisecond to charge before 01 can fire. Circuit can operate from -20°F to 150°F.

r

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SUPPLY: 10-17 V, ±1%

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200 E-2METER(100 mA)

N)50 12

200 S2@ 25°C(THERMONETICS1810)

76

Agc rf threshold detectorprovides fast slewingby Roland J. TurnerAmerican Electronics Communications Corp., Lansdale, Pa.

In both radar and communication systems, an auto-matic -gain -control loop is commonly employed to keepsignal level constant for enhanced signal detection. Assystems become more adaptive, the agc loop must bemore sophisticated, frequently forcing simple circuits toperform multiple functions.

Meeting this demand is an rf threshold detector forthe agc loop in an rf receiver. The detector can processsignals of 1 megahertz to 1 gigahertz with a slew rate ofseveral volts a microsecond. It also permits delayed agcoperation and can perform over a wide range of tem-perature and supply -voltage variations.

Furthermore, below the detection threshold, the sig-nal can be processed linearly in the rf section of the re-ceiver. Above the detection threshold, the output of therf section is rapidly leveled so that such detrimental ef-fects as limiting and hangup cannot occur in subsequenti-f stages. This fast action prevents the receiver from

being desensitized at high signal levels and permits low-level targets to be detected even in the proximity ofheavy clutter.

With the threshold power level (typically 0 to 5 dBm)applied at the detector's rf input, the input voltages ofthe operational amplifier are equalized so that there isno output voltage. For signal levels below the threshold,the op amp's inverting input swings positive, relative tothe noninverting input, and the op -amp output is

clamped by diode D1 near the quiescent bias voltage setby potentiometer R1. This clamp prevents the output ofthe op amp from swinging to the negative supply volt-age and enhances the recovery time of the detector at itsthreshold level.

As soon as the rf input develops 3 millivolts of recti-fied bias voltage across capacitor C1, the detector's out-put goes positive to 1 v, thereby activating the agc loopin which it is installed. Only the differential offset volt-age between the dual Schottky diodes, D2 and D3, is im-pressed across the op amp's differential input. The opamp provides 50 decibels of gain, while Schottky diodeD3 provides automatic temperature stabilization for thedetector. Diodes D4 and D5 are temperature -stabilizedreference diodes that desensitize the detector to powersupply variations.

The rf section of the receiver is gated by switching thevoltage at the detector's gate input from its normal

Closing the loop. Threshold detector for agc loop in rf receiver can handle broadband signals with frequencies of 1 megahertz togigahertz at slew rates as fast as 1 volt/microsecond. Dual Schottky diodes and high -slew -rate op amp account for circuit's speed. Tempera-ture compensation, from 0°C to 60°C, is provided by diodes D2 and D3, while diodes D4 and D5 compensate for supply variations of ±6%.

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77

-10-v bias level to 10 v. This overrides any signal condi-tion, forcing the detector's output to go to 8 vdc andforcing the associated attenuator in the agc loop to itsmaximum attentuation state.

For power levels above the detection threshold, thedetector produces 4.2 v at its output per decibel of inputpower over the operating temperature range of 0°C to60°C. Less than 0.5 dB of loop dynamic range is con-

sumed by the static offset voltage of the transfer func-tion over the same temperature range.

Moreover, the transfer function remains constant andunaffected by ±6% variations in the supply voltages.Less than 0.3 dB of loop dynamic range is consumed bystatic offsets in the transfer function for the same supplyvariations. For signals greater than 2 dB above thres-hold, the detector slew rate exceeds 1 v/ps.

Phase comparatorfor servo loopsby Francis E. AdamsSan Bernadino Microwave Society, Corona, Calif.

An easy -to -build phase comparator offers a number ofadvantages for use with dc servo motors and in voltage-controlled -oscillator loops. The output of the compara-tor is zero for inputs that are in phase, and, unlike theoutput of discriminators, it remains real, even for ex-treme differences in the two input -pulse frequencies.Moreover, the circuit, which is composed of low-cost,readily available ics, can operate at a frequency that islimited only by the type of devices employed.

Both J -K flip-flops, FF1 and FF2, are preset so thattheir Q outputs are at logic 1. After an input pulse atfrequency f1 clocks FF1 and causes its Q output

come logic 0, and an input pulse at frequency f2 clocksFF2 and produces a logic 0 at its Q output, the presetdelay containing three NAND gates resets the flip-flops.The propagation delay time of these NAND gates assuresthat both flip-flops are preset.

The time lapse between FF1 being clocked and FF2being clocked determines the duty cycle of the pulsetrain seen by the algebraic adder. As input pulse fre-quencies f1 and f2 approach each other, this duty cyclebecomes smaller. When the two inputs are in phase

= f2), the duty cycle is zero, except for a narrow con-tribution due to the preset time of the NAND gates,which is usually less than 1 microsecond.

If f1 is greater than f2, there is a positive output cur-rent that is proportional to the phase error. If f2 isgreater than f1, then there is a negative output current,which is also proportional to the phase error. ForG = f2, the output current is zero.

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Comparing pulse frequencies. Phase comparator produces outputthat is proportional to difference between input -pulse frequencies.Output is positive when 11 is greater than f2, zero when fl equals f2,and negative when f1 is less than f2. Duty cycle of signal driving alge-braic adder depends on when flip-flops FF1 and FF2 are clocked. In -

phase inputs result in zero output because duty cycle is zero.

78

Diode switching matricesmake a comebackPoor noise immunity of standard logic gates has restricted diode use,

but cost advantages of matrices now can be realized by constructing

these networks with high -noise -immunity integrated circuits

by Dave Guzeman, Teledyne Semiconductor. Palo Alto, Calif.

O Since the advent of high -noise -immunity logic, diodeswitching matrices are being used more extensively inlogic systems, particularly those for code conversion, be-cause diode gates cost less than standard logic gates.Once a very popular logic building block, the diodeswitching matrix had lost ground because of the poornoise immunity of conventional logic gates.

The two most common 5 -volt logic families, transis-tor -transistor logic (TTL) and diode -transistor logic(DTL), usually experience noise immunity degradationbecause of the voltage drop, about 0.7 v, across a for-ward -conducting diode. Improvement in circuit noiseimmunity becomes important for code conversion ap-plications, such as decimal -to -excess -three encoders.And substituting a simple diode gate for a standard gatecan reduce parts costs-often by a factor of four.

A noise immunity problem arises whenever simplediode gates are driven by conventional TTL or DTL.Since noise immunity voltage for any gate is the differ-ence between the guaranteed input threshold voltageand the gate output voltage, the already narrow 400 -millivolt noise immunity offered by most TTL is easilyexceeded by the additional diode voltage drop.

Noise immunity: problem and solution

Suppose a simple diode AND gate is driven by a stan-dard era, active output gate whose maximum outputvoltage in the logic 0 state is 0.4 v. As shown inFig. 1(a), the forward -biased diode at input A, whichdrops around 0.7 v, makes the logic 0 output voltage(VOL) of the driving gate equal to 1.1 v. Since the guar-anteed input logic 0 threshold of conventional TTL de-vices is 0.8 v, the noise immunity becomes 0.8 - 0.4 =0.4 v, exceeding TTL's 400-mv noise immunity.

Consider the same circuit when high -noise -immunitylogic is used, as indicated in Fig. 1(b). Now, the guaran-teed driving gate Vol, increases to 1.5 v and the guaran-teed input threshold increases to as high as 5 v. Addingthe 0.7-v diode drop to the 1.5-v VoL of the driving gatebrings the output voltage of the diode AND gate to 2.2 v.The worst -case logic 0 noise immunity becomes 5 -2.2 = 2.8 v. Many devices in high -noise -immunity fam-ilies have open -collector or passive pull-up outputswhose guaranteed VOL is 0.5 v. Then noise immunity ofthe diode AND gate is better yet: logic 0 output is 0.5 +0.7 = 1.2 v, and noise immunity is 5 - 1.2 = 3.8 v.

This significant improvement in noise immunity over

that of conventional TTL becomes important for codeconversion applications; for example, decimal -to -ex-cess -three encoders that use keyboard switch inputs.With high -noise -immunity logic, the keyboard switchescan be located remotely from the logic cards, and worst -case noise immunity can be as high as 4.3 v.

The excess -three encoder of Fig. 2(a) consists of 10keyboard switches, four high -noise -immunity dual -in-put NAND gates and several diodes. Essentially, the en-coder uses the same principle as the simple diode ANDgate. As individual keyboard switches are closed, thediodes tied to the supply voltage through pull-up resis-tors become forward -biased. In this case, the diodes arewired to make the input to the NAND gates the comple-ment of the desired excess -three code.

The NAND gates restore the input signal levels for fullnoise immunity in the system. An inhibit line is alsoprovided to block or transfer data from the keyboardswitches into the system logic.

This encoder, however, may present a problem sinceits output becomes 1111, which can be mistaken forsome other number, causing an unwanted output whenthe inhibit line drops low. A more usable circuit is onewhose output goes to 0011, the excess -three code for

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1. Noise Immunity. When conventional TTL gate with active outpudrives diode AND gate (a), noise immunity of TTL driving gate is ex-ceeded because of the diode's forward voltage drop. Using high -noise -immunity logic driving gate (b) solves the problem since itsguaranteed input threshold is 5 V, rather than the 0.8 V of standardTTL. Noise immunity, which is 0.4 V for (a), increases to 2.8 V for (b).

79

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STROBE TELEDYNE302 HD,

2. Excess -three encoding. Diode matrix (a) converts keyboardswitch inputs to complementary excess -three code. NAND gates in-vert the signal and restore signal level. Another arrangement (b)codes the 1111 output, which could be mistaken for another num-ber, to 0011 (excess -three code for zero) whenever strobe line goeslow. Third encoder (c) employs quad latch for interfacing keyboardoutputs with holding register. In this switching matrix, the diodes pro-vide a true, rather than complementary, excess -three output code.

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3. Saving dollars with diodes. Substituting a simple diode gate forstandard logic gates can considerably reduce parts cost-often by a

factor of four. For example, serial NAND gate and inverter (a) ofBCD decoder/counter can be replaced by diode AND gate (b).

zero, rather than 1111. To implement such an encoder,shown in Fig. 2(b), several NAND gates are used to dis-connect all keyboard switches from their commonground and to ground output lines 4 and 8. This corre-sponds to the complement of 0011. Since the NANDgates are open -collector devices, the matrix resistorsserve as pull-ups for the NAND gates, while protectingtheir outputs from being grounded.

Another encoder variation should be implemented if

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the keyboard outputs must be fed into a holding regis-ter, as indicated in Fig. 2(c). Here, the diodes are con-nected within the matrix to provide true excess -threeoutputs, rather than the complementary form. Theseoutputs then drive a quad latch, which consists of fourType D flip-flops. The latch is provided with an enableinput that prevents data from being entered into theflip-flops, except when the enable line is low.

Besides encoder circuitry, diode gates can be used ex-tensively in combinational logic. For example, manycircuits in digital systems use NAND gates followed byinverters. In most instances, this common configurationcan be replaced by a simple diode AND gate, at cost sav-ings as high as four to one. The BCD decoder/counter ofFig. 3(a) provides a typical circuit for diode gate substi-tution. In Fig. 3(b), two diodes and a resistor replace theNAND gate and inverter.

80

Approximating true log outputat high frequenciesNew way to build high -frequency log amplifiers eliminates interstagephase shift by using twin -gain amplifier blocks that consist of aunity -gain non -limiting amplifier and a high -gain limiting amplifier

by Douglas Clifford, Hewlett-Packard Co., Loveland. Colo

0 Many circuit analysis applications, such as those in-volving tuned receivers and spectrum analyzers, requiredisplaying signals with a very broad dynamic range.Signal levels can typically vary from -120 to + 10 deci-bels referred to 1 milliwatt. But to display even a por-tion of such a signal requires some form of compression.Usually the signal is processed by forming a logarithmicfunction of signal level.

A recently developed technique eliminates the objec-tions of poor frequency response above 5 megahertzthat is characteristic of the previously least complicatedmethod, successive limiting. The new design is similarto successive limiting, but it eliminates interstage phaseshift by using twin -gain amplifier blocks to approximatethe log curve as a series of straight lines.

Comparing approximation methods

Successive limiting, or linear approximation, is themost sophisticated of three traditional nonlinear meth-ods, which use progressively more complex compensat-ing circuitry to improve accuracy. The new twin -gainamplifier technique achieves accuracy with no compen-sating circuitry.

The method that requires heaviest compensation em-ploys feedback with a nonlinear element. Generally, atransistor's base -emitter junction is used, since its char-acteristic is exponential.

The second technique, which can achieve equal accu-racy with less compensating circuitry, is also based onan exponential characteristic-that of transistor collectorcurrent. A single, simple transistor amplifier can usuallyprovide exponential gain over a range of more than 20dB. For larger dynamic ranges, transistors must be cas-caded with intervening gain blocks to allow each stageto operate within its range.

The third method, successive limiting, has been themost popular at high frequencies because of its simplic-ity. Successive limiting approximates the logarithmiccurve by summing either the rf signal outputs or the de-tected video signal outputs of a series of linear ampli-fiers that limit at a predetermined level. Figure I illus-trates the circuit and its output characteristic.

Poor frequency response is the main limitation of suc-cessive limiting. At frequencies above 5 MHz, phase shiftbetween stages causes the rf signal components to besummed out of phase, and the logarithmic responsedeteriorates unless delay networks are inserted.

In applications where the log of the rf signal must bedetected before further processing, detectors can beplaced at the output of each amplifier. This solves thephase shift problem, but complicates circuitry and in-creases over-all thermal sensitivity because the detectorsdo not track each other as temperature changes.

A recently developed technique eliminates both the

RF

INPUT

USED WITHSUCCESSIVEDETECTIONLOG AMP

DETECTOR

DELAY

DETECTOR DETECTOR

0 DELAY 410

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OUTPUTDETECTOR

LOG OUTPUT

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1. Successive limiting. Summing the outputs of cascaded limiting amplifiers yields logarithm of input signal. Limited output of each stage isadded to that of previous stage to approximate log curve. Delay networks become necessary when operating above 5 megahertz to compen-sate for phase shift between stages. Optional detectors allow H signal to be detected before additional processing.

81

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2. Double -amplifier log stage. Twin -gain amplifier block (a) can betion. Low -gain (GL) amplifier does not limit input signals, but high-gaiGI, must be unity. Plot (b) shows how eight cascaded stages of twinreflects addition of outputs from both limiting (M) and non -limiting (N)

cascaded to form log amplifier that does not need phase -shift correcn (GH) amplifier does, at limit level VL. For logarithmic output to result-gain amplifiers approximate log curve. Final output voltage, (Vo)(m+H),stages for total signal range of -80 to 0 dBm.

need for multiple detectors and rf phase shift problems.The method is similar to successive limiting, because anumber of identical blocks are used with output charac-teristics that approximate the log curve with a series ofstraight lines.

As shown in Fig. 2(a), the signal is applied simulta-neously to two amplifiers that form a twin -gain circuit.The low -gain (GL) amplifier does not limit an input sig-nal, but the high -gain (GH) amplifier does, limiting it ata voltage level of VL. The relationship between outputvoltage (Vo) and input voltage (V,) can be written as:

V. = V,(GH + GL)when V, is less than VL/GH, and:

Vo = V,GL + VLwhen V, is greater than VL/GH.

If V, is less than VL/(GH + GL)N, the limit level for Ncascaded amplifier blocks, the overall amplifier will belinear. However, when the magnitude of V, causes thehigh -gain amplifiers in each block to limit, the systembecomes nonlinear.

When all the stages are limiting, the output of one isstill the input drive to the next. For M stages driven intolimiting:

(Vo)m = VL( 1 + GL2 + GL3 + . . + GLm-1) + V,GLmCombining N stages of non -limiting blocks and Mstages of limiting blocks gives:

(Vo)(m+/.) = VL( 1 + GL + GL2 + . + m-1) +V,GLm(GH + GL)N

If GL is set to unity, then:(Vo)(m+N) = VLM + V,(GH + 1 )N

The maximum non -limiting gain for N §tages is foundby setting M = 0 and letting Vo = VL:

(GH +1)N = VL/V,or:

N = log(VL/V,)/log (GH +1)Substituting T = M +N, where T is the total number ofgain blocks:

M = T+ log(NYVL)/log(GH + 1)If GH and VL are the same for each block, this equationreduces to:

M = K2 Kilog(V,)where K1 = 1 /log(GH +1)

and K2 = T - Kllog(VL)Since V,(GH + 1)N is greater than or equal to VL:

(Vo)(M+N) = VLM + Vx, for Vx between 0 and VL.This last equation indicates that Vo is proportional to

M, which is in turn related to log(V,), making Vo pro-portional to the log of the input. It should also be notedthat GL must equal unity for the log approximation tohold.

A plot of the two parts of (Vo)(m+N) illustrates thelogarithmic relationship between the output and the in-put. As an example, the graph of Fig. 2(b) results forcascaded twin -gain blocks when M + N = 8, GH + 1 =10 dB, and VL = 0 dB into 50 ohms. Assuming GL = 1and N=0 yields the output of M limiting blocks:

(Vo)m = VLMAnd setting M = 0 and keeping GL = 1 gives the out-put voltage for N non -limiting blocks:

(Vo)N = V,(GH + 1)NThe graph shows the contributions of both (Vo)m and(VO)N for all combinations of M and N. The two outputsare simply added together for a total output voltage.Both output voltage level and input signal range be-come larger with increasing M and decreasing N.

From theory to hardware

A log amplifier with almost any given dynamic rangeand log fidelity can be constructed with twin -gain am-plifier blocks. The fewer the stages used, the more gaineach stage must provide for a given range, and thegreater the deviation from the actual log curve.

The computer printout of Fig. 3 compares an eight -

stage log amplifier to a five -stage one. For both compu-tations, the maximum and minimum errors (differ-ences) between the calculated values of (Vo)(m+N) andthe actual log of V, are printed. Also shown are thecomputed output voltages for inputs from -80 to -10dBm. Output voltage figures are normalized to reflect a1-v output change for a 10 -dB input step.

The calculation for the eight -stage log amplifier, inFig. 3(a), indicates a maximum error of 0.03 v and aminimum error of 0 v when GH = 6.68 dB and VI, = -1dam into 50 ohms. (Here, maximum error represents

82

(a) GAIN DB,LIMIT 76. 68.- 1

MAX ERROR= 3.12457E-02 MIN ERROR= 0DB= -80 VO UT= 1.00247DB= -70 VO UT= 2.00211DB= -60 VO UT= 3.00176DB= -50 VO UT= 4.0014DB= - 40 VO UT= 5.00105DB= - 30 VO UT= 6.0007DB= -20 VO UT= 7. 00035DB= -10 VO UT= 8

(b) GAIN DB,LIMIT 714,-5VMAX= .699427

MAX ERROR= 8. 13584E- 02 MIN EkkOk= 8.99811E-02DB= -80 VOUT= .979577DB= -70 VOU I= 2. 07 618DB= - 60 VO U'1'= 3.00364DB= - 50 VO UT= 3.92999DB= - 40 V0111= 5.01443UB= -30 VO UT= 5.9825508= 20 VO U'1 = 6.9157408= -10 VU UT= 8

3. Computer comparison. Printouts for eight -stage (a) and five -stage (b) twin -gain log amplifiers list normalized (1 V = 10 dB) out-put voltage for inputs from -80 to -10 dBm. Maximum and minimumerrors across this range are computed as difference between calcu-lated (Vo)(m+H) and actual log of V1. Eight -stage amplifier, whoseGH = 6.68 dB and VL = -1 dBm, gives maximum error of 0.03 Vand minimum error of 0 V. Five -stage amplifier, with GH = 14 dBand VL = -5 dBm, provides errors of 0.08 V max and 0.09 V min.

the largest positive deviation from the desired output,and minimum error the largest negative.) Error levelsare higher for the five -stage amplifier, as indicated inFig. 3(b), with GH = 14 dB and VL = -5 dBm into 50ohms. Maximum error becomes 0.08 v, while minimumerror is about 0.09 v, bringing the peak -to -peak error to0.17 v or 1.7 dB.

As can be seen from the circuit equations, the criticaldesign parameters are limit level VL and high gain GH.These quantities are influenced by the desired log rangeand number of stages. A computer program is generallyused to determine them for the dynamic range and logfidelity desired.

One way to implement a twin -gain log amplifier is touse two differential transistor pairs driven in paralleland feeding a common load, as illustrated in Fig. 4(a).Transistors Qi and Q2 form the unity -gain amplifier,while transistors Q3 and Q4 provide a high gain of GHand limit at VL. This design, it should be noted, is com-pletely analogous to the theoretical model. Differentialpairs are used because of the excellent limiting theyprovide when they are overdriven.

The gain of the low -gain amplifier is:GL = RL/(2R1 + 2re,) = RL/(2R2 + 2re) = 1

where R1 = R2, and re° is transistor dynamic emitter re-sistance. High gain GH is determined by:

GH = RO2R3 +20 = RL/(2R4+ 2re)where R3 = RI. Limit level VL is fixed by the peak -to -peak current swing allowed in RL due to the high -gainamplifier:

VL = IRLUsually, GH and VL are found first from a computer

model of the circuit. Actual resistor values can then bedetermined from the equations. Amplifier bandwidth isestablished by components RL, L and C. Transistorsshould be chosen so that amplifier input and output ca -

4. Building a log amp. Two differential pairs (a) drive common loadto realize twin -gain log amplifier. Limit level VL of high -gain (GH) pairis determined by allowable peak -to -peak current through RL. Singletransistor (b) can also be used. When diodes are forward -biased,amplifier gain is GH, and limit level is fixed by current flowing in diodelimiter. For both circuits, low gain GL is unity.

pacitances are small to obtain broadband frequencyperformance.

Another design method, shown in Fig. 4(b), uses thesame amplifier to provide both GL and GH. Diodes Diand D2 are forward -biased for small signal levels sothat:

GH = RIARB 2rb) = RL/(RB+2rb)where R1 = RL, and rb is diode resistance. Low gain GLis obtained through the emitter resistance path:

GL = RL/RI = 1The limit level for the high -gain portion of the ampli-

fier is determined by how much current is flowing in thediode limiter:

VL = 11R2 + 12R3where VL is the peak -to -peak voltage of the limit level.When the signal begins to reverse -bias the diodes, turn-ing them off, the effective transistor emitter resistanceincreases, and gain drops. The final amplifier gain ap-proaches unity.

Test results for this log amplifier configuration verifyits predicted performance. An eight -stage amplifier, forexample, with a nominal operating frequency of 20wiz, provides an 80 -dB input range for signal levelsfrom -80 to 0 dBm. Moreover, its maximum output de-viation from a true log curve is only 0.3 dB. For thistight peak -to -peak ripple performance, the emitter re-sistors must be adjusted to assure that GL = 1 when astage is limited.

83

Doubling op ampsumming powerDesign equations make calculations for non -inverting amplifier inputas simple as those for inverting input so that amplifier efficiencyis maximized when several signals are summed at the same time

by Raymond G. Kostanty, Bendix Corp., Navigation and Control division, Los Angeles, Calif.

111 Summation of multiple signals is a useful circuittechnique whenever more than one signal must be am-plified or attenuated with a single amplifier-for ex-ample, in instruments or avionics equipment. And theversatile operational amplifier makes it possible to sumsimultaneously on both its inverting and non -invertinginputs.

Unfortunately, designers frequently utilize only theinverting input because calculations for the non -invert-ing input are usually tedious. A common practice is touse the inverting input of another amplifier, rather thangoing through the mathematics for the non -inverting in-put of a single stage.

A new set of equations simplifies summation circuitdesign by making the resistors for one input as easy tocalculate as the resistors for the other. Thus, a single opamp may perform as well as two that use only the in-verting input.

Relationships between signal gain, input and feed-back resistors, and input and output voltages are un-complicated for the inverting input, and each can behandled separately. But previously, the non -invertinginput required the solution of simultaneous equations-one equation for each applied input. Although theseequations were only first -order functions, their solutioncould become cumbersome for three or more inputs.

The new equations use up to two grounded resistors-one for each side of the amplifier-to control availableamplifier gain. This technique permits all signal gainsand all input resistors to be calculated without simulta-neous equations and with only simple arithmetic.

Circuit functions are elementary

A few basic assumptions are necessary to minimizeequation complexity. The amplifier, for example, is as-sumed to have infinite gain, infinite input resistance,and zero output resistance. Moreover, each of the am-plifier's inputs is considered to be directly coupled froma low -impedance source resistance.

The equations set the dc resistance from the ampli-fier's inverting input to ground equal to the dc resist-ance from its non -inverting input to ground. This min-imizes output null shift with changing temperature.

Output/input relationships for the fundamental am-plifier configuration of Fig. 1 are easily defined. Let E.be output voltage, E1 an input voltage at the invertingterminal, and EN an input voltage at the non -inverting

terminal. For the inverting amplifier input:E./En = KI1, E0/Ei2 = KI2, and E./EIN = KIN

where K1 represents the desired gain of the signal ap-plied to the inverting input, and subscripts 1 through Ndesignate signal number. For the non -inverting input:

Eo/EN1 = KN1, Eo/EN2 = KN2, and E./ENN = KNNwhere KN is the desired signal gain through the non -in-verting input. Once a convenient value for feedback re-sistor RF is selected, the input resistors can be found:

R11 = R12 = RF/KI2, and RIN = RF/KIN (1)RN1 = RF/KN1, RN2 = RF/KN2, and RNN =

RF/KNN (2)The values of resistors Rs and RA depend on the rela-tionship of the sum of the inverting gains to the sum ofthe non -inverting gains.Let: SKIN = K11 + K12 + + KINand: 1KNN = KN1 KN2 KNNIf: 1 + SKIN is greater than or equal to MKNN (3)then: Rs = 00

EIN

E12

E,,

Rs RF1-"AN-0---"VARINKIN

1/V \

Kit

Kip

EN1

EN2

KN,

Ri2V\/.,

R

v\A,

ENN

KN2

RN1

A/V

1. Double summation. Finding resistor values when signals aresummed at both inverting (I) and non -inverting (N) inputs of op ampcan be.reduced to elementary calculations. Up to N inputs to eitherterminal can be accommodated. Simple equations relate input andoutput voltages to signal gain. Input resistor values depend on RFand signal gain: RIN = RF/KIN, and RNN = RF/KNN. Resistors Rsand RA are determined after comparing gain summations.

84

and: RA = RF/(1 4 -SKIN EKNN) (4)If: 1 + SKIN is less than EKNN (5)then: Rs = RF/(K' - SKIN) (6)and: RA = RF/(1+K' - EKNN) (7)where: K' = RF/Rs + SKIN (8)If Eq. 5 rather than Eq. 3 is satisfied, a minimum valueis arbitrarily assigned to K', which represents the sum ofthe inverting gains:

K' must be greater than or equal to EKNN - 1 (9)

Utilizing the results

Using these equations is not difficult and can be illus-trated by a few examples. Suppose that an amplifiermust be designed for K11 = 1, K12 = 2, KN1 = 0.5, andKN2 = 2; all other inputs are zero. First, a convenientvalue must be chosen for RF. (It should be noted thatthe overall resistance level of the final circuit is pro-portional to RF, and that amplifier offset current limitsthe maximum value of RF.) Selecting an arbitrary RF of50 kilohms allows values of the input resistors to befound with Eqs. 1 and 2:

R11 = 50k/1 = 50 kilohmsR12 = 50k/2 = 25 kilohmsRN1 = 50k/0.5 = 100 kilohmsRN2 = 50k/2 = 25 kilohms

Since SKIN = 3 and EKNN = 2.5, Eq. 3 is satisfied:1 + 3 is greater than or equal to 2.5

so that:Rs = 00

and from Eq. 4:RA = 33.3 kilohms

The final design is illustrated in Fig. 2(a). If signal con-ditions remain the same, but another input, K13 = 3, isadded, input resistor values do not change, and:

R13 = 50k/3 = 16.7 kilohmsBecause Eq. 3 is still satisfied, Rs = 0q but:

RA = 11.1 kilohms

Figure 2(b) shows this completed design.If a non -inverting, rather than inverting, input is

added to the first amplifier example, resistor values,when RF is 50 kilohms, are unchanged for R11, R12, RNI,and RN2. For the new input, KN3 = 3:

RN3 = 50k/3 = 16.7 kilohmsEquation 3 is no longer satisfied, since SKIN = 3 andEKNN = 5.5, but Eq. 5 is:

+ 3 is less than 5.5Now, the minimum value of K' is found from Eq. 9:

K' is greater than or equal to 5.5 - 1 = 4.5Using this value for K', Rs and RA can be computedwith Eqs. 6 and 7, respectively:

Rs = 33.3 kilohmsRA = 00The finished circuit is shown in Fig 2(c). If some of

the non -inverting gains are expected to increase or someof the inverting gains to decrease, a larger value for K',such as 8, would be more appropriate. Resistors Rs andRA then become Rs = 10 kilohms and RA =14.3 kilohms, as indicated in Fig. 2(d).

Modified designs

Given an existing circuit, it is possible to modify itwith the design equations. Suppose non -inverting gainmust be increased by 20% for the amplifier of Fig. 3(a),in which RF = 50 kilohms, R11 = 25 kilohms, R12 = 50kilohms, RNI = 10 kilohms, Rs = 16.7 kilohms, andRA = 25 kilohms. Existing signal gains must be deter-mined first, using Eqs. 1 and 2:

K11 = 50k/25k = 2K12 = 50k/50k = 1KNI = 50k/ 10k = 5

Next, find K' for SKIN = 3. From Eq. 8:K' = 50k/16.7k + 3 = 6

For the modified circuit, KNI must be 20% higher, or:KNI = 5(1.2) = 6

2 V/V

1 V/V

0.5 V/V

2 V/V

16.7 kt23 V/V

2 V/V

1 V/V

0.5 V/V

2 V/V

RF

Rs33.3 kS2

":" 2 V/V

1 V/V

0.5 V/V

2 V/V

3 V/V

2 V/V

1 V/V

0.5 V/V

2 V/V

3 V/V

Rs10 kS2'VVV--25 kft

50 kit.

100 kit

A 14.3 kS2

RF

50 kt2kE2

Id)

E0

2. Amplifier examples. When another inverting input is added to amplifier (a), as in (b), values of existing input resistors are not affected,but RA changes value If non -inverting input is added instead, as in (c), Rs becomes necessary and RA is eliminated. Amplifier (d) is final de-sign for modified version of (c) that can handle increased non -inverting gains or decreased inverting gains.

85

3. Making changes. New design equations are also useful for modifying existing circuits. When non -inverting gain of amplifier (a) is in-creased by 20%, from 5 to 6, resistors to inverting input are unaf-fected. As shown in (b), only RN1 and RA must be changed.

Checking the minimum value for K' with Eq. 9:K' = 6 is greater than or equal to 6 - 1

Since the inequality holds, K' = 6 is satisfactory.The value of Rs does not change because K' and the in-verting signal gains remain the same, but:

RN1 = 50k/6 = 8.33 kilohmsand from Eq. 7:

RA = 50k/(1+ 6 - 6) = 50 kilohmsThe modified amplifier circuit is drawn in Fig. 3(b).

Instead of just a 20% increase, suppose KNI is doubledin value to 10. Since the minimum K' now changes:

1 = 9K' is greater than or equal to 10 -Select K' = 10, then:

RN1 = 50k/10 = 5 kilohmsRs = 50k/(10 - 3) = 7.13 kilohmsRA = 50k/(11 - 10) = 50 kilohmsAll the design equations developed assume that the

impedance of a source resistance is low and can effec-tively be neglected. However, this is not always true. Ifsource resistances are some constant known values, theequations are easily modified. Simply subtract a givensource resistance from the appropriate calculated inputresistor. For example, if RF is 50 kilohms, K11 is 2, andthe source resistance driving E11 is 2 kilohms, then:

R11 = 25k - 2k = 23 kilohms

Ac considerations

Amplifier inputs can also be capacitively coupled.The generalized amplifier configuration of Fig. 4 showsboth ac and dc circuit elements and parameters. (Ofcourse, subscript AC denotes an ac element or signal,while subscript DC is for a dc element or signal.)

Although the equations used thus far involve only dcquantities, ac signal analysis parallels the dc. Ac out-put/input relationships, for instance, are the same asthose for a dc signal:

EDCIN

EDCI2

EDCI1

EACIN

EACI2

EACI1

EACN1

EACN2

EACNN

EDCN1

EDCN2

E DCNN

4. Generalized amplifier. For complete design analysis, both ac(AC) and dc (DC) elements and signals must be taken into account.Dc relationships are simply those developed for amplifier of Fig. 1.And ac solutions for signal gain and input resistors are identical, butinvolve ac quantities. Since computing RsAc and Rpm! requires bothac and dc parameters, dc solution should always be found fir$t.

E./EACIN = KACIN and Ea/EACNN = KACNNAnd input resistor computations are also equivalent:

RACIN = RF/KACIN and RACNN = RF/KACNNThe values for resistors RSAC and RAAC, however, de-pend on both ac and dc signal conditions.If: 1 + EKDCIN + EKAciN is greater than or

equal to EKDCNN + EICACNNthen: RsAc = 00and: (RADcRAAc)/(11.Apc + R AAc) = RF/

(1 + EKDCIN +EKACIN -21(DcNN - EKACNN)

If: 1 + EKDCIN + XKACIN is less thanEKDcNN + EKACNN

(RSACRSDC)/(RSAC + R spc) = RF/(K'Ac - /KDCIN IKACIN)

and: (RAACRADC)/(RAAC +RADC) = RF/11 K'AC - IEKDC NN+EKAcNNA

where: K'AC = RF/RSDC EKDCIN +RF/RsAc EICACIN

And the minimum value for K'Ac becomes:K'Ac is greater than or equal to

EKDcNN +EKACNN - IWhen using these equations to analyze a circuit, the dcproperties must be calculated before tackling any acproblems. Of course, the dc input resistors and RSDCand RADC are computed with Eqs. 1 through 9.

A few practical circuit considerations should also beremembered. Signal frequencies applied to capacitiveinputs should be at least 100 times greater than themaximum frequency on the direct inputs so that capaci-tors C1 and C2 can properly isolate frequency bands.And time constants CiRsAc and C2RAAC, as well as thetime constant formed by each input capacitor with itsinput resistor, should be about 0.l/6.28fac seconds,where fa,. is the lowest frequency on any of the capaci-tive inputs. El

then:

86

One-shot timing performance:don't take it for grantedStudy of industry standard monostable multivibrator-the 9601 -type of one-shot-reveals that vendor -to -vendor variations intiming accuracy are wide enough to prevent device interchangeability

by David E. Green, Honeywell Information Systems Inc. Billerica, Mass.

All too often, designers presume that a component'sdata sheet is precise. Inaccurate performance specifica-tions are not intentional misrepresentations on the partof the manufacturer. Instead, they result from problemsinherent in processing techniques, device geometries, orpackaging effects. But, no matter what its cause, exces-sive performance variations-particularly those of so-called building blocks that can be used in a number ofapplications and that are readily available off -the -shelffrom several manufacturers-must be brought to the de-signer's attention.

Consider, for example, the industry standard re-triggerable monostable multivibrator, typified by the9601. A recent study of a dozen sample lots of theseone -shots from several different companies shows thatthe variations in output pulse width are so severe-sometimes approaching 60%-that some manufacturersare re-evaluating their current designs, whereas othersare already in the process of redesign.

Timing errors become especially significant for smallvalues of timing capacitance. For instance, the one -shot's minimum true output pulse is specified to have amaximum value of 65 nanoseconds, but approximateextremes of 30 and 92 ns were observed.

Examining the problem

Pulse width variation for the monostable is specifiedat a minimum of 3.08 microseconds and a maximum of3.76 ps about a nominal output of 3.42 µs. Or, in -specifi-cation variations of timing accuracy can be thought ofas ± 10%. Therefore, after accounting for timing resistorand timing capacitor tolerances, as well as supply volt-age variations, the designer must deal with an overalltiming limit tolerance of ± 15% to ±20%, making any ad-ditional one-shot timing inaccuracies difficult to handle.

Adding a trimmer potentiometer is the simplest wayto compensate for this wide tolerance spread, or evenpoor one-shot timing-but an acceptable trimmer is

vcc

cx

c,10 )FT,

2

INPUT 9601

13

8

6

1 02.110 pF

vcc

4 ki21N4524

1 5 pF

35 V

15 pF 24

2N709

13 pF

4 IcS2

vcc

1N4524

- 5 pF

15 pF Z 241,1.2

2N709

13 pF

50 ns MAX

1N3064

0 1.5 V

1.5 V

>1N3064

OUTPUT PULSE -01WIDTH

- - - V

14-OUTPUT PULSE-01WIDTH

1. Testing the one-shot. Test circuit for retriggerable monostable multivibrator employs unit TTL load on each output.Timing network formedby Rx and Cx determines output pulse width at Q and Q. Capacitors C1 and C2 are fixed at 10 picofarads (including stray capacitance andfixture capacitance), and minimum Cx is held to 5 pF. Output pulse width is measured at device's low-level logic threshold.

87

SAMPLELOT

1

2

3 \

6

7

8

- E

- 1C

- 15

I

I

II

I

ns

A

/111

/ 1

/1

I

1

1

1

ft eft

Se.

44Zes.).7,...1ftr.

378 ns 29 Ais

Ja"

MEAN PULSE WIDTH.20 las

Rx 4 k 50 kS2 4 k1,1 34 k!...! 50 kSZ

C. 5 pF 5 pF 1,600 pF 500 pF 500 pF

3 vs 23.97

34 1(2

1,600 pF

50 ksz

1,600 pF

2.PlodIng the results.Pulse width variations of over 500 9601 -type one -shots are shown as percentage deviation frommean pulse width (77)for entire group. Test points for 12 sample lots are plotted individually. Values noted for Rx and Cx are those used to obtain indicated meanpulse widths from 68 ns to 24 ps. Scattered distribution of results indicates significant discrepancy between actual and specified timing per-formance Also, output pulse variations from one vendor to next are so great that parts cannot be used interchangably.

88

generally more expensive than the multivibrator itself.And for most printed circuit boards, no provision ismade for adding a trimmer at some later date if a prob-lem arises.

Specified one-shot timing accuracy implies that thepart holds pulse -width variations to -±-1 0% for outputsabove and below the nominal 3.4 -us value. However,extensive testing of over 500 of these multivibratorsshows that this is not true. The study notes the variationin output pulse width for 12 sample lots of 9601 -typeone -shots from a number of different vendors.

The test circuit used is illustrated in Fig. 1. Stray ca-pacitance and capacitance from the test fixture are rep-resented by capacitors C1 and C2. The total value forSach of these capacitors is fixed at 10 picofarads to per-mit the use of a variety of test fixtures. Timing capaci-tance Cx is held to a minimum value of 5 pF since theminimum data sheet value of 0 pF is not really achie-vable in practice.

Both Q and Q outputs are terminated with a unittransistor -transistor logic load and a 15-pF load capaci-tor that includes probe capacitance. (In this case, a unitload is the equivalent of a standard TTL gate that re-quires the one-shot to supply 60 microamperes for itshigh output and to sink 1.4 milliamperes for its low out-put.)

All pulse widths for the study were measured atthe low-level logic threshold of the Q output.

The graph of Fig. 2 summarizes test results by scom-paring the mean pulse width for each sample lot (x) tothe mean pulse width for all the units tested 01). Finalvalues of 31 are indicated along the horizontal axis,showing the mean pulse width obtained for the timingcomponents used. For every combination of timingcomponent values, there is a set of 12 data points, eachpoint representing the percentage deviation of meanpulse width z for a given vendor from the group meanwidth of TE, which ranges from 68 ns to 24 its.

Analyzing test results

Several observations can be made from the graph.For instance, the data point at 2.29 us, near the stan-dard test point of 3.4 us, suggests that the number ofunits meeting specification is not very high since devia-tions from z are significant. Also the ±10% toleranceband is drastically exceeded for several pulse widths, in-dicating a serious discrepancy from predicted perform-ance.

For some sample lots, output pulse width divergesfrom its specified value as pulse width increases, eventhough published timing data states that the outputwidth should be linearly related to timing componentvalues when Cx is greater than 1,000 pF.

In addition, for narrow output pulses, performancetracking from vendor to vendor is particularly poor,with a highly undesirable broad distribution of datapoints. A user changing vendors would encounter sig-nificant timing performance differences, especially sincethe plot deals only with deviation from a mean, anddoes not show worst -case errors. For example, whenRx = 50 kilohms and Cx = 5 pF, supposedly identicaldevices from vendor 6 and vendor 12 can generatepulses ranging from 237 to 732 ns in width.

Published timing dataThe expected output pulse width of the widely used9601 type of monostable multivibrator is easily deter-mined from its data sheet. Generally, how the unit'stiming is computed depends on the value of timing ca-.pacitance Cx. When Cx is greater than 1,000 pico-farads, output pulse width can be computed:

T = 0.32RxCx(1 + 0.7/Rx)where T is in nanoseconds, timing resistance Rx inkilohms, and Cx in picofarads. For Cx values of lessthan 1,000 pF, manufacturer's timing curves, likethose shown, must be used.

lo'

1103H

A

a_

H102

3H

10

Rx = 50 kitRx = 30 ki-ZRx = 20 k S."2

Rx = 10 k2Rx = 5 kg2

1 1 I 1 I

10 102TIMING CAPACITANCE, Cx (pE)

10

A singular advantage to testing pulse width is theability to select those vendors whose products fallwithin the desired tolerance of ±-10% over the full tim-ing range. One-shot timing should be monitored for allpulse widths of interest by using permissible combina-tions of Rx, between 5 and 50 kilohms, and Cx, up to1,000 pF.

As this study decidedly points out, in -spec perform-ance at one pulse width does not imply across-the-boardin -spec performance. One vendor's products, for in-stance, exhibited unorthodox characteristics eventhough the one -shots passed the standard 3.4 -us ± 10%pulse width test for Rx = 10 kilohms and Cx = 1,000pF. Some devices displayed a variation of ±40% arounda 68-ns mean pulse width, while others could not gener-ate pulses wider than 3.5 us under any conditions.

Once the vendors whose products track together areselected, additional testing should still be done for abso-lute certainty of timing performance. To virtually elimi-nate any excessively inaccurate one -shots, the testsshould fix the allowable ± 10% timing tolerance as the 3climit of a Gaussian distribution of test results. Based onthe graph of Fig. 2, the recommended pulse widths andtiming networks are: 85 ns ±10%, 5 kilohms and 5 pF;380 ns ±-10%, 50 kilohms and 5 pF; 3.4 us ± 10%, 10kilohms and 1,000 pF; and 17 us ± 10%, 50 kilohms and1,000 pF. 0

89

Active resonators save stepsin designing active filtersResonator model allows active filter sections to be treated as

common components, side-stepping design details that bog down analysis;the model employs a simulated inductance that remains inherently lossless

by Randy Brandt, Integrated Electronics Inc., Los Gatos, Calif.

Active filters make possible the realization of inex-pensive high -Q networks at low frequencies. Passive fil-ters, on the other hand, tend to become costly, lossy,and unwieldy in physical size when large inductancesare required. Since active filters simulate inductance,extremely large values can be realized while holdingdown filter cost, losses, and size. Furthermore, the ever-decreasing price of today's monolithic operational am-plifier, the heart of any active filter, is constantly im-proving the attractiveness of building an active, ratherthan passive, filter.

However, because of the proliferation of active filteranalysis techniques, only a core of full-time design spe-cialists can differentiate between the merits of variousapproaches and select the optimum solution. The occa-sional filter designer finds it easier to build a passive cir-cuit, despite the advantages of the active approach.

But a basic building block, called the active resona-tor, allows even the occasional filter designer to handlean active filter as an ordinary circuit component. Thisactive resonator model is common to all active filter sec-tions. It consists of a tuned RLC circuit for resonanceand an op amp for the necessary gain and isolation.

Modeling the active resonator

An active filter section, regardless of how many am-plifiers it contains, is the fundamental repetitive portionof a complete active filter. Generally, the active filtersection can perform as a filter itself or be cascaded to re-alize higher -order filter functions. The term "activeresonator" is simply another label for active filter sec-tion. With varying degrees of difficulty, any active filtercan be reduced to active resonator form.

Because of its utility and simplicity, a sound choicefor demonstrating how to form an active resonatormodel is the popular biquad active filter. This filter isparticularly noted for its insensitivity to variations incomponent values. When it has three amplifiers, asshown in Fig. 1(a), the biquad filter provides both low-pass and bandpass outputs. By adding a fourth sum-ming amplifier, the circuit can supply a high-pass, all -pass, or notch output.'

The network's transfer function between its band-pass output, (V.)Bp, and its low-pass output, (VOLp, isthat of a non -inverting integrator:

(Vo)Lp/(Vo)Bp = 1 /sR'C'

where s is the Laplace variable. Feedback current is:

it = (Vo)Lp/Rf = (Vo)Bp/sR'RfC'

Solving for the equivalent impedance of the loop withthese two equations gives:

ZL = (Vo)Bp/if =

showing ZL to be inductive in nature. Therefore, ampli-fiers A2 and A3, and feedback resistor 111 can be re-plAced with the equivalent inductance:

L = R'RfC'(I)

connected in a negative feedback loop around ampliferAl. Now the general form of the active resonator can bedrawn as depicted in Fig. 1(b).

Identifying equivalent inductance L is the key to de-riving the active resonator model. Once L is defined interms of existing components in an active filter section,

1. Resonator model. Biquad filter section (a) can oe reduced to ac-tive resonator model (b) by replacing amplifiers A2 and A3 withequivalent inductance L. This simulates L with non -inverting integra-tor in negative feedback loop, but other techniques can be used.Very high but lossless inductances can be realized. Single -amplifierresonator can be treated as complete filter section.

90

the active resonator model can be used to represent thatparticular active filter section.

Since L is known for the three -amplifier biquad net-work, it can be handled as a single -amplifier circuit.This reduces analysis complexity and allows the de-signer to concentrate on his over-all filter requirementswithout being unduly concerned with the details of eachfilter section.

For the biquad filter, inductance L may be simulatedin several ways by using different non -inverting integra-tors in a negative feedback loop around an operationalamplifier.2 Of course, any other technique for simu-lating a stable inductance is also suitable for the biquadnetwork or whatever filter section is being modeled asan active resonator.

Because L is simulated, its inductance can be verylarge and yet remain absolutely lossless if ideal ampli-fiers are used. Although ideal operational amplifiers arefictitious, practical op amps can approach the ideal sothat inductance L stays virtually pure (lossless). This istrue whenever resistance into the summing junction isan order of magnitude less than the amplifier open-loopinput impedance, and when the gain of the feedbackloop is high enough to prevent open -loop rolloff fromaffecting desired Q.

Therefore, assuming that loop gain and amplifier in-put impedance are sufficiently large, the only lossy ele-ment in the network is the parallel resistor, RQ. It can beregarded as the Q -setting resistor, even though theproduct of RQC really determines the 3 -decibel band-width, and both the RQC and the LC products establishthe Q of the active resonator.

Matching the transfer function

The transfer function of the resonator's tuned circuitmust be identical to that of its passive counterpart. Forthe entire resonator of Fig. 1(b):

Vo/V, = s/R,C(s2 + s/RQC + 1 /LC)Analyzing this function in the complex s -plane yieldsthe graph of Fig. 2(a). The location of the complex -con-jugate pair of poles is determined by the roots of thedenominator, while the positions of two transmissionzeros (roots of the numerator) are fixed at frequencies ofzero and infinity.

This means that the logarithmic magnitude responsehas a bandpass characteristic with a shape as illustratedin Fig. 2(b). The slope of each curve in the vicinity ofresonant frequency fc, is a function of Q. The slope awayfrom resonance is eventually 6 dB per octave because ofthe zeros that are located at zero and infinity.

The transfer function of a passive parallel RLC net-work can be written as:

G(s) = hs/(s2 + /as + co02)where h is the attenuation factor of the network, andOw = wo/Q. Comparing the coefficients of G(s) to thecoefficients of Vo/V, for the active resonator yields:

coo = 1 /(LC)1/2 (2)and:

Aw = 1 /RQC or Q = cooRgC (3)and:

h = 1 /R,CThe magnitude response of G(s) reaches a maximum

at w = coo, and the 3 -dB bandwidth is determined by the

la)

40

SE, 20

CD

IW

Omsplane

RESONANCE

-20-

SLOPE = 6dB/OCTAVE

I

Q = 0 - 100Q = 0 - 100= 0 - 1

0-01

(b 1 FREQUENCY (Hz)

a

100 fo

2. Resonator response. Characteristic behavior of active resonatoris identical to that of tuned RLC circuit. Pole -zero plot (a) illustratesbandpass nature of resonator transfer function-there are two com-plex -conjugate poles and two zeros. Magnitude of pole vector isfixed by radian center frequency wo, while vector direction is functionof 0. Slope of resonator magnitude response (b) depends on Q near

resonance and then becomes a constant value.

zw coefficient of s in the denominator. At w = coo, re-sponse magnitude becomes:

A(coo) = h/AcoFor the active resonator, the response magnitude at coois found by substituting h = 1 /RiC and Au) = 1 /RQC inthis last equation. Then:

A(w.) = RQ/R, (4)Since the impedance, at resonance, of a parallel

tuned LC network with lossless inductors is infinite, theclosed -loop gain of the active resonator at resonance issimply equal to a resistance ratio. The active resonator,then, has all the properties of a parallel RLC networkand can be described in familiar terms once inductanceL is identified.

Designing with the resonator

The placement of poles and zeros in the complex -frequency plane fully defines the shape of a filter's re-sponse. Furthermore, the locations of these poles andzeros are determined strictly by the Q and coo of thetransfer function. And since Q and coo are known for theactive resonator, complete active filter networks cannow be designed.

In general, filter design with either active or passivesections is a matter of obtaining the best curve fit over aband of frequencies for a given set of specifications. Thedesigner usually begins by searching through tables or

91

Bandpass transformationsThe appropriate low-pass approximation' function fortransforming to a second -order bandpass function has asingle pair of complex -conjugate poles in the left-hands -plane. To transform fourth -order functions, the trans-formation equations for the second -order functions areused twice.

Transforming each low-pass complex -conjugate pole(a) into its bandpass equivalent requires six parameters:the over-all Q of the bandpass filter at its center fre-quency (0.), the bandpass center frequency (f0), and thereal and imaginary parts of the two low-pass poles.

Since the vectors drawn from the origin to the poles in(a) are defined in terms of 0 and f0, it is convenient towrite the transforms with Q and fo as dependent vari-ables. As shown in (b), the low-pass complex -conjugatepole pair transforms into the bandpass plane as two pairsof complex -conjugate poles and two pairs of zeros.

The bandpass pole Qs are identical, and the center fre-quencies are geometrically symmetrical about the centerfrequency of the over-all filter. The zero pairs are locatedat co = 0 and (.,) = 00, thereby establishing the bandpass

character. Further, for each pair of complex -conjugatepoles and each pair of zeros, there is a filter section with

and f, given by the Q and fo of the transformed polepair.

The bandpass 0 transformation for a low-pass com-plex -conjugate pole pair can be written as:

ry (r2y2+ 8ry - 16y 16) 1/21 1/28y

Here, y is defined as:y = (Re/0.)2

where Re is the real part of the low-pass pole pair, and 0,is the cutoff -frequency Q. And r is defined as:

r = 1 + (1m/Fle)2where lm is the imaginary part of the low-pass pole pair.The f, transformation is:

00% = [Opy1/2 (Qp2y 1 )1/2]f000% = foi [Oy1/2 (Qp2y 1)1/2]

where (f0')1 and (f0')2 are the resonant frequencies of thebandpass filter sections, and fo is the resonant frequencyof the low-pass filter.

BANDPASS

0= secla

( b)

DOUBLEZERO

by using a computer program to find the mathematicalfunction that most closely approximates his require-ments. In doing so, he may select any one or a combina-tion of such well-known functions as Butterworth,Chebyshev, or Bessel.

Once the function or functions are chosen, the de-signer decides on the order of the filter, based on char-acteristics such as shape, minimum stopband attenua-tion, maximum passband ripple, group delay, andphase response. The order of a filter function fixes thenumber of sections needed for a given response. Andthe coefficients of the filter's characteristic equation de-termine how each section is to be tuned for Q and f0.

As an example, a typical fourth -order bandpass fil-ter-the type frequently used in low -speed telephonedata communications systems-illustrates designingwith the active resonator. Suppose the specificationsare: a center frequency (f0) of 2,125 hertz, an over-allpassband gain [A(con)] of 200 (46 dB), a 3 -dB bandwidth(M3) of 400 Hz, a minimum stopband attenuation(Amin) of 60 dB at a lower cutoff frequency (fL) of 1,270

Hz, a maximum passband ripple (Amax) of 0.1 dB, andgeometrical symmetry.

First, the filter type and function order that best fitthe specifications must be found. To do this, the band-width at -60 dB (Mw) is computed from the upper (fu)and lower (fL) frequencies about geometric mean fn:

fu = f02/fL = (2,125)2/1,270 = 3,560 HZThen, for this case:

Af60 = fu -fL = 3,560 - 1,270 = 2,290 HzAnd the center -frequency Q (Q) of the entire filter is:

Qc = fo/Af3 = 2,125/400 = 5.32Shape factor On is determined next:

= Af60/Af3 = 2,290/400 = 5.13The design step that follows often involves the trans-

formation of a normalized filter function into the properfiltering plane. After transforming and denormalizingthis function, the designer can tune each resonator to aparticular Q and cutoff frequency. Tables of transferfunctions are usually written for low-pass functions sothat realizing other filter types requires transformingthe low-pass function into the desired function.

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Using the computed value of 2s, and specified valuesof Amin and Amax, and published filter data3 shows thata fourth -order Chebyshev filter will satisfy the ex-ample's skirt, bandwidth, and ripple requirements. Thenormalized coefficients of the low-pass Chebyshev func-tion are found in a table of. low-pass Chebyshev poly-nominals.4 For a ripple of 0.1 dB and an order of four,the filter's characteristic equation is given as:

D(s) = (s2 +0.458s+ 1.153)(s2 + 1.616s + 0.789)Solving for the roots of D(s) yields:

SA1,A2 = -0.229 ±1.05j, Sm.,B2 = -0.808 ±0.369jThese low-pass roots contain two complex -

conjugate pole pairs, which transform (see panel,"Bandpass transformations") into bandpass equivalentsof four complex -conjugate pole pairs and eight zeros.Since there are four pairs of poles, four active resona-tors are needed to attain the requirements.

Finding resonator components

From the low-pass-to-bandpass transform equationsin the panel, the values of Q and fp can be computed foreach resonator in the bandpass filter. Low-pass roots sAiand sA2 characterize the first two resonators:

Qi = 23.3, (f0)1 = 2,350 HzQ2 = 23.3, (f0)2 = 1,925 Hz

while sBi and sB2 characterize the last two resonators:= 6.6, (f0)3 = 2,135 Hz

Q4 = 6.6, (f0)4 = 2,120 Hz

Off -the -shelf resonators

Packaged active resonators, available as standardproduct lines from more than a dozen companies, canalmost reduce active filter design to a matter of re-sistor selection. Some manufacturers refer to theirlines of active resonators as universal active filters, butthe circuit function is the same.

The larger suppliers include Beckman InstrumentsInc., Fullerton, Calif.; Datel Systems Inc., Canton,Mass.; Kinetic Technology Inc., Santa Clara, Calif.;Optical Electronics Inc., Tucson, Ariz.; and TRW Semi-conductor division, Lawndale, Calif.

A standard family of hybrid microcircuit activeresonators also is offered by Integrated ElectronicsInc., principally for use in audio and subaudio appli-cations. In large quantities, they range in price fromabout $5 to $8.

Figure 3(a) shows the bandpass filter configurationusing the active resonator representation. It should beremembered that the resonator model employs anequivalent inductance requiring practical simulationand that each resonator section actually consists of threeamplifiers and associated circuitry, as noted in Fig. 3(b)for the input resonator. Once the components for theresonators are known, those required to complete each

04.58 H L 0

5.56 H L

1,000 pF

Ho

1.58 MS -2

158 kil

b I

250

C , 1,000 pF

Ro

490 kSZ

Ri

250 kSt

5.63HO L

11,000 pF

Ro

495 kS2

Ri

8.26HO L

C 111,000 pF

Ro

1.93 MS2

190 kft

Ri

v

RECOMMENDED OP AMPS:

TYPE 741FAIRCHILD gA776 1 LOW

SOLITRON UC4250 POWER

3. From model to design. Fourth -order bandpass filter (a) is represented by four cascaded resonators. Each resonator, with its simulatedinductance, actually requires three amplifiers (b), making 12 op amps necessary for entire filter. Component values can be found, onceand fo are known for each resonator. Capacitor values are assigned for computation convenience. R9 principally determines 0 of resonator.

93

Rf

45.8 k12

1+"158 k11

Vi -AAN--R

8 12

3

RESONATOR2

64

7

RQ

1.58 Mf2

0

- 10

- 20

- 30

- 40

- 50

- 60

70

R

250 kS2

Rf

-1VVV55.6 kit

8 12

37

RESONATOR2

64 5

R0 -VWv

490 k.S2

Ri

250 kit

Rf

-"OA.56.3 kS2

1+ V

d6

12

3 7

2 6

4 5

RESONATOR

RQ

495 kS2

190 kS2

Rf

-A/VV82.6

37

RESONATOR2

4

-4---

-v

1.93 MS2

2 3 4 5 FREQUENCY (kHz)

RESONATORS:

INTEGRATEDELECTRONICSµAR 1700

4. Ready-made resonators. Active filter design is considerably simplified by using packaged resonators that are available for a number offiltering functions. Those in this diagram are biquad networks connected to realize bandpass filter of Fig. 3. Only three components must beadded to each package-R, for gain adjustment, RQ to fix resonator 0, and Rf to set resonant frequency.

filter section can be found.To keep the analysis simple (neglecting the input im-

pedance of practical operational amplifiers), a conve-nient value is chosen for capacitor C. Generally, Cshould vary between 800 and 1,000 picofarads for re-sistor values to remain reasonable. By letting C = 1,000pF and computing the radian center frequency (co. =27Tfo) for each resonator, L can be found from Eq. 2:

L= 1/coo2CThe value of resistor RQ is determined with Eq. 3:

RQ = Q/w0CSince there are four resonators and the over-all requiredgain is 200, then each resonator must provide a gain of50. Eq. 4 becomes:

A(coo) = RQ/124 = 50which can be solved for input resistor R1:

R1 = RQ/50After the component values for the four resonators

are computed, the other components needed to simulateinductance L can be found. Again, the value of 1,000 pFis chosen for capacitor C' to simplify the calculations.Feedback resistor Rf is set equal to resistor R':

Rf = R' = Rso that Eq. 1 can be used to find R:

R = (L/C)"Active resonators, however, are available as standard

products from several manufacturers, as noted in the

panel, "Off -the -shelf resonators." These packaged cir-cuits often reduce the final design step to choosing re-sistor values, once Q and fo are known.

For instance, the µAR 1700 resonator from IntegratedElectronics is a biquad network that can be used for theresonator sections in the fourth -order bandpass filterdesign example. Components C, L, RQ, and Ri are com-puted as before; of these, only RQ are R1 are requiredfor the actual filter implementation, as indicated inFig. 4. None of these component values differ fromthose already calculated.

Next, the "internal" resonator parts are found. In ad-dition to setting C' = 1,000 pF, R' is assigned a value of100 kilohms for convenience, and then Rf is computedfrom Eq. 1:

Rf = L/R'C'The resulting values of Rf are noted in the figure. Whenthe µAR 1700 resonator is used to build an active filter,RQ effectively sets resonator Q, and Rf effectively setsresonator fo. The magnitude response of the fourth -order bandpass filter is also illustrated.

REFERENCES:1. J. Tow, "Step -by -Step Active Filter Design," IEEE Spectrum, December 1969, pp. 6 4-68.2. L. C. Thomas, "The Biquad: Part I-Some Practical Design Considerations," IEEE Trans-actions on Circuit Theory, Vol. CT -18, No.. 3, May 1971, pp. 350-357.3. A. Zverev, Handbook of Filter Synthesis, John Wiley & Sons, 1961.4. R. P. Salton, E. L. Key, "A Practical Method of Designing RC Active Filters,"M. I. T. Lincoln Laboratory, Tech. Report No. 50, May 6, 1954.

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Active filters getmore of the actionBuilt around the new, better, cheaper IC op amps, active filtersare beginning to move in on passive filters; their advantages includeflat passbands with sharp corners, inherent isolation, and easy tuning

by Lucinda Mattera, Circuit Design Editor

For all practical purposes, an active filter is just anRC network tacked on to an operational amplifier-oramplifiers-and its price and performance depend es-sentially on those of the op amp. Recently IC op ampshave improved so much on both counts that active fil-ters have started challenging passive filters at the lowerend of the frequency spectrum. In fact, the very lowestend is by now all theirs.

A great many are being built in-house. They are rela-tively straightforward to design, because they can beeasily handled in mathematical terms and lend them-selves to computer -aided design. But with the manufac-turers of active filters busily cutting prices and introduc-ing standard products that can be customized by thebuyer, the make -or -buy decision is becoming more dif-ficult than it was a year ago.

Presently, communications applications in telephoneequipment and various military programs are makingheaviest use of active filters. They are also being ex-ploited in some areas of data acquisition, notably tele-metry, medical research, oceanography and the moni-toring of geophysical phenomena. But much larger andpractically untapped markets exist in process control,data acquisition, computer terminals, and modems.Other potential markets include pager systems, petro-chemistry, and instrumentation.

From this listing, it's clear that active filters performthe same functions as passive filters, providing eitherlow-pass, high-pass, bandpass or band -reject (notch)outputs. Their response characteristics are also identi-cal, since they can realize a Butterworth, Chebyshev,Bessel, Gaussian or Cauer (elliptic) response. As a re-sult, deciding which type of filter will do the better jobboils down to the traditional design tradeoff betweencost and performance.

Two frequency breakpoints -100 hertz and 20 kilo-hertz-can be used as soft guidelines for the decision.Active filters s,hould be considered only if they are tooperate at very low frequencies or in the audio region-say, from 0.001 Hz to 20 kHz. Above 20 kHz, the passivefilter costs less than the active and provides comparableor better performance. Below 100 Hz, passive perform-ance is quite sloppy, so that the active filter is the morepractical choice almost regardless of cost. From 100 Hzto 20 kHz, however, the active filter's cost does not really

change, while the passive filter's steadily drops, makingthe performance the deciding factor in this region.

Over the audio range and below, the active filter hasa flat constant -amplitude passband and sharp cornerfrequencies. Moreover, even when operating at fre-quencies below 10 Hz, it provides reasonably high val-ues of Q, allowing good selectivity to be obtained. Incontrast, the vlf passive filter requires very high induc-tance values so that the inductors are physically largeand cannot provide the Q needed for good selectivity.

Above 20 kHz, the op amp is the limiting factor. Itsgain -bandwidth product determines the highest fre-quencies at which the filter can work. The output powerlevel of most low-cost general-purpose lc op amps be-gins to roll off at about 20 kHz, attenuating the filteroutput voltage. But op amps with gain -bandwidth prod-ucts large enough to sustain filter operation above 20kHz are expensive, costing $5-$10 instead of $1.

Comparing active and passive

In general, it's the component parts of the active filterthat contribute most to its cost-the IC op amps costnearly a dollar each, whereas resistors and capacitorsget only a few cents apiece. With the passive filter, onthe other hand, the design time needed to produce de-sired performance is the expensive element.

This can be inferred from a comparison of active ver-sus passive performance: The behavior of practical inductors is very nonlinearat low frequencies, especially with respect to tempera-ture coefficient. But because even low-cost general-pur-pose op amps offer dependable temperature perform-ance, the active filter can achieve a corner frequency astight as 100 parts per million per °C without too muchdifficulty. Obtaining a frequency accuracy within only 5% canbe troublesome with the passive filter, but is easy withthe active. Getting sharp corner frequencies, which are inherentin the active filter, requires many inductors and capaci-tors in the passive -filter. This makes the passive biggerthan the active for the same skirt selectivity. The active filter can supply a controlled gain over itsentire operating frequency range. The passive filter al-ways attenuates a signal.

95

Additionally, the active filter is easily tuned to the de-sired operating frequency with a resistor, while the pas-sive must be tuned with an inductor and/or capacitor. Impedance matching at either the active filter's inputor its output is unnecessary because its op amp providesit with inherent isolation in the form of a high input im-pedance and a low output impedance. For the passivefilter, impedance matching can prolong design timeinordinately, and proper termination may even involveactive devices (an emitter -follower or an op amp) ateach end. Realizing higher -order filter functions is a simplematter of cascading active -filter sections, each of whichprovides at least a second -order filter function. This is amarked improvement on implementing higher -orderfunctions with the passive filter, which requires the ad-dition of inductors and capacitors that make the designmore complex and interaction problems more acute.

Mathematically, in fact, the active -filter section canbe treated as a second -order transfer function that issynthesized as a pole pair rather than a low-pass orhigh-pass filter section. This makes the active filter easyto manipulate on paper or to design with the aid of acomputer without special complicated programs.

Other cost considerations

Admittedly, the passive filter operates without beingtied to a power supply, while the active cannot. Op -amppower supplies are common to so many applications,however, that the addition they make to the price isusually very reasonable.

And even so, there are situations in which active fil-ters are more cost-effective than are passive. Several ac-tive filters, for instance, can fit on one printed -circuitboard, while at least one board is usually needed foreach passive filter. The cost of associated hardware likepc boards, connectors, and cables could be substantialenough to tip the balance toward active filters.

Moreover, active filters often help lower productioncosts. When housed in small tc-compatible packagesthey can save assembly time, and are adaptable to exist-ing automatic production machinery, like insertion andwire -wrapping equipment.

Today's practical active filter is one that uses an ac-tive device to synthesize inductance. There are four ba-sic types.

1. Non -inverting. Positive -feedback active fitter (low-pass, in thiscase) maintains zero phase shift between input and output. Thisleast -used filter circuit minimizes component count.

r-vv\-->-*I

e0

Data acquisition: promisingAlthough computer -controlled data acquisition sys-tems are popular, only a few contain analog -to -digitalconverters that use filters to precondition incominganalog signals for improved data analysis accuracy.The filters that are used, however, are generally ac-tive, since much of the data being collected occurs atfrequencies of 20 hertz or below.

Only rather specialized data gathering systems-forexample, systems for special automobile testing, off-shore drilling operations, and checking bridge con-struction-presently employ filters. For the most part,process control, where a good deal of data acquisitionis done in the noisy environment of industrial machin-ery, remains a holdout against filtering.

Manufacturers selling data acquisition systems withprefiltering include: Digital Equipment Corp., Maynard,Mass.; Data General Corp., Southboro, Mass.; andAnalogic Corp., Wakefield, Mass. Another company,Datel Systems Inc., Canton, Mass., will be introducinga prefiltered multiplexing system at the Wescon show.

The least used-the positive -feedback filter (Fig. 1)-isalso the only one to employ a noninverting op amp.This filter, which is also known as the voltage -controlledvoltage source, usually requires the fewest resistors andcapacitors and is easily tunable over a wide frequencyrange. It is the only practical active filter circuit that of-fers zero phase shift without needing a second amplifierfor signal inversion.

The other three circuits incorporate negative feed-back, using the op amp in its inverting mode. For these,the output signal is out of phase with the input by 180°.Common names for the three are multiple -feedback,state -variable, and biquad active filters.

Negative -feedback filters

The multiple -feedback active filter (Fig. 2), which isthe most widely used, consists of a single op amp and anassociated RC network. As a bandpass filter, it offersconstant -gain -and -bandwidth performance that doesnot change as the filter's center frequency is shifted.Two variations of this filter-the bridged -T and thetwin -T active filters- have only one feedback path. Butthey are less popular than the multiple -feedback ver-

2. Most popular. Multiple -feedback filter nas two or more negative-

feedback paths. Here a bandpass function is realized. The shining ofcenter frequency does not affect filter's gain and bandwidth.

96

Rf

sion, because they need more passive components andhave higher output impedances.

Both the state -variable (Fig. 3) and biquad (Fig. 4)active filters realize a transfer function through theanalog computing technique of integrating and sum-ming. The former is based on general state -variabletheory, while the latter is a modified state -variable filterthat involves quadratic equations.

Simultaneous low-pass, high-pass, and bandpass out-puts are available from the state -variable filter. The bi-quad filter provides simultaneous low-pass and band-pass functions, but requires an additional amplifier torealize a high-pass output. This choice of output func-tion is why these circuits are often referred to as univer-sal active filters or active resonators [Electronics, "Ac-tive resonators save steps in designing active filters,"April 24, p.106].

Both these types of filter require two or three op ampt,each, in addition to the necessary resistors and capaci-tors, making them rather more expensive than the mul-tiple -feedback filter. In exchange for this higher cost,however, they do offer a choice of output functions andsimpler design procedures. Also, they are relatively in-sensitive to passive -component tolerances. The Q, gain,and operating frequency of the two can be indepen-dently adjusted with resistors.

Better temperature stability can be obtained from thestate -variable and biquad filters than from the multiple -feedback filter, but op -amp quality must be better; themultiple -feedback filter is not as sensitive to amplifierperformance. On the other hand, since the gain -band-width product of cascaded amplifiers is smaller than thegain -bandwidth product of a single amplifier, the upperfrequency limit of the state -variable and biquad filterstends to be lower than that of the multiple -feedback fil-ter circuit.

As for the relative merits of the biquad and the state -variable filters, the former is usually the better for alow-pass or bandpass function, and the latter better for

3. Versatile. State -variable filter requires three op amps to supplyhigh-pass, low-pass, and bandpass outputs at same time. Operatingfrequency, gain, and Q are inaependently adjustable. Also, circuit isnot sensitive to passive -component tolerances.

e,

BANOPASSOUTPUT

LOW-PASS,0 UTPI IT

4. Modification. Biquad active filter offers most advantages of state -variable circuit, but cannot produce a high-pass function without ad-ditional amplifier. sets gain, RQ sets Q, and Rf sets frequency.

a high-pass function. But the values of the resistors andcapacitors in a biquad may be so high that their tem-perature coefficients become inadequate. In that case,the state -variable filter is to be preferred, since its per-formance parameters are set by component ratios and itcan make use of low resistor and capacitor values, withtheir better temperature coefficients. For example, theQ of the state -variable is determined by a resistance ra-tio, not a single resistor value as with the biquad.

Deciding to make or buy

As a rule, active -filter users build their own circuits ifthey have the necessary design experience, and if theyuse filters in large quantities. Active filter suppliers findtheir main customers are among those users who lackdesign know-how, or who have particularly stringentperformance requirements.

In contrast to the ones built in-house on pc boards,purchased active filters are always plug-in modules thatare housed in ic-compatible packages. These ready-made units are either modular encapsulated assemblies(Fig. 5) of packaged discrete -type components or preci-sion hybrid circuits (Fig. 6) that contain chip amplifiers,chip and/or discrete capacitors, and thick -film and/oithin-film resistors. They are usually negative -feedbackfilter circuits of the three types discussed above, and canrange in price from about $26 for a single standard unitto a few hundred dollars for a single special unit.

Only about four years ago, the market for active fil-ters seemed to have a bright future. But many poten-tially large markets have remained relatively unpene-trated because of widespread in-house design, the firmestablishment of passive filters, and the lack of filteringin many data gathering applications. Nevertheless, ac-tive filter sales are expected to be close to $10 millionfor 1972, climbing to $19 million by 1975.

While the current market is growing at the rate of10% to 15% per year, usage of active filters is probablygrowing much faster since many more filters seem to bebeing built in-house than are being sold by filter manu-facturers. To attract more sales, some filter suppliers arehoping to launch the same kind of customer -educationcampaign that was extremely successful for the op amp.That goal should be helped along by the decliningprices of recent and upcoming new filter products.

Because most filters are custom items, their manufac-turer is primarily in the business of selling engineering

97

5. Ott -the -shelf. Modular -type filters manufactured by Frequency Devices are assembled from discrete amplifiers, resistors, and capacitors.Several venoors supply similar filters in both standard and custom models, as either factory -tuned or customer -tuned circuits.

services. Filter makers who do supply standard filtersattribute only about 30% of their sales to them.

Several companies are offering the universal activefilter as a standard product, but its reception has beenmixed. Some users say that its principal feature, its vari-ability, is useless since filter needs are usually special-ized. The filter's data sheet is said to be difficult to un-derstand, and tuning it to desired specifications may notbe easy. Tuning can be further complicated when sev-eral of the devices are cascaded, because their tunedcomponent values generally differ from resonator toresonator. Finally, the universal filter is expensive be-cause it contains more than one op amp.

However, as one supplier points out, this filter can beused as a basic building block by the manufacturer torealize a whole line of filters, without harming the fil-ter's tuning versatility. The manufacturer can choosethe filter function he wants and then encapsulate. Even-tually, therefore, the universal filter will cost the manu-facturer less to make-and his customer less to buy.

Filter makers stress lower pricing

One of the oldest suppliers of modular -type active fil-ters, Burr -Brown Research Corp., Tucson, Ariz., iskeenly aware of the need for a low-cost ready-madeunit. This month, the company is introducing its seriesATF76 filters that are about half as expensive as its ear-lier units and are intended to be priced about 10% be-low competing lines. The new filters are fixed -tunedunits that employ lc op amps instead of discrete transis-tors. Single -unit prices begin at $29 for a two -pole low-pass Butterworth filter.

Ron Gadway, product marketing engineer, data con-version products, sums up the filter maker's biggestproblem, "Our competition is really the customer him-

self. If we can't give him what he wants for his price,he'll build it himself." Burr -Brown expects to expand itsstandard line with a state -variable filter before the endof this year, and to add a voltage -tunable filter shortlyafterwards.

Another manufacturer of modular -type filters is Fre-quency Devices Inc. of Haverhill, Mass. This small com-pany has an interesting way of keeping parts cost low.Alan Schutz, director of engineering, explains, "We buycapacitors with tolerances of ±20%, but know their ac-tual values to within ±0.5%. Resistor values are theneasy to determine with a simple computer program."

A recently introduced family of tunable active filters

98

6. Chips and films. Hybrid active filters tend to be customized cir-cuits of thick- and thin-film resistors, chip capacitors, and chip ampli-

fiers. Pictured is digitally tunable bandpass filter made by SpragueElectric for the military. Molded tantalum capacitors (on left and rightsides) are sometimes used to furnish required capacitance.

7. Module maker. Alan Schutz of Frequency Devices thinks thatsuppliers must teach customers how to select and use active filters.

from Frequency Devices frees the customer from thedifficult and time-consuming job of capacitor trimming.The capacitors are inside the package, and tuning is ac-complished with outboarded resistors. Frequency De-vices is one of the few companies with a standard seriesof voltage -tunable active filters. Tuning ranges for theseextend down to 0.01 Hz and up to 50 kHz. Single -unitpricing starts at $210.

Manufacturers that make hybrid active filters do so,for the most part, as a byproduct of their other hybridbusiness. A well-known supplier of hybrid circuits forseveral years is the Semiconductor division of SpragueElectric Co., in Worcester, Mass. Eugene Donovan, op-erations manager, hybrid circuits, points out, "Anybodywho depends on filters totally is going to have a difficulttime. At Sprague, we build hybrids and can serve sev-eral markets with the same technology, because thecomponents used in our converter products can also beused in our filters."

In an attempt to break hybrid filters out of the

8. Hybrid maker. Active filter suppliers must also service other mar-kets to survive, asserts Eugene Donovan, Sprague Electric.

11.00011w

9. Instrument maker. Variable active filters can be used as designaid to find filter needed, observes Ernest Lutfy, Krohn -Hite Corp.

predominantly custom market, Sprague intends to in-troduce a second line of standard filters in the nextmonth or so. The filters will be tunable, using externalresistors to control Q, frequency and gain. Both band-pass and notch functions will be available for fre-quencies of 30 Hz to 10 kHz. Pricing is not yet firm.

Motorola Semiconductor, Phoenix, Ariz., is aimingparticularly for penetration of the modem area with ac-tive hybrid filters. But, observes Don Kessner, managerof systems, industrial applications, "because of cost, thehybrid active filter will probably never replace the pc-board active filter used in those modems where space isnot critical." Only when the "so-called all-mos datamodem" becomes practical does he feel that a high -vol-ume special market may develop for the inexpensivehybrid filter. Intended for low -speed operation, thismodem would comprise two packaged circuits-a digitalMOs chip and an analog front-end conditioner for thechip. The analog portion could be a hybrid filter.

Kinetic Technology of Santa Clara, Calif., which re -

99

covered from bankruptcy officially this last December,is selling both modular and thick -film hybrid active fil-ters. The company's standard hybrid filters are state-variable circuits that provide a variety of response char-acteristics, from Butterworth to elliptic. The least expen-sive filter in this family sells for $26 singly, dropping toless than $5 in quantities over 10,000. It includes an ex-tra op amp.

Fred Glynn, Western regional sales manager, offers abit of customer advice. "If frequency accuracy within1% is acceptable," he says, "the customer can use inex-pensive 1% resistors to tune our filters without difficulttrimming. If his accuracy requirement is tighter, we sug-gest that he use a less expensive filter [of ours] and tuneit with a fixed resistor and a trimmer potentiometer."

For completeness' sake, the instrument type of activefilter (Fig. 10) should also be mentioned. It can providea number of filtering functions over a wide frequencyrange. The user selects the ftInctions he wants (low-pass,high-pass, or a combination of these) and then dials thefrequency he wants.

Krohn -Hite Corp., Cambridge, Mass., manufacturesa series of these variable active filters. The company'sinstruments can perform low-pass, high-pass, band-passand band -reject filtering from 0.001 Hz to 3 MHz. Pricesrange from $450 to $2,075 for frequency accuracies of±2% to -±10%.

"Because our instruments are tunable and can be op-erated over a wide frequency range, they are sometimesused as a design aid to help pinpoint the fixed -fre-quency filter that will be needed," notes Ernest Lutfy,sales manager. Medical researchers are also using thevariable filter, for example, to test the frequency re-sponse of the ear, or to listen to the heartbeat of a fetuswhile filtering out unwanted signals from its expectantmother.

Users justify building in-house

In-house active filter design is done by companieswho can spread engineering costs over a number ofproducts. "We seldom buy outside because it's just tooexpensive," says Farouk Al -Nasser, a principal scientistat the test instrument division of Honeywell Inc., inDenver, Colo., who is involved in designing data stor-age systems. But he cautions that learning how to de-sign active filters may take as long as two to three years,because existing literature does not cover practical con-siderations for the op amp. Most filter theory still treatsthe op amp as an ideal element having infinite gain andperfect isolation.

Many modem manufacturers have a staff of active fil-ter design specialists. One of these is Paradyne Corp. ofClearwater, Fla. "The cost of active filters depends onwho designs them," says Tam Saliga, senior engineer."Using only one op amp, we can build a [multiple -feed-back] filter with four to five poles for around $1 to$1.50."

Paradyne even standardizes its active filter designs tosome extent to realize additional cost savings. Most ofthe filters the company incorporates in its modems usethe same two values of capacitance, enabling Paradyneto buy capacitors in very large volume.

Specializing in pc -board modems (Fig. 11), Intertel

10. Variable active filter. When filter frequency must be contin-uously varied, an instrument -type filter can be used. Corner fre-quencies and filter function can be selected from front panel.

11. Tight fit. Intertel Inc. employs narrow -band active filters to elimi-nate noisy sidebands in receiver portion of pc -board 201 -typemodem. Complete modem measures only 9.5 by 12.9 inches.

Inc. in Burlington, Mass., uses active filters exclusivelyto keep its modems as small as possible. "We need veryspecial filters and prefer designing our own," saysGeorge Harlem, marketing coordinator. "Nobody elsecan build them as cheaply as we can, and nothing thatwe could buy is equivalent in terms of performance."

Many designers actively prefer active filtering to pas-sive. Jerry Holsinger, Intertel president, explains why:"In a sense, passive filter design is a black art. Active fil-ter design is really a totally new concept in which thegeneral-purpose building block is not a physical compo-nent, but simply a second -order transfer function." He'sreferring to the fact that an active filter can be com-pletely described by its pole -zero plot, which alwayscontains a pole pair, permitting the filter to be easilymanipulated mathematically.

One designer, John DeFalco, who is a lead engineerat Honeywell Information Systems in Billerica, Mass.,personalizes his preference for active filters. "Passive fil-ter design is just a matter of looking up data in tablesand charts-it's a lot more fun designing an active fil-ter," he says.

100

The integrated Schmitt trigger:a versatile design component

Availability of the Schmitt trigger in an IC version is expandingits use in common circuits, such as multivibrators and pulsestretchers; here are a few design tips on how best to apply it

by John A. DeFalco, Honeywell Information Systems, Billerica, Mass.

As basic digital circuits go, the Schmitt trigger re-quires careful and sometimes time-consuming design.That fact has deterred many circuit and systems design-ers from working with it, despite its versatility.Recently, however, several manufacturers have intro-duced an integrated dual Schmitt trigger, the type 7413,which is completely compatible with the popular type7400 TR circuits.

To use the type 7413 to its best advantage, the de-signer should first take an inside look at the chip andsee how it operates. That means understanding how toderive the values of the major parameters from the cir-cuit diagram.

The circuit's most important parameters are its posi-tive- and negative -going threshold voltages, VT+ andVT-. VT+ must be exceeded to switch the output from ahigh to a low state, while at VT_ the output switchesfrom low to high.

These voltages, together with the effects of tempera-ture and power supply variations, can be easily calcu-lated for the chip from the circuit diagram of Fig 1.Each half of the type 7413 Schmitt trigger is actually acombination of 7400 -type logic and the basic Schmitt

trigger. Logically, the integrated Schmitt functions as afour -input NAND gate; tying all four of the inputs to-gether allows the circuit to be driven by signals withlarger amplitudes.

Analyzing the IC Schmitt

Multiple -emitter transistor Qi operates as a diode (itscollector -base junction is shorted). Transistors Q2 andQ3 are the actual Schmitt trigger, while transistors Q4through Q9 make up a NAND gate with conventionalTTL-type output characteristics. Two of these transistors,Q5 and Q9, function as emitter -base diodes (collectoropen).

When the input (assuming all four inputs are tied to-gether) is low, Q2 is off and Q3 is saturated. To calculatethe positive -going threshold voltage, the circuit ofFig. 2a (left) can be used to obtain the Theveninequivalent (right) with transistor Q3 in saturation. Sum-ming voltage drops around the input loop,VT+ = -VBE1 Vr2 VEwhere VBE1 is the base -emitter voltage of transistor Qiand Vy2 is the emitter -base voltage required to turn ontransistor Q2. Voltage VE from the emitters of Q2 and

INPUTS

4 kS2

'/s,'0,

AAAA

2 kS2 1.2 kS2

460 S2

1.5 ks2

1 5 kil

1.6 kS2 2 130 12

0,,

1 kS2

7

vcc

OUTPUT

1. Integrated Schmitt circuit. Each Schmitt trigger contained in the type 7413 package functions logically as a four -input NAND gate. Tyingall four inputs together maximizes the size of signal that can be accepted. Transistors 02 and 03 are basic Schmitt; remaining transistors formTTL-type NAND gate. Multiple -emitter transistor Oi and transistors 05 and 09 operate as diodes. Output of Schmitt is TTL-compatible.

101

Q3 to ground can be found from the Thevenin equiva-lent circuit:

YE = (46012)(4.6 v)/(750 S2 + 450 S2) = 1.74 vAssuming values of VBE1 = 0.7 v and Vy2 = 0.55 v:

VT+ = -0.7 v + 0.55 v + 1.74 v = 1.59 vNegative -going threOiold VT- can be determined by

assuming transistor Q2 is on and saturated. As the inputto the Schmitt trigger drops, transistor Q3 begins to turnon and the circuit conditions of Fig. 2b apply. When Q3turns on, transistor Q2 is in the active state and its col-lector voltage is:

V02 = Vcc 1C2RC2 (1)Computing Q2's collector current:

Ic2 = [a2(Vi - VBE2) /RE (2)where a2 is the common -base current gain of transistorQ2. Substituting Eq. 2 into Eq. 1 and solving for Vi witha2 = 1 yields:

V1 = VBE2 -V73 VCC RC2(V1 VBE2)/REor:

V1 = VBE2 (Vcc - Vy3)/(1 +RC2/RE) (3)

1 02

VBE2

VI

R c22 kS2

Vc2

RE460 E2

1.2 kS2

Vcc+5 V

2. Calculating threshold voltages. Positive and negative switchingthresholds are the most important Schmitt parameters. Simple wayof finding positive -going voltage (VT+) needed to switch from high tolow state is to use Thevinin equivalent (right) of circuit (left) in (a),with 02 in cutoff and 03 in saturation. To compute negative -goingthreshold (VT_), 02 is saturated while 03 is cut off, as in (b).

The equation for VT-- becomes:VT- = -VBE1 VBE2 - V73 + VC2 = -VBE1 V1

Replacing V1 with Eq. 3:VT- = -VBE1 VBE2 (VCC -V73)/(1+RC2/RE)

Since VBE1 approximately equals VBE2, this equationreduces to:

VT- = (Vcc - V73)/(1 Rc2/RE)With the circuit component values shown and with Vy3 =0.55 v, the negative -going threshold voltage can be eas-ily evaluated:

VT-- = (5 v - 0.55 v)/[1 + (21d2)/(460 2)1 = 0.83 vBoth threshold voltages vary considerably with sup-

ply voltage Vcc. For example, a 1-v change in Vcc willcause a variation of 380 millivolts in positive -goingthreshold voltage

dVT+/dVcc = 0.38Similarly, for VT_:

dVT_/dVcc = 141+ Rc2/RE) = 0.185The type 7413 Schmitt trigger can operate over a

wide temperature range. Positive -going threshold VT+ isalmost insensitive to temperature changes because itsthermal variations either cancel or are negligible. Andnegative -going threshold VT_ is only slightly tempera-ture -dependent:

VT_ = Vcc -V7/(1 +RC2/RE)Differentiating this equation with respect to tempera-ture (T) yields the negative -going threshold tempera-ture dependence:

dVT_/dT = dVy/(1 +Rc2/RE)dTSince dVy / dT = -2 my/°C, then:

dVT_/dT = 0.37 my /°C.

Widely used Schmitt circuits

The integrated Schmitt trigger is useful in a variety ofapplications. For instance, Fig. 3a shows a simple RCmultivibrator that can be implemented with only one-half a type 7413 Schmitt trigger, plus a single resistorand a single capacitor.

Circuit operation is simple. Capacitor C is initiallyuncharged and has a voltage across it that is less thanVT+; the circuit's output level is high. The capacitorcharges through resistor R and through multiple -emit-ter transistor Q. When the voltage across C reachesVT+ (about 1.6 v), the Schmitt changes state so that itsoutput goes low, discharging C through R and saturatedoutput transistor Q7. When capacitor voltage drops toVT_ (about 0.8 v), the Schmitt switches to its high stateand C begins to charge again.

Several dc considerations influence the selection ofresistor R. It must not draw excessive current from theoutput, but its value must be high enough to preventthe loading of subsequent stages. Its maximum value isrestricted by the current -sinking capability of outputtransistor Q7. A resistance of 390 ohms is recommendedby one manufacturer of the type 7413 Schmitt for afanout of 2.

With R = 390 ohms, the equations for output pulsewidth are:

tH = 0.150tL = 0.34C

where tH is the period of time (in nanoseconds) duringwhich the multivibrator is high, and tL the duration (innanoseconds) of the low output period. (The units of ca -

102

INPUT

(c)

140 S2 ,-SILICON DIODE

1390 St)

tH

OUTPUT

1/27413

Vcc

'/27413

he- t

OUTPUT

OUTPUT

3. Using the Schmitt. Simple multivibrator (a) requires only externalresistor and capacitor; adding diode and second resistor achieves50% duty cycle. For pulse stretcher (b), extra resistor compensatesfor unit -to -unit processing variations so that output pulse width ismore predictable. Biasing Schmitt at its mid -threshold point enablesit to convert sine waves to square waves (c).

pacitance are picofarads.) Multivibrator frequency inhertz, therefore, will be:

f = (2.02 x 10-3)/Cwhere C is in farads.

As the timing equations indicate, the multivibratoroutput is low approximately 70% of the time. Adding aresistor and a diode, as shown by the dashed lines, re-duces the discharge cycle time, yielding a multivibratorwith a duty cycle of 50%. With the values shown, outputfrequency becomes:

f = (3.3 x 10-3)/CAgain, C is expressed in farads and fin hertz.

A relatively simple one-shot (or pulse stretcher) canbe built with the circuit configuration of Fig. 3b. Whenan input pulse is applied to NAND gate G1, its outputgoes low, but the Schmitt trigger's output remains high.Before the Schmitt can switch to its low output state, ca-pacitor C must charge to VT+. The charging resistor isthe base resistor of transistor Ql. Output pulse width forthis circuit is nominally:

t = 1.95Cwhere t is in nanoseconds and C in picofarads.

Variations in the charging resistor cause output pulsewidth to vary from unit to unit. Performance can be im-proved by inserting a resistor between the supply andthe capacitor. Pulse width then becomes:

t = 0.26Cfor tin nanoseconds and C in picofarads. Pulse width isreduced with the additional resistor.

Another useful circuit converts a sine wave to a

The Schmitt trigger reviewed

A variation of the basic Eccles -Jordan bistable multi -vibrator, the Schmitt trigger is also called an emitter -coupled binary. Unlike the conventional binary, it ex-hibits hysteresis, switching from one state to anotherat different threshold voltages, depending on the di-rection of the triggering input. Additionally, theSchmitt's input terminal is not involved in regenerativeswitching and so keeps the same potential during andafter transition, creating an excellent triggering circuit.

Normally, the Schmitt operates with a loop gain ofgreater than unity. Circuit hysteresis can be elimi-nated by making the loop gain equal to unity throughresistance adjustment. The positive- and negative -go-ing threshold voltages can also be shifted.

For a more -than -unity loop gain, input voltage v1must reach positive -going threshold V1 before theSchmitt can switch to its high output state (v0 = VH).When vi decreases, it must pass the V1 threshold levelbefore the transition to the low output state occurs(vo = VL). The circuit is unstable in the region be-tween VL and VH. For the low output state, 01 is offand 02 on; for the high state, 01 is on and Q2 off.

Vo

VH

VL

Vcc

'4 LOOP GAIN 1j LOOP GAIN = 1LOOP GAIN - 1

V2 v,

square wave, as shown in Fig. 3c. Resistors R1 and R2bias the Schmitt trigger at the mean value of its thres-hold voltages to obtain the necessary 50% output dutycycle. To avoid differentiating the input signal, the im-pedance of capacitor C at the operating frequency of in-terest should be much less than the parallel resistance ofR1 and R2:

C approximately equals (4.3 x 10-3)/fwhere C is in farads and fin hertz.

The converter can be operated at frequencies up toabout 8 megahertz. If all four inputs of the Schmitt trig-ger are tied together, peak input voltage can be as highas 6.5 V. If only one input is used, maximum input volt-age becomes 5.5 V peak. The minimum input voltageshould be about 1 V peek.

BIBLIOGRAPHY"TTL Schmitt Trigger," Texas Instruments Application Report, Bulletin CA -152

103

Electronic fuel injectionreduces automotive pollutionAn MOS read-only memory is at the heart of a British systemthat minimizes pollutants by measuring exact quantitiesof fuel and timing their insertion into combustion chambers

by Malcolm Williams, Joseph Lucas (Electrical) Ltd., Shirley near Solihull, England

0 In a massive effort to limit automotive exhaust pollu-tion, one of the devices being evaluated carefully is anelectronically controlled fuel -injection system.

Besides the advantage over standard carburetion ofincreased power offered by fuel injection, the accuratecylinder -to -cylinder fuel distribution and optimum fuelcontrol under turbulent manifold air conditions enablefuel injection to minimize exhaust pollution.

It is unlikely, however, that a fuel -injection systemalone will meet the latest legal emission requirements,and some form of exhaust treatment also will be neces-sary. Nonetheless, the cost of exhaust treatment in a ve-hicle fitted with fuel injection would be lower than itwould be without fuel injection.

To achieve low -pollution exhaust emissions, a highair -to -fuel ratio is required over the engine's completeworking range. This minimizes wasted fuel, and, as a

consequence, gives rise to fewer partially burnt pollu-tants. It is also important to obtain an accurate mea-surement of engine conditions and fast, accurate mea-surement of air -mass flow. The system must be able tosupply the optimum amount of fuel when the air in theinlet and exhaust manifolds is resonating.

The engine parameters that best meet these require-ments are throttle angle and engine speed. But the costof a complex control function is prohibitive if standardanalog electronic techniques are applied. However, byusing a digital memory to store the fuel -demand charac-teristics, a system becomes economically attractive.

A prototype fuel injection system has been developedfor a standard 150 -cubic -inch, six -cylinder Triumph se-dan. Engine speed and throttle angle information arestored in a digital memory containing 256 seven -bitwords. Each word in the mos read-only memory repre-

FUEL TANK

FUELPUMP FILTER

11

PRESSUREREGULATOR

ATMOSPHERICPRESSURE SENSOR

SOLENOID (ONE FORINJECTOR EACH CYLINDER)

( ILYAIR INLET

TEMPERATURESENSOR

POWERAMPLIFIERS

CONTROLUNIT

-4- TIMINGCIRCUIT DIGITAL

MEMORY

ANALOG TODIGITAL

CONVERTER

ANALOG TODIGITAL

CONVERTER

THROTTLEANGLE SENSOR

-4- INTER-POLATIONFUNCTION

SPEED

SENSOR

CRANKANGLESENSOR

C:=1

ENGINETEMPERATURESENSOR

1. FIll 'er up. The electronic fuel -injection system shown as part of the auto power plant is designed to provide accuiate amounts of fuel tothe engine cylinders based on demand (throttle angle), engine speed, engine temperature, and ambient conditions.

104

THROTTLEANGLE

SENSOR

AUXILIARYDISTRIBUTOR

CONTACTS

VOLTAGEPROPORTIONAL TOTHROTTLE POSITION

SHAPINGCIRCUIT

TRIANGULARWAVE

GENERATOR

CLOCK

DUALCOMPARATOR

SUMMINGAMPLIFIER

SUMMINGNETWORK

90° PHASELAGGED

TRIANGULARWAVE

GENERATOR

UP

--DOWN

.00

4 BITUP/DOWNCOUNTER

SUMMINGNETWORK

POWERSTAGE

GROUP 1

VOLTAGE PROPORTIONALTO FUEL REQUIRED

D GITAL 00 -MEMORY -so -256 -WORD -ow -

7 -BIT n:

.00

SUMMING AMPLIFIER up

-11410 TIME -TO -VOLTAGE

CONVERTER

VOLTAGEPROPORTIONAL

TO ENGINE SPEED

DUALCOMPARATOR

4 B TUP/DOWNCOUNTER

DOWN

SUMMINGNETWORK

SUMMING AAMPLIFIER

-IP- SYNCRONIZATIONCIRCUIT

--100SOLENOIDINJECTOR

BANKGROUP 1

VOLTAGE -TO -TIME

CONVERTER-

r

ENGINETEMPERATURE

SENSOR

r --BAROMETRIC

PRESSURESENSOR

AIRTEMPERATURE

SENSOR

STEERINGCIRCUIT

POWERSTAGE

GROUP 2

SOLENOIDINJECTOR

BANKGROUP 2

2. Electronic controller. The complete fuel -injection system comprises TTL, MOS, and linear devices to process analog information fromengine and throttle to produce signals that help determine the exact fuel quantity to be fed into each cylinder.

V REFERENCE

VOLTAGEFOLLOWER

OUTPUTVOLTAGEPROPORTIONALTO ENGINESPEED

AUXILIARYDISTRIBUTOR

CONTACTS

SYNCHRONIZEDTRIGGERCIRCUIT

3. Speeding ticket. To get engine -speed information, auxiliary con-tacts are mounted on the distributor. The circuit ;shown above con-verts the time measured between contact pulses into analog voltaae.This voltage is converted to digital signals.

sents a different quantity of fuel. By reading out theright word at the right time, the correct quantity of fuelis injected into the induction port of the engine. The se-lection of the word is controlled with the informationsupplied by strategically placed sensors that monitor the

engine'sBoth digital and linear ICs were used. Their functions

include counting, comparison, and amplification to con-vert analog data into a form that will address a digitalread-only memory and for interpolation between theexact digital steps. Interpolation is necessary becausethe memory covers the range of possible engine fuel re-quirements and must progress smoothly from one stateto another.

When the driver switches on the ignition, the electricfuel pump mounted in the trunk sends fuel to the sole-noid injectors in the engine. Injection pressure is con-stant, and the controller determines the quantity of fuelinjected by controlling the time the injector is open.Hence, each word stored in the memory corresponds toa time interval.

On turning over the engine, auxiliary contacts in thedistributor cause the solenoid injectors to commencefueling at the correct point in the engine cycle and alsoprovide engine -speed information to the control circuit,selecting the appropriate memory word (Fig. 2). With acold engine, the fuel supply is increased over theamount a hot engine would need by multiplying thequantity stored in the digital memory by a factor de-pendent on the engine's temperature sensor. This sen-sor, which is fitted on the engine block, is tailored toprovide easy starting with minimum emissions andthereby function as an automatic choke.

The driver controls the power delivered by the engineby depressing the accelerator pedal, which controls the

105

throttle aperture in the air intake. The angle of the re-stricting butterfly valve, in conjunction with the enginespeed, measures air flow. Both the driver's demand andthe engine's air intake can be measured by coupling apotentiometer to the throttle shaft. As the throttle is de-pressed, extra air flows into the engine, and simulta-neously a new word is addressed in the memory, thusoptimizing the amount of fuel injected into the cylin-ders.

To account for changes in air density due to climaticconditions and radiant heating by the engine of the in-take air, an atmospheric pressure sensor and air -inlettemperature sensor are also installed.

Data converted

The throttle angle and engine -speed informationboth have to be converted into digital form to addressthe memory. Whenever the combination of throttleangle and engine speed hit a precise point in thememory, the engine's fuel demand is obtained by directreference. However, when the values of throttle angleand engine speed are between these exact memory sites,the engine fuel demand is calculated by interpolationfrom the adjacent stored data.

For the throttle signal, a potentiometer output pro-portional to throttle angle is first shaped to define moreclosely the changes at the initial low throttle opening.The signal is then converted into digital form by asimple analog -to -digital converter, which uses a feed-back resistor network. For signals of equal amplitude,the output from the amplifier is zero, and the digitalword -signal feedback from the counter is equal to theinput analog signal. When this analog signal increases,the output from the amplifier decreases from zero until

4. Memory lane. Digital words representing throttle angle and engine speed are fed into a decoder circuit, which then selects a programed line in the memory matrix to calculate fuel quantity.

the comparator threshold level is reached.The counter is then allowed to count up the clock

pulses, thus changing the digital word until equality ofboth signals again is achieved. The digital signal re-mains constant until an error greater than half the least -significant bit occurs, at which point the digital valuechanges to reduce the error. This particular a -d con-verter tracks the throttle signal rapidly.

The auxiliary contacts mounted in the distributorprovide engine -speed information, which is turned intoan analoe voltage from the time between contact pulses

10.EXHAUST POLLUTION EMISSIONS IN EXPERIMENTAL CAR(grams/mile)

Pollutant U. S. Federal CaliforniaAchievedon Test Engine*

1971 LEGISLATIONI 2

Carbon Monoxide

Hydrocarbons

Nitrogen Oxides

23

1975 LEG ISLATION3' 4

Carbon Monoxide

Hydrocarbons

Nitrogen Oxides

"7-mode California cycle

2.2

3.4

0.41

3.0

23

2.2

4.0

12

0.5

1.0

3.5

0.8

0.8

3.5

0.8

0.8

REFERENCES

1. Federal Register, Vol. 33, No. 108, June 4, 1968

2. State of California Air Resources Board, Nov. 20, 1968

3. Federal Register, Vol. 36, No. 128, Part II, July 2, 1971

4. State of California Air Resources Board, Resolution 20-4, Jan. 21,1970

12 1000110 1000100 1000000 0111101

3.6 1000001 0111101 0110111 0110010

7.5 0110110 0110000 0101010 0100011

5.7 0100111 0100010 0011011 0010101

I 1183 1364 1580

ENGINE SPEED (RPM)

1800

5. Fuel program. Each box in the memory program has a digitalcode number representing location and proper amount of fuel re-quired for that particular operating condition.

106

(Fig. 3). On closure of the first contacts, capacitor C 1rapidly charges toward a reference voltage. After about5 microseconds, S 1 opens, and the capacitor decaysthrough a fixed resistor R for the remainder of the en-gine revolution. When the second distributor contactcloses, this voltage is sampled for about 10 ps throughswitch S2 and is stored on capacitor C2. The voltage fol-lower acts as a buffer to prevent discharge of capacitorC2. This cycle is repeated for every engine revolution.

Another a -d converter changes the analog voltagerepresenting the engine speed to a digital word. The twofour -bit digital words-one representing throttle angle,the other representing engine speed-are fed to decod-ing circuits; each decoder circuit then selects a particu-lar line in the memory matrix (Fig. 4).

Engine -speed conversion

For example, if line A on the throttle input is selectedand a positive voltage is impressed on the line, thendiode D will conduct. If line B is sensed by the engine -speed decoder, the positive voltage through diode Dwill be sensed on line B if the particular line sensed hasno diode on line . If the particular line sensed has nodiode, then a negative voltage would be sensed. So bythe presence or absence of a diode, a binary 1 or 0 canbe programed for any particular input line.

This example shows a simple memory matrix of 16one -bit words. To increase the number of bits, separatematrixes should be addressed simultaneously. The dig-ital memory used in the controller consists of 256 words,each of seven bits. mos transistors are used to form thematrix instead of diodes.

The digital information (Fig. 5) stored in the squarecorresponding to the intersection of throttle angle 9.6°and engine speed 1,580 rpm is 0110111. The data in theadjacent sites in the memory bear no relation to eachother, and whatever the optimum fuel required by theengine at the appropriate site, it can be provided by thecontrol system.

6. Injection plot. Without interpolation, a three-dimensional plot ofspeed, throttle angle, and fuel amount would look like this series odiscrete and flat planes produced by an X -Y plotter.

The fuel surface represented by the stored informa-tion in the memory would consist of a number of flatplanes (Fig. 6), the height being proportional to the fuelquantity to be delivered per engine stroke. However,the required surface cannot have these discrete steps.The control unit achieves a smoothly varying surface bylinearly interpolating stored data whenever the combi-nation of the throttle angle and engine speed do not hitan exact memory site (Fig. 7).

Circuits interpolate

There are two interpolation circuits-one for enginespeed and one for throttle angle. Each generates a posi-tive and negative triangular wave of fixed amplitudeand frequency. The effect, for each parameter, is tomake the memory sites each side of an intermediatepoint read out alternately for periods proportionate tothe distance of the sites from the intermediate point. Todo this, the triangulations superimpose on the sensorvoltage from the summing amplifier. To distinguish be-tween the two parameters, one wave generator is placed90° out of phase behind the other.

When a sensor output voltage corresponds exactly toone of the 16 matrix input levels tied to that sensor, thepositive and negative triangular oscillators are equal inamplitude, and the running voltage level in the com-parator is within the threshold levels identifying thatparticular matrix line. When the sensor voltage movesslightly, one triangle peak pushes the comparator volt-age within the levels identifying the next matrix line fora fraction of the triangle cycle time.

Half -way between the lines, half the triangle extendsinto the next line level, and so on. To connect voltagelevels and matrix lines, each line in each parameter isidentified by a four -bit digital word, and an a -d con-verter translates voltage into word. Hence, two four -bitwords act on each of the seven memory planes, identi-fying in each plane a particular memory site. All sevensites are read out simultaneously, making a seven -bit

7. Bumpy road. With interpolation to facilitate continuous engineoperation, the surface of an X -Y plot becomes a series of undula-tions, assuring smoother engineer operation.

107

A B

01

1

k

q 401 r'G

)

I

s St

J K. L

3

M N 0 P

THROTTLE ANGLE

8. Gas station. When fuel demand coincides with an exact memorysite, the interpolation signal causes only that site to be addressed(point F); but when fuel needs don't correspond to an exact site-which is normally the case-an interpolation of as many as four adja-cent word sites may be necessary (point Y).

word identifying an exact injector opening time. Be-cause most throttle and engine -speed selections will besomewhere between exact sites, most of the time thememory output, under the influence of the interpolationcircuits, is cycling around four adjacent sites.

Fig. 8 shows the effect of the triangular waves on thememory where the memory sites, alphabetically la-belled, represent the engine conditions when the fueldata have been measured. The solid lines represent thedecision points where the a -d converter changes fromone word to the next, thus selecting a different memorysite. When the driver's demand, i.e., throttle angle andthe resulting engine speed, are both sent to the samememory site, the interpolation signal causes only thatmemory site to be addressed. For example, if F is theselected point, the resultant path traveled through thematrix is the square bounded by p, q, r, and s. When thedriver demands more power, point x would be selected,and the output from the memory would be alternativelythe words stored at memory sites F and G.

As the matrix is swept at a constant velocity, the timefor which each word appears at the output of thememory is proportional to the throttle -angle positionbetween F and G. A lag in the summing circuit aver-ages the memory output to give linear interpolation be-tween F and G. With the throttle angle and enginespeed set to select the point Y-the typical operating sit-uation-the output from the memory consists of the fouradjacent word sites G, H, K, and L in cyclical sequence.These words are averaged to produce a two-dimension-al interpolated surface (Fig. 7).

To control the fuel delivered to the engine, auxiliarydistributor contacts activate the synchronization circuit,

9. It's a gas. Prototype unit contains both ICs and discrete semi-conductors, but follow-on versions will replace analog with digitaldevices. Protrusions on the top of the unit are power resistors usedto set the time -constant of the solenoid fuel injectors.

which, by means of the steering circuit, turns on an ap-propriate group of injectors. At the same time, the volt-age -to -time converter commences its timing period.

This period is a direct function of the voltage sup-plied from the memory, but it's modified, depending onengine temperature, air temperature, and barometricpressure. At the end of the timing period, the steeringcircuit is reset, and the appropriate group is turned off,cutting the fuel supply to those particular cylinders.

Prototype has standard parts

The prototype unit specifically developed to controlthe fuel system for the test vehicle (Fig. 9) is 2.25 inchesby 6.75 in. by 10.25 in. All the components, as well assome discretes, are readily available ics; for instance, astandard MOS ROM has been programed with the infor-mation pertaining to the Triumph that had been ob-tained from engine tests. However, in production units,custom -designed integrated circuits would be used ex-clusively.

Although the system is in the early developmentphase, it has already shown considerable improvementover currently available fuel -control devices. Develop-ment is being continued to assess the full potential ofthis type of control system. The pollution figures fromthis unit have fallen short of meeting the new Federaland California requirements for 1975 (see Table 1), al-though it did perform within the limits of previous legis-lation. This unit has shown that accurate fueling underboth steady-state and transient conditions can reducepollutants and work in conjection with a total antipollu-tion system.

Current work is aimed at digitizing the analog speeu-measurement stage and the analog fuel -measurementstage after the memory. A digital interpolation tech-nique is being devised so that the only analog stage inthe system will be throttle -angle sensing. This shouldmean that all the electronics can be packed on onebipolar lc and one MOS IC. El

108

Take a bit of advice:use 16-bit converters carefullyTheir wide dynamic range and extremely fine resolution allow designsimplification, while improving performance and cutting costs.But take care in applying them, or their performance will be wasted.

by Wayne Marshall and Cyril Brown, Analog Devices Inc., Norwood, Mass.

A 16 -bit analog -to -digital or digital -to -analog con-verter that actually works is something of a moderntechnological marvel (See Part I of this two-part articlein the last issue of Electronics). True 16 -bit devices arenow available off -the -shelf, but at prices on the order of$1,000. The extremely fine resolution, monotonicity,high accuracy, linearity, and broad dynamic range thatcharacterize these converters make them ideal for awide variety of applications-from nuclear research toprecision function generation.

However, the unsophisticated user may waste the ad-vantages of the converter's tight performance specifica-tions unless he exercises extreme care in circuit design.Potential perils that must be considered include thermo-couple effects, voltage drops in short lengths of wire,low-level noise, radio -frequency interference, and even

millivolt common -mode signals. In short, factors of onlysecondary concern in the design and use of a 12 -bit con-verter can have an overwhelmingly adverse impact onthe operation of a 16 -bit unit.

To understand how and where these precision con-verters can be most effectively applied, it is helpful tobegin by studying their key characteristics, then exam-ining applications that these characteristics suggest, andfinally discussing methods to ensure that the deviceswill operate properly in a real -world environment.

Would you believe 65,536:1?

The most outstanding characteristic of a 16 -bit con-verter is its extremely wide dynamic range-that is, theratio of full-scale value to the value of the least -signifi-cant bit (LsB) it can handle. For a 16 -bit converter, the

-6 V

+8 V

+1 V

-0.5 V

+0.09 V

-6 V

+8 V

+1 V

°04°-0.5 V

+0.09 V

0

0

0

0

0

GAIN -SWITCHINGLOCIC

1

DIGITALLY ADJUSTEDOFFSET CURRENT-4-

10-BITA-D

CONVERTER

V

16 -BITA- D

CONVERTER

PROGRAMMABLECURRENTSOURCE

}16 -BITDIGITALOUTPUT

}DIGITALOUTPUT

1. Simplicity. Complexity of conventional gain -changing data -acquisition circuitry (top) is reduced by exploiting wide dynamic range of 16 -

bit converter (bottom). Bottom circuit is not only simpler, it's also more accurate, faster, and less expensive.

109

dynamic range is 216:1, or 65,536:1, or slightly morethan 96 dB. Thus a d -a converter with a full-scale out-put voltage of 10 v can change its output in steps assmall as 150 µV, approximately.

This wide dynamic range means that many naturallyoccurring variables-like light and sound levels-can behandled by these converters without range -switching orvariable -gain amplifiers. The high resolution implied bya wide dynamic range means that accurate ratio mea-surements can be made between two large -amplitudesignals that differ by only a small amount.

A true 16 -bit converter must have a linearity specifi-cation commensurate with its resolution. For 16 bits,this means that the maximum deviation from perfectlinearity should never exceed 0.0015% of full scale.Some applications that only need, say, 12 bits of resolu-tion are better served by a 16 -bit converter because ofits superior linearity.

Scintillation counters, ion chambers, and other nu-clear instruments, for example, are frequently used toseparate energy levels, charge levels, or particle mo-menta into well defined categories. The number of cate-gories that can be obtained is determined by the resolu-tion of the converter, but the uniformity of the category"widths" is determined by its linearity.

Monotonicity is the tough one

Monotonicity is the toughest single specification thata converter must meet, because it imposes a maximumlimit of ±1/2 LSB on the converter's step -to -step non -linearity. What is most difficult is preserving the con-verter's monotonicity over a useful temperature range.Monotonicity is particularly important in digital servosystems. If such a system is trying to find a null, and theconverter is non -monotonic around the balance point,the null balance will never be attained.

Speed is a converter parameter that can be all-impor-tant in one application and insignificant in another.Automatic testing systems and CRT displays obviouslydemand fast converters. However, many slower systemscan benefit from using high-speed a -d converters tofight noise. The trick: take several readings of the sameinput signal in quick succession and average them.Noise will be reduced proportionally to the square rootof the number of readings.

Accuracy's true meaning

The definition of accuracy is a semantic problem thattends to separate the purists-who think in terms of Na-tional Bureau of Standards certification-from the engi-neers and scientists with data to acquire or distribute.Since the best zener reference sources drift at some 5ppm/ °C, it is difficult to see how a converter can claimany reference to NBS certified standards. The reality isthat 16 -bit converters don't claim absolute accuracy to0.0015%, but offer 15 ppm resolution, linearity to 15ppm, and excellent stability, which can be exploited forvaluable results.

Absolute accuracy is certainly the critical specifica-tion for a digital voltmeter, which must make error -freereadings from a variety of unrelated sources. By con-trast, an a -d converter usually takes readings within agiven system, where relative voltage magnitudes, not ab-

16-BITD -A

CONVERTER

0TIME

COUNTER

CLOCK

VFC

cc

TIME

DIGITALCOMPAR-

ATOR

FREQUENCYCOUNTER

CHART RECORDER,PRINTER, ETC.

=.-

2. Function generator. D -a converter is used as ramp generator insetup for testing linearity of voltage -to -frequency converter.

solute ones, are required. Nonetheless, of course, therelative magnitudes must be measured with considera-bly certainty, but this requires high linearity if the con-verter uses a reference common to all sources, ratherthan absolute accuracy.

Closely related to a converter's accuracy is its stabilityover both time and temperature. This stability must becommensurate with the need for repeating measure-ments day after day without introducing discrepanciesbetween one day's results and the next. This is often arelative accuracy factor, since the absolute values ofreadings may be unimportant so long as they can be re-peated with precision. An example occurs in computer -output microfilming, where it may be necessary to up-date data on a piece of film that was originally recordeddays, or even months, earlier.

Eliminating range switching

What applications do the preceding characteristicssuggest? One obvious one is the elimination of range -switching and variable -gain amplifiers. An example ofsuch an application is in a multichannel data acquisi-tion system that must digitize analog signals developedby thermocouples, strain gauges, and other transducers(Fig. 1). The upper diagram of Fig. 1 shows the ratherelaborate arrangement required to switch amplifier gainautomatically from channel to channel to bring the low-level signals up to the converter's full-scale input range.The bottom illustration shows the dramatic reduction incomplexity provided by a 16 -bit converter.

But the 16 -bit machine does more than simply elimi-nate a few extra components. It can improve perform-ance and cut costs at the same time. To understandhow, suppose that the system of Fig. 1 requires thenominally 8-v input to be resolved within 1 millivoltover the range of 8 to 9 v. Since a 10 -bit converter with

110

a 10-v reference provides only slightly more than 100increments between 8 v and 9 v, preamplification by 10is needed to obtain the desired resolution.

How can a voltage between 8 v and 9 v be multipliedby 10 and still fit into the converter's 10-v amplituderange? The answer is to use an op amp and apply to itssumming junction a stable bias current having a magni-tude that is exactly sufficient to make the amplifier out-put zero when the 8-v input is applied. This will allowthe 1-v difference signal between 8 v and 9 v to be ex-panded to fill the converter's full 10-v span. In this way,the 10 -bit converter can resolve the amplified signalvariation to 1 part in 1,024, or slightly better than 1 my.However, in addition to a programable-gain amplifier,the auxiliary equipment now requires a bias source out-put to be fed into the amplifier's summing junction.

If the system involves many suppressed -zero readingslike the foregoing, the circuitry for generating the pre-cise biasing currents adds significantly to the complexityof the over-all conversion equipment; it also adds errorsources at the 10 -bit level, even though 1-mv resolutionof the expanded 1-v signal swing requires performanceat roughly the 13 -bit level.

Although a 16 -bit a -d converter costs appreciablymore than any 10 -bit counterpart, over-all cost ofequipment is considerably reduced, and performance isimproved: the 1-v interval between 8 v and 9 v is re-solved into more than 6,000 150-,uv steps, with 16 -bit,rather than 10 -bit, operation. Further, because it takesan automatically switched amplifier roughly 500 micro-seconds for each range change, the digitizing rate isgreatly enhanced by use of the 16 -bit converter, sincerange switching is eliminated.

A 16 -bit converter can be surprisingly useful in preci-sion function generation. Because the LSE is such a tinyfraction of the full-scale output of a 16 -bit d -a con-verter, the converter can be programed to produce a

3. Precise positioning. To approach the quality of a real photo-graph while using a TV -type raster -scanning approach, this CBSLaboratories electron -beam recording system uses a 16 -bit d -a con-

verter to set the beam's vertical position. Computer -enhanced photoof earth was taken from an orbiting satellite.

wide variety of output functions with a quantizing noiselevel approximately 96 dB below full scale.

The usefulness of such a function generator is illus-trated in Fig. 2. A setup is shown for testing the line-arity of precision voltage -to -frequency converters(vFCs). The automatic testing setup makes use of thed -a converter's excellent linearity as a ramp generator.Clock pulses accumulated in the up -down counter con-tinually update the d -a converter, feeding an analogvoltage ramp to the VFC undergoing the linearity test.By holding the quantizing noise of the converter's rampwaveform down to the -96-dB level, while simulta-neously ensuring linearity at least tenfold better thanthe voltage -to -frequency converter's own performancespecification, highly accurate calibration curves can beplotted.

The technique can also be applied to digital fre-quency synthesizers to produce output waveforms inwhich harmonically related noise is some 96 dB belowthe full-scale signal level. In such an application theconverter's output would be arranged for bipolar signalswings.

An undistorted view

Although CRT displays are widely used for presentingdata to human operators -in aircraft flight controls, in-teractive computer terminals, newsprint preparation,and so on -there are many additional applications forthe basic idea of using a deflected electron beam as atool for generating and displaying data that have notyet been fully developed.

For example, "photographs" of Mars and other plan-ets could be transmitted to earth -borne cam-eras, but they would have to undergo a considerableamount of digital massaging before emerging in con-ventional photographic format. Similarly, in geologicaland mineral explorations, where sonar and explosive re-verberations are echoed from inner -earth strata and re-corded for later transformation into pictures of the

COMPUTER

STOREDDATA

8 -BITDAC

16 BITDAC

SWEEPGENERATOR

BRIGHTNESSCONTROL

ELECTRONGUN

VERTICALPOSITIONCONTROL

HORIZONTALSWEEPS /I

/ -DEFLECTIONSYSTEM

PHOTOGRAPHICPLATE

111

earth's geological cross-section, the raw data is pro-cessed by a computer before being converted into animage.

In both these instances, the final picture is producedby exposing a piece of photographic film inside a vac-uum system to a digitally positioned electron beam.And it is often wise to use a 16 -bit d -a converter to posi-tion the beam, even if 16 bits of positioning are notneeded. The reason is a need for the 16 -bit converter'slinearity.

To see why this is so, consider the electron -beamrecording system marketed by CBs Laboratories (Fig. 3).This system uses a raster -scanning process not unlikethat of conventional television, but with eight bits ofbright -to -dark -gray shading, and digital control of thevertical position. To avoid visible distortion in the pic;tures it produces, the CBS system imposes tight toler-ances on the spacing between its horizontal scan lines.

Because a d -a converter's specifications allow an er-ror of up to ±1/2 LSB on its output amplitude, it would bepossible for successive horizontal scan lines to vary byas much as half a line width in their vertical positioningif the d -a converter's resolution were the same as thevertical resolution of the system. By using a 16 -bit con-verter in a system that requires only 12 bits of verticalresolution, CBS has cut the sloppiness with which its4,096 scan lines are positioned from ±1/2 line width to±-1 /32 line width. The quality of the picture that resultsis evident in Fig. 3.

Preserving the performance

For the user to get all of the performance of which a16 -bit converter is capable, he must avoid the inadver-tent introduction of errors on the order of 1 LSB. This isnot as easy as it sounds. For example, just 15 mA-thefull-scale output of some d -a converters-flowingthrough 2 feet of 18 -gauge wire will drop approximately165 luv, the equivalent of slightly more than 1 LSB.

To combat this problem, converter manufacturershave introduced four -terminal output -connection tech-niques (Fig. 4) that allow the user to include the imped-ance of the connecting circuit inside the amplifier'sfeedback loop. In short, feedback signals are derivedfrom the load, ensuring that the converter's output am-plifier places the desired voltage at the actual load ter-minals, and not merely at the converter's output pins.

In some applications-CRT displays and certain auto-matic test systems, for example-the output -voltagetransients produced by the d -a converter cannot be tol-erated. Deflection amplifiers tend to integrate theseglitch spikes, creating dc offsets that may persist formany microseconds, creating a noticeable distortion inany smooth CRT trace.

Similarly, semiconductor testers that use d -a con-verters to control applied voltages and currents cannottolerate glitches either. When these converters try tocreep up slowly on critical threshold voltages, largeglitch spikes can burst through the critical region, trig-ger erroneous responses, and even damage sensitive de-vices. In such applications, the use of a sample -and -hold deglitch module becomes mandatory.

The problem of getting data into a 16 -bit a -d con-verter is analogous to the difficulties in transmitting

E

FEED BACK CURRENTINDEPENDENT OF LOAD

LOADCURRENT

NEGLIGIBLEAMPLIFIERBIAS CURRENT

LOAD

4. Error reduction. Four -wire output connection eliminates errorscaused by voltage drop between converter output and load.

data from a 16 -bit d -a converter to a remote load. Be-cause the dc power for the a -d converter must travel afinite distance from the power supply, and perhaps passthrough printed -circuit board interconnections with rel-atively high resistances, there is likely to be a voltagedrop across the power cable and connectors that willraise the entire converter to some finite common -modevoltage. This voltage may easily exceed a few 15011vleast -significant bits. In the absence of some subtle pre-cautions in feeding analog data into the measuring cir-cuitry, the digital conversion is therefore likely to be inerror by many least -significant bits, because of this com-mon -mode effect alone. The solution is to use a high-performance differential input circuit, or buffer, at thea -d converter's front end. The common -mode rejectionof such a circuit then scales the common -mode voltagedown to negligible proportions.

Shot noise, 1/f noise, and thermal noise can only beheld to an irreducible minimum by careful circuit de-sign and component selection. To keep the noise down,extreme care must be taken with the wiring associatedwith the converter. In particular, analog and digitalgrounds should be kept separate to prevent the leakageof large digital pulses onto the analog lines.

Because of high source impedances and other con-straints imposed by various signal sources, it is muchmore difficult to minimize noise effects when measuring,instead of generating, precise analog values. In fact, the16 -bit a -d converter is vulnerable to radio -frequency in-terference, 60 -Hz pickup, feedthrough from digitalpower -supply transients, and even magnetic couplingfrom nearby motors and transformers. Therefore, evenif all possible care has been taken to minimize circuitnoise, it still may be necessary to use the data -averagingtechnique mentioned earlier. This technique exploitsthe converter's high speed by taking several readings ofthe same input data. In this way, averaging techniqueswill yield a reading that approximates more closely thetrue analog input. (Noise is reduced in proportion to thesquare root of the number of readings.)

112

Tables shorten design timefor active filtersBoth low-pass and high-pass Butterworth -Thomson filters, which use eitherunity -gain or infinite -gain amplifiers, can be designed from tables ofnormalized component values; filter orders as high as 10 are covered

by Farouk Al -Nasser, Honeywell Test Instruments division, Denver, Colo.

El As the lc operational amplifier grows steadily betterand cheaper, active filters are becoming more popularthan passive. Their performance is superior and morepredictable, they have no need for impedance match-ing, nor are nonlinear inductor properties a problem,since the active filter uses an op amp and an associatedRC network to simulate inductance.

But perhaps the greatest attraction that active filtershold for the designer is that they lend themselves to abuilding-block approach. Being inherently isolated,they can be cascaded to realize higher -order filter func-tions, and the passive -component values needed to im-plement each filter block or section can be computed ina normalized form and tabulated. This also means thatactive -filter design can be reduced to a matter of look-ing up tables, once the engineer has determined thetype of filter required and chosen a filter circuit.

Selecting the right type of active filter depends on thesignal being processed, as well as the time- and fre-quency -domain properties that the filtered signal musthave. The Butterworth type of filter, for instance, exhib-its flat passband amplitude characteristics up to the cut-off frequency, a rolloff of -6n decibels per octave be-yond cutoff (where n is the order of the filter), andnonlinear phase characteristics that lead to a nonlineargroup delay. On the other hand, the Thomson filter(also referred to as the normalized Bessel filter) has alinear phase response in the passband, and an ampli-tude response that is not as flat as that of the But-terworth filter in the passband and stopbands. Groupdelay for the Thomson filter is constant up to cutoff.

In some cases, a compromise characteristic that tradesoff the best properties of the Butterworth and theThomson filter is needed. The result is the class of But-terworth -Thomson filter. Its characteristics varysmoothly between the maximally flat amplitude of theButterworth filter and the maximally flat envelope de-lay of the Thomson filter.

Butterworth -Thomson filter properties

In the complex frequency plane, the poles of the But-terworth -Thomson filter lie between those of the But-terworth and Thomson types, as shown in Fig. 1. Theactual pole location is denoted by P, the length of thevector to the pole by R, and the angle of this pole vectorby O. Letting subscript BT represent the Butterworth -Thomson filter, subscript B the Butterworth filter, and

subscript T the Thomson filter, the equation that de-fines the location of a Butterworth -Thomson pole canbe written as:

PBT = RTmeXPH(OB - MOB - 9T))]where m is a parameter that varies between 0 and 1.When m = 0, the Butterworth -Thomson poles are thesame as those of the Butterworth filter:

PET = eXP(JOB) = PBWhen m = 1, the Butterworth -Thomson and theThomson poles are the same:

PBT = RTeXP(JOT) = PTFrom these equations, the pole locations, the magnitudeand angle of the pole vectors, and the filter Q factor canbe computed for various values of parameter m. Tables1 through 6 list this data for m = 0, 0.2, 0.4, 0.6, 0.8,and 1 for both even and odd filter orders from 2 to 10.Data for intermediate values of parameter m can be ob-tained by interpolation.

From the general transfer function of the But-terworth -Thomson filter, which can be found in refer-ence literature, both the frequency- and time -domaincharacteristics can be obtained. Graphs 1 and 2 relatefilter gain to normalized frequency for m = 0.4 andm = 0.8, respectively. The group delay characteristics,again for m = 0.4 and m = 0.8, are drawn in Graphs 3and 4. For any order filter, in either the frequency ortime domain, the Butterworth -Thomson filter changessmoothly from the Butterworth to the Thomson charac-teristics, as parameter m varies from 0 to 1.

Active -filter circuits synthesize a second -order trans-fer function with one or more op amps and an RC net -

1. Pole locations. Butterworth -Thomson fitter compromises the flatamplitude of the Butterworth filter with the flat envelope delay of theThomson filter Its !Soles (PBT) are located between those (PB) of theButterworth filter and those (PT) of the Thomson filter.

113

TABLE 1

POLE LOCATIONS FOR m = 0

Order Real Imaginary MagnitudeAngle from

neg. realaxis (deg.)

0factor

2 -0.70711 0.70711 1.00000 45.00000 0.70711

3 -1.00000 0.00000 1.00000 0.00000-0.50000 0.86603 1.00000 60.00000 1.00000

4 -0.92388 0.38268 1.00000 22.50000 0.54120-0.38268 0.92388 1.00000 67.50000 1.30656

5 -1.00000 0.00000 1.00000 0.00000-0.80902 0.58779 1.00000 36.00000 0.61803-0.30902 0.95106 1.00000 72.00000 1.61803

6 -0.96593 0.25882 1.00000 15.00000 0.51764-0.70711 0.70711 1.00000 45.00000 0.70711-0.25882 0.96593 1.00000 75.00000 1.93185

7 -1.00000 0.00000 1.00000 0.00000-0.90097 0.43388 1.00000 25.71430 0.55496-0.62271 0.78245 1.00000 51.48570 0.80294-0.22252 0.97493 1.00000 77.14290 2.24698

8 -0.98079 0.19509 1.00000 11.25000 0.50980-0.83147 0.55557 1.00000 33.75000 0.60134-0.55557 0.83147 1.00000 56.25000 0.89998-0.19509 0.98079 1.00000 78.75000 2.56292

9 -1.00000 0.00000 1.00000 0.00000-0.93969 0.34202 1.00000 20.00000 0.53209-0.76604 0.64279 1.00000 40.00000 0.65270-0.50000 0.86603 1.00000 60.00000 1.00000-0.17365 0.98481 1.00000 80.00000 2.87939

10 -0.98769 0.15643 1.00000 9.00000 0.50623-0.89101 0.45399 1.00000 27.00000 0.56116-0.70711 0.70711 1.00000 45.00000 0.70711-0.45399 0.89101 1.00000 63.00000 1.10135-0.15643 0.98769 1.00000 81.00000 3.19623

TABLE 3

POLE LOCATIONS FOR m = 0.4

Order Real Imaginary MagnitudeAngle from

neg. realaxis (deg.)

Ct

factor

2 -0.77715 0.62932 1.00000 39.00000 0.64338

3 -0.97622 0.00000 0.97622 0.00000-0.60258 0.81318 1.01211 53.46100 0.83981

4 -0.91747 0.33698 0.97740 20.16790 0.53266-0.49363 0.89617 1.02312 61.15300 1.03633

5 -0.96990 0.00000 0.96990 0.00000-0.82884 0.52982 0.98371 32.58790 0.59342-0.42026 0.94279 1.03222 65.97430 1.22806

6 -0.94334 0.22850 0.97062 13.61640 0.51446-0.74738 0.65067 0.99093 41.04320 0.66294-0.36750 0.97258 1.03970 69.30030 1.41455

7 -0.96698 0.00000 0.96698 0.00000-0.89375 0.38787 0.97429 23.46010 0.54506-0.67773 0.73250 0.99794 47.22410 0.73623-0.32766 0.99328 1.04593 71.74330 1.59604

8 -0.95191 0.17265 0.96744 10.28030 0.50816-0.83984 0.50312 0.97901 30.92440 0.58286-0.62016 0.79008 1.00440 51.87040 0.80979-0.29645 1.00853 1.05120 73.61980 1.77299

9 -0.96530 0.00000 0.96530 0.00000-0.92061 0.30503 0.96982 18.33180 0.52673-0.78804 0.58929 0.98401 36.78860 0.62434-0.57134 0.83319 1.01026 55.56030 0.88411-0.27128 1.02026 1.05571 75.11010 1.94581

10 -0.95561 0.13869 0.96562 8.25786 0.50524-0.88324 0.40843 0.97310 24.81720 0.55087-0.74041 0.65560 0.98895 41.52340 0.66784-0.52990 0.86636 1.01557 58.54810 0.95826-0.25052 1.02959 1.05963 76.32480 2.11490

work. First -order transfer functions, on the other hand,are realized with a simple passive resistor -capacitorcombination, so that an active third -order filter is ac-tually an active second -order circuit cascaded with apassive first -order RC network.

To realize high -order filters, second -order and/orthird -order filter sections are cascaded. If the filter orderis even, only second -order sections are. used. For ex-ample, a sixth -order filter is obtained when three sec -

TABLE 2

POLE LOCATIONS FOR m = 0.2

Order Real Imaginary MagnitudeAngle from

neg. realaxis (deg.)

Gfactor

2 -0.74314 0.66913 1.00000 42.00000 0.67282

3 -0.98804 0.00000 0.98804 0.00000-0.55189 0.84115 1.00604 56.73050 0.91145

4 -0.92089 0.35967 0.98863 21.33390 0.53678-0.43822 0.91164 1.01150 64.32650 1.15409

5 -0.98484 0.00000 0.98484 0.00000-0.81940 0.55883 0.99182 34.29390 0.60521-0.36431 0.94842 1.01598 68.98710 1.39440

6 -0.95464 0.24348 0.98520 14.30820 0.51601-0.72778 0.67917 0.99546 43.02160 0.68390-0.31255 0.97057 1.01966 72.15020 1.63120

7 -0.98335 0.00000 0.98335 0.00000-0.89756 0.41069 0.98706 24.58720 0.54986-0.65070 0.75798 0.99897 49.35490 0.76761-0.27429 0.98524 1.02271 74.44310 1.86431

8 -0.96628 0.18372 0.98359 10.76510 0.50896--0.83600 0.52926 0.98945 32.33720 0.59178-0.58822 0.81141 1.00220 54.06020 0.85188-0.24483 0.99562 1.02528 76.18490 2.09390

9 -0.98250 0.00000 0.98250 0.00000-0.93021 0.32331 0.98480 19.16590 0.52934-0.77746 0.61608 0.99197 38.39430 0.63795-0.53590 0.85034 1.00512 57.78010 0.93779-0.22142 1.00334 1.02748 77.55510 2.32017

10 -0.97154 0.14743 0.98266 8.62893 0.50572-0.88731 0.43102 0.98646 25.90860 0.55587-0.72420 0.68154 0.99446 43.26170 0.68660-0.49204 0.87947 1.00775 60.77410 1.02406-0.20237 1.00930 1.02938 78.66240 2.54337

TABLE 4

POLE LOCATIONS FOR m = 0.6

Order Real Imaginary MagnitudeAngle from

neg. realaxis (deg.)

CIfactor

2 -0.80902 0.58779 1.00000 36.00000 0.61803

3 -0.96454 0.00000 0.96454 0.00000-0.65189 0.78218 1.01822 50.19150 0.78098

4 -0.91363 0.31462 0.96629 19.00180 0.52882-0.54872 0.87744 1.03489 57.97950 0.94300

5 -0.95519 0.00000 0.95519 0.00000-0.83734 0.50078 0.97566 30.88180 0.58260-0.47673 0.93409 1.04871 62.96140 1.09989

6 -0.93203 0.21388 0.95625 12.92460 0.51300,0.76590 0.62165 0.98643 39.06480 0.64397-0.42357 0.97184 1.06013 66.45050 1.25144

7 -0.95088 0.00000 0.95088 0.00000-0.88954 0.36543 0.96168 22.33300 0.54055-0.70377 0.70606 0.99690 45.09330 0.70826-0.38258 0.99892 1.06968 69.04350 1.39798

8 -0.93769 0.16189 0.95156 9.79540 0.50740-0.84300 0.47717 0.96868 29.51160 0.57454-0.65132 0.76748 1.00660 49.68070 0.77274-0.34991 1.01938 1.07777 71.05470 1.54005

9 -0.94841 0.00000 0.94841 0.00000-0.91089 0.28716 0.95508 17.49770 0.52426-0.79779 0.56242 0.97611 35.18290 0.61176-0.60627 0.81458 1.01543 53.34040 0.83744-0.32320 1.03545 1.08472 72.66520 1.67811

10 -0.93990 0.13020 0.94887 7.88679 0.50477-0.87879 0.38623 0.95992 23.72580 0.54616-0.75575 0.62934 0.98348 39.78510 0.65066-0.56752 0.85167 1.02344 56.32220 0.90168-0.30089 1.04844 1.09076 73.98720 1.81256

and -order sections are cascaded. Odd -order filters areimplemented by cascading a third -order section withone or more second -order sections. For a seventh -orderfilter, therefore, one third -order section is cascaded withtwo second -order sections.

Different circuits can be used to realize the basic sec-ond -order or third -order active filter section. Two popu-lar configurations, which require only one op amp persection, are the positive -feedback and the multiple -

114

TABLE 5

POLE LOCATIONS FOR m = 0.8

Order Real Imaginary MagnitudeAngle from

neg. realaxis (deg.)

Qfactor

2 -0.83867 0.54464 1.00000 33.00000 0.59618

3 -0.95300-0.69963

0.000000.74822

0.953001.02436

0.0000046.92200 0.73207

4 -0.90939-0.60331

0.292600.85544

0.955311.04678

17.8357054.80600

0.525240.86753

5 -0.94071-0.84491-0.53356

0.000000.471730.92225

0.940710.967681.06547

0.0000029.1757059.94860

0.572650.99845

6 -0.92071-0.78333-0.48063

0.199620.592130.96824

0.942100.981951.08097

12.2329037.0863063.60070

0.511620.626781.12454

7 -0.93505-0.88496-0.72878-0.43895

0.000000.343360.678711.00204

0.935050.949230.995881.09397

0.0000021.2059042.9624066.34370

0.536320.683251.24611

8 -0.92361-0.84549-0.68166-0.40517

0.151420.451430.743671.02805

0.935950.958461.008811.10501

9.3105428.0988047.4909068.48960

0.506680.566810.739971.36362

9 -0.93181-0.90106-0.80671-0.64063-0.37716

0.000000.269710.535510.794531.04877

0.931810.940560.968271.020631.11453

0.0000016.6636033.5772051.1205070.22020

0.521920.600140.796581.47752

10 -0.92441-0.87399-0.77020-0.60482-0.35349

0.121960.364420.602760.835421.06572

0.932420.946920.978031.031371.12281

7.5157222.6344038.0468054.0963071.64960

0.504330.541720.634910.852621.58817

feedback active filters. The first uses the op amp in itsnoninverting unity -gain mode, while the second uses itas an infinite -gain device.

The cutoff frequency and the Q factor of the positive -feedback filter are more sensitive to passive componenttolerances and amplifier gain variations than the mul-tiple -feedback filter. However, for the same cutoff fre-quency, the positive -feedback version does not demandas much bandwidth from the amplifier. Additionally,both the second- and third -order positive -feedback fil-ters require one fewer resistor than the same -order mul-tiple -feedback filters.

Low-pass Butterworth -Thomson filters

A second -order low-pass filter section using a unity -gain amplifier and another using an infinite -gain ampli-fier are shown in Fig. 2a and 2b, respectively. The cir-cuits in Fig. 2c and 2d are the comparable third -orderlow-pass filter sections.

The transfer function of the second -order low-passpositive -feedback filter of Fig. 2a can be written as:

G(s) = 1 /[s2C1C212.112.2 + sC2(Ri + R2) + 1]where s is the Laplace transform variable. For the sec-ond -order low-pass multiple -feedback filter of Fig. 2b:

G(s) = (-R3/R1)/[s2R2R3C1C2+ sC2(R2 + R3+ R2R3/Ri) + 1]

For the third -order positive -feedback filter of Fig. 2c:G(s) = 1 /[s3C1C2C3R1R2R3

+ s2(C2C3R3(Ri + R2) + CiC3Ri(R2 + R3))+ s(C3(Ri + R2 + R3) + CIRO + 1]

For the third -order multiple -feedback filter of Fig. 2d:G(s) = 1 /[s3R1R2R3C1C2C3

+ s2((R2R3 + R3R4 + R2R4)(RiCiC3/R4)+ (RI +R2)R3C1C3)+ s((R3R4 + R2R3 + R2R4 + RiR3 + R IRO(C3/R4)+ (RIR2Ci/R4)) + (RI R 2)/R4]

TABLE 6

POLE LOCATIONS FOR m = 1

Order Real Imaginary MagnitudeAngle from

neg. realaxis (deg.)

0factor

2 -0.86603 0.50000 1.00000 30.00000 0.57735

3 -0.94160-0.74564

0.000000.71137

0.941601.03054

0.0000043.65250 0.69105

4 -0.90476-0.65721

0.270920.83016

0.944451.05882

16.6697051.63250

0.521930.80554

5 -0.92644-0.85155-0.59059

0.000000.442720.90720

0.926440.959761.08250

0.0000027.4696056.93570

0.563540.91646

6 -0.90939-0.79965-0.53855

0.185700.562170.96169

0.928160.977491.10222

11.5411035.1079060.75080

0.510320.611191.02331

/ -0.91949-0.88000-0.75274-0.49669

0.000000.321670.650471.00251

0.919490.936950.994851.11881

0.0000020.0787040.8316063.64390

0.532360.660821.12626

8 -0.90968-0.84733-0.71114-0.46217

0.141240.425900.718651.03439

0.920580.948341.011031.13294

8.8256726.6861045.3011065.92450

0.505990.559610.710851.22567

g -0.91550-0.89113-0.81480-0.67436-0.43314

0.000000.252660.508580.773051.06007

0.915500.926260.960501.025861.14515

0.0000015.8295031.9715048.9007067.77530

0.519710.589410.760611.32191

11) -0.90913-0.86885-0.78377-0.64175-0.40832

0.113960.343000.575910.817581.08127

0.916250.934100.972611.039371.15580

7.1446521.5430036.3085051.8703069.31190

0.503910.537550.620470.809791.41531

Tables 7 and 8 give the normalized capacitor valuesthat satisfy these transfer functions when all the resist-ors have the same value. Table 7 lists the capacitancesfor the positive -feedback Butterworth -Thomson filterfor m = 0.2, 0.4, 0.6, and 0.8 for both even and odd fil-ter orders from 2 to 10.for the multiple -feedback Butterworth -Thomson filter.Interpolation yields the normalized capacitor values forintermediate values of parameter m.

How to use the tables and graphs

Now that all the data needed to put an active But-terworth -Thomson filter together is at hand, a generaldesign procedure can be outlined. Of course, the filtercharacteristics that will satisfy the specifications mustfirst be selected. This is done by choosing the best valueof parameter m, as well as the necessary filter order,from Tables 1 through 6 and Graphs 1 through 4. (Thedesired filter operating frequency is set equal to the nor-malized frequency of 1 radian/second.)

If a low-pass function is required, the first steps are to.find the proper normalized capacitor values for each fil-ter section from Table 7 or 8, depending on the circuitpreferred, and then choose a convenient value of resist-ance. (A different resistance value may be assigned foreach section.) Actual capacitor values (Ca) are found bya simple division:

Ca = Ca/coaRwhere Ca is the normalized capacitor value, coo is the ac-tual filter operating frequency, and R is the resistancevalue chosen for a given section.

High-pass filter functions synthesized with the posi-tive -feedback circuit can also be designed from the nor-malized capacitor values given for low-pass filters inTable 7. Since the positions of resistors and capacitorscannot be interchanged for the multiple -feedback cir-

115

( ,I(APii )

GAIN FOR m= 0.4

NORMALIZED FREQUENCY (RADIANS/s) -4.0.1

10

0

-0

2

_

20

n = 2 \0.2

-40 03a 4

.;7

n = 6

- %-

23.

ft-60 cocn 6

11

n

n.8

10 ,...s.- *1

-808

10

I -n

, ..

--100

GRAPH 3

10

5

4

GROUP DELAY1FOR m = 0.4

Ad\

02 04 06 0.8 1.2 14 16 18

NORMALIZED FREQUENCY (RADIANS/s)

cuit, Table 8 cannot be used for this high-pass filter. Fig.3 shows the two active filter circuits that correspond tothe low-pass filters of Fig. 2a and 2c. The second -orderhigh-pass positive feedback filter is illustrated in Fig.3a, and the third -order version of this filter is drawn inFig. 3b.

Designing the filter

The design procedure for an active high-pass But-terworth -Thomson filter is similar to the one for a low-pass filter. After the correct value for parameter m andthe desired filter order have been selected, the norma-lized capacitor values are picked from Table 7. Norma-lized resistor values are then computed:

R. = 1/C.A convenient value is next chosen for capacitor C; a dif-ferent value of C may be chosen for each filter section.The actual resistor values (Ra) can then be found fromthe normalized resistor values:

Ra = Rn/cooC

likAI'll :,

GAIN FOR m = ILO

NORMALIZED FREQUENCY (RADIANS s) ---4.0.1 10 0

----`..s,

Nk, 20L ti-1

Z -6 n 8 dillikial 1NIngillMI 60 zL.,

n=10 Iiii.-lit

z

-8

-10010

-12

.1 s

120

GRAPH 4

10

5

4

GROUP DELAY FOR m =0.8

^=2

0.2 04 06 08 1 12 14 16 18

NORMALIZED FREQUENCY (RADIANS/s)

where ca. is the actual filter operating frequency.A few specific examples will clarify the general proce-

dures just outlined.A fourth -order multiple -feedback low-pass But-

terworth -Thomson filter is needed with m = 0.4 andwo = 10,000 radians/second. From table 8, the norma-lized capacitor values can be obtained. For the first fil-ter section:

C1. = 2.8812 and C2. = 0.3633For the second section:

C1. = 1.4147 and C2n = 0.6753Setting the resistors for both sections equal to 1,000ohms, the denormalizing conversion factor becomes:

wait = 104(103) = 107The actual capacitor values can then be computed. Forthe first section:

CI = 2.8812/107 = 0.28812 microfaradC2 = 0.3633/107 = 0.3633p.F

And for the second section:C1 = 1.4147/107 = 0.14147 µF

1 1 6

C2 = 0.6753/107 = 0.06753 itifThe component values needed to build the filter arenow known.

A fifth -order positive -feedback high-pass But-terworth -Thomson filter must be designed for m = 0.2and coo = 1,000 radians/second. The normalized ca-pacitor values are found in Table 7. For section 1:

C1, = 1.3369, C2,, = 1.7467, and C3,, = 0.4276For section 2:

Clo = 2.7449 and C2,, = 0.3529The normalized resistor values for section 1 become:

R1,, = 1/1.3669 = 0.732R2,, = 1/ 1.7467 = 0.573R3n = 1/0.4276 = 2.34

And for section 2:Rlo = 1/2.7449 = 0.365R2 = 1/0.3529 = 2.84

Choosing a convenient value for capacitor C -let C =0.1µF = 10-7 farads -allows the denormalizing conver-sion factor for the resistances to be calculated:

woC = 103(10-7) = 10-4The actual resistor values for section 1 can then be read-ily determined:

R1 = 0.732/10-4 = 7.32 kilohmsR2 = 0.573/10-4 = 5.73 kilohmsR3 = 2.34/10-4 = 23.4 kilohms

And for section 2:R1 = 0.365/10-4 = 3.65 kilohmsR2 = 2.84/10-4 = 28.4 kilohms

The filter can now be assembled from the computedcomponent values.

Practical considerationsFor the most part, literature on active filter design

supposes the op amp to be ideal -that is, it is assumedto have infinite gain, infinite input impedance, and zerooutput impedance. But when operating frequency be-

comes high and filter Q large, the finite gain -bandwidthproduct of an op amp, as well as its sensitivity parame-ters, can no longer be neglected.

A common assumption is to consider the actual opamp gain -bandwidth product, fa, to be at least an orderof magnitude larger than the desired filter cutoff fre-quency, fo. However, for a second -order positive -feed-back filter:

fa/fo = - foa/fo) (1)where Q is the desired filter Q, and foa is the actual filtercutoff frequency. This frequency ratio can also be ex-pressed solely in terms of filter Q:

fa/fo = Q/(Qa/Q - 1) (2)where Qa is the actual Q. The same relationships can bedeveloped for the second -order multiple feedback filter,which uses an infinite -gain as opposed to a unity -gainamplifier:

fa/fo = 1.5Q/(1 - foa/fo) = 1.5Q/(Qa/Q - 1)Suppose that the actual cutoff frequency, foa, must

deviate less than 5% from the desired cutoff frequency,fo, and that actual filter Q, Qa, must be within 2% of thedesired filter Q. Using Eq. 1 yields:

fa/fo must be greater than Q/0.05 = 20Qor, from Eq. 2:

fa/fo must be greater than Q/0.02 = 50QSince the latter condition is the more stringent, it is theone that must be obeyed.

If a fourth -order filter, with m = 0.2 and fo = 1,000hertz, is being designed, Table 2 indicates that Q =0.53678 for section 1 and Q = 1.15409 for section 2.The gain -bandwidth product of the amplifier for thesecond section must satisfy the condition:

fa must be greater than 50Qfo = 5(1.15409)(103)fa must be greater than 57.7045 kilohertz

to achieve less than 2% accuracy in the Q of the filter. Amultiple -feedback filter would require even more am-plifier bandwidth, because:

2. Low-pass filters. Second -order low-pass filter can be implemented with unity -gain amplifier in positive -feedback circuit (a), or with infinite -

gain amplifier in multiple -feedback circuit (b). Third -order filters (c) and (d) are second -order filters that have been cascaded with first -orderRC network at input end. Tables 7 and 8 give normalized capacitor values for these low-pass filters having orders up to 10.

117

TABLE

NORMALIZED CAPACITOR VALUES

7

USING UNITY -GAIN AMPLIFIERSm = 0.2 I m = 0.4 I m = 0.6

I m = 0.8Order Section1

C(1) C(2) C(3) I C(1) C(2) C(3) I C(1) C(2) C(3) I C(1) C(2) C(3)2 1 1.3456 0.7431 I 1.2868 0.7771 I 1.2361 0.8090 I 1.1924 0.83873 1 1.3950 3.2775 0.2190 I 1.3963 3.2851 0.2185 I 1.3963 3.2853 0.2185 I 1.3951 3.2779 0.21894 1 1.0859 0.9422 1.0900 0.9604 1.0945 0.9785 1.0996 0.9965

2 2.2819 0.4283 2.0258 0.4716 1.8224 0.5123 1.6575 0.55065 1.3669

2 74491.74670 35291

0.4276 1.37962 37%

1.76510.3944

0.4234 I 1.39222.0976

1.78410.4335

0.4192 1.40481.8742

1.80360.4700

0.4150

6 1 1.0475 0.9835 1.0601 1.0013 1.0729 1.0193 1.0861 1.03742 1.3741 0.7344 1.3380 0.7611 1.3057 0.7871 1.2766 0.81243 3.1995 0.3006 2.7211 0.3400 2.3609 0.3769 2.0806 0.4113

7 1 1.3546 1.5423 0.4920 1.3726 1.5601 0.4860 1.3909 1.5791 0.4799 1.4094 1.5992 0.47382 1.5368 0.6520 1.4755 0.6805 1.4209 0.7081 1.3722 0.73483 3.6458 11_2622 3 0519 0.2995 2.6138 0.3344 2.2782 0.3668

8 1 1.0349 0.9988 I 1.0505 1.0171 1.0664 1.0356 1.0827 1.05442 1.1962 0.8539 1.1907 0.8762 1.1862 0.8984 1.1827 0.92043 1.7000 0.5856 1.6125 0.6147 1.5353 0.6428 1.4670 0.66984 4.0845 0.2329 3.3733 0.2683 2.8578 0.3012 2.4681 0.3318

9 1 1.3487 1.4715 0.5197 1.3696 1.4889 0.5127 1.3908 1.5077 0.5056 1.4124 1.5279 0.49842 1.2862 0.7901 1.2690 0.8139 1.2535 0.8373 1.2396 0.86043 1.8660 0.5305 1.7503 0.5598 1.6494 0.5880 1.5610 0.61504 4.5162 0.2097 3.6863 0.2434 3.0941 0.2747 2.6514 0.3036

10 1 1.0293 1.0061 1.0465 1.0249 1.0639 1.0439 1.0818 1.06332 1.1270 0.9118 1.1322 0.9327 1.1379 0.9537 1.1442 0.97473 1.3808 0.7323 1.3506 0.7570 1.3232 0.7814 1.2984 0.80524 2.0324 0.4845 1.8871 0.5138 1.7621 0.5418 1.6534 0.56865 4.9415 0.1910 3.9918 0.2231 3.3235 0.2529 2.8289 0.2804

TABLE 8

NORMALIZED CAPACITOR VALUES USING INFINITE -GAIN AMPLIFIERSm = 0.2 I m = 0.4 I m = 0.6 I m = 0.8Order Section

C(1) C(2) C(3) I C(1) C(2) C(3) I C(1) C(2) C(3) I C(1) C(2) C(3)2 1 2 2294 0 4485 I 2 3314 0.4289 2.4271 0.4120 I 2.5160 0.39753 1 1_3495 5.2591 0.1405 I 1.3423 5.1960 0.1419 1.3337 5.1220 0.1436 I 1.3236 5.0383 0.14574 1 2.8266 0.3620 2.8812 0.3633 2.9355 0.3648 I 2.9894 0.3665

2 1.2850 0.7606 1.4147 0.6753 1.5370 0.6075 1.6518 0.55255 1 1.2640 2.9081 0.2771 1.2713 2.9226 0.2757 1.2785 2.9372 0.2742 1.2857 2.9520 0.2728

2 1.0588 0.9150 1.1833 0.7932 1.3004 0.6992 1.4100 0.6247

6 1 2.9506 0.3492 3.0039 0.3534 3.0578 0.3576 3.1121 0.36202 2.2033 0.4580 2.2833 0.4460 2.3613 0.4352 2.4372 0.4255'1 0 90111 1.0665 1.0199 0.9070 1.1306 0.7870 1.2340 0.6935

7 1 1.2297 2.7070 0.3202 1.2436 2.6252 0.3174 1.2578 2.6444 0.3146 1.2722 2.6647 0.31172 1.9561 0.5123 2.0416 0.4918 2.1244 0.4736 2.2045 0.45743 0.7867 1.2153 0.8986 1.0173 1.0031 0.8713 1.1004 0.7594

8 1 2.9964 0.3450 3.0512 0.3502 3.1067 0.3555 3.1631 0.36092 2.5618 0.3987 2.6287 0.3969 2.6952 0.3954 2.7611 0.39423 1.7569 0.5667 1.8442 0.5375 1.9284 0.5118 2.0094 0.4890d fl AQ87 1 1E1 c n 90411 1 1944 0 9037 0.9526 0.9955 0.8227

9 1 1.2138 2.5053 0.3388 1.2311 2.5240 0.3353 1.2487 2.5440 0.3318 1.2667 2.5654 0.32822 2.3703 0.4287 , 2.4416 0.4230 2.5120 0.4178 2.5813 0.41323 1.5914 0.6220 1.6794 0.5834 1.7640 0.5498 1.8450 0.52034 0 6792 1 5054 0.7302 1.2288 0.8241 1.0314 0.9109 0.8838

10 1 3.0184 0.3431 3.0746 0.3488 3.1317 0.3546 3.1898 0.36062 2.7355 0.3757 2.7982 0.3774 2.8611 0.3793 2.9241 0.38143 2.1969 0.4603 2.2711 0.4502 2.3441 0.4411 2.4156 0.43284 1.4535 0.6775 1.5414 0.6290 1.6255 0.5874 1.7058 0.55115 0.5729 1.6472 0.6693 1.3306 0.7587 1.1078 0.8412 0.9430

fa must be greater than 1.5(50)Qfofa must be greater than 1.5(50)(1.15409)(103)fa must be greater than 86.5568 kHz

The infinite -gain amplifier, however, has lower sensi-tivity parameters than the unity -gain amplifier. 0BIBLIOGRAPHYFarouk Al -Nasser, Tables Speed Design of Low -Pass Active Filters," EDN, March 15,1971.Aram Budak, Active Network Synthesis," class notes, Colorado State University, 1971.A. Budak and D. Petrela, Frequency Limitations of Active Fitters Using Operational Ampli-fiers, IEEE Transactions on Circuit Theory, Vol. CT -19, No. 4, July, 1972.R. Golden and J. Kaiser, Root and Delay Parameters for Normalized Bessel and But-terworth Low -Pass Transfer Functions, IEEE Transactions on Audio and Electrocoustics,Vol. AU -19, No. 1, March, 1971.Analysis and Synthesis of Transitional Butterworth -Thomson Fitters and Bandpass Ampli-

fiers," RCA Review, Vol. 18, March, 1957. pp. 60-94.

3. High-pass filters. Circuits (a) and (b) correspond to low-passconfigurations on Fig. 2a and 2c, but provide high-pass function. Re-ciprocals of normalized capacitor values in Table 7 are used to de-termine resistor values for these high-pass filters.

1 1 8

Instrumentation amplifierconditions computer inputsTwo -stage amplifier detects more than 100 multiplexed signalsat computer -speed scanning rates with minimum noise over widefrequency range; signal levels can range from microvolts to volts

by Thomas C. Lyerly, IBM General Systems Division, Boca Raton, Fla.

Since the job of data gathering has become so com-plex that computers are needed to process measurementinformation, increasingly stringent performance re-quirements are being placed on the instrumentationamplifier. A single instrumentation amplifier mustfrequently accept more than 100 multiplexed signalswith levels ranging from a few microvolts to severalvolts. The amplifier must also reject unwanted noise sig-nals from dc to hundreds of megahertz, as well as pro-vide a noise -free, properly scaled, single -ended outputsignal that can be sampled quickly for processing.

Precision low-level signal conditioning can beachieved with a two -stage amplifier that employs cas-code transistor pairs, degenerative feedback, and bal-anced frequency compensation to provide exceptionalgain -bandwidth performance without gain -adjustmentpotentiometers. Even in noisy environments, this ampli-fier can detect microvolt signals at high scanning rates.It can also be adapted for programable gain selection.

The environment for the precision amplifier is the

computer analog input subsystem, such as the typicalone shown in Fig. 1 for the IBM System/7 computer. Asmany as 128 analog input signals may be connectedthrough single -pole low-pass filters to the multiplexer,which is made up of p -channel MOSFET switches. Themultiplexer can handle up to eight parallel groups ofsignals, with each group consisting of up to 16 parallelchannels.

The differential output of the multiplexer is con-nected to an instrumentation amplifier through a baluntransformer that serves as a high -frequency noise filterfor the amplifier. Multiplexed analog input signals mustbe accurately processed by the amplifer at scanningrates as fast as 20 kilohertz without any adverse effectsfrom noise sources that are both external and internal tothe analog input subsystem.

External noise may be separated into two types-common-mode, and normal- or differential -mode sig-nals. Differential -mode noise is the easier to reject. Itcan be filtered by passive low-pass networks located at

LOW-PASSNORMAL -MODE

FILTER

ANALOG -AA/V-4INPUT

COMMON -MODEINPUT

MULTIPLEXER

DIGITALINPUTS

CHANNELDRIVER

GROUPDRIVER

it

15

PARALLELCHANNELS

,s,

BALUN

INSTRUMENTATIONAMPLIFIER

UP TO HIGH -FREQUENCY7 GROUPS OF COMMON -MODE16 CHANNELS FILTER

OUTPUT

1. The environment. Analog input computer subsystem challenges the instrumentation amplifier. Data is filtered before being multiplexed toeliminate normal- or differential -mode noise. Balun transformer acts as high -frequency common -mode noise filter for the amplifier.

119

INVERTING A1INPUT I>

\2

L__

GAINSELECTIONSWITCHES

NON -

INVERTINGINPUT

R1 OUTPUT

Poi

Rf

3

"sR', Rf _L-r

2. Basic amplifier design. Double -amplifier input eases demandson individual amplifiers Al and A2. Amplifier A3 rejects unwantedcommon -mode noise signals by subtracting balanced common -mode signals from A1 and A2.

the multiplexer inputs, as shown in Fig. 1, since a givenchannel is generally sampled at a rate that is muchslower than the speed at which the amplifier scans thechannels.

Common -mode noise is more difficult to reject be-cause low -frequency common -mode filtering reducesthe multiplexer's ac common -mode rejection ratio,while increasing its common -mode settling time. Forthe analog input subsystem to operate at fast multi-plexer -scanning rates, the instrumentation amplifiermust be able to reject common -mode noise over a largebandwidth. Therefore, a balun transformer is placed atthe amplifier input as a high -frequency common -modefilter to reject the common -mode noise beyond thebandwidth of a practical amplifier.

(This noise is filtered to prevent the amplifier fromrectifying rf noise on the input lines and effectively pro-ducing dc offset errors. The balun transformer of Fig. 1is a low-pass common -mode filter with a bandwidth ofapproximately 5 megahertz.)

Noise within the analog input subsystem, which takesthe form of capacitively coupled noise signals andswitching transients, is primarily caused by the multi-plexer because of the device capacitance of the MOSFETswitches. This internal noise source appears to the am-plifier to be primarily common -mode noise as a result ofthe balanced design of the multiplexer and the low-passinput filter.

Configuration outline

An instrumentation amplifier that provides excellentrejection of unwanted common -mode noise is sketchedin Fig. 2. The circuit also offers good gain -bandwidth

characteristics and can be adapted for programablegain selection.

Amplifiers Al and A2 provide the desired input char-acteristics and signal ranging. A third amplifier, A3, actsas an inverting unity -gain device for differential inputsand operates as a precision broad -bandwidth subtractorfor unwanted common -mode signals. To reject com-mon -mode signals over a large bandwidth. Al and A2must perform as broadband unity -gain amplifiers, gen-erating balanced common -mode signals for subtractoramplifier A3.

The common -mode rejection ratio of the over-all am-plifier can be expressed as:CMRR = (Itr/R1)(1-1-2Rm/R0/[(1/CMRR4-1/CMRR2)

(1-1-2Rmiltn)(Rr/Ri) + (Rf/CMRR3(111+R1)+ Rf/(Ri+Rf) - Re/(Ri'+111'))/R1'011' + Rol

where CMRR1, CMRR2, and cmRR3 are the individualcommon -mode rejection ratios of amplifiers A1, A2, andA3, respectively.

Other common -mode input errors, not included inthis equation, are caused by the voltage -divider effectbetween the source impedance of each analog input lineand the common -mode input impedance of its ampli-fier. To prevent common -mode signals from being con-verted into differential signals from source imbalance atthe input of the over-all amplifier, amplifiers Al and A2must maintain a high common -mode input impedanceover a large bandwidth.

The high impedance of these two amplifiers alsohelps the over-all amplifier to reject the transients gen-erated when the multiplexer channels are switched.These transients are caused by common -mode voltages,sometimes as high as 10 volts, that are switched into theinstrumentation amplifier inputs at rates that can ap-proach several hundred volts per microsecond.

The first stage

A first -stage design that satisfies the tough input per-formance requirements is illustrated in Fig. 3. Basically,the circuit attempts to eliminate amplifier input errorscaused by offset voltage, bias current, offset -voltagedrift, offset -current drift, and input impedance.

Input offset voltage can be reduced to less than 2 mi-crovolts with the nonlinear potentiometer network of re-sistors R1, R2, and R3 and the voltage divider set up byresistors Ri and R. The input -offset voltage drift withtemperature is also low because the difference betweenthe base -emitter voltage drops of matched input transis-tors Qi and Q2 is nearly zero.

Additionally, input bias current can be adjusted toless than 1 nanoampere by parallel potentiometers R6and R7, which are driven by the high -impedance con-stant -current source, consisting of cascode transistors Q3and Q4 and resistor Rs. The potentiometers are alsodriven by the common -mode input voltage through afeedback network in the emitter circuit of the Q1 -Q2 in-put transistor pair. The network, made up of transistorsQ6, Q6, and Q7 and resistor Rs, supplies a constant volt-age for biasing resistors R10 and R11 that is independentof the common -mode input voltage.

The input -impedance component of the amplifierfrom the feedback bias network is several thousand

120

megohms. Therefore, this feedback circuit provides astable bias current without reducing the input imped-ance of the amplifier. A heated -substrate matched -inputtransistor pair can further improve the bias current, theoffset -current drift, and the offset -voltage drift of theamplifier.

To increase the amplifier's common -mode input im-pedance, FETS Q8 and Q9 are connected in a cascodeconfiguration to feed the common -mode emitter voltageof transistors Qi and Q2 back to their collectors. Thefeedback reduces the effective input capacitance, but in-creases the effective input resistance between the baseand collector of both input transistors. The impedancein the emitter loop of the Q1 -Q2 input pair is also in-creased by a cascode pair, Qio and Qii, along with re-sistor R12, in the emitter -current source.

The first -stage design can provide a common -modeinput resistance of more than 2,000 megohms and an in-put capacitance of no more than a few tenths of a pi-cofarad. It also offers a good common -mode rejectionratio, as well as power -supply rejection ratio because ofthe high drain output impedance of the FET cascode cir-cuits. (Voltages V1 and V2 are zener-stabilized levels.)

The second stage

Performance requirements for the second stage aredetermined primarily by the programable signal rang-ing and gain -bandwidth requirements of the over-all in-strumentation amplifier. An ideal amplifier has an infi-nite open -loop gain so that its closed -loop voltage gainis determined only by external resistive networks. How-ever, a practical amplifier's gain accuracy decreases forincreasing values of closed -loop gain because it has a fi-nite open -loop gain. The closed -loop gain for the prac-tical amplifier of Fig. 2 can be written as:

CLG = (1 +2R,./Rri)(Rf /R1)[1 /(1+ 1/A)(1 + 2Rm/Ra][1/(1 + (Ri + Rf)/ ARO]

where A represents open -loop gain:A=Al=A2=A3Instrumentation amplifiers with large closed -loop

gains usually require gain -adjustment potentiometers ifa high degree of gain accuracy must be maintained.However, a second -stage design with sufficient gain caneliminate the need for potentiometers without degrad-ing gain accuracy. A schematic of a high -gain secondstage is shown in Fig. 4.

The dc gain of the stage is directly proportional to theimpedance at the drain terminal of FET Qi. A high -im-pedance node is developed at point A because the Qi-Q2 cascode pair drives the Q3 -Q4 cascode pair and FETQ5 is connected as a source -follower. The dc resistancefrom node A to ground may be as high as 500 meg-ohms, depending on the quiescent current of the cas-code pairs and the resistance in the emitter circuits oftransistors Q2 and Q.

Cascading the stages

The circuit permits voltage gains in excess of severalmillion to be achieved with a single stage. To make thegain of the stage less sensitive to changes in transistorparameters, emitter degeneration is provided by the re-sistors labeled RE so that the voltage gain is approxi-mately equal to the ratio of the resistance of high -im-

pedance node A and the value of resistor RE.When the first- and second -stage designs are cas-

caded, they form a differential amplifier with a stableand well-defined open -loop dc voltage gain that can ex-ceed 140 decibels. Since the open -loop gain is verylarge, the errors in the closed -loop gain caused by a fi-nite open -loop gain are reduced to a negligible level.Therefore, gain -adjustment potentiometers are not re-quired, arid the closed -loop gain of the instrumentationamplifier can be established by resistive networks alone.

To satisfy the fast sampling -rate requirements of theanalog -input subsystem, the settling time of the ampli-fier must be minimized. Settling time is determined byboth bandwidth and slew rate, which is a measure of therate at which the amplifier output can change.

Slew -rate limiting

Slew rate is limited in feedback amplifiers when themaximum output rate of change that is fed back to theinverting input is less than the rate of change at thenoninverting input. Under these conditions, a large dif-ferential error is produced across the amplifier inputs.The differential input impedance drops while the ampli-fier is slew -rate limiting and may be further reduced ifthe input step voltage exceeds the amplifier differentialbreakdown voltage.

The low input impedance that occurs during slew ratelimiting can produce large errors if low-pass filters withlong recovery time constants are associated with themultiplexer, because charge is transferred from the fil-ter capacitors to the amplifier inputs. To minimize thiserror, the amplifier must have a fast slew rate, as well as

3. First stage. Differential input amplifier stage almost zeroes out er-rors caused by offset voltage, offset -voltage drift, bias current, off-

set -current drift, and input impedance. The circuit, which hasmatched input transistors, Q1 and 02, offers a high common -modeinput resistance, but it holds input capacitance to a fraction of a. pi-cofarad. Cascode transistor pairs act as constant -current sources.

121

4. Second stage. Since this stage can attain voltage gains of severalmillion without losing gain accuracy, gain -adjustment potentiometersare not needed. Circuit gain approximately equals the resistance ra-tio of high -impedance node A and resistor RE.

a relatively high open -loop input impedance.In a practical amplifier, one that must operate over a

wide range of closed -loopsponse time is achieved for large closed -loop gains byextending the natural break frequencies of the open -

loop amplifier to obtain the largest possible gain -band-width product. Amplifier capacitance, which determinesbandwidth, can then be kept small, and the slew rate,which is also fixed by amplifier capacitance, can be heldat a large value.

A high open -loop gain presents a difficult frequency -

compensation problem when a fast unity -gain closed-loop response is needed. For example, suppose thesame bandwidth must be available from a single -pole 6-dB/octave amplifier for unity -gain operation and for aclosed -loop gain of 512. To do this, the amplifier's open -

loop gain must be reduced by a factor of 512 at the de-sired bandwidth by increasing the internal compensa-tion capacitance by a factor of 512. The increase in ca-pacitance decreases the slew rate by a factor of 512 anddegrades the unity -gain time response. One solution tothe problem is to select the appropriate frequency -com-pensation components digitally so that the settling timefor each gain setting is optimized.

The simplified Bode plots of Fig. 5 show the individ-ual frequency responses of the over-all amplifier, alongwith the closed -loop responses for unity gain and a gainof 512. The bandwidth for a closed -loop gain of 512 isdetermined primarily for first -stage capacitors C1 andC2 and second -stage capacitor C1, all of which assumesmall values. The 125 -kilohertz upper frequency limit isdetermined by the RC networks of Fig. 2.

The capacitive component and the resistive compo-

140

120

100

\ -12 dB/OCTAVE

\OPEN -LOOP RESPONSE\ V FOR GAIN OF 512

\80

OPEN -LOOP RESPONSEAMPLIFIER CLOSED -LOOP \ FOR UNITY GAINRESPONSE FOR GAIN

60 OF 512

-\\ -6 dB/OCTAVE

40

20 AMPLIFIER CLOSED -LOOPRESPONSE FOR UNITY GAIN

10 102 10' 104 106 106

FREQUENCY (Hz)

-6 dB/OCTAVE

5. Response curves. Cascaded first and second stages result inamplifier that maintains its unity -gain bandwidth of almost 10 mega-hertz over wide range of closed -loop gains. For instance, the upperfrequency breakpoint is 125 kilohertz for a closed -loop gain of 512.

nent of high -impedance node A of the second stage es-tablish the first break point of the amplifier. Since theresistive componentoccurs at a relatively low frequency with only a smallvalue of capacitance, thereby permitting slew rates ofseveral hundred volts per microsecond to be realized.

The second break frequency, at around 4 kHz, is de-termined by time constants R13C1 and R14C2 in the firststage. The resulting two -pole response reduces theopen -loop gain at a rate of 12 dB/octave, which in-creases slew rate and the high -frequency loop gain morethan the 6-dB/octave rate.

The unity -gain bandwidth can be determined by alag -lead network that is digitally selected at the high im-pedance node of the second stage, as shown in Fig. 4.This type of unity -gain compensation has the advantageof a 12-dB/octave rolloff. Unlike the compensation for again of 512, the unity -gain compensation increasesbandwidth while decreasing slew rate so that the settl-ing times for the two gain settings are approximatelythe same. Similarly, opposing compensation networkscan be traded off for gain values between unity and 512.

Two additional lead -compensation networks in thefirst stage (time constants R15C1 and R16C2) and one inthe second stage (time constant 2REC4) complete theover-all amplifier's internal frequency compensation.These three lead networks cancel poles in those cascodetransistor pairs that have two natural poles.

The gain degeneration employed throughout the am-plifier design stabilizes the lag and lead compensationnetworks, and provides an over-all gain -bandwidth per-formance that is determined by passive components, in-stead of sensitive semiconductor parameters. 0

122

Dynamic zero -correction methodsuppresses offset error in op ampsIn data -acquisition systems. the offset voltage and offset voltagetemperature drift of a FET-input op amp can be held to onlya few microvolts by a sample -and -hold correction technique

by Richard C. Jaeger and George A. Hellwarth, IBM General Systems Division, Boca Raton, Fla

0 Although today's monolithic FET-input operationalamplifier offers the advantages of high input imped-ance, large open -loop gain, fast slew rate, and low in-put -bias current, it often has a high initial offset voltagethat drifts with time and with changing temperature.

However, certain dynamic zero -correction techniquescan drive the initial offset voltage to zero and reduce theeffect of initial offset current when the amplifier is usedfor signal conditioning in a multiplexed or sampleddata -acquisition system. One such scheme keeps theamplifier's input voltage to only a few microvolts and itsoffset voltage temperature drift to merely a few hun-dredths of a microvolt per degree Celsius.

This method overcomes the shortcomings of previousdynamic zero -correction techniques. One method, forexample, controls drift by inserting a dc correction sig-nal into the amplifier's input with a periodically oper-ated switch or modulator, an auxiliary ac -coupled am-plifier, and a demodulator switch and filter. Thisscheme is not only expensive, but it produces carrier -frequency noise from the switches and recovers slowlyfrom an overload condition.

Recent methods require switches operating synchro-

nously between the cycles of a multiplexer or an analog -to -digital converter so that the switches and demodula-tion filter become a measure -and -hold circuit. Aftermeasuring the magnitude of the input offset voltage(with the amplifier input, shorted by a switch), the cir-cuit holds the correction voltage inserted at the ampli-fier input. This technique is sometimes hampered by er-rors in the sample -and -hold circuit and by feedbackinstability during the correction cycle.

Zeroing out offset error

In the improved zero -correction scheme (Fig. 1), theamplifier is also driven by a multiplexer, and the offsetvoltage is dynamically eliminated between multiplexercycles. A set of switches, which are synchronouslylinked to the multiplexer timing control, change the am-plifier's operating mode to eliminate offset error. mos-FETS are usually used as the switches because of theiroperating speed and predictable switching action.

Zero correction is implemented by disconnecting andgrounding both inputs of amplifier A1, allowing the for-ward gain of the over-all amplifier to generate a largeoutput voltage that is fed back to the input of interstage

1. Dynamic zero -correction. Offset voltage of over-all amplifier is held to a few microvolts by inserting correction voltage at input ofamplifier A2. By applying correction voltage at interstage between Aland A2, errors due to sample -and -hold inaccuracies can be minimized.Sample -and -hold circuit stores correction voltage while over-all amplifier has its feedback loop open and is disconnected from source.

123

TO GATEDRIVE A

- TO GATE -DRIVE B

GATEDRIVER

+15 V

740 -TYPE

TO GATE DRIVE A

+15 VGATE

DRIVE B

10 Id/

-15 Vp -CHANNEL MOSFETs, FLOATING SUBSTRATES

0

0

lam.11N11

4,

ERROR -STORAGEMODE

(2 m /DIV)

AMPLIFICATIONMODE

OUTPUT

GATEDRIVE A

2. Practical circuit. Zero -correction scheme for popular 740 -typeop amp employs MOSFET switches to cycle op amp between errorstorage and amplification modes. Sample -and -hold circuit, which iscomposed of switch S5, transistors 01 and 02, and capacitor C1, in-serts correction current, rather than correction voltage, into an inter-mediate stage of op amp. Scope trace shows op -amp output.

amplifier A2. The feedback voltage is sampled and heldwhile amplifier Ai is returned to normal operation byreconnecting its input to the signal source.

The over-all amplifier is cycled between two modes ofoperation-amplification and error storage. The errorstorage cycle begins when switches S1 and S2 areopened and switches S3, S4, and S5 are closed. Thiscauses Ai to amplify its own offset voltage and thesampling circuit to derive the correction voltage.

Opening switches S3, S4, and S5 and closing switchesSi and S2 start the amplification cycle by driving Aiwith the input -signal source and closing the over-allamplifier's normal feedback loop. The correction volt-age remains applied to amplifier A2 so that Ai's offset isreduced by an amount determined by Az's gain.

The zero -corrected amplifier offset, therefore, can be

10 20 30 40

TEMPERATURE (DC)

3. Almost -zero drift. Offset voltage of zero -corrected 740 -type op amp

is initially 3µV and has temperature drift of under 0.05 µV7°C.

expressed in terms of Ai's offset and A2's gain:Vos = Vosi/(1 + GA2)

where Vos1 is the equivalent amplifier input offset volt-age without correction, and GA2 is the open -loop gain ofA2. The correction voltage stored on capacitor Ci is:

Vc1 GAiGA2Vos1/(1 + GA2) + V053where V083 is the offset voltage of unity -gain amplifierA3, and GA1 is the open -loop gain of amplifier Al.

Because the correction voltage is applied after thefirst stage of the over-all amplifier, the effect of errorscaused by sample -and -hold inaccuracies is significantlyreduced. Resistor Reg is made equal to the parallel com-bination of resistors R1 and R2 to correct for the errorcaused by bias current Liu, which flows through theseresistors during normal amplifier operation. Similarly,the error due to bias current 1B2 is compensated for byresistor R3, which has the same value as resistor Rs.

Getting practical

Figure 2 shows a practical zero -correction scheme forthe popular FET-input 740 -type op amp. The compo-nents are numbered to correspond with the labels ofFig. 1. Amplifiers Al and A2 of Fig. 1 become the op -amp's input and output stages, respectively.

The sample -and -hold circuit, which is formed byswitch S5, transistors Q1 and Q2, and capacitor C1, in-jects a correction -signal current, instead of a correction-signal voltage as shown in Fig. 1, into the interstage off-set adjustment port of the op amp. Resistor Re is in-cluded to stabilize the negative feedback of the correc-tion loop during error storage.

When switch S3 opens, the correction voltage on ca-pacitor C1 is disturbed because the circuit's gate -drivesignal is coupled through the gate -source capacitance ofthe MOSFET that is being used as the switch. CapacitorC2, which is returned to the gate -drive signal having op-posite polarity, neutralizes this error. The scope tracedepicts the circuit's output as the op amp cycles be-tween the error -storage mode and the amplificationmode, where the source voltage is zero.

A plot (Fig. 3) of offset voltage (referred to the opamp's input) as a function of temperature illustrates theremarkably low drift this zero -correction scheme can at-tain. The circuit brings the initial offset voltage down toonly a few microvolts and holds offset voltage tempera-ture drift to less than 0.05 µv/ °C. 0

124

Programs in Getel speaktest engineer's languageEnglish -based language and translator can be applied to automatictest equipment, making it easy for engineers and techniciansto write in new routines and check out program parameters

by Gene Kierce, General Electric Co., Schenectady, N.Y.

BecaUse each computer -controlled test system mustbe addressed in its own language, only the operatorshave had the opportunity to become fluent in those lan-guages. As a result, many engineers with product qual-ity responsibilities have not been able to easily checkwhat parameters actually were being measured. Suchdifficulties have even spread to the equipment trouble-shooters, who had to figure out what the test equipmentwas testing before they could even begin the task offinding out what was wrong with the equipment undertest.

To solve such problems, test equipment engineersfrom 15 different departments at General Electric Co.joined forces to develop a single language and a trans-lator that applies it to any piece of automatic test gear.

language, Getel (for generaltest engineer language, pronounced jee-tell), is based onEnglish, so that an operator needs little formal trainingand almost anyone else can understand what's actuallybeing tested.

Experience with the language has shown that tech-nicians and engineers can learn to read and understanda Getel program in anywhere from a few minutes to acouple of hours and can be programing proficiently inless than a week. The use of English also allows even atypist to correct many spelling and programing errors,and troubleshooters can use the source listing as acheckout routine.

Getel is now in wide use in many General Electricplants, furnishing inputs to a wide range of systemssuch as the GE -MAC tester controlled by, a GE -PAC 30controller, the Hewlett-Packard rf tester, the tape -driven Systomation Fixit tester for checking wiring, andthe tape -driven Texas Instruments T1553 integrated -cir-cuit tester.

Mini -translator. Although English is the most conve-nient language for an operator, it is difficult to translateinto a useful format for controlling machines. Origi-nally, the plan was to develop a large central softwaretranslator to process Getel. The translator was to pro-duce an intermediate language that could be processedby a smaller machine, which in turn would control aspecific instrument. However, the language and thetranslator became larger and larger as the developmentwent on, so that only the largest computers could beused to process the translation program. Although thissoftware translator has actually been designed (and

named Mark III), it is not actually in use. Rather, asmaller translator, the Mark I, is in regular use, since itcan fit into a minicomputer with an 8,192 -wordmemory.

The Mark I can translate from Getel into any lan-gauge that the user desires. In the case of the GE -PAC30 -GE -MAC test system, the Getel compiler translatestest statements directly into GE -PAC 30 assembly code.

A medium -size translator, the Mark II, has also beendeveloped. It can fit into a 16,384 -word machine, and ismounted in a computer, but has not yet been used at GEbecause the Mark I has been able to serve all the users'needs to this time.

Filling the blanks. The Mark I's translation from Ge-tel into a tester's language is performed with a tem-plate -type approach. The Getel statement is consideredto have a fixed portion that corresponds directly with astatement in the translated language, and a variableportion, which contains the specific numbers relating tothe test at hand. For example in the statement

100 SET 11' TO 50 OHMSthe value for the load, 50, is a variable. The remainderof the statement is fixed and thus, if the variable part isdeleted, the statement appears with a hole in this place(denoted by an asterisk) and thus can be considered tobe a template.

100 SET 'LP TO * OHMSSuch templates are part of the automatic test equip-

ment (ATE) conversion table, which is composed by atest engineer for each particular automatic test system.The ATE table thus relates Getel to a particular test sys-tem, requiring only the specific numbers to fill the holesand thus complete an instruction to the automatic testsystem in its own language. For example, the corre-sponding statement in GE -PAC 30 assembly code for theabove term, as might be required for the GE -MAC testsystems would be

LHI RE,2BAL RF, MONITRB* +8DC A(Z99999)** *

Z99999 DC 50The statement in Getel is called a source statement

and the translated form is called the object statement.Once the templates have been created for the ATE con -

125

version table, any engineer can write programs in Getelwithout concerning himself with the details of the par-ticular automatic test equipment that will perform thetests. However, note that not all Getel statements willhave holes-many will be control -type statements thathave direct counterparts in the object language thatcontrols the tester.

Getel is based on a logical assignment of tasks to manand the computer, taking advantage of the capabilitiesof each. The early steps of carrying out a test programeither are creative or require decision -making abilitythat is best performed by a man, while the later stepsare best assigned to the computer, since it can store andretrieve data without error. To demonstrate the assign-ment of tasks, here are the typical steps in the process ofperforming a test.

After getting together all the necessary prints, sche-matics, and specifications the test operator must estab-lish parametric requirements for the unit to be tested.This is best done by a man at present, since he can eval-uate the circuit performance and thus set limits on thevarious parameters to be tested. However, some designautomation programs are closing the gap since they canbe designed with a capability to analyze the circuit andrelate certain internal parameters to input-output re-quirements.

Next, the operator must determine the best test se-quence, taking into account the likelihood of failure foreach test and the relative importance of each test inmeeting the specifications. The next step is to determinewhat actions must be taken based on the results of thetest.

1. Easy reading. Test routine for simple inverter circuit is written as instructions for manual test (left column), and also in programing lan-guages for four different testers. Getel program for same test is at right. Note close correspondence between Getel terminology and instruc-tions for manual test that would be performed by a technician at the test bench.

8 16

R2

6 --1114---

9 7

CIRCUIT INPUT REQUIREMENTS :

+12 volts dc on pin 8

-12 volts dc on pin 9

Ground on pin 7

Logical 1: +6.1 volts dc 1pin 6Logical 0: + 0.0 volts dc J

CIRCUIT OUTPUT REQUIREMENTS :

Unloaded output, pin 16

Logical 0, or 'down level'

High limit: +0.5 volts dc 112 ma.Low limit: +0.0 volts dc

Logical 1, or 'up level'

High limit: +12.0 volts dc0 ma.

Low limit: +11.3 volts dc

MANUAL TESTINSTRUCTION A

1.0 Test 1

Apply 12 volts dcto pin 8 referenceto pin 7.

Apply -12 volts dcto pin 9 referenceto pin 7.

Apply 12 ma dcto pin 16 referenceto pin 7.

Apply 6.1 volts dcto pin 6 referenceto pin 7.

Measure output dcvoltage on pin 16reference to pin 7.

Compare output dcvoltage against highlimit -0.5 volts dc-and low limit -0volts dc.

Record the valueif it fails.

01 @TEST NO. 01@

02 FB +12.00, TB08

03 FC -12.00, TB09

04 TGO7

05 FE +012.0, TE16

06 FD +06.10, TD06

07 MV16/H +0.5v/L +0.0v

08 PFC

B

TID001

BV11200BC1PL2W1001

BV21 200BC2NL2W1102

W0911

BIXO3M1200

BVX03M1 200

BV30610BC3PL2W0703

W201403

MTRSVPOR

MAXP0050P0

MI NPOOOOPO

RI U4

C

98000004000101 01 2085080002 1 1 208508000341 20807 80004061 07048001 00000047 1 201 1 000003000022 1 60000000021 400007 0000202050000000

D GETEL

0410203108

208839

208939

208739

248134219631

248533209633

100 Test 1

110 Apply 12.0VDCto 'pin 8'

120 Apply -12.0 VDCto 'pin 9'

130 Apply 12.0 MADCto 'pin 16'

140 Measure 'DCvoltage',10±.1%

150 VDC at 'pin 16'

160 Record 'result'

170 Compare 'result'to '0.5, '0.0'goto 'HIGHM','LOWM'

180 Perform Test 2

190 HIGH; MESSAGETESTI FAILEDHI

200 LOWM; MESSAGETESTI FAILEDLO

A: AAI Model 1000 IC tester; B: TI 553 IC tester; C: Fairchild Model 5000; D: GE -PAC 200 controller

126

2. Test run. At GE, test engineers use the Mark II time-sharing system to prepare Getel programs. After accessing the system, Getel is com-piled with the Mark I translator program (Getel MI). In this example, Getel is translated to Fortran for use on the Hewlett-Packard rf tester. The

output of the system is a tape to be inserted in the tester to control the actual test.

1. BETELPROGRAMWRITTENFUR

PIECE OFFARDVVARE

TEST ENGINEERDESIGNS TEST

GETEL LANGUAGEREF. MANUAL

GETEL MARK IUSERS MANUAL

TEST ENGINEERWRITES TESTPROCEDURE INGETEL

2: ACCESS MARK II TIML SOARING

DIAL MARK IITIMESHARETELEPHONE NO.

PROGRAMPUNCHED ONPAPER TAPE

GIVE USER NUMBER,SYSTEM AND GETELPROGRAM NAME

PUT GETEL TAPE INTELETYPEWRITERREADER AND PRESSRUN

CREATE FILEFOR OUTPUT

COMPILEUSINGGL TELMARK I

ACCESS GETELMARK II COMPILERAND RUN

GIVE OUTPUTFILE NAME

GIVE ATETABLE NAME

GIVE GETEL TESTPROGRAM NAME

ATE TABLE WAS WRITTEN ANDPUT IN TIME-SHARE SYSTEMAT AN EARLIER TIME

TELL WHETHER LINENUMBERS WANTEDON OUTPUT

COMPILECOMPLET

TURN TELETYPE.WRITER PUNCHON

LIST OUTPUT FILEAND GET OBJECTTAPE

SIMULTANEOUSLYGET OBJECTLISTING

SELECTOUTPUTOPTIONS

SELECTOUTPUTOPTIONS

TAPE READYTO BE RUN

IS

ATECOMPUTERCONTROL

TAPE MUSTBE COMPILEDON COMPUTERIN ATE

IN OUR CASE THISOUTPUT TAPE IS INFORTRAN

4. LIST GETEL MARK I OUTPUT ANDCONTINUE IF NECESSARY

PUT FORTRANPROGRAM INPHOTOREADER

LIBRARY ROUTINESFROM MAGNETIC TAPE

LOAD ADDRESSOF BASICCONTROL SYSTEMAND PRESS RUN

LOAD ADDRESS OFFORTRAN STARTAND PRESS RUN

ABSOLUTEBINARYTAPE

OPTIONALASSEMBLYLISTING

RELOCATABLEBINARY TAPE

(011 AINAIIS01.11INARY 1APIBY 1 Olt IRANCOMPIt A (ION

LOAD HEWLETT-PACKARD FORTRANCOMPILER FROMMAGNETIC TAPE

LOAD HEWLETT-PACKARD BASICCONTROL SYSTEMFROM MAGNETICTAPE

6. I OADAND II !: I HARDWAltl

LOAD ABSOLUTEBINARY TAPE INHEWLETT-PACKARDCOMPILER

HOOK UPHARDWARE TOBE TESTED

HARDWAREGETS TESTED

LOAD ADDRESSOF ABSOLUTEBINARY TAPEAND RUN

127

Likewise, the operator is best able to decide howmuch data is enough and how best to control the oper-ator displays. He also can explore other possible ways ofperforming the test, if he decides that the test stationcannot do it.

However, after this, the computer can take over. Thecomputer can be instructed about what equipment isavailable and what its capabilities are. From this instru-ment pool, the computer can choose the instruments,since it can even keep track of which instruments are inuse on other tests and which instruments are availablefor this test.

The computer can then translate the instructions intomachine code to operate the instruments, using look -uptables. This is one step that a man performs poorly-it isan unthinking task and errors often creep in. Also, thetranslation of these machine codes back into English tosee if any errors have been introduced is unnecessarywith the computer. The machine can also optimize testtime by checking the machine code for duplications.Thus, with Getel, the user can describe the parameter tobe tested and the computer will select the instrumentfor the job.

Test instrumentation falls into three categories:sources (power supplies, signal generators); sensors(digital voltmeters, electronic counters); and loads (re-sistors, capacitors, inductors). To control such instru-ments, the operator uses as statements simple impera-tive sentences containing verbs that are commonly usedby test engineers. Prefixes, suffixes, and units abbrevia-tions for Getel are taken from IEEE standards and Gov-ernment documents.

The user also can define synonyms and insert stan-dard routines into the body of the program to composenew complex test functions based on groups of simpletest functions.

As an example of how Getel differs from languagesused in the automatic testers, consider a typical invertercircuit that is common enough to be tested practicallyon any of several types of automatic testers. The testwill be programed in each of several languages and alsoin Getel. (The actual meaning of each command in thelanguages is not really important for this discussion-theexample is presented only to illustrate complexities.)

Testing. To test the inverter, appropriate supply volt-ages must be applied along with a certain signal level tothe input. Then the output must be measured and com-pared with the design value, and the output must be re-corded if the inverter fails the test.

The circuit is shown in Fig. 1, along with a set of testinstructions written for interpretation by a technicianactually doing manual testing. The instructions in thecolumn for tester A-AAI Corp.'s model 1000, a popularintegrated circuit tester-are almost self-evident. Thistester uses a pseudo -variable -field technical programinglanguage, in which the alphabetic terms are used; FBmeans fix bias supply B, and TB means tie (connect) biassupply B, but still an engineer might find it difficult tointerpret the instructions with certainty unless he ac-tually knew the language.

Tester B, 553, also uses some alphabetic charac-ters, but Tester C, Fairchild's model 5000, uses numericcode only, as does Tester D, the GE -PAC 200 controller.

In many cases, single instructions for the manual testmust be expanded into several subinstructions for theautomatic tester.

In Getel, there is little difference between the instruc-tions for manual test and the instructions for automatictesting. Only line numbers have been added and all la-bels have been apostrophized.

Most users at General Electric access Getel throughGE's Mark II time-sharing system (the Mark II in thiscase bears no relationship to the presently unused MarkII translator for Getel; the redundancy occurred be-cause of the assignment of the name Mark III to thelarge translator, and this term propagated through laterversions of Getel translators).

Step by step. Before the test engineer signs onto theMark II system, he familiarizes himself with the unit tobe tested and designs the test. He then converts the testinstructions to a Getel program. The Getel programthen is punched on paper tape in ASCII (American Stan-dard Code for Information Interchange), and then theengineer dials the GE Mark II system on a telephonehooked up to a teletypewriter, as shown in the diagramin Fig. 2.

Upon request from the time-sharing system, he giveshis user number to identify himself as a qualified user,and the system then queries him on which of the twoavailable languages-Basic or Fortran-he wants to use.Since the Mark I translator is written in Fortran, he re-sponds with that selection. He then gives a name to hisGetel program and enters the paper tape into the tele-typewriter reader for insertion in the time-sharingmemory. He then creates a file in the time-sharing sys-tem in which the translated program (the object pro-gram) will be stored.

After telling the system that he wishes to use the Ge-tel Mark I program, he goes through some bookkeepingsteps with the teletypewriter, loads in the proper ATEconversion table, and the system then delivers apunched tape of the object program for use on the au-tomatic test system that he intends to use. This tape canthen either be processed further on the test system'scomputer or the test can be run directly from the tape,depending on the tester in use.

Anyone can use GetelGetel is available to users outside General Electric. Ithas been put on GE'S Network Service, a time-sharingservice centered in Cleveland. Remote concentrators inLos Angeles, Kansas City, Atlanta, Teaneck, N.J.,Schenectady, N.Y., and Washington, D.C., link the cen-tral computer complex-which comprises a GE -635 cen-tral processor, a GE -4020 communications processor,and a disk file complex-to remote buffer units in majormetropolitan cities. Customers can gain access to thesystem with a local phone call. Overseas, the networkcan be used in such cities as Amersfoort, Brussels, Lon-don, Manchester, Birmingham, and Paris. In the west-ern hemisphere, outside the continental United States,the network can be dialed from remote units in suchcities as Mexico City, San Juan, Montreal, Toronto,Vancouver, and Anchorage.

128

GETEL VOCABULARY

OPERATIONS

APPLY

CALCULATE

CLEAR

COMPARE

COMPLETED

CONNECT

CONTINUE

DEFINE

DELAY

DISCONNECT

END

EXECUTE

EXTERNAL

GOTO

IF GOTO

IF -PERFORM

INSERT

LET

MEASURE

NOTE

PAUSE

PERFORM

PROCEDURE

READ

RECORD

RESERVE

RESET

ROUTINE

ROUTINE END

SELECT

SENSE

SHARE

TEST

TITLE

TURNOFF

TURNON

USE

I t .I(' SlliNAI

ZERO MAG

ONE MAG

RT

FT

NOISE

FREQ

SKEW TIME

SQUARE WAVE

BW

IMP

PHASE-JIT FER

RT

FT

TIME ASYM

OVERSHOOT

UNDERSHOOT

PRESHOOT

DROOP

RINGING

ROUNDING

DC -OFFSET

MULTIPLIERS

P (10-12)

N (10-9)

U (10-6)

M (10-3)

K (103)

MEG (106)

G (102)

I !MI IN I I IIVAI

TIME

SEC

MIN

HR

START

STOP

TRIG

FIRST POS SLOPE

FIRST NEG SLOPE

CHANNEL A

TRIANGULAR WAVE

FREQ

BW

IMP

PHASE -JITTER

NON LIM

TIME ASYM

PEAK- DEGEN

DC -OFFSET

UNITS

AACAMP ACAMPS AC

ADCAMP DCAMPS DC

VACVOLT ACVOLTS AC

VDCVOLT DCVOLTS DC

WATTWATTS

A/SECAMP/SECAMPS/SEC

DB

DEG

DEG -C

DEG -F

DEG -K

DEG -R

FD

HY

HZHERTZ

HR

OHM

PCT

PPS

RAD

REV

SEC

S -PARAMETERS

V/HZ

AM SIGNAL

MODUL-AMPTD

CAR R-AMPTD

CARR-FREQ

HARMONICS

NONHARMONICS

NOISE

PHASE -JITTER

DC SIGNAL

POWER

CUR-LIM

VOLT-LIM

IMP

RIPPLE

RIPPLE -F RE()

NOISE

DISTORTION

CUR MONITOR

VOLT MONITOR

FM SIGNAL

FM -INDEX

CAR R-FREQ

MODUL-FREQ

HARMONIC DIST

NONHARMONIC DIST

AMPTD-MODUL

MODUL-DIST

NOISE

SUFFIXES

-TRMS (true rms)

-AU (average)

-PP (peak -to -peak)

-P (peak)

129

Sceptre rules benevolentlyover computer -aided designSome practical tips on solving nonlinear problems with Sceptre reducethe complexity and cost of this computer program; tradeoffs mustbe made between circuit models, solution accuracy, and running time

by George C. Kenney, North American Philips Corp., Briarcliff Manor, N.Y.

Solving linear and nonlinear circuit problems is theprovince of a powerful computer program calledSceptre. Unfortunately, its reign has been limited by itscomplexity, high cost, and lengthy computer time.Sceptre, however, can be a practical and very valuableengineering instrument if used properly.

Sceptre, which stands for system for circuit evaluationand prediction of transient radiation effects, can deter-mine initial dc conditions and transient responses togeneral forcing functions for linear and nonlinear sys-tems. Although it is primarily intended for circuits, itcan find solutions for systems in any discipline.

Until recently, Sceptre was available only by batchrun at a computer facility, making it costly, time-con-suming, and difficult to use. As a result, many nonlinearproblems were solved by hand calculations, circuit ex-periments, or by piecewise linearization with ECAP(electronic circuit analysis program).

But now, input/output data for a Sceptre programcan be handled by a remote teletypewriter terminal(through software provided by Computer SciencesCorp., Infonet div., El Segundo, Calif.). This allows theuser to solve nonlinear problems with an ease ap-proaching that of time-shared ECAP, and with reason-able expenditure of time and cost.

1. Circuit problem. Hysteresis of this flip-flop can be computed andplotted with Sceptre. Circuit elements are labeled for easy computercallout, with letters L and R differentiating between left and right sideof flip-flop. Current sources are denoted by J.

Sceptre accepts input system data in two forms: asnonlinear, first -order, differential equations or as engi-neering descriptions of a circuit (similar to ECAP). Initialdc conditions are computed or supplied by the user ifknown, then a transient analysis of the system's re-sponse to forcing functions-such as time -varying volt-ages or currents-is carried out. It is also possible to runinitial conditions only and then, after inspection, runtransient conditions, or compute only the transientmode by supplying the initial conditions.

Sceptre recognizes standard passive elements such asresistors, capacitors, inductors, transformers, and theideal diode. Linear dependent sources-like voltage -

controlled current or voltage sources or current -con-trolled voltage or current sources-can also be used.These circuit elements enable the user to synthesizeEbers-Moll models for transistors as well as diodes thatare operational in the large- or small -signal region.

Models stored on tape can be retrieved for use at anypoint in a circuit. The models can be interconnectedgroups of passive or active, linear and nonlinear ele-ments. Nonlinear "black boxes" are implemented by ta-bles or a Fortran expression. A special section allowsspecial parameters to be defined that may be unrelatedto the primary problem. Moreover, the user may writehis own Fortran program and insert it into a normalSceptre run as a subroutine.

Using Sceptre. Printout is in tabular and/or selectedgraphical form. Sceptre will print any or all sources, inaddition to circuit element currents or voltages, whichare defined as a function of time or of any otherparameter. The plots are easily requested, automaticallyscaled, and labeled.

An automatic termination feature stops the programupon satisfaction of any Fortran expression involvingany of the circuit elements. For example, the statement

TERMINATE IF( -1R7 GT.10.I.AND.R9 LT.I2.2)will terminate the run when the reverse current throughR, is greater than 10.1 milliamperes, and the voltageacross R.. is less than 12.1 volts.

Sceptre uses the state -variable principle as its mathe-matical basis. Capacitor branch voltages and inductorlink currents are the state variables chosen to form anetwork of first -order, nonlinear, differential equations.This method is very efficient since computation time re-lates only to the number of state variables and not thenumber of elements.

130

+5V

-5V

FREQUENCY = 1kHz

R1L0.731(S2 TC1L

0.5pF

ES

VR

RLL0.316k 1-2

RLR0.3161(2

IC3L R3L0.5 pF 3.16k52

R6L102

CESL10pF

REL1052

R2L42k 2

JESL

RC 102

CCSLti

OpF

JCSL

RST2052

12.1 V

EST

JFL aNIE

(a) HIGH FREQUENCY MODEL

R3L3.161(2

+2V

-2VFREQUENCY = 100kHz

0

JC5mA

RLL0.316k S2

CCSL10 pF

11-*JCSL

R1L0.73k2

ES

R2LVR0,2V

421(2

1_

CESL10pF

JESL

JFL aNIE

(b) LOW -FREQUENCY MODEL

01

JC5mA

R3R C3R3.161(2 0.5 pF

RC 102

CCSR10pF

R6RJCSR 10 2

JFR aNIE

02

RJC1M52

RSB2012

JESR -CESR10pF

RER1052

R2R42k52

12.1V ESB

RST20 2 EST

CCSR10pF

JCSR

JFR

Q2

RSB2012

aN IE

R3R3.16k52

JESR

11112.1V

CESR10pF

12.1V ESB

1

R2R42k52

R1R0.73

TC1R0.5pF

-T VR

_L

R1R0.73k2

- VRT 0,2V

2. Sceptre models. High -frequency model (a) on flip-flop includes transistor speed-up capacitors and lead resistance. These circuit ele-ments, however, severely slow up solutions at low frequencies because Sceptre must take thousands of steps to arrive at answer. Changingto model shown in (b) speeds solution. Increasing frequency of forcing function and decreasing its amplitude also helps.

131

Ebers-Moll pnp transistor model

There are usually two circuit equations associated with theEbers-Moll transistor model: one for the collector -current,If., and the other for the emitter current, IF.

The collector current is:

lc = Ics(e8i valet - 1)where L., is the base -collector saturation current with thebase -emitter shorted, and 0, the slope of the natural log ofle versus

This equation can also be written as:

ic = Ico(eeivB'c' - 1)/(1 - aiaN)where Ie is the base -collector saturation current with thebase -emitter open, a, the inverted common -base currentgain, and a, the normal common -base current gain. Forcomputer program listing, the collector current becomes:

r MODE EQI ATION (OD Vli'C)Similarly, the expression for the emitter current can be

written as:

IE = IEs(eNvivE - 1)where I is the base -emitter saturation current with thebase -collector shorted, and 0, the slope of the natural logof 1H versus VH,H.

Another version of the equation is:

Ii: = IE0(e6N vivE - 1)/(1 - aiaN)where IH is the base -emitter saturation current with thebase -collector open. The program listing for IF becomes:

IF = DIODE EQUATION (ON, VB.E)The model's circuit elements are defined as: rH, the base -

spreading resistance; re, the series collector resistance; C,,the collector diffusion capacitance; C1 e, the collector junc-tion transition capacitance; CdE, the emitter diffusion ca-pacitance; and C,H, the emitter junction transition capaci-tance.

The first step in preparing a problem for analysis withSceptre is to draw an equivalent circuit using resistors,inductors, capacitors, transformers, sources, and anynecessary stored models. Circuit elements may be linearor nonlinear, and defined by a numerical constant,tabular list, or Fortran expression.

Next, name or number all nodes and name each cir-cuit element. Then choose current flow direction in eachpassive element and source. Assign circuit values in aconstant set of parameter units. (For high speed, a goodset is kilohms, picofarads, microhenries, milliamperes,volts, and nanoseconds.)

Circuit elements can now be easily combined to forman Ebers-Moll large -signal transistor equivalent circuit(see "Ebers-Moll pnp transistor model," p. 74). Theemitter current, 4, and the collector current, 1, are en-tered as DIODE EQUATION (0,V) or DIODE TABLEXY to achieve numerical convergence for the initialcondition solution.

An example will illustrate how to use Sceptre andhow to implement model changes in order to achieve asuccessful run. The circuit hysteresis of the flip-flop inFig 1 is to be predicted by the computer. The diagramuses a labeling scheme that is convenient for calling outcircuit elements in a program. Besides the usual nu-merical differentiation between components, the lettersL and R distinguish between elements on the left sideand right side of the circuit.

The Sceptre model of the flip-flop in Fig. 2(a) uses aslightly modified version of the Ebers-Moll transistorequivalent shown on p. 74. Since the flip-flop's transis-tors never saturate, current source ail, can be omitted.Diode JCSL (or icsR) replaces current source lc, anddiode JESL (or JESR) replaces source IE. Both the diffu-sion and transition emitter capacitances are combinedin capacitor CESL (or CESR), while the diffusion and

transition collector capacitances become CCSL (orccsR). Also, small speed-up capacitors (5 pF) and leadresistances (10 ohms) are included for better accuracy.

Because the flip-flop's hysteresis is reflected in the dif-ference between the collector voltage of Q, and Q2, re-sistor RO is added. Circuit hysteresis, which is a functionof R1L (and R IR) and R3L (and R3R), can be pre-dicted by computing the voltage across RO.

Operating frequency range for the flip-flop is 1 ki-lohertz to 10 megahertz. Therefore, a forcing functionwith a frequency of 1 kHz is a reasonable choice for theexcitation voltage. To guarantee that the flip-flop willtrigger, the amplitude of the forcing function will be5 v. Let the forcing function, then, be E, = -5cos271000t, where t is time.

Fail-safe. For the model of Fig. 2a, Sceptre will cor-rectly solve the dc case but will fail to give a transientsolution. The reason for the failure will be indicated asSMALLER MINIMUM STEP SIZE REQUIRED.

This type of failure, which is sometimes called the Ei-genvalue problem, is caused by a conflict in circuit timeconstants that will incapacitate any nonlinear analysis,computer or otherwise. The flip-flop has natural fre-quency modes caused by short time constants that re-quire very small time steps for accurate analysis. Be-cause of the long running time to complete the solution,Sceptre will decline to solve the problem.

There are several elements aggravating the flip-flop'stime -constant problem. Speed-up capacitors, header ca-pacitances, and transistor lead resistance do not affect alow -frequency solution, but they do complicate solutionprocesses and increase program time.

Step size is determined by the specified problem du-ration (stop time) and by the smallest time constant ofthe circuit. The initial step size chosen by Sceptre is 10-3times the stop time. This step size is tested by the inte-

132

gration routine for accuracy, and if that size is found tobe erroneous, a new step size that is half the previousvalue is attempted.

The test process is repeated until a small enough stepsize is found or until the step size is smaller than 10-5times the stop time. If the step size required is less thanthis value, the run is terminated because a smaller min-imum step size is required.

A successful run can be achieved without changingthe low -frequency hysteresis by removing all speed-upcapacitors and all lead resistances as shown in Fig. 2(b).It is also helpful to decrease the magnitude and periodof the forcing voltage, E5, to speed up the integration.

Actually measuring circuit hysteresis helps to deter-mine how to modify E. A measurement will show thatthe hysteresis is about 0.5 v at 1 kHz as well as at 100kHz; therefore, changing the frequency of E. from 1 kHzto 100 kHz will speed the solution without affecting ac-curacy. Reducing the amplitude of E. from 5 to 2 v alsoaids the solution without impairing the triggering of theflip-flop. Switching from a cosine wave to a trianglewave is another simplification. To see the change in hys-teresis at high frequencies, another run could be madeat 10 megahertz with the original model and original E..

Figure 3 reproduces the successful run of the pro-gram input data and the hysteresis plot. The forcingfunction, E,, is entered as a table; all diodes are repre-sented by the exponential diode equation. The programrequests a plotted output of VRO, the voltage across re-sist& RO, versus E8. The plot correlates fact withtheory -computed hysteresis is 0.4 v; the measured is0.5 v.

A brief look at cost considerations is also essential. Because Sceptre is a large program that requires expensiveFortran compilation, a good deal of its cost tends to bea fixed overhead. The flip-flop problem, for example,can be run with identical numerical results on an IBM360-65 or a Univac 1108, using a conversational, re-mote, job entry teletypewriter. The price of the IBM runwill be approximately $90, 80% of which is overhead,while the Univac solution costs $30 with 20% overhead.

Defined parameters. Another example will serve to il-lustrate the flexibility of Sceptre through the use of itsspecial defined parameters section. Suppose the prob-lem is to solve a set of first -order, simultaneous, differ-ential equations that may be entirely independent ofany electrical network:

X'(t) = -6X(t) + 5Y(t) + 10

RrPPTRE SYSTEM INPUT PLOT OF VMS VS ES

VRO

2.500E000 1

1CIRCUIT DESCRIPTION 1 1 1 1

FLIP FLOPELEMENTSES.11-1ETARIE 11TIME)

2.000E00 1--°-ERBL.3-2.0R2L.2-8'42JESL.0-3.010DE EQUATION(1.2E-11.35.)CESL.0-3.10EREL.6-7.i 1.500E000 1---- R3L.15-323.16JC11.4-3.DIODE EQURTION(1.2E-11.35.)CCsL.4-3.1001..3-4.,97.JESLERcL.3.!_4.11

-3.

.I1.000E...00 1----

RIL.i0-5..316 . I

RLR.10-15..316RST.10-17Y.02EST.17-0.12.1RSB.11-9..n2ELMO-9.12.1

5.000E-01 1--

1.

ER.O..11.0 --0.R114,11-12,73 1-FVS-TE-RES4SR211.12-8.42 0. rTEREIR.12-13.0JESR.10-13EDIODE EOURTION(1.2E-11.35.)coR.16-13.10R5R.5-I3.3.16JCSM.14-13xDIODE EOURTIONI1.2E-11.35.) -5.000E-01 1--CCSR.14-13.10 1

JI.R.13-14,97.4ESR ,

.FRCR.15-14.0RJC.7-8.1c00R0415-5.1801 -1.0000.00

liERER,16..7.0FUNCTIONS

1----

TOLE I0.-2 1

At1J210E3.-2OUTPUTSYRA,RLOTLE5)01.4f010(RER010/21 .RN4c,J!LOT

RUN CONTROLSU74114tteCgnTIONS

STOP Timp.12p3MINIMUM STEP SIZE ..001RERUN DEScRIPTIoRI1)

(a) PROGRAM INPUT DATA

E2-1.500..00 1----

J

.4.000E00 2.000000 0.-5.000E.00 -1.000E*00

(b) HYSTERESIS PLOT

1.000E.D0

3. Computer printout. Program listing (a) shows set of Fortran instructions needed to predict flip-flop hysteresis. A graph of the hysteresis(b) is obtained by requesting a plot of the collector difference voltage (between 0, and 02), represented by VRO, versus the forcing function,E,. Distance between colored lines is predicted hysteresis voltage, which is 0.4 volt compared with measured value of 0.5 V.

133

Modified pnp Ebers-Moll modelA few minor modifications of the conventional Ebers-Molltransistor model improves its speed without adversely af-fecting its accuracy. Eliminating extraneous resistancesand carefully combining diffusion and transition capaci-tances implements the change.

The equation for transistor collector current, Ie, can bewritten as:

IC = - 1)while the expression for transistor emitter current, 1E, be-comes:

IE = IE(o.euN valE -All modified circuit elements are defined in terms of the

original model:C, = 3C./4CH'e = 4 + CdC

CE = CdECc = Car + Cu` = CAC + CH.('CcE = collector -emitter header capacitancers, = base -spreading resistanceCd,. = 01 Ts lc

where Ts is storage timeCdE TE IE

where TE is the minority carrier transit timeTE = I /(0.11,ha = I/1.2wT

where cos, is the alpha cutoff frequency, and co, is thebeta cutoff frequency

CU` = Cob° CCEwhere Co, is the output capacitance with the emitter open

CIE = Cibu CCE

where C,,, is the input capacitance with the collector open.

CE

I I

CBC

CCE

Y'(t) = 5X(t) - 7Y(t)The initial conditions are X(0) = 6 and Y(0) = 5.

Each of the derivatives may be entered under theprogram listing DEFINED PARAMETERS in explicitform. A proper sequence would be:

CIRCUIT DESCRIPTIONDIFFERENTIAL EQUATION EXAMPLE(Enter data, for instance, as in Fig. 3(a).)DEFINE PARAMETERSDPX = EQUATION 1 (PX,PY)DPY = EQUATION 2 (PX,PY)PX = 6PY = 5OUTPUTSPX(X), PY(Y), XSTPSZ, PLOTFUNCTIONS(Define equations X'(t) -6X(t) + 5Y(t) + 10 andY'(t) = 5X(t) - 7Y(t) by using dummy variables Aand B for X and Y, respectively.)EQUATION 1 (A,B,) = (-6.*A + 5.*B + 10.)EQUATION 2 (A,B) = (5.*A-7.*B + 2.)RUN CONTROLSINTEGRATION ROUTINE = TRAPSTOP TIME = 100ENDSince the derivatives of PX and PY (DPX and DPY, re-

spectively) are entered in the program, the functions ofPX and PY must be updated at each integration step.

It should be noted that the initial values of the vari-ables X and Y are entered as PX = 6 and PY = 5; thedifferential equations themselves are entered under DE-FINED PARAMETERS. Since the quantities X and Yare treated like the state variables of a general transientproblem, they are subject to the same step -size limita-tions in whatever Sceptre integration routine is used.

When the defined parameters feature is used, itshould be remembered that Sceptre can only solve non-linear, first -order, differential equations. Higher -order

equations must be reduced to a set of first -order ones.Limitations. There are several important factors to

keep in mind when using Sceptre. The first one is toknow the application. Sceptre can solve very compli-cated nonlinear problems; if the problem is linear, useECAP. It is often worthwhile to simplify the problem byusing different models at different frequencies.

Another consideration is computer models. For mostnonlinear applications, transistors can satisfactorily behandled by Sceptre with the Ebers-Moll model shownin "Modified pnp Ebers-Moll model," above. It offers agood compromise between speed and accuracy. Alwaysremember that the simplest satisfactory circuit modelhas the best.chance of running.

Sceptre is limited to two types of active dependentcircuit elements for accurate dc (initial condition) analy-sis. These are a current source that depends on a currentand a nonlinear element, like the diode. The diode mustbe entered as a diode equation or a diode table. Anyother active dependent circuit elements (such as volt-age -dependent current sources, passive elements thatdepend on either voltages or currents, and tables for ze-ner diodes, tunnel diodes, or any device whose charac-teristic curve does not monotonically increase) maycause convergence difficulties in the dc solution.

However, these elements present no difficulty for thetransient solution portion of Sceptre. They even offer analternate method of obtaining a circuit's initial condi-tion when the dc method fails.

To approximate a dc steady-state solution, some ini-tial conditions can be assumed and a transient solutionrun (with the forcing function set to zero and all capaci-tors given equal values) for a duration of five constants.Using the steady-state values obtained in this way asinitial conditions, a transient run with a proper forcingfunction can be made. This technique should only beused after unsuccessful attempts to solve the dc case.Finding initial conditions by transient response will al -

134

ways require two runs to achieve a final solution.Another difficulty often encountered is the Eigen-

value or small -time -constant problem. First, it shouldbe determined whether the elements causing the troubleare necessary to get the desired solution. About 90% ofthe time, they are superfluous and only serve to bogdown the program.

One method of solution is to use a simple model atlow frequencies and a complex one at high frequencies,where the forcing -function frequency and the Eigen-values are compatible. A good low -frequency model isone that has no capacitances except large diode shuntcapacitors and that uses E, at the highest possible fre-quency without appreciably changing the dc solution.

An appropriate, but not overly complex, modelshould be used for a second run at higher frequencies.This two -model technique will probably be more satis-fying and less expensive than using the same model forhigh and low frequencies, as can be done with ECAP.

Even if the problem involves conflicting Eigenvaluesand all attempts at separate solution are unsatisfactory,there is yet another approach. The user can allowSceptre to take a smaller step size than the normal 10 -times the stop time. A specific minimum step size (forexample, MINIMUM STEP SIZE = 0.00001) is calledout as a RUN CONTROLS instruction. Sceptre followsthe same process to determine step size-starting with10-3 times the stop time and dividing by two each inte-gration pass until the specified limit is reached.

It is also useful to call out a maximum step size (likeMAXIMUM STEP SIZE = 100) that is about 1% of thestop time. The program can then take large steps intime toward the solution when the derivative of thestate variables are changing slowly. For example, a cir-cuit problem may require very small step sizes in thebeginning, but it could correctly take large steps later,near the steady-state condition.

Excessive computer time is not a concern when a verysmall step size is specified. A built-in counter logs inte-gration passes and automatically terminates the runwhen the number of passes exceeds 20,000. When stepsize is varied, it is a good idea to call for XSTPSZ,PLOT under the OUTPUTS instruction so that step size

El

la) VOLTAGESOURCEINDUCTOR LOOP

O(b) CURRENT -SOURCE

CAPACITOR CUT SET

Ic) DC SOLUTION FOR LOOP Id) DC SOLUTION FOR CUT SET

4. T r.polog Ica I restrictions. To solve the dc case (initial conditions)for a voltage -source inductor loop (a) or a current -source capacitorcut set (b), Sceptre requires the addition of a resistance-in seriesfor the loop (c) and shunting for the cut set (d).

Nonlinear computer programsAt present, there are four computer -aided design pro-grams for solving nonlinear circuit problems: Sceptre,NET -1, Circus and TRAC. Each one has its own specialapplication and, when properly matched to a problem,will minimize both time and cost. Generally, Sceptre isconsidered the most powerful, flexible, and expensiveof the four; it can solve many problems beyond thereach of the others.

NET- I (network analysis program) employs predeter-mined stored Ebers-Moll models of junction diodesand bipolar transistors for a good compromise betweenspeed and accuracy. But the program's flexibility is lim-ited. NET -1 does not allow the user to account for suchthings as junction breakdown, base narrowing or con-ductive modulation.

Circus (circuit simulator) employs a somewhatawkward charge -control model that is mathematicallyequivalent to the Ebers-Moll model. Program restric-tions include acceptance of only pulse or sine inputs,limited element library, and no tables or analytical ex-pressions.

TRAC (transient radiation analysis by computer) cannothandle stored elements, tables, or analytical expres-sions. However, a problem that can be solved withTRAC will be done more economically and faster thanwith Sceptre.

is plotted as a function of time.Sceptre has three integration routines: TRAP, XPO,

and RUK, which (in this order) are increasingly accu-rate, time consuming, and costly. For most applications,XPO, which gives a 2.5 -term approximation of the Tay-lor series, offers optimum speed and accuracy.

Although Sceptre can handle up to 300 circuitbranches, it is advisable to limit the number of branchesto 70. The Fortran compiler cannot handle more than70 branches at once, and large programs become diffi-cult to run.

There are several reasonable topological restrictionsimposed by Sceptre for dc solutions. Two are shown inFig. 4-a voltage -source inductor loop and a current -source capacitor cut set (dual of a loop, connecting onenode to another node). The dc case for these problemsis solved by adding a small resistor, Rx, to the loop anda large resistor, R), to the cut set. The resistors shouldbe eliminated for the transient run since cut sets andloops are acceptable for the integration routine. Itshould be noted that a diode, instead of a resistor, canbe used to prevent the formation of a cut set, as it doesin the Ebers-Moll model.

Very small and very large passive element valuesshould be avoided in Sceptre because of the time con-stant problem. Also, zero values of resistance, induc-tance, or capacitance will cause a run to terminate inFortran. Because Sceptre can plot the current throughvoltage sources and the voltage across current sources, azero -impedance element can be represented by a zero -value voltage source, and a zero -value current generatormakes an ideal infinite -impedance element. Moreover,the diode capacitances in the Ebers-Moll model shouldnot be neglected since their exclusion would cause solu-tion errors.

135

Optinet guides electronic productsfrom design through marketingSoftware system goes beyond usual optimization and anaysis functionsof CAD programs-helping users develop a prototype,control production, and dramatically expedite marketing procedures

by Robert Hall, Dean Hall Associates Inc Los Altos, Calif.

The various people involved in designing, building,and selling electronic equipment have various require-ments-the engineers want to optimize design, the pro-duction staff aims for maximum efficiency, and the mar-keting men seek to reach the right customer. Now theyhave a software package that can satisfy all of theirgoals. Called Optinet, the program can be used to opti-mize circuit designs, keep track of production controls,and expedite marketing procedures.

Optinet includes a full set of computational facilitiesand uses them to perform modeling with variable para-meters. Also provided is storage for models, solutions,and intermediate results, as well as commercial productdata. Another feature is a dial -up access capability thatbrings the system to manufacturers and customers.

The software package is available through Nationalcss Inc., Stamford, Conn., and Sunnyvale, Calif. Bynext March, other time-sharing services are expected tooffer the program.

Optinet generally requires a large computer facilityon the order of the IBM 360/67. The program is writtenin Fortran 4. Though Optinet is one of the fastest andleast -expensive analysis programs available, designanalysis itself is not always the highest -priority consid-eration when introducing a new product. With its sensi-tivity analysis, worst -case diagnosis, production mod-eling, and market data capabilities, Optinet can cutcosts and time involved in the critical process of trans-ferring the product to the production and marketingstages.

Optinet is designed for devices, components, and sub-systems that can be described in terms of piecewise-linear ac models. Additional modeling capability isadded regularly so that the system will be able tohandle dc, nonlinear and transient calculations some-time next year.

A closer look. Modeling with Optinet is straight-forward. Networks are broken down into subnetworks,sections, and elements. A catalog of more than 75 ele-mentary sections provides easy access to lumped, dis-tributed, active, passive, analytical, numerical, andhypothetical models. Up to 15 networks can be definedsimultaneously, each with its own frequency range andperformance requirements, permitting modeling ofpiecewise-linear and multistate networks. A total of 15elements in these networks may be identified as thevariable parameters of the model.

Basically, Optinet requires three types of files-net-work, frequency, and performance-to solve an analysisproblem. They are numbered to correspond to eachother; for example, files N I, F 1, and P 1 form a set, asdo files N2, F2, and P2. Up to 15 complete file sets areavailable. The network file gives the circuit description,the frequency file lists the frequencies of interest withina design band, and the performance file defines circuitrequirements.

Data files (30 in all) are independent of the other filesand contain values of frequency -dependent circuit ele-ments or circuit specifications, which are defined in ei-ther a network or performance file. These data files canbe used anywhere in the analysis.

A variable file is required for design, because the usermust specify the circuit elements he is willing to vary tomeet desired performance specifications. This file allowseither a circuit element as called out in a network file ora circuit parameter as specified by a performance file tobecome a variable. Limits and nominal values for thevariables are established by the file, which can containup to 15 lines.

A criterion file is also required for Optinet's designcapability and can have up to 15 lines. The criterion filedefines a function that represents best circuit perform-ance. The function usually has one form for perform-ance optimization and another for worst -case analysis.For example, an optimization criterion could be a func-tion whose minimum value represents best perform-ance, while a worst -case criterion could be a functionthat goes to zero if desired specifications are not met.

Optinet provides a sensitivity analysis capability, too.It can vary individual parameters by any desired per-centage and print the resulting variations of the per-formance requirements. A trace capability lets the userplot frequency -dependent performance as a function ofa variable parameter over its entire range.

Ample storage facilities are another feature: up to 15complete problem groups can be saved in a private diskarea. When a problem group is retrieved, the contentsof all files are reset exactly as they were when the prob-lem group was saved. The problem then may be contin-ued from the last result.

Information for use by multiple subscribers may bestored in read-only files for general access. The contentsare retrieved by code names supplied along with the in-formation at the time it is stored. These names also can

136

INPUTMATCHINGCIRCUIT

(a) AMPLIFIER BLOCK DIAGRAM

GAIN -

LEVELINGCIRCUIT

HEWLETT PACKARD 35821E

IbI TRANSISTOR CHARACTERIZATION

OUTPUTMATCHINGCIRCUIT

FORWARD NETWORKAVERAGE VALUES

GM DBR OHM

OHMRHM

2

=

=

6.4985519.000110.2284.470666

REVERSEAVERAGE

GMR

RHM

NETWORKVALUES

DROHMOHM

5

=

=

.

=

-19.096139.0471-46.3705.482

MAXIMUM VALUES MAXIMUM VALUES

GM DB . 9.39645 AT F 1.6 GHZ GM DB = -17.4579 AT F = 3 GHZ

R OHM . 20.2859 AT F = 3 GHZ R OHM 52.4157 AT F = 1.6 CH7

OHM 16.3528 AT F 3 GHZ OHM . -40.3196 AT F = 3 GH7

RHM .48 AT F = 2.39999 GHZ. RHM .520001 AT F . 3 GHZ

MINIMUM VALUES MINIMUM VALUES

GM DR = 4.02796 AT F 3 GHZ GM DB = -21.2096 AT F = 1.6 GHZ

OHM = 18.17 AT F = 1.6 GHZ R OHM = 28.2906 AT F = 3 GHZ

OHM = 4.14764 AT F = 1.6 GHZ OHM = -52.9882 AT F 1.6 GHZ

RHM .469999 AT F = 2.1 GHZ RHM = .46 AT F = 1.7 GHZ

1. Desired amplifier. Transistorized microwave amplifier (a) must supply gain of 12 decibels 3- 1 dB and have 50 -ohm input and output im-

pedances from 1.6 to 3 GHz. Due to transistor transmission characteristics, gain-leveling and matching circuits can be separated. Important

transistor properties are tabulated in (b) for forward and reverse performance.

be stored in a directory that can be printed out duringany Optinet session.

The program uses a time-shared computer systemprimarily because it is the best choice of communi-cations. Through time-sharing, Optinet can rapidlyservice scattered users by providing mutual access tomodels and performance criteria.

Furthermore, Optinet offers a number of conveniencefacilities. For example, it controls the cost of compu-tation. Total dollar expenditure is reported on demand,and estimates of the cost of computation are availablebefore the computation is run.

Information and diagnostics keyed to the currentstate of the problem may be obtained by typing "?".Successively deeper explanations are given when "?" istyped again. Also included is an adaptive editor tospeed the flow of information, manage files, and adjustto the user's style.

Design example. How Optinet works is best illus-trated by following a hypothetical project from designthrough marketing, and restricting the example to fourbasic areas: design, interpretation of measured data,production control, and marketing.

Suppose the desired product is a broadband amplifierthat uses microwave transistors. Its specifications are: aminimum gain of 12 decibels with a flatness of ± 1 dB; a

center frequency band of 2 to 2.5 gigahertz; a totalbandwidth of 1.6 to 3 GHz; a minimal number of stages;and 50 -ohm input and output impedances, with max-imum reflection coefficients of 0.2.

Data on a suitable transistor is prestored in the Opti-net public data file by the device's manufacturer. UsingHewlett-Packard's type 35821E transistor for this ex-ample, it is characterized in the file by S parameters at15 volts and 15 milliamperes over a frequency range of100 to 4,500 megahertz.

The major transistor design problems are gain vari-ation and mismatched input and output impedances.Since this particular transistor has low reverse trans-mission, gain -leveling and matching circuits can be sep-arated as shown in Fig. 1(a). Transistor properties rele-vant to the problem are computed from S parametersstored in the public file, as shown in Fig. 1(b).

Optinet describes the transistor for both forward (in-put) and reverse (output) characteristics. Average, max-imum, and minimum values are tabulated for gainmagnitude (GM), resistance (R), reactance (x), and re-flection coefficient (RHM). Also noted is the frequency atwhich the value occurs as well as its units callout. Forexample, maximum input resistance is 20.2859 ohms at3 GHz, while minimum output resistance is 28.2906ohms at 3 GHz.

137

(a) PARTIAL AMPLIFIER NETWORK

RS

SOURCE H -P 35621E

SECTION 1 SECTION 2CATALOG S1 65ELEMENT 1/5 RS S11M S21MELEMENT 2/6 XS S11P S21PELEMENT 3/7 ZO S12M S22MELEMENT 4/8 S12P S22P

lb) NETWORK FILE

16.6 nH

1.23 pF

N2

SECTION CATA Lon FLF.MFNT1/51 S1 502 65 1C1D9

105D133 16.6C124 2 4.3C105 G5 109

1013Li 50

(c) FREQUENCY FILE

F2LINE FREQUENCY

DATA FILE

D13LINE DATA

1 1.6 1 2.952 1.7 2 2.33 1.8 3 2.62

1.9 4 2.545 2 5 2.376 2.1 6 2.37 2.2 7 2.158 2.3 8 2.68q 2.39999 9 1.98

10 2.49999 10 1.9111 2.59999 11 1.8612 2.69999 12 1.7713 2.79991 13 1.7314 2.89999 14 1.6315 3 15 1.59

10 -'MHO

SECTION 34

L

C

G

4.3 nH

H -P 35821E

SECTION 4 SECTION 52 65L S11M S21M

S11P S21PS12M S22MS12P S22P

El EMENT2/6 FLEMENT3/7 E I FMENT4/E0 5n

1C21)111 1C3D11 1041112106014 icinn irvir,1.23C9 1E-5

1D10 1D11 1D1211114 1D]5 1D1C

0

(dl VARIABLE FILE

V

RL

LOAD

SECTION 6L1

RLXL

LINE notimori NED-BOUND POS-BOUND VA LUE1 9 1 2 1.232 10 2 6 4.33 11 11 13 12

12 10 2C 16.6

(e) PERFORMANCE FILE

P2LINE MEASURE

1 nm2

3 X

(f) CRITERION FILEC

FORMPLOTD102

WEIORT10

LINE OPERATOR SOURCES1 SUM P2

REFERENCE cnvnnaF12C11 SO

2. Gain -shaper. Partial amplifier (a) is described by its network file (b). Frequency file (c) sets test frequencies in operating band, while datafile shows corresponding values of transistor gain. Variable file (d) establishes specification limits, performance file (e) defines amplifier gainrequirements, and criterion file (f) optimizes gain flatness.

Of the several procedures that could be used to de-sign the amplifier with Optinet, a very direct one is tofirst ignore input and output matching (since about thesame amount of gain is lost across the entire band dueto mismatching), and find approximate element valuesfor an interstage circuit that provides adequate controlover gain slope. Next, amplifier input and output im-pedances are computed and approximate element val-ues for 50 -ohm matching networks are found. Finally,the complete circuit is assembled, overall performancecriteria are defined, and optimization is used to adjustthe various element values for best performance.

The data in Fig. 1(b) indicates that the transistor's

maximum input resistance and minimum output resist-ance nearly match at the high end of the operating fre-quency band if a series inductance is used to balanceout reactance. It can also be seen that the gain rolloff,from a maximum of 9.4 dB at 1.6 GHz to a minimum of4 dB at 3 GHz, is about 6 dB per octave.

Since there are two transistors, approximately 12 dBof gain rolloff must be introduced at the low end to flat-ten amplifier gain response. Thus, at least three reactiveelements are needed to increase the gain control cir-cuit's reactance slope. Values will be chosen to providethe flattest and highest gain within the operating band.

Figure (2a) illustrates a partial amplifier design and

138

Fig. 2(b) is its description. The network is partitionedinto sections that correspond to lines in the network fileand elementary sections in Optinet's catalog of subcir-cuits. Elementary sections are represented by mnemon-ics (like Si and L1) or numbers in the catalog.

The mnemonics are listed in the CATALOG column ofnetwork file N2 to indicate which sections are needed.Certain element values are required to complete thesection description. For example, Fig. 2(a) shows thatsection 1 contains a voltage source (S1), described by asource resistance (Rs), a reactance (xs), and a character-istic impedance (zo). These elements are assigned ap-propriate numerical values each time they are used, asdone on the first line of the network file.

Eight S parameters are required to completely de-scribe each transistor's performance at any frequency.The S parameters are complex numbers forming a 2 -by -2 matrix, and are represented by mnemonics S 11Mthrough S22P (M is for magnitude, P for phase). Thedouble -number designation fixes the S parameter's rowand column location in the matrix. For instance, S11Mis the magnitude of the S parameter in the first row andfirst column of the matrix; S21P is the phase of the Sparameter in the second row and first column of thematrix. Because each transistor is described by identicalS parameters, only one set of eight must be stored; thesevalues go into data files D9 through D16.

Also included is a master numbering system for thecircuit elements. Every network file has four ELEMENTcolumns, differentiated by numbers 1/5, 2/6, 3/7, and4/8. A number is assigned to each element in a networksection. For any single section, Optinet can accept up toeight elements, the maximum required to completelydescribe any network section. From the network file ofFig. 2(b), it can be seen that section 2 comprises ele-ments 1 and 5 (1C1D9 and 105D13) through elements4 and 8 (1C4D12 and 1C8D16).

Section 3 of the partial amplifier calls for catalog sub -circuit number 4, which is a parallel inductance (L), ca-pacitance (C), and conductance (G). Because the con-ductance merely accounts for minor parasitic losses, it isspecified as 10v5 (noted as 1E-5 in Fortran) mho.

Program files. Network elements may be made vari-able and/or frequency -dependent. Figure 2(c) shows afrequency file; it gives the frequency points to be eval-uated and the data file for S21M. The latter representsthe variation of element S21M over the frequency rangecalled for in frequency file F2. Whenever network per-formance is computed, the appropriate gain for S21M ischosen from data file D13. If the frequency of interest is2 GHz on line 5 of the frequency file, corresponding gainis 2.37 on line 5 of the data file.

If an element value is stored in one of 25 special loca-tions, called common storage locations, it can be usedfor several elements in a network and/or it can be madea variable parameter. To be stored in one of these loca-tions, a flag designated by a mnemonic Cl through C25must immediately follow the element's numerical value.Element values stored in this way act as multipliers.

Data files can be treated similarly. If data files arecalled out as shown for the eight S parameters (1C1through 1C8) in line 2 of network file N2, the elementvalue is the number stored in the selected common loca-

tion multiplied by the appropriate data file entry.The variable file of Fig. 2(d) specifies a set of variable

parameters whose values are to be adjusted for best per-formance: up to 15 numbers of a maximum of 25 storedin common locations Cl to C25 can become variables.These are listed (by number) in the COMMON column. Arange for each variable must be defined by listing itslower limit (NEG-BOUND) and upper limit (PosBouND).Nominal variable values are called out in the VALUEcolumn.

Variable file V presents the data for amplifier gainand the passive gain -leveling circuit elements shown inFig. 2(a). Line 1 calls for the 1.23-picofarad capacitorstored in common location C9, line 2 the 4.3-nanohenryinductor in C10, and line 4 the 16.6-nH inductor in C12.Line 3 stores amplifier gain in common location C11and confines its value to 12 ± 1 dB. Storage locations forgain -control elements are also noted in the network file.

Values of variables may be assigned or changed bymaking an appropriate entry in the variable file, as wellas in any file where the common location is referenced.Variables are required for all of Optinet's higher com-puting functions, such as sensitivity analysis and optimi-zation. During optimization, any changes in variableparameter values are readily examined by printing thevariable file.

The performance file of Fig. 2(e) defines the proposednetwork's performance requirements. Line 1, for in-stance, requests the gain magnitude (GM) to bepresented in the form of a plot versus frequency when-ever the network is analyzed. The REFERENCE columncites the nominal value of the variable of interest (gainmagnitude in this case) and its storage location. Acallout of 12C11, for example, refers to the variablelisted on line 3 of the variable file; its nominal value is12 and it's stored in common location C 11.

The gain affects the criterion function because itsweight is positive (not zero). Weight value is assignedby the user and reflects the relative importance of thequantity being computed.

Two other factors influence the weight value. One isthe magnitude of the quantity, and the other is how of-ten it is computed during a run. Gain, for example, iscomputed 15 times (because of the 15 frequencies in theband) and has a high value of 10 to 15 dB. Reflectioncoefficient, however, is found only once in the band andhas a low value of 0.1 to 0.2. To make these two quan-tities approximately equal in importance, the user couldassign a weight of 1 to the gain and a weight of 1,500 tothe reflection coefficient.

Since gain is specified as a point -by -point measure(Purr) in performance file P2, it contributes a value tothe criterion function at each point in the operating fre-quency band. This value is the WEIGHT (10) multipliedby the square (sQ) of the difference between the gainmagnitude and the reference. The COMPARE column inthe performance file indicates what mathematical oper-ation should be carried out.

if

Minimizing the criterion value, WEIGHT (GM-REF)2,will bring the gain closer to the reference at each pointin the band. Since the reference is a variable parameter,an optimization search can adjust it to a value that givesthe flattest gain curve.

139

(a) FINAL AMPLIFIER DESIGN

2.9 nH 2.36 nH 3.14 pF-____mm_______4,..._____mers__

17.4 nH

1.4 pF 4 nH 6.1 nH 3.7 nH

1 8 3 nH

_II_ .

'pF 10 MHO

35821E

1.26 pF

35821E

i

(b) NETWORK FILE

NO

SECTION CATALOG ELEMENT1/5 ELEMENT2/6 ELEMENTS/7 ELEMENT4/8

2 2 2.891730163 11 1. 800250114 2 2.361160I85 12 3.0268IC196 1 3.13776C207 05 1C1D9 1C2D10 1C3D11 1C4D12

105D13 1061114 1C7015 1C8D168 4 17.412C12 1.39919C9 1E-59 2 3.99244C10

10 65 109 1010 1011 10121013 1D14 1015 1016

11 2 6.0872C1312 11 1.2579801413 2 3.71329C15

(c) PERFORMANCE

FORWARD NETWORKAVERAGE VALUES

GM DsRHM

MAXIMUM VALUES

GM 09RHM

MINIMUM VALUES

GM DBRUM

PROCEED WITH PLOTS?

GM DB 13.95$ OHM

1.

1.67

1.41.9

2

2.1FRE() 2.211Hz 2.3

2.399992.499992.599992.699992.799992.69999

CHECK

2

14.4017 .137713

14.9977 AT F 2.79999 DMZ .214116 AT F 2.59999 0142

13.997 AT F 2.2 GHZ .015975 AT F 2 GHZ

(Y OR (42( Y

14.25 14.55 14.65 15.15 15.4'0 .0500001 .1 .15 .1

I I I 1 1I

;;a :::::

...-- REFLECTIONK.:::- -

COEFFICIENT-i14.

.. 1GAIN ...

___3 4r.

3. Optimum amplifier. Final optimization results in amplifier shown in (a) and described by network file (b). Optinet can also predict per-formance of finished amplifier. Performance check (c) notes that minimum gain is 14 dB at 2.2 GHz, and maximum input reflection coefficientis 0.22 at 2.6 GHz. Gain and reflection coefficients are plotted.

For optimization, only the first line of performancefile P2 is used, because the other lines have no weights.When an analysis is run, the network gain magnitude isplotted, and network input resistance (R) and reactance(x) are automatically computed and stored in files D1and D2 for use in solving the input matching problem.

The criterion file of Fig. 2(f) gives the final require-ments for a function whose minimum represents bestperformance. Contributions from one or more perform-ance files can be combined to create the criterion func-tion in the way specified by the OPERATOR column. Pos-sible operators are sum (sum), maximum (mAx), andproduct (PRO). Sum and maximum are generally usedfor design purposes, while product is usually listed forworst -case analysis. Performance files to be combined toform the criterion function are listed in the SOURCEScolumn.

First -order design. Now that the Optinet files neededfor a solution are established, the amplifier design prob-lem can be run. Figure 2 contains all the files needed toestablish an interstage gain control circuit.

Next, an output matching network can be found bycomputing input and output impedances across the op-erating band. The complete first -order design is thenoptimized to produce the best performance.

The final amplifier design, its network file, and a finalperformance check are shown in Fig. 3. As indicated inFig. 3(c), the amplifier's maximum reflection coefficientdoes not quite meet desired specifications; its value is0.216 at 2.6 GHz. Minimum gain, however, exceeds theoriginal design objective with a value of about 14 dB at

2.2 GHz. To improve the reflection coefficient, anothercomputer run would be necessary and some degrada-tion permitted in gain performance.

With the initial part of the product design finished,the time and expense incurred thus far can be exam-ined. Slightly more than 24 engineering hours in addi-tion to seven hours on a time-shared terminal are re-quired. A reasonable time -and -cost estimate for theentire design task is about a week of engineering timeand around $300 to $700 for computer time, includingthe investigation of alternative circuits.

The design is not complete until sensitivity and worst -case performance are checked. Optinet's sensitivityanalysis indicates the change in network performance aseach variable circuit element is individually increasedby some small amount. Worst -case analysis predicts cir-cuit performance if all the variables are changed simul-taneously. For this amplifier, the key performance spec-ifications are minimum gain and maximum inputreflection coefficient.

For sensitivity analysis, these two performance mea-sures are called for by altering performance file P2 asshown in Fig. 4(a). The variables to be changed are thegain and circuit elements whose optimized values areindicated for the amplifier of Fig. 3(a). Nominal valueof each variable will be increased by 1%.

Figure 4(b) illustrates the results of the analysis (po-tentially troublesome areas are surrounded by boxes).Nominal values of gain and reflection coefficient areprinted, along with the incremental change that occursin these quantities when a given variable is increased.

140

Numbers 1 through 11 correspond to the variableslisted on the same -number lines in the variable file.

A 1% increase in variable 1, the 1.4-pF capacitor inFig. 3(a), causes a 0.003 increase in the reflectioncoefficient and a 0.07 -dB increase in the gain. For thisdesign example, an increase in any variable causingmore than a 1% change in a performance measure isconsidered potentially troublesome. Therefore, any in-crement greater than 0.002 in the reflection coefficientand greater than 0.14 in gain is surrounded by a box inFig. 4(b). (Note that gain performance never goes out ofspecification; taken as a whole, the amplifier design is

satisfactory.)The cost of sensitivity analysis is usually nominal (un-

der $10 in this case). The analysis not only pinpoints theelements that may need to be adjusted in the final de-sign but also helps to define acceptable tolerances onother elements. And it could be useful to overdesign acircuit by using more than the minimum number of cir-cuit elements, thereby reducing all of their sensitivities.

Worst -case analysis is the next step. Optinet can de-termine what specifications will not be met, at what fre-quencies in the band, as well as for what combinationsof component values and value tolerances. The neces-sary files are given in Fig. 5(a); these must be usedalong with the network file of Fig. 3(b).

Worst -case analysis. For the amplifier example, theworst -case criterion function must go to zero if the de-sired specifications are not met at any point in the band.The variables in the variable file are normalized valuesof the eight S parameters that characterize each transis-tor. The boundary values shown reflect a ± 10% toler-ance as specified by the manufacturer.

Performance file P2 places an upper bound (UB) onminimum gain to assure that the first term in the crite-rion function will be 0 if the gain falls below 13 dB. Line2 of the file sets a lower bound (LB) for the maximumreflection coefficient to make certain that the secondterm of the criterion function is 0 if the maximum re-flection coefficient in the band exceeds 0.33. The prod-uct operator (FRO) in the criterion file sets the criterionfunction equal to the product of the terms in file P2.

When the worst -case performance objectives definedby the performance file are exceeded, Optinet termi-nates the search and prints the results as shown in Fig.5(b). The normalized S parameters that cause worst -caseperformance are listed in the VALUE column of a newvariable file. (Note that none of the worst -case S para-meter values exceed their specified tolerance.)

According to the analysis, the reflection coefficientwill be 0.346 at 3 GHz and, therefore, not within specifi-cation. Minimum gain, however, stays within design ob-jectives -its value is 13.9 dB at 1.8 GHz. Worst -case anal-ysis always identifies the frequency with the poorestperformance.

When the limit for the maximum reflectioncoefficient is changed to 0.5, gain variation is empha-sized. Running through worst -case analysis again yieldsthe results shown in Fig. 7(c) and a different set of S -parameter values. Gain will be just over 13 dB at 2.2GHz and still within specification. Reflection coefficientalso meets the desired limit with a value of 0.346 at 3GI -1z. Cost for this worst -case analysis is about $55.

(a) PERFORMANCE FILE FOR SENSITIVITY ANALYSIS

P2LINE MEASURE FORM

1 CM MIN2 RHM MAX

(b) SENSITIVITY

FORWARD NETWORK 2

PERFORMANCEPARAMETER VALUE

MAX RHMMIN GM

.21611613.997

PERFORMANCEPARAMETER VALUE

WEIGHT REFERENCE COMPARE

ANALYSIS RESULTS

INCREMENT OUE TO 12 CHANGE IN VARIABLE1 2 3

En=.070467 .046E922

5.02765E-4.0131348

INCREMENT DUE TO 1% CHANGE IN VARIABLE7

MAX RHM .216116 .00141792 I.R0125E-4 -7.512E-4 MEMOMIN GM 13.997 .00505447 .00344276 -.004911772 -.

PERFORMANCE INCREMENT DUE TO 11 CHANGE IN VARIABLE

PARAMETER VALUE 9 10 11

MAX RHM .216116 .00196241 8.47638E-4 .00172377

MIN CM 13.997 -.00534058 .0O244141 -.0E295639

4. Sensitivity analysis. Performance of final amplifier is checkedfor sensitivity to changes in individual variables. A 1% increase ineach variable is introduced separately. Performance file (a) indicates

that gain and reflection coefficient should be tested. Results in (b)

have possible trouble spots noted with a box.

The worst -case performance study indicates the Sparameters that should be avoided at specific fre-quencies for acceptable amplifier performance. Vari-ations in transistor parameters generally are compen-sated for by adjusting circuit elements, and Optinet candetermine appropriate ranges and parameters.

Another application for the Optinet system is inter-pretation of measured can deter-mine the values of the variable model parameters thatprovide the best fit between computer and measureddata. Using this feature requires that a bench model ofthe Optinet-designed amplifier be built and tested.

Because of tolerance ranges in purchased compo-nents, it's highly unlikely that the test data for the pro-totype will accurately match predicted performance.But Optinet accepts the measured performance dataand finds the new variable values needed to make mea-sured performance match the computed. The programindicates those parts of the circuit responsible for anydiscrepancy and notes corrective action required.

Implementing this Optinet feature involves using thesame files that are employed for design. However, themeasured data is stored in data files to establish ampli-

. fier performance for each frequency in the band. Thesedata files are then listed in the REFERENCE column of aperformance file. Optinet will automatically adjust cir-cuit element values to achieve the best match for thereference (measured) data. The user then can determinethose elements that require adjustment and by whatamount.

Production modeling. Transferring a product fromdevelopment to production usually causes many prob-lems. Some can be reduced or even eliminated if bothan Optinet model and prototype are available to pro-duction personnel.

A study of the prototype quickly shows what toler-ance must be held and what performance changes oc-cur, with certain circuit element variations. As pilot

141

(a) FILES DEFINING WORST -CASE ANALYSIS

V

LINE COMMON NEC. -ROUND Pm -Boutin VALUF1 1 .9 1.1 12 .9 1.1 13 3 .9 1.1

4 .9 1.1 15 5 .9 1.16 6 .9 1.17

8

7

8 .91.11.1

P2

LINE MEASURE. FORM WEIsHT RFFFI'EMCF COMPARE1 Oft MIN 1 13 UR2 RHM MAX 100 .33 LP

C

LINE OPERATOR SOURCES1 PRO P2

(b) WORST -CASE ANALYSIS RESULTS

V

LINE. COMMON NES-ROUND POS-ROUND VALUE1 1 .9 1.1 .9993432 2 .9 1.1 .9458083 3

4

.9

.91.11.1

1.0627.949303

5 5 .9 1.1 .9903296 .9 1.1 .990838

7 7 .9 1.1 1.027448 8 .9 1.1 1.04C263

FORWARD NETWORK 2

MAXIMUM VALUES

RHM = .346239 AT F = 3 nPz

MINIMUM VALUES

nm DR = 13.9353 AT F = 1.8 nm7

(c) MODIFIED WORST -CASE ANALYSIS

V

LIME rommor! tiEn-snumn PrIs-ROUND VALUE1 1 .9 1.1 1.043182 2 .9 1.1 .9150403 3 .9 1.1 1.079184 4 .9 1.1 1.033495 5 .9 1.1 .9124436 6 .9 1.1 .9040257 7 .9 1.1 1.003448 8 .9 1.1 .921671

FORWARD NETWORK 2

MAXIMUM VALUES

RHM = .324711 PT F = 3 sul

mINIMUM VALUES

GM PR = 13.0834 AT F = 2.2 C.M7

5. Worst -case analysis. If all circuit variables are changed at thesame time, amplifier performance can be checked for worst -caseconditions. Files (a) define worst -case gain (GM) and reflectioncoefficient (RHM) when transistor S parameters are varied by± 10%. Printouts (b) and (c) show results.

models are built and checked. Optinet can interpret testdata for the adjustment of the production process toprovide target performance. Optinet also can even con-tinuously monitor production so that drifts can be cor-rected before the product goes out of specification.

Optinet also can compensate for variations in state-of-the-art components that may be the only devicesavailable for a given production run. With an Optinetproduction model of the whole product, data on thedoubtful parts can be entered into the program. Optinetthen will investigate the corrective action possiblethrough controlled changes in other circuit parameters.

Another consideration in production modeling is an-swering requests for quotations that involve some de-viation from standard performance. It may be difficultto determine quickly whether these special specifica-tions can be met on the production line. With Optinet,the special specifications can be used in the optimiza-tion routine. Knowing the best values for the elementsand the best performance obtainable can greatly im-prove bidding accuracy and production planning.

Marketing. The final step in developing a new prod-uct is marketing. Through its public data file, Optinetcan make this task easier, as well as reduce time and ex-pense for both seller and buyer. Since the program isavailable through a time-shared network, any sub-scriber has easy dial -up access to the public file and,therefore, to the Optinet product model. A potentialcustomer can explore the properties of the product oreven run through a complete design, as was done herewith the Hewlett-Packard transistor.

Instead of spending months exchanging samples,building prototypes, and trying to agree on mutually ac-ceptable product performance, the manufacturer andhis customer can trim this exploratory period to a mat-ter of weeks. Costs, too, are dramatically reduced be-cause less engineering time is needed.

Suppose a conventional sample -and -build period isabout three months. Engineering costs, including sup-port and overhead expenses, normally would be about$10,500. Optinet could reduce the time factor to twoweeks, dropping engineering costs down to $1,750. Add-ing about $700 for computer time brings the total ex-penditure to $2,450, a significant saving.

Since Optinet's public data file has the same capacityas its working file, there is ample space to store productdata, frequency ranges, performance properties, andcomponent tolerances. The amplifier example could berepresented explicitly by its network file description. Orthe circuit's two -port performance may be given interms of S parameters or any other equivalent nu-merical description.

If an Optinet subscriber already has a model in hisprivate files, it can be transferred to the public diskwithout charge and stored for $10 to $20 per month.The public file can be updated from subscribers' privatefiles at any time.

As the Optinet system grows in scope, the catalog ofproducts in its public data file also will grow. It shouldbe remembered, however, that the program's most up-to-date source of product information is its directory,which can be listed simply by giving a command duringan Optinet terminal session.

142

Program calculates load effectsof high-speed digital circuitsDigital interconnections are analyzed by program called Line as ifthey were transmission lines; from a minimum of,input data itaccurately computes line voltage, plots ringing characteristics

by Laurence P. Flora, Burroughs Corp., Pasadena, Calif.

High-speed digital circuitry often lands its designerwith the job of analyzing the loading effects, like circuitringing and delay, that result from line discontinuities.This analysis is highly complex, and requires a com-puter's speed and accuracy.

However, it has to be performed in terms of trans-mission line equations, and ECAP (electronic circuitanalysis program) and its equivalents are really onlysatisfactory for standard lumped -constant circuitry. Alumped -element model doesn't fit transmission lines tooaccurately. Besides, the programs take an extremelylong time to solve even moderately complex problemsof this nature.

To help the engineer plot an accurate analysis of ahigh-speed transmission line, a program called Line wasrecently developed. It's based on a general load config-uration that represents all circuits to be used in the sys-tems under study. It also is based on what the generalload effects are when a unit step or unit ramp functionis transmitted down the line, and closely approximatesany reflection without reference to the line's historyfrom time zero. The program, which is written in For-tran, is conversational, and can be run on a time-sharedterminal. In contrast to existing computer programs,Line can precisely analyze a transmission line problem,but it cannot handle a general circuit consisting of vari-ous lumped components.

Line makes use of the accurate, yet general, load con-figuration of Fig. 1. Besides being an adequate repre-sentation of the circuits used in most systems, this RCnetwork may also model a purely resistive discontinuity(i.e., when R, = 00) or purely capacitive discontinuity(R5 = 00, R2 = 0, and R3 = co).

Computing the reflection

To understand how Line solves for general load ef-fects, consider the response of a line to a unit step or aunit ramp function. These two forcing functions arechosen since either provides a good approximation formost input waveforms.

For the load of Fig. 1, the reflection voltage due to aunit step function is:

[Vr(t)]step = K2 + (K, - K2)e-tir (1)while a reflection voltage due to a unit ramp functioncan be expressed as:

[Vr(t)]ramp = K2t + r(K,) - 1(2)(1 - e-t/r) (2) Now on educational leave at Massachusetts Institute of Technology, Cambridge, Mass.

where:K, = (R2R3 - ZoR, -.ZoR3)/(R2R3 + ZoR, + ZoR3)

and:K2 = (R,R, + R2R3 - ZoR, - ZoR, - ZoR3)/

(R,R3 + R2R3 + ZoR, + Zolt, + ZoR3)and:

r = Ci(R,R,R, + ZoR5R2 + ZoR5R3)/(R,R3+ R2R3 + ZoR, + ZoR, + ZoR3)

and Zo is the line output impedance.Now the solution can be generalized, and compu-

tation time minimized. Since the reflection voltage mayassume an infinite number of waveforms, the final solu-tion must be some approximation that produces accu-rate results from a minimum of information. With suchan approximation, comparatively little need be knownabout the line's immediate past history, and the com-plexity due to multiple reflections is minimized.

Of course, any waveform can be approximated as aseries of small steps. But a better approach in this con-text is to use a series of small ramps, since this is nearlyan exact approximation of a pulse with a finite risetimeand falltime - the usual shape of waveforms trans-mitted over lines in high-speed digital systems.

Assume that the input waveform is a ramp with aslope of A volts per second up to time T1. Then, at Tthe slope increases by an amount B, which gives a newslope of A + B. By superposition, reflection voltage is:

Vr = A[Va].,U(t) + B[Vr(t - TilrampU(t - T1)where U(t) is a unit step function, and U(t - T5) a de-layed unit step.

The forward voltage at time T which is represented

1. General load. RC network accurately represents most loadedtransmission lines in high-speed digital systems. When R2 - cc, it isresistive; when 13, 00, R2 - 0 and R, oo, it is capacitive.

143

ENTER

REQUEST COMMANDREAD AL STRING

WHAT IS NEXTWORD ?

NO MOREWORDS

PRINT ERRORMESSAGE

ADD CHANGEAND

LOADLOADS

READ LINE IMPEDANCE,PROPAGATION VELOCITY

READ CALCULATION TIMEINTERVAL, LINE LENGTH

IS LINE TOO LONG

NO

STORE CONSTANTS

[READ GENERATORIMPEDANCE

IND GENERATORREFLECTION CONSTANTS

READ DISCONTINUITYDATA

FIND REFLECTIONCONSTANTS FOR EACHDISCONTINUITY

YES

PRINT FP OR

RUN EXECUTECOMPUTE

ARE DISCONTINLI ICONSTANTS STORE,

NO

READ CONSTANTS

YES

READ TIME LIMIT,INITIAL LINE VOLTAGE,GENERATOR VOLTAGE

DOES SEGMENT CONTAINDISCONTINUITY?

NO

PLOTGRAPH

READ DISCONTINUITIES,MAX AND MIN VOLTAGES

PLACE PLOTTINGCHARACTER IN OUTPUTARRAY FOR EACH VOLT-AGE TO BE PLOTTED

PRINT ARRAY

REPEAT FOR

EACHVOLTAGE

YES

FIND NEW INCIDENTVOLTAGE FROMREFLECTION CONSTANTSAND DATA FORADJACENT SEGMENT

STORE INCIDENT VOLTAGESAT THIS DISCONTINUITY

ADD LEFT AND RIGHTINCIDENT VOLTAGES

STORE TOT AL VOLTAGE

REPEAT FOREACHSEGMENT

V

NEW INCIDENTVOLTAGE = INCIDENTVOLTAGE OFADJACENT SEGMENT

2. Flow chart. Once initial data iS entered, Line computes incident voltage and reflection constants for each line segment, storing only inci-dent and transmitted voltages from previous adjacent segment. There are three basic instructions: LOAD (describing physical line proper-ties), RUN (establishing initial electrical conditions), and PLOT (graphing reflection voltage at several load points).

144

3. Input voltage. Line accepts input waveforms as piecewise linear

functions with up to 20 breakpoints. For example, the voltage wave-form shown is described by an initial value (0,0) and four break-points with coordinate locations of (1,3), (4,3), (5,0), and (10,0).

by V, (T,), can be expressed as:

Vf(T2) = A [K2T, r (Ki - K2) (1 - e

And the final equation for the reflected voltage is:V. = V,(Ti)e-th'r + (A + B)[Vr(c10],amp

+ (ATIVr(c101.,ep - (AT,)(K, + 1)e -"'r (3)where:

V,(T,) = forward voltage at the end of the last timeinterval

Vr(dt)ramp = the unit ramp reflection of Eq. 2A + B = the new ramp slopeVr(dt)step = the unit step reflection of Eq. 1AT, = the incident voltage at the end of the last time

intervaldt = the time interval.Note that only two pieces of information about the

line's history need be saved for the next calculation-theincident voltage, AT and the transmitted voltage,V,(T,), at the end of the last time interval.

Using the resultsTo program Eq. 3 into a computer, the values of cir-

cuit variables R R2, R2, and C or mathematical vari-ables K1, K.2, and r must be stored. Also, the inputwaveform must be represented in memory, for example,by a table of voltages or by an equation.

The reflected and transmitted voltages are calculatedat each discontinuity, but need to be stored for only onetime interval. However, it is convenient to save thetransmitted voltage for each interval since the instan-taneous line voltage is the sum of two transmitted volt-ages (one for each direction). Some provision shouldalso be made for the distance between loads so that thetransmitted voltage (plus the reflected voltage due tothe voltage incident in the opposite direction) reachesthe next load after a suitable time delay.

The program Line reads the values of R,, R2, R2, andC and calculates and stores K K2, and r. The inputwaveform is described by a piecewise linear functionthat has up to 20 breakpoints. Total line voltage at eachdiscontinuity is also stored and can be plotted. Thecomputation interval is determined from the resolutionrequested by the user; it is the output time interval di-vided by 10. This allows a very close approximation of

any waveform, including a step with a fast risetime.The instruction sequence for Line is shown in the

flow diagram of Fig. 2. To start the program, the com-mand RUN LINE (or equivalent instruction, dependingon the time-sharing system used) is used. After this,there are three operating instructions that can be re-peated as many times as desired.

Operating instructions

The first of these is LOAD or LOADS, which allows theuser to describe the line's physical properties. Forproper operation, Line requires the line impedance, thepropagation velocity on the line, how often (at whattime intervals) the voltages should be computed, the to-tal length of the line, the impedance of the driving gen-erator, and the positions and values of loads on the line.

To describe a load for Line, load position (distancefrom the generator), and the values of R R2, R, and C,must be entered. Up to 19 loads can be accommodated.Constants representing the loads are saved in a disk file.

Any consistent set of units may be used. For instance,the system of ohms, feet, seconds, and farads is accept-able, and velocity would then be entered in feet per sec-ond. But this system may be cumbersome, and a moreconvenient set of units is kilohms, inches, nanoseconds,and picofarads. Velocity is then expressed in inches pernanosecond. (It should be noted that the unit of capaci-tance multiplied by the unit of resistance must be con-sistent with the unit of time.)

The second operating instruction describes the inci-dent voltage waveform, and uses the command RUN,EXECUTE, R, E, or COMPUTE. For this computation, Linerequests the maximum time for which the voltages areto be computed, the initial line voltage, and the break-points of the input voltage waveform. For instance, aninput voltage like the one illustrated in Fig. 3 would bedescribed by initial voltage (0, 0) and breakpoints (1,3),(4,3), (5,0), and (10,0).

The time at which the last breakpoint occurs must beequal to or greater than the maximum time for whichthe voltages are computed. When this last breakpoint isentered, Line calculates the voltage waveforms at everyload and writes them in a disk file.

If one of the commands describing the incident volt-age is given before the physical properties of the linehave been established (through a LOAD command), anerror message is typed. When this occurs, the commandRUN LINE must be entered again.

The third and last operating instruction, PLOT orGRAPH, causes Line to graph the voltage at one or moreof the load points. If several separate plots are desired,the command must be given several times. Line printseach load's number and position, and asks for the num-ber of waveforms the user wants plotted, plus the num-bers of those loads for which plots are desired.

Along with the load numbers, Line lists load posi-tions, and the typewriter character with which each loadwill be plotted. Finally, the program asks for the desiredminimum and maximum voltage scale for each plot. Allplots are superimposed. If either the PLOT or GRAPHcommand is given before the voltage waveforms havebeen computed, an error message is printed, and thecommand RUN LINE must be given again.

145

RUN LINERUNNING

WHAT IS YOUR COMMAND?ADD LOADS

WHAT IS THE LINE IMPEDANCE?.100

WHAT IS THE PROPAGATION VELOCITY?8

AT WHAT TIME INTERVALS DO YOU WANT THE VOLTAGES?1

HOW LONG IS THE LINE?60

THE LINE WILL BE BROKEN INTO SEGMENTS .800E 00 LONG.WHAT IS THE IMPEDANCE OF THE GENERATOR?.020

DISCONTINUITIES ARE OF THE FORM R1 IN PARALLEL WITHC, ALL IN SERIES WITH R2, ALL IN PARALLEL WITH R3.INPUT LOAD POSITION, C, R1, R2, AND R3.INPUT 5 ZEROS IF NO MORE DISCONTINUITIES.?1,0,1000,1000,1000?12,10,1000,.100,1.0?24,5,1000,.200,2.0?36,15,1000,.067,.667?48,5,1000,.2,2760,10,1000,.1,1?0,0,0,0,0

WHAT IS YOUR COMMAND?RUN

VOLTAGES WILL BE COMPUTED FOR EVERY.1002 01 INCREMENT IN TIME.

WHAT IS THE MAXIMUM TIME?100

WHAT IS THE INITIAL LINE VOLTAGE?0

INPUT WAVEFORM BREAKPOINTS BY ENTERINGTIME,VOLTAGE75,5?100,5

THE VOLTAGES AT THE DISCONTINUITIES HAVEBEEN WRITTEN IN THE OUTPUT FILE LINEV.

WHAT IS YOUR COMMAND?PLOT AND STOP.

NUMBER 1 2 3 4 5 6POSITION 0.80 12.00 24.00 36.00 48.00 60.00HOW MANY VOLTAGES DO YOU WANT PLOTTED?3

INPUT THE NUMBERS OF THE DISCONTINUITIESAT WHICH THE VOLTAGES ARE TO BE PLOTTED.?1,3,6

DISCONTINUITY PLOTTINGNUMBER POSITION CHARACTER

1 .800E 003 .240E 026 .600E 02

WHAT ARE THE MINIMUM AND MAXIMUM VOLTAGES?0,10

4. Line example. Sample program and plot shows total line voltageversus time for three points of discontinuity along a line. Differenttypewriter characters represent the three ringing waveforms, whichare plotted at 1 -nanosecond intervals.

A RUN command may be given several times, as canthe PLOT command. RUN causes Line to find the re-sponse of the loaded line to different input waveforms.Either STOP or END terminates the program.

It is also possible to obtain the voltage response atsome point on the Line where there is no load, withoutaffecting voltage at that point. The user simply inserts aload where desired by letting R2 and R3 be several or-ders of magnitude larger than the line impedance.

To make Line's commands more readable, punc-tuation and the words ADD, CHANGE and AND may beused. Then a simple command to completely describe aproblem, compute the waveforms, obtain a plot, andstop would be: ADD LOADS, RUN, PLOT AND STOP.

Figure 4 is a sample run of the program to find theringing characteristics of a line at three points of dis-continuity for 100 nanoseconds. Total line voltage isplotted at 1-ns intervals along the line. The program re-stricts minimum and maximum voltage excursions to band 10 volts, respectively, if the line voltage exceedsthese limits. 0Printed copies of Line are available at $0.75 each from the author, Laurence P. Flora, 40Highland Ave., Cambridge, Mass. 02139.

0. .50002 01 .7500SI I I

.1000B 01:

.2000E 01:

.30002 01:

.4000E 01: &

.5000E 01:

.60002 01:

:gggE gl:: &.9000E 01 &.10002 02 &.1100E 02 &.1200E 02 : &.13002 02 &,1400E 02.1500E 02.1600E 02.1700E 02.18002 02.1900E 02.20002 02.21002 02.22002 02,2300E 02.24002 02.25002 02.2600E 02.27002 02.28002 02.2900E 02.30002 02.31002 02.32002 02.33002 02'

.3400Eo2

.36002 02

.3700E 02

.3800E 02

.39002 02

.4000E 02

.41002 02

.4200E 02

.4300E 02

.4400E 02

.4500E 02.4600E 02.47002 02

.48002 02

.4900E 02

.50002 02

.5100E 02

.52002 02

.5300E 02

.550020202

.5600. 02

*

*

* &

&* & :

*A :*:

$4*

:

: & *: & *

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: &: & *

: && *

: &: & *

: &: & *:&*:&*

:&

&:

'A.'4:

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02.5900E 02 'A:

.6100E 02 *&:

.6200E 02 *4:

.63002 02 *4:

.6400E 02 *&:

.6500E 02 *4:

.66002 02 *4:

.67002 02 *:

.6800E 02

.69002 02

.7000E 02 *2

.71002'02 *:

.7200E 02

.7300E 02

.7400E.20 0202

.7600E 02

.77002 02

.78002 02 :1

.79002 02 :&

.80002 02 ;&

.81002 02 :&

.8200E 02 :&

.83002 02 :&

.8400E 02 :&

.8500E 02 :&

.86002 02

.87002 02

.8800E 02

.89002 02

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.95002 02

.96002 02.97002 02.98002 02.99002 02.1000E 03

END LINE 1 MIN, 33.4 SEC

146

Computer helps design ofcomplementary MOS logicAccurate characterization of MOSFET current -voltage curve permits computermodeling of silicon -gate C/MOS logic circuits; switching performance of bothcombinational and sequential logic circuitry can be predicted or analyzed

by James Foltz and Fuad Musa, Motorola Semiconductor Products Inc., Phoenix, Ariz.

Complementary metal -oxide -semiconductor logiccircuitry is being more widely used as the demand in-creases for digital systems that operate at low power lev-els and from low supply voltages. ctmos satisfies theserequirements with its extremely low dynamic power dis-sipation and its essentially zero quiescent power con-sumption. Moreover, silicon -gate cimos can operatefrom very low supply voltages-as little as 1 volt,thereby further reducing power requirements.

Complementary logic structures, however, can be-come quite complex, making the use of computer -aidedanalysis essential, since the basic cimos logic element,the inverter, requires two devices-an n -channel and ap -channel mos field-effect transistor. To use the com-puter, a practical model of the silicon -gate MOSFET isneeded that satisfies cimOS requirements.

The model must be suitable for both transient analy-sis and determining the effect of mos device pa-rameters, especially threshold voltage, on circuit per-formance. As threshold voltage becomes smaller, oper-ating speed can be increased, but possibly at the price ofhigher power consumption.

The MOSFET model

Because of its simplicity and accuracy, the low -fre-quency large -signal equivalent circuit of the MOSFET(Fig. 1) provides a good basis for developing the appro-priate equations for cimos computer analysis. ThroughSceptre, a general-purpose computer program, andMOSFET current and voltage relationships, this equiva-lent circuit can be used to predict cimos switchingspeed, power dissipation, and the effect of thresholdvoltage on transient response and power -speed product.

The MOSFET model is a four -terminal device consist-ing of drain -source current generator IDS and five ca-pacitors that represent the device's gate -source CGS,gate -drain COD, gate -substrate COB, drain -substrateCDB, and source -substrate CSB capacitances. For an re-channel MOSFET, current flows from the drain terminalto the source terminal; for a p -channel transistor, cur-rent flows from source to drain.

Model capacitors CDB and CSB represent junction ca-pacitances and can be evaluated readily by conven-tional methods. However, since CGS, COD, and CGB aremos gate -oxide capacitances, they are functions of pro-cessing parameters and device geometry, as well asMOSFET terminal voltages. Although the sum of these

latter capacitances is constant, their individual valuesvary with biasing conditions and also depend on the di-rection of current flow between drain and source termi-nals. Detailed descriptions of how to evaluate mos ca-pacitances are available.1,2,3,4

This model does not account for any source or drainseries resistances because the effect of these resistancescan be neglected, due to the extremely low current de-veloped by the MOSFET at silicon -gate cimos operatingvoltage levels. (Peak current is about 100 microamperes,while drain -source voltage approximately equals the1.5-v gate -source voltage).

Characterizing the model

In the linear region, the current generator, IDS, can bewritten as: 5,6,7

IDS = Bo[(VG - Vo - VD/2)VD -(VG - Vo - VS/2)Vs-(2/3)KAIVD 20F13/2-IVS 2ciF13/2)] ( I)

where all voltages are referenced to substrate potential:B. = Zp.C./LVo = OMs - Qss/Co + 24 F

1. MOSFET model. Low -frequency large -signal equivalent circuit ofMOSFET serves as model for complementary MOS logic. Equationfor current generator, 'Ds, represents model's current -voltage char-acteristic, which can be applied to C/MOS design or analysis. Cur-rent flows from drain to source for n -channel device.

147

n -CHANNEL (n11160 VT ", 0.5 V Vc, 1.8 V x -160

140 -140

120

100

<c

3 80O

60

40

20

X

VG = 1 6 V

VG = 1.4 V

VG = 1.2 V

VG = 1 v

X

0 0.5 1.0 1.5 2.0Vos (V)

-120

-100

-80

-60

- 40

-20

0

1 l I

-1.0 -1.5Vos (VI

Devicetype

Bo

(A/V2)Vo(V)

OPTIMIZED PARAMETERS

ND

(cm -3)X0

(microns)C1SS /CO

(V)L

(microns)VTIV)

n1 2.85 X 10-4 -0.57 4.3 X 1015 0.117 0.27 3.9 0.48

p1 -1.4 X 10 4 0.24 1.1 X 1015 0 115 0.30 5.2 -0.25

n2 8.9 X 10 4 -0.68 1.12 X 1016 0.122 0.24 20.0 1.20

p2 -3.49 X 10 4 0.14 4.72 X 1015 0.122 0.33 25.0 -1.0

2. Mathematical versus practical. Device parameters needed to compute model current IDs, are noted in table for small (nl and pl) andlarge (n2 and p2) transistors. Parameters are mathematically optimized to approximate the current -voltage characteristics of real devices. I -Vcurves for nl and p1 MOSFETs embody the comparison of predicted results (solid lines) with measured data (test points).

IN

VDD

VDUT

(a)

0

2.25 - 2.2501 00

2.0 - 2.0000 00

1.75 - 1.75o1 00

1.5 - I.500E 00

1.25 - 12501.0

1.0 - 1.000E 00

0.75 - 7.500E-02

0.5 - 5.0000-01

0.25 - 2.5000-02

0 - 0.0

-0.25 -0.0

MEASURED

(0.5 V/cm, 2 µs/cm)

2.0001 02 6.0000 02 1.0000 03 1.404E 03 1.0000 034.000E 02 0.0000 02 1.200E 03 1.0000 03 2.0002 03

I I I I I I I I I I I

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

TIME (µs)(b)

PREDICTED

148

Ko = (2Eoes6N01/2/C0VG is the gate voltage, VD the drain voltage, Vs thesource voltage, Z the channel width, L the channellength, it the inversion layer mobility, Co the gate -oxidecapacitance per unit area,. Eo the permittivity of freespace, Es the relative dielectric constant of silicon, NDthe substrate impurity concentration, Ords = he metasemiconductor work function difference, Qss the fixedpositive charge at the silicon/silicon-oxide interface, OFthe Fermi substrate potential, and e the electron charge.

In the saturation region, VDSAT replaces VD in Eq. 1and is defined by:5

VDSAT = Va - Vo 410/2[1 -(1 ± 4(Va- Vo + 24)/K02)1/211/2 (2)

(In Eq. 2, where a choice is indicated, the sign is + forn -channel and - for p -channel.) To simplify compu-tations, the channel conductance in the linear region,gds, can be regarded as a linear function of VG, providedthat Vs = 0 and VD) is much less than 241F:

dinsgds = = Bo(V - VT)

U V D V D = constantwhere threshold voltage VT is:

VT = Vo K0(2001/2When channel conductance gds is plotted against gate

voltage VG for an actual mos device, the value of vari-able Bo (slope) becomes smaller with increasing gatevoltages. This is due to reduced surface mobility and tothe series source resistance, which lowers the gate -source voltage below the applied gate voltage. For allsilicon -gate MOSFETs, variable Bo can be approximatedby a constant when VG is less than or equal to 2 v.

Modeling C/MOS logicA computer -aided technique can be developed to op-

timize the values of Qss, Vo, oxide thickness Xo, channellength L, and impurity concentration ND so that thecurrent -voltage relationships calculated with Eqs. 1 and2 closely approximate those measured for practical sili-con -gate cimos devices.

The table in Fig. 2 lists the most important optimizedparameters for two pairs of n -channel and p-channelMOSFETS. The upper two sets of values, n1 and p1, arefor small transistors, while the lower two, n2 and p2, arefor large transistors. Both the predicted (with themodel's equations) and the actual (from existing transis-tors) current -voltage characteristics of devices n1 and plalso appear in Fig. 2. The differences between the pre-dicted and the measured curves are small.

The basic element of the ctmos logic family is the in-verter, which is shown in Fig. 3a along with its transfercharacteristic. Figure 3b shows the inverter's predictedand measured switching performance. The printout re-flects the computed switching speed, based on the opti-mized parameters of transistors n1 and p 1. And the os-cilloscope trace displays the switching action of a circuit

3. C/MOS logic Inverter. Basic C/MOS logic element is inverter (a)comprising p -enhancement MOSFET (top) and n -enhancementMOSFET (bottom). Voltage transfer function shows transition from

logic 1 to logic 0. Computer plot (b) of output voltage versus timeprojects inverter switching performance using n1 and p1 param-eters. Scope display is for inverter built with n1 and pl MOSFETs.

4. Minimizing device count. Flip-flop (a) requires 20 MOSFETs, asshown in (b). But three transistors are redundant and can be re-moved-one between either 01 or 02, another between 04 or Q5,and the third between Qg or 07. Final flip-flop (c) uses 17 MOSFETs.

149

1.75 ---

1.5 ---

1.750+00

1.500+00

1

111

11.25 --- 1.250+00 1--

11

1 TRIGGER1

1.0 --- 1.000+00 1--

11

0.75 --- 7.500-0111--1

Q OUTPUT1

11

0.5 --- 5.000-01 1--

1

1

1

0.25 - 2.500-01 1--11

1

1

0 --- 0.000 1--1111

-0.25 --- -2.500-01 1--11

1

1--- -5.000-01 1--

1

11 1

-0.75 - -7.500-01 1

1

MEASURED

(0.5 V/cm, 10 ps/cm)

1

1.000+04 3.000+04 5.000+04 7.000+04 9.000+040.000 2.000+04 4.000+04 6.000+04 8.000+04 1.000+05

0 10 20 30 40 50 60 70

TIME (As)

PREDICTED

80 90 100

5a. Flip-flop Q output. Predicted switching performance is plotted by computer for O output of toggle flip-flop that is simulated with n2 andp2 parameters of Fig. 2. Oscilloscope trace displays same 0 output for actual flip-flop built with practical n2 and p2 MOSFETs.

built with actual nl and pl transistors. Each switchingwaveform is the voltage across load capacitor CL (2 pi-cofarads) when the inverter is operated from a 1.5-v dcsupply and is driven by a 1.5-v input having 100 -nanosecond rise and fall times.

Power -speed product

One of the most important performance parametersof any switching circuit is its power -speed product;power consumption and operating speed are directlyproportional to each other. Here, the c/mos inverterhas the advantage of dissipating power only during itstransition, when charging or discharging its load and in-ternal capacitances. However, I2R power may be dis-sipated if both MOSFETs conduct simultaneously duringtransition, when the supply voltage and the input signalamplitude exceed the sum of the n- and p -channelthreshold voltages. Dissipated power then becomes afunction of input rise and fall times and increases withslower signals. Therefore, the ctmos inverter's power -

speed product, which is defined as VDDIDD/frequency,may not necessarily be constant with frequency if theinput signal is sinusoidal or has varying rise and falltimes. The MOSFET model can be used to predict thepower -speed product by employing a function subrou-tine in conjunction with Sceptres to calculate the aver-age inverter current drain, IDD

For example, if an inverter's sum of threshold volt-ages is about half a 1.5-v supply, its power -speed prod-uct goes up by a factor of four when input rise and falltimes are increased from about 0.1 microsecond toaround 5 /is. The power -speed product for an inverterhaving a sum of threshold voltages that is greater thanthe supply does not change with slower inputs.

Sequential logic circuits

In addition to combinational logic, sequential ctmoslogic circuit performance can also be predicted with theMOSFET equivalent circuit. Sequential circuits can beconsidered as interconnected combinational logic

150

2.25- 2.250+00 1

1 1 1 1 1 1

1

1

1

2.0 - 2.000+0011 11 11

1.75 -- 1.750+00 1--1

1 11 11

1,5 - 1.500+00 1--1

1 frfr.1,11

1

1

1.25 --- 1.250+00 1--1

1

11

1.0 - 1.000+001

1 11 1

0.75 - 7.500-0111-- MEASURED 1

1

11 TRIGGER *It

1

0.5 5.000-01 .01 --11

1

1 .11

Q OUTPUT

0.25 - 2.500-01 I__1

., --I1

1 ... 1

1 (0.5 V/cm, 10 ** 1

0 - 0.000 1..*

ps/cm)******** ..,

1....1

1 1

1 1

1 1

1 1 1 1 1 1 1 1

1-0.25 - -2.500-01 1

0.000

0

1.000+04 3.000+04 5.000+04 7.000+04 9.000+042.000+04 4.000+04 6.000+04 8.000+04 1.000+05

10 20 30 40 50 60 70 80 90 100

TIME ( us)

PREDICTED

5b. Flip-flop a output. Computer predicts switching action of flip-flop a output by plotting output voltage versus time. Again, device para-meters of n2 and p2 MOSFETs are used to simulate flip-flop. Switching performance of practical flip-flop is shown by scope trace.

blocks, like gates and inverters, with appropriate feed-back. A toggle (type T) flip-flop, for example, can beimplemented with the blocks noted in Fig. 4a.

In this form, the flip-flop requires 20 transistors, as in-dicated in Fig. 4b. A closer inspection, however, revealsthat a few transistors serve the same functional purpose.

P -enhancement transistors Qi and Qz, for instance,have identical bias conditions; their gates and sourcesare common. One of these transistors can be eliminatedwhen the drains of the two have been tied together. Thisis possible, since their common drains will be bufferedfrom the logic output node by transistor Q3.

The same reasoning applies to transistors Q4 and Q5,since their drains are also common, once Qi and Q2 aretied together. Moreover, transistors Q6 and Q7 have anidentical biasing arrangement, allowing one of them tobe eliminated after connection of their drains, whichwill be buffered from the output by transistor Q8. In all,three devices are redundant and may be removed. Thefinal flip-flop, Fig. 4c, requires 17 transistors.

The MOSFET model can be employed to predict theswitching performance of the toggle flip-flop, as wasdone for the inverter. The parameters of MOSFET5 n2and p2 can be used for computation, and actual n2 andp2 transistors can be used to breadboard the flip-flop.

Both the predicted and measured Q and Q outputforms are noted in Fig. 5, when each output drives a 7-pF load. The longest part of the switching cycle, about20 is, is the fall time of the 0:5 output, Fig. 5b. 0REFERENCES1. C.T. Sah, "Characteristics of the Metal -Oxide -Semiconductor Transistor," IEEE Transac-tions on Electron Devices, ED -11, July, 1964, pp. 324-345.2. C.T. Sah, N.C. Pao, "The Effects of Fixed Bulk Charge onhe Characteristics of Metal -Oxide -Semiconductor Transistors," IEEE Transactions on Electron Devices, ED -13, April,1966, pp. 393-409.3. Paul Nygaard, "An investigation of Voltage -variable Gate -Oxide Capacitance," MotorolaInc., Internal Communications, 1971.4. William Lenin, "MOS voltage -variable Capacitance Study," Motorola Inc., Internal Com-munications, 1972.5. A.S. Grove, "Physics and Technology of Semiconductor Devices," Wiley, 1967.6. D. Frohman-Bentchkowsky, A.S. Grove, "Conductance of MOS transistors in Satura-tion," IEEE Transactions on Electron Devices, ED -16, January, 1969, pp. 108-113.7. Robert H. Crawford, "MOSFEr in Circuit Design,'' McGraw-Hill, 1967.8. Paul Nygaard, "Sceptre Subprogram Library," Motorola Inc., Internal Communications,1970.

151

Aedcap: the circuit designer'scomputer -assisted slide ruleThis powerful conversational software system solves circuit problemseasily; designs can be analyzed quickly for dc, ac, and transient analysis,and their sensitivity to component tolerances can also be determined

by Ronald A. Rohrer and Jorge E. Rodriguez, Sof Tech Inc., Waltham, Mass.

Although the virtues of computer -aided circuit de-sign are well known by now, most engineers still avoidusing the computer because they don't know how to in-terface with the machine. A year -old fully conversa-tional computer program called Aedcap, however, al-lows the designer to communicate with the computer inan instruction -reply format that is written in engineer-ing terms.

Available on a time-shared basis, Aedcap (Auto-mated Engineering Design Circuit Analysis Program)provides as much analytical power as batch -processedsoftware packages while making efficient use of com-puter time to hold down design costs. Circuits can betreated as prototypes being probed with an instrument.

Aedcap can perform linear and nonlinear dc analysis,small -signal ac analysis, and large -signal transient anal-ysis. All three analysis modes can be easily inter -coupled. Moreover, the roles of signals and parameterscan be interchanged so that a single computation canassess accurately the effects of every circuit parameterperturbation on a selected signal.

The program can simulate circuits composed of linearresistors, capacitors, and inductors; independent voltageand current sources; voltage -controlled current sources;junction diodes; bipolar junction transistors; and mosand junction field-effect transistors. Theoretically, thereis no limit to the size of the circuit Aedcap can accom-modate, but, from a practical point of view, circuit sizeis restricted by the amount of computer memory avail-able. Presently, hundreds of circuit nodes can beanalyzed in a single computer run.

Models are built-in

Diode and transistor models are predefined; the usermerely specifies the electrical parameters that character-ize the active device. If the user chooses to leave a para-meter value unspecified, the program inserts a defaultvalue, which usually simplifies the model.

Once characterized, a model can be stored so that itcan be called out by name when needed to describe acircuit. Models for physical devices are used to reducethe circuit being described to N nodes (not including

MODELS

MODELS

MODELS

MODELS

MODELS INITIALCONDITIONS USER AEDCAP

MAN-MACHINcINTERFACE

SMALL -SIGNALAC

ANALYSIS

LARGE SIGNALTRANSIENTANALYSIS

NONLINEARDC

ANALYSISINITIAL

CONDITIONSTEXT EDITOR

FREQUENCYRESPONSE

NOISEANALYSIS

QUIESCENTOPERATINGPOINT

STATICTRANSFERCHARACTERISTIC

MIP

TIMERESPONSE

-CASE

SUPERVISORYAND DEFINED

COMMANDS

SPARSE MATRIX MANIPULATOR

SENSITIVITY,STATISTICAL,AND WORST -CASEANALYSIS

ASENSITIVITY,STATISTICAL,AND WORST -CASEANALYSIS

V

SENSITIVITY,STATISTICAL,AND WORSTANALYSIS

DATASTRUCTUREGENERATOR

ADJOINT CONCEPT PRINTOR

PLOT

(al ( b )

FILE SYSTEM

MODELS

STANDARD ELEMENTS

NEW ELEMENTS

NETWORKS

FUNCTIONS

ANALYSISINTERFACE

ANALYSIS ,0 0- -0ROUTINES

OUTPUTPOST

PROCESSOR

1. Framework. Flowcharts map Aedcap's analysis (a) and control (b) structures The program can perform dc, ac, or transient analysis, aswell as sensitivity, statistical, or worst -case analysis. Sparse matrix (one having many zero -valued entries) conserves computer time; adjointnetwork technique permits reversing roles of signals and parameters. Aedcap's interactive framework eases interface between user andcomputer. Conversational language and built-in active device models keep program instructions simple.

152

the datum or ground node) and B branches. Eachbranch is defined by a relationship between the branchcurrent and the branch voltage. The unknown circuitvariables are the N node voltages.

Aedcap employs nodal analysis to solve circuit prob-lems. The program applies Kirchoff's current law ateach node to produce a set of N independent equationsin matrix form. A large circuit often has a nodal admit-tance matrix that is typically 75% to 95% sparse. (Spar-sity denotes the percentage of zero -value entries in thematrix). The sparse matrix approach saves computertime. Flow charts for Aedcap's analysis and controlstructures are presented in Fig. 1.

To perform dc analysis, Aedcap replaces capacitorsand inductors by open and short circuits, respectively,and then solves the circuit for fixed source values. A setof static transfer characteristics can be obtained by solv-ing for sequential values of a given source.

Of course, dc analysis is used to determine a circuit'squiescent operating point so that linearized model para-meters can be computed for small -signal ac analysis.Nonlinear elements are then replaced by linearized

equivalents, and the resulting linear circuit is solved atsequential frequency points.

Large -signal transient analysis is used to determinethe time -domain response of a circuit to various inputwaveforms, starting with the initial conditions foundwith a dc analysis.

Full sensitivity analysis capability

Aedcap allows the user to perform dc or ac sensitivityanalysis, finding the change in a circuit output para-meter caused by variations in one or more circuit ele-ments. Since dc or ac sensitivity analysis is an inherentpart of any dc or ac solution, its presentation does notrequire a new solution of the circuit. Worst -case analy-sis and statistical analysis are also available as part of adc or ac solution.

Worst -case analysis computes the output degradationthat will occur if all the element parameter tolerancesvary collectively in the most pessimistic possible man-ner. A design that passes this test may be used with theutmost assurance that it will function properly.

Statistical analysis with Aedcap predicts the percen-

Bipolar transistor modelAedcap offers a built-in bipolar junction transistor modelthat is an extension of the Ebers-Moll charge -controlmodel used by most programs. The model includes anemission coefficient in each exponential term that char-acterizes a junction. Additionally, three series parasiticresistances and an output resistance augment the dctransistor characterization, while nonlinear capacitorsmodel the base and depletion layer charge storage. Alinear collector -substrate capacitance is also added tocomplete the modeling of transistor charge -storage ef-fects.

The circuit shown is an npn transistor model. It is char-acterized by six equations-two defining junction cur-rents IBE and IBC, and the other four defining capaci-tances OBE', OBE2, QBC1, and QBC2:

IBE = IEB[eXP(C1VBERIBEkT) - 1]IBC = les[exp(qVite /nBekT) - 1]

ro

VI3E

f0QBEI = CjE0 dV/(1 - Vicl)BEY/2

--- aFTFIBE

VacQBE2

QBCI = CjC0I.

dV/(1 - V/Oscy/2

QBC2 = aRTRIBCIn all, 18 parameter values are needed. Default values areput in by Aedcap when parameters are not specified.

For a pnp transistor, polarity is reversed for voltagesVBE and Vgc, currents IBE and IBC, and dependent gener-ators aftlBc and aFIBE. Voltages VBE and VBC coincidewith terminal potential differences only when the voltagesacross resistors rB', re', and rE' are negligible.

ParameterSymbol

AedcapName

TRANSISTOR PARAMETERS

ParameterName

0

DefaultValue

Type Transistor type, npn or pnp

OF BF Forward common -emitter current gain 100

OR BR Reverse common -emitter current gain 1

re' RB Base ohmic resistance 0

rc' RC Collector ohmic resistance 0

rE' RE Emitter ohmic resistance 0

ccs CCS Collector -substrate capacitance 0

TF TF Forward transit time 0

TR TR Reverse transit time 0

C jE CI CJEO Zero -bias base -emitter capacitance 0

Cico CJCO Zero -bias base -collector capacitance 0

I Es I ES Base -emitter saturation current 1 X 10-14

I cs ICS Base -collector saturation current 2 X 10 14

rIBE NBE Base -emitter emission coefficient 1

nBc NBC Base -collector emission coefficient 1

(DBE PHIBE Base -emitter junction potential 1

(PBC PHIBC Base -collector junction potential 1

ro RO Output resistance .

153

LOGIN PROCEDURE

ATTACH AEDCAP TIME-SHARING FACILITY LOGOUT

{EDITDESIGNFILE

NAME

PRINTF LISTF

CKTMODELFNCTNFNCTNLCONTROL

NEW FILE FILE ALREADY

EXISTS

INPUT EDIT

AGAINBLANKBOTTOMCHANGEDELETEFINDGOTOINPUT QUIT

.4111

INSERT

LOCATENEXTPRINTREPLACETOP

UP

DOUBLE CARRIAGEVERIFY

RETURN FILE

ERASE COST

MANUAL

COM-

CONTINUE

BATCH

ANALYZE

REPEAT

QUIT

CKTNAME QUIT

SET UP DATASTRUCTURE FOR CKT

CONTINUE

QUIT

1

TO

{BY

TIMESOCT

DEC

SPECIFY OUTPUT LISTSAND DEVICE NAME

QUIT

OUTPUT S

FROM

TO

VS

PERFORMANCE OFANALYSIS PROGRAMSAND/OR PRINTING OR

PLOTTING OF RESULTS

UPON COMPLETION

OF PROGRAMS

CONTROLS

QUIT SHOW ACAN

OCAN

USEIRANSHOW

PARM VALUESWEEP parm

1 FROM value

TO value

PRINTPLOT

BY value

TIMES valueOCT integerDEC integer

PROBE

SENS

WORSTLWORSTH

SAVES- t

SAVES

1SPECIFY LIST OF VARIABLESTO BE SAVED BY ANALYSIS

QUITROUTINE

2. Road map. Using Aedcap does not require special skills. Road map charts basic chain of command and shows how they are related toeach other. The three primary command areas are COM-, controls, and input/edit. Instructions typed on terminal by user are underlined.

tage of circuits that will be out of tolerance in a produc-tion run. This analysis is a variation of sensitivity analy-sis that yields a simulated standard deviation of thedesired circuit output parameter. The standard devia-tion figure gives a tolerance or voltage deviation withinwhich roughly two-thirds of the circuits in a productionrun will fall. Before his design is firm and the produc-tion line set up, the designer can learn what his yield islikely to be.

In practice, Aedcap's statistical analysis has only lim-ited accuracy. But, taken in conjunction with other de-sign uncertainties, the predictions Aedcap makes can beuseful to engineers engaging in statistical design.

Instructions are conversational

Three types of commands are available to the Aedcapuser. The road map of Fig. 2 outlines the instructionsincluded in each major command area. Control com-mands, for instance, are the various analyses that maybe performed, while input/edit commands are the in-structions needed to describe or modify circuits. Thecentral command area, designated as COM-, provides ac-cess to the controls and input/edit sections, and alsocontains several auxiliary commands.

Sitting at his computer terminal, the user logs into thetime-sharing network and then gains access to Aedcap

by typing ATTACH AEDCAP. The system responds withthe word COM-, signifying that it is ready to accept anycommand listed in the COM- area on the road map.(User -supplied commands are underlined).

The designer then calls for a circuit already filed inthe system, or he describes a new circuit. He may do thisby typing DESIGN AMPLIFIER CKT, if "amplifier" is theformal name by which he wishes to file his circuit. Thesystem then searches for any circuit with this name. If itdoes not find one, the system notifies the user, who maythen proceed to describe his circuit.

After executing any edit commands given by the user,the system returns to the COM- area, from which theuser can exit with the command ANALYZE. ANALYZEprecedes requests for the various analysis routines listedunder controls. When the analysis is complete, the sys-tem returns to COM-. If he wishes, the user may now ter-minate the session and log out to study his results. Thecircuit he has just analyzed may be filed in the Aedcapsystem for future reference or for subsequent additionalanalysis.

Pointing out some limitations

Parameter determination and modeling are still twoof the most significant limitations to the effective appli-cation of circuit -simulation systems. Aedcap attempts to

154

minimize these problems with a large model library.Device models can be stored permanently and madeavailable for future designs and other engineering users.

Although Aedcap's built-in bipolar junction transis-tor model (see panel) is adequate for most circuit appli-cations, it does neglect a number of higher -order effectsthat may occasionally be important. For example, thecommon -emitter forward current gain, is not a con-stant, as assumed in the Ebers-Moll and Aedcap mod-els. However, a reasonable representation of the betavariation can be obtained by augmenting Aedcap'sbuilt-in model with other standard elements.

Other shortcomings of the modeling equations canoften be handled in a similar manner. Aedcap's mod-eling equations do not currently extend to microwavefrequencies, but microwave devices can be simulatedthrough suitable manipulations.

Another common problem is getting the series expan-sions for the solutions to converge. Aedcap minimizesthis problem, with the help of the designer. For ex-ample, a bistable circuit can be particularly trouble-some, since the computer does not know which of thetwo stable modes represents the desired solution. Thedesigner's knowledge of the circuit he is analyzing

(a)

12 V

5 0 el dc 12.1 0 e2 dc xfer ac 1.2 1 3 ql q2n35634 0 3 q2 q2n35635 2 rl 1k5 4 r2 1k3 0 j1 dc jvary

5 0 gl dc 12.1 0 e2 dc xfer act.2 1 3 ql q2n35634 0 3 q2 q2n35635 2 rl 1k5 4 r2 1k3 10 r3 1.2k10 0 e3 dc -12.

3. Designing with Aedcap. Differential transistor pair (a) must supply voltage gain of 50 ±10%. After approximating value of ideal current source that provides desired gain, real supply (E3) and series resistors (R3) can be substituted, as in (b). Tables are Aedcap circuitdescriptions. Once all circuit nodes are numbered, elements are described on a line by listing the higher -potential node first. Transistorterminal nodes must be ordered-collector, base, then emitter. Alsoa transistor must be identified as one of Aedcap's built-in models.

should suggest to him that this may occur. He can avoidthe problem by biasing the simulated circuit so as toeliminate the superfluous solution.

The bistable example illustrates a general property ofsimulation circuits. Practical circuits will always presentmore possibilities than could be envisioned by any setof program equations. The designer, therefore, musthave some idea of what he wants his circuit to do, andhow it is likely to perform before he can make intelli-gent use of a simulation system. He cannot expect thecomputer to describe all the possibilities inherent in aparticular design.

Using Aedcap is easy

A typical design session will illustrate how to workwith Aedcap. Figure 3a shows an every -day circuit-adifferential transistor pair containing transistors Qi andQ2, resistors R1 and R2, voltage sources E1 and E2, andideal current source J1. The circuit has five nodes, whichare numbered. (The ground node is always made 0 byAedcap convention; otherwise, any node numberingscheme will do.)

The Aedcap description for the differential pair alsoappears in Fig. 3a. It is a listing, by node connection, ofthe circuit elements. Only a few simple rules must befollowed to describe a circuit. Each line in the table de-scribes an element; the node that lies at the higher po-tential is listed first. Therefore, supply E1 has its nodeconnections written as 5 and then 0, since node 5 is at 12volts and node 0 is ground.

For transistors, the collector node is listed first, fol-lowed by the base and emitter nodes, respectively.Transistors, it should be noted, must be separately de-scribed as models so that the computer can refer tothem when they are used in a circuit. Failure to specifyall 18 parameter values of Aedcap's built-in transistormodel will cause default values to be used.

The differential pair of Fig. 3a is to be a preampliferin a larger circuit configuration. Its load resistance willbe 1 kilohm, and a single -ended voltage gain of50 ± 10% is desired. The power supplies are + 12 v and-12 v. (The negative supply is to be added later in placeof the ideal current source.) Transistor model param-eters are known and stored in the Aedcap file.

From circuit design experience, it is known that thegain of this circuit depends on the value of transistoremitter current, IE. The design procedure, then, consistsof establishing an ideal current source (JO to determinethe correct value of IE. After this value is found, theideal current source can be replaced by an emitter resis-tance and a negative supply.

A computer run

Once the circuit is described, the current for J1 can beestimated and tested. Since the frequency response ofthis preamp should be essentially flat, ac voltage gaincan be quickly checked by computing the voltages atnodes 2 and 4 for a signal frequency of 1 hertz (for sim-pler calculations). Knowing the voltage at either node 2or node 4 would be sufficient, but finding the potentialat both nodes will help confirm expected performance.

To test a 2 -milliampere value of J1, the user simplytypes a request for an ac analysis, specifying the 2-mA

155

AEDCAP CIRCUIT PREAMP

F2 GAIN(VM(4),VM(1))F2 0.00E+00

103 1.00E+13 3.44E+011.26E+03 3.44E+011.58E+03 3.44E+012.00E+03 3.44E+012.51E+03 3.44E+013.16E+03 3.44E+013.98E+03 3.44E+015.01E+03 3.44E+016.31E+03 3.44E+017.94E+03 3.44E+01

104 1.001.04 3.44E0111.26E+04 3.44E+111.58E+04 3.44E+012.00E.04 3.44E+012.51E+04 3.44E+013.16E+04 3.44E+013.98E+14 3.44E+015.01E+04 3.44E+016.31E+04 3.44E+117.94E+04 3.44E+011.00E+05 3.44E+011.26E+05 3.44E+011.58E+05 3.44E+012.00E+05 3.44E+012.51E+05 3.44E+013.16E+05 3.44E+013.98E+05 3.44E+015.011.05 3.44E+016.31E+05 3.44E+017.94E+05 3.43E+01

106 1.00E+06 3.43E+011.26E+06 3.41E+011.58E+36 3.40E+012.00E+06 3.37E+012.51E+06 3.34E+013.16E+06 3.28E+013.98E+06 3.21E+115.01E+06 3.12E+016.311+06 3.00E+017.94E+06 2.86E+01

10' -- 1.00E+07 2.70E+011.26E+07 2.53E+011.58E+07 2.35E+012.00E+07 2.16E+012.51E+07 1.96E+013.16E+07 1.76E+013.98E+07 1.55E+015.01E+07 1.34E+016.31E+07 1.12E+017.94E+07 9.03E+001.00E+08 6.80E+001.26E+08 4.57E+00

105

108 -

1.00E+01

0 10

2.00E+01 3.00E+01 4.00E+01

20 30 40

GAIN (dB)

4. Performance check. Computer plot of frequency response for differential pair in Fig. 3b shows that gain is about 35 dB out to 1 MHz.

estimate in place of NARY in the table of Fig. 3a. At thesame time, he requests a printout of the voltages atnodes 2 and 4. The computer will find that both volt-ages are approximately 7.3 v.

Since the estimate of 2 mA yields a voltage gain ofonly 7.3, the analysis is repeated for a current source of10 mA. This gives a satisfactory gain of about 55.3.

Ideal current source Ji can now be replaced by a realresistor and a real supply. By calling in'the Aedcap edi-tor, source J1 can be removed, and a 1.2-Idlohm resistor(R3) and a -12-v supply (E3) can be inserted. The prac-tical differential pair is illustrated in Fig. 3b, along withits Aedcap description.

Again, circuit gain is checked by computing the volt-ages at nodes 2 and 4 for a 1 -Hz input. If the gain is notwithin the desired specification of 50 ±-10%, the value ofresistor R3 must be changed. A computer run showsthat the gain is within tolerance, indicating that the cir-cuit is essentially designed.

At this point, there are a number of possible analysesthat can be performed. For example, the circuit's dctransfer characteristics can be determined by plottingthe output voltages at nodes 2 and 4 as functions of dcinput E2. Or the common -mode gain can be computedby first calling in the Aedcap editor to connect Qi's base

to Q2's base and then looking at the output voltagetransfer curve at node 4.

The circuit's pulse transient response can also bechecked out by using standard Aedcap pulse functionsor any user -desired pulse function. And the sensitivityof the circuit can be tested to see how well the design islikely to fare under production conditions.

Since the circuit's frequency response was initially as-sumed to be flat, a sensible computation is checking thegain of the differential pair over a broad range of fre-quencies, taking advantage of Aedcap's ability to do fullfrequency sweeps. The computer printout of Fig. 4shows the results of sweeping the circuit from 1

kilohertz to 100 megahertz and obtaining a plot of gain(in decibels) versus frequency. The graph verifies thatthe frequency response will be essentially flat to 1 MHz.

Program availability

Aedcap requires a large in-house computer, or it canbe used interactively through the time-sharing facilityof National css in Stamford, Conn. The computer ter-minals that the program can now accommodate includethe IBM model 2741, Teletype models 33 and 35, andthe Tektronix types T4002, T4002A, and T4010 graphiccomputer terminals.

156

Easy -to -useHypi programmakes possibletransition fromnonlinear to lineartransistor modelActing as an interface between linearand nonlinear analysis programs,a new computer program called Hypiconverts parameters of nonlinearcharge -control transistor modelto those of linear hybrid -pi model

by John R. Greenhaum, General Electric Co., Syracuse, N.Y.

PRINT TITLE, IDENTIFY TRANSISTOR

READ DATA

WHAT ARE VALUES OF VCB, JN

FOR I = 1 TO M NEXT I 1

YESIS INPUT VALUE OF JNGREATER THAN

STORE STATEMENTDATA FOR NEXT LOWER

STORED VALUE OF JN VALUE OF JNAS J5, B5, D5, U5, E5

NO

IS INPUT VALUE OF JNLESS THAN

YESSTORE STATEMENT

DATA FOR NEXT LARGER

STORED VALUE OF JN VALUE OF JNAS J6, B6, D6, U6, E6

NO

STORE TABLE VALUES GO SUB TO GET

AS JI, 61, D1, Ul, El LINEAR APPROXAS J1, Bl, DI, Ul, El

EXIT

CALCULATE VBE

CALCULATE SMALL SIGNAL PARAMETERS

PRINT RESULTS

NEW RUNYES

NO

END

Most nonlinear computer programs can analyze cir-cuits only in the time domain, while linear computerprograms perform analysis in the frequency domain.However, practically all available transistor perform-ance data is in nonlinear form, making it inappropriatefor the linear programs. Consequently, an intermediateprogram is needed to convert nonlinear transistor mod-els to linear models, so that the linear programs can beused for frequency analysis.

A new short program, which is called Hypi (pro-nounced high -pie), enables the user to describe his cir-cuit with a nonlinear transistor model, but perform hisanalysis with a linear computer program, like Cornap(Cornell network analysis program), ECAP (electroniccircuit analysis program), ACnet (ac network analysis

157

1. Hypi computer program. Flowchart outlines how Hypi converts nonlinear charge -control transistor model to linear hybrid -pi transistormodel. The user simply supplies data for transistor collector current and base -collector voltage. Previously stored table contains data forcharge -control model parameter values. (Linear interpolation is used to bridge table values.) After reading user input data, Hypi solves equa-tions relating charge -control parameters to hybrid -pi parameters. Sample program develops model for type 2N1711 transistor.

NYPII.

100 PRINT"PRC.ChAM TO DERIVE SMALL SIGNAL HYSPID PI FROM LANGE SIGNAL"11D PRINT DATA"12V PRINT "ISO kiR bl.b8,k2.1.C.N3.hb.Al.A1,A2.42,11.1C.12.118,13.1C9140 hEr vi.PNII.P2.PNIL,TI:TNETA W.T2.TWETA 1,41.01.02.k2150 1.01 21.VCE, V2:VAC. 113.18i, JI.JN, J02.11. J3.JC, JAI:a14O CI.OJE,C2.CDC,E:3.ETC-C4.CTE,C5.CE,C6.CC,81.GME,R4.ROE170 PIM pi.hCC114 Ncm 6(11:01.t D(1).31, 11(1),ICN. r(1):7C1ISO PnIAT :DOLL 011711.240 PNINT"210 DAIA 23.,7.081,27.. -12,i1.1 -10,1.62E-13,.420-1322.4 dtAJ N1,142.03.01,A2,12,13232 JA1A240 NEKJ VI.P2,71,T2,61.02050 LeT A5.1.E7262 DIG C(50>,b(516),2(5b).11(50),V(92)276 LOT M.22dwd VAIST294 00A DATA TABLE 14 CE4uTONIC ILENEASIMG CULFENTS360 JAL% .8225E-3.e...56,5.E-103.0-6310 J974 .OBIE-3,2.,.56,5.2-10,3.E-6322 JAI0333 .;ATA .010 -3,28.,.56,5.E -10,3.E-6340 JA14 .02E -3,25,06,58-10,3E-6350 DATA .63E-3,28,.58 5E-12 3E-636.1 2ATA370 JAIN .072-3,30,.67,50-12,3E-6380 dA7ASSJ 321A .0E -3,55..72,5E -10.3E-6402 2A14 .34-3,05.03.50-10,3E-6410 Gbf.422 ;22a .56-3,70.,.67,5.,-10,3.1-6430 JATA 1.0-3,96.,.12.5.0-18,3.E-6440 BAIA 2o -3,105,57,50-16,3E-6450 GAT. SE -3,117,53,5E -14,3E-6

470 JAI.: 7i -3,140,47,5E -10,3e-6.80 JATA 10E -3,145,012,5E -10,3E-6496 DATA 200-3,156,38,52-10,3E..6530 DATA 300 -3,160,36,5E -10,3E-6510 GAIN 500-3,160,33,50-10,33-6520 Fyn 1:1 TO II531 Niid C(1).11(1),D(I)d(1).V(1)542 NEXT 1

556 OWINT YOUN WALKS FON VC6,J11 MC;560 Rif VC6.I/2 lb VOLTS J8.21 IN AMPS570 INPUT V2,JI580 PRINT590F011 1.1 10 MCOO IF .11.4(1) THEN 6711618 IF J1dO(1) THIN 730620 LET 01:0(1)630 LET D10(1)640 LET UMW65d LET 01:6(1)660 SO TO 1000670 LET 25:C(1)60C LET 95.6(1)690 LET 55.2(1>700 LOT U5.11(1)711 LET 05.8(I)7211 60 TO 960730 LET .16.C(1)746 LET 86.0(I)750 LET 06.2(1)760 LET 116.11(1)778 LET 06.0(1)700 LAT YI415790 LET Y2.06

NYPIP. CONTINUED

00d GO SUS 1270810 LOT 81:13622 LET y1.05830 LET 12:26840 GO SUS 127065d LAT 01:13660 LE7 11:85872 LET 72.U6891/ GO SUS 1272908 LET U1.13910 LET X1.05926 LEI 72:06938 GO SUS 12709144 LAT E1.Y3356 AU TO 1006560 NEXT I

1600 LET V3.LOGIJI/127/TI1610 LEI J2.13.0(EXP(TE4V2)-1.11026 LET J3aJb/21-J11030 LEI J4.J1/01-J21642 LOT CI.Tibute(J1.12)1.56 LOT C0.70..E1b(22.13)1060 LAT C3.42/(P2,,2)'11121070 LET C4.A1/(rl-W3)'1111000 LEI CS:CI...CA11.90 LET C6:C22C31109 LAT 61.11.211:18 LET 114.81/011128 PRINT1139 PRINT1110 PRINT -FOR VC15."1V21.00."1.111159 PRINT"1100 PRINT'RBeiR1.'RCr'1112.'8E.'SR3,'ffE.'IN41176 PRINT 'ROC.-11,5,"CC:":06,"CEd"gC5,'GME.'1011160 PRINT'VOE.'1113IMO PRINT1220 PRINT" IF YOU WANT A NEW RUN TYPE I. 008 NO1230 LET 1:21240 INPUT X1250 IF X.1 TNEN5501253 STOP1266 REM SUROUTINE FOR LINEAR APPROXIMATION1270 LET A . (Y2 -Y1)/(.16-0)1280 LET 0.Y1-04.151290 LET 13 .A4J14.01390 RETURN1319 END

Nil RUN TYPE 9'

program), or any one of several other programs.Developed at General Electric, Hypi can be run on a

time-shared basis and is written in Basic language. Itconverts the parameters of the nonlinear large -signalBeaufoy-Sparkes charge -control transistor model to theparameters of the familiar linear small -signal hybrid -pitransistor model. The panel, "From charge -control tohybrid -pi," shows the two models and the conversionequations.

There are several ways to solve these equations. Forinstance, they can be solved directly, if not very conve-niently, with the nonlinear program, Sceptre (system forcircuit evaluation and prediction of transient radiationeffects) [Electronics, Aug. 16, 1971, p. 721. Alternatively,Hypi can be used alone, after the values for two of the

parameters for the charge -control model, current den-sity .41 and base -collector voltage Vgc, have been com-puted manually. Or, again, the nonlinear program, Cir-cus (circuit simulator), can be used to find the JN andVBc values, and then Hypi used to finish the conversion.

Examining Hypi

Hypi's flowchart (Fig. 1) is a generalized descriptionof how the hybrid -pi model data is obtained. The pro-gram identifies the transistor type being examined,reads the data describing the charge -control transistorcharacteristics, and then asks the user for the operatingconditions specific to his circuit's performance.

Hypi represents the charge -control model parametersof forward gain $N., inverse gain PI, normal time con-

158

stant TN, and inverse time constant Ti, as points on thecurves normally used to describe these functions. (Thisdata can be obtained from published transistor liter-ature.) The Hypi program automatically provides linearinterpolation between adjacent parameter values whennecessary. Therefore, a proper result is obtained whenan evaluation is requested for a value of current densityJN that does not exactly correspond with one of thelisted entries.

User input data is examined to determine whether itagrees with the charge -control model data previouslystored or whether an interpolation is required. Thecharge -control model equations are then solved, and theresults inserted in the conversion equations for the hy-brid -pi model. The outcomes of these computations arelabelled with the hybrid -pi parameter descriptions.

A sample Hypi program is also included in Fig. 1.Statements 100 through 200 identify the program, thetransistor that is being evaluated (in this case, type2N1711), and the variables in the program. Statements210 through 540 cause the data describing the transistorto be read into the program. By changing this data, dif-ferent transistors can be modeled.

The charge -control model parameters are called out

in statements 210 and 230. Statement 210 provides datafor base bulk resistance RBB, collector bulk resistanceRcc, emitter bulk resistance REE, base -emitter capaci-tance A1, base -collector capacitance A2, saturation emit-ter current 'Es, and saturation collector current Ics.Statement 230 enters data for intrinsic base -emitter po-tential 01, intrinsic base -collector potential 02, and con-stants 01, 02, NI, and N2.

Statement 270 indicates the number (m) of differentcollector current values to be stored in the program.Statements 300 through 510 list these various values ofcurrent JNm, in addition to the values for forward gainfiNin, inverse gain thm, normal time constant TNm, andinverse time constant Tim. This creates a data table, withthe current values given in increasing order.

User input data for current JN and voltage VCB is re-quested by program statements 550, 560, and 570. Withthis input information, Hypi searches its data table todetermine if the input current value agrees with a storedcurrent value. If no agreement is found, a linear inter-polation is performed between the two stored currentvalues between which the input current value falls.

This procedure is described in statements 590through 960. The lower data point values for RN, fil, TN,

R1

+47 V ---41,---"VVV-L

25

50

125

250

022N1711

0

2N1711

032N1490

RL

LOAD

R2L

ALL INDUCTORS IL) AND RESISTORS R1 AND R2 ARE DUE TO LEAD LENGTHS

NONLINEAR TRANSISTOR OPERATING CONDITIONS

VE3c

-5.54

-12.40

-16.70

-18.20

03

Jr, (A) VEic (V) JN (A) VBc (V) JN (A)

0.0132 -13.90 0.0027 6.16 0.996

0.00536 -14.00 0.00626 -13.00 0.519

0.00228 -14.10 0.00848 -17.30 0.220

0.00151 -14.10 0.00924 -18.80 0.119

+24 Vdc

2. Sample analysis. Voltage regulator can be examined for potential instabilities. Nonlinear Circus program is used first to determine collec-tor currents and base -collector voltages of all three transistors for four different load conditions. Table shows results of Circus analysis of thetransistors for load resistances of 25 to 250 ohms, which cause load current for the 24 -volt regulator to vary from 1 to 10 amperes.

159

From charge -control to hybrid -piWhen a transistor operates under varying conditions, anonlinear model is needed to describe device behaviorproperly. One such model, a simplified version of theBeaufoy-Sparkes charge -control transistor model, isshown along with a tabulation of its parameters and sometypical values.

The equations to determine the current generators forthe model are:

11 = (1 /fiN + 1)JN - Ji12 = -JN + (1 /p, + 1)JI

where:JN = lEs[exp(ONVBE) - 1]J1 = Ics[exP(B1VBc) - 1]

The depletion and diffusion capacitances for the modelcan be expressed as:

CTE = Al /(01 VBE)N1CTC = A2/(c52 - VB14N2

CDE = O\TN(JN IES)

CDC = ICS)

The accuracy of nonlinear transistor modeling and theconvenience of linear problem -solving can be combinedby converting the nonlinear charge -control model param-eters to the parameters of the linear hybrid -pi modelshown. Four equations must be solved:

gmE = ONJNRBE = PN/ONJN = flN/gmECc = A2 / (02 - VCC)N2 OiTI(J1 + ICS)CE = A1/(4)1 - VCE)Nl 8NTN(JN 1ES)

Generally, base -collector resistance RBc is assumed tobe so large that it can be neglected.

NONLINEAR CHARGE -CONTROL MODEL

REE

CDE

CTE CTC

II 11

Rc

CDCIiiRCC

R BE

RBB

B

LINEAR HYBRID -PI MODELCc

grnE VBE

Para-meter

Definition Samplevalue

R BB

RCC

REE

Rc

RE

CTC

CTE

CDC

CDE

ICS

I ES

JN

ON

01

A2

01

02

ON

0,

N1

N2

TN

Base bulk resistance

Collector bulk resistance

Emitter bulk resistance

Collector reverse -bias leakage resistance

Emitter reverse -bias leakage resistance

Collector depletion capacitance

Emitter depletion capacitance

Collector diffusion capacitance

Emitter diffusion capacitance

Saturation collector current when VBE = 0

Saturation emitter current when VBC = 0

Forward current generator

Inverted current generator

Normal beta with Vetc = 0, VBE = 0

Inverse beta

Base -emitter capacitance

Base -collector capacitance

Intrinsic base -emitter junction potential

Intrinsic base -collector junction potential

q/mkT, 1 < m < 2, T = 25°C

q/mkT, 1 < m < 2, T = 25°C

Constant, 0.33 (graded junction)to 0.5 (step junction)

Same as Ni, usually N2 < Ni

Normal storage time constant

Inverted storage time constant

55 S2

5S2

1 mil

10 M11

30 MS1,

0.485 pA

3.5 fA

72

0.62

3.7 pF

3.3 pF

1.1 V

1.1 V

40.1

29.4

0.34

0.10

120 ps

35 ns

and TI are stored as J5, B5, D5, U5, and E5, respectively.Upper data point values for these same parameters arestored respectively as J6, B6, D6, U6, and E6.

The values for the hybrid -pi model parameters arecalculated with the equations listed in statements 1000through 1100. Printout instructions for these computedvalues are given in statements 1140 through 1180. State-ments 1220 through 1250 allow additional circuit oper-

ating conditions to be examined and, therefore, otherparameter values to be generated at the user's option. Ifno further modeling is required, the program stops.

Using Hypi

A design example will illustrate how the Hypi pro-gram can simplify circuit analysis. The voltage regulatorof Fig. 2 is to be examined to identify any potential cir-

160

la)

259 RES RUN 1_112.909

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3.470963E 918.6900000. 822.0776040-01

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( b )

25V REG

_17.94 112469

RUN I.

ELAPSED _TIME

TRANSFER FUNCTION_ CRLTICAL FREQUENCIES - Hi

OUTPUT VARIABLE - I RL1SOURCE VARIABLE - 14

GAIN CONSTANT IS 5.9664833D-03

P Q_LE P_O_S LT IONS

REAL PART IMAGINARY PART ORDER-2.74806490 08 O. 1

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FUNCTIONIN FRFOUENCY IN IMPEDAU_E_

TRANSFERSCALED RY 1.000D 08

POLYNOMIALS - RADIANSAND 1.0000 03

DENOMINATOR DEGREEIN S.

NUMERATORCOEFFECIENTS

DEGREEIN SCOEFFECIENTS

1,000_001101(.1(110_04D_SLQ_ 1_Z_ .C110110ANDOCIfICIQ011. CIO 101.86421780292370D 01 11 1.82507986367618D 01 92.6744959R2R19170 11 10 1.-952.21164.522AD.86D_11 8

5.344559084114750 01 9 4.441617336461980 01 7

3.104.44159315380D 01 1-19_3A 6163 216.Ak ID 011.169884435379860 01 7 3.59471232049698D 00 53414516494686251110 4,6247967M/9830-01 4

6.148752089695850-01 5 -5.280801379067990-03 3

8.910538394723560-02 4 -1.88926194533646D-03 2

6.59065593013516D-03 3 -1.279931354482660-04 1

A, LA17.321.8137/61D- 06_ 2 2.63368.06764232.6a-075.683390326587980-09

113/1411111 7_12:11 2 0

3. Frequency response. Nonlinear transistor model data computed by Circus is entered into Hypi so that hybrid -pi model and, therefore,linear program can be used to analyze regulator. Subsequent frequency analysis by linear Cornap program provides plot (a) of regulatorcharacteristics for 1 -ampere load, as well as tabulation (b) of pole -zero locations. Potential instability is outlined in color.

cuit instabilities that could cause unwanted oscillation.First, the collector currents and base -collector voltage

drops of all the transistors are found with the nonlinearCircus program for four different load conditions. Inthis case, load current ranges from approximately 1 am-pere to 10 milliamperes, as load resistance is variedfrom 25 to 250 ohms. The table in Fig. 2 gives the re-sults of this analysis.

The current and voltage values are then entered intothe Hypi program; a separate run is needed for eachtransistor. The hybrid -pi model data supplied by Hypican then be entered into any one of several linear analy-sis programs. For this example, the widely used linearprogram, Cornap, is chosen for convenience. With acommand of only a single instruction, Cornap can pro-vide transfer functions, pole -zero locations, and plots.

Figure 3a is a Cornap frequency -domain plot of the

regulator's gain, phase and delay characteristics whenload current is about 1 A. Amplitude values and peakamplitude locations vary with transistor collector cur-rent. The peak (outlined in color) in the vicinity of 14kilohertz for all characteristics indicates the presence ofa potentially critical pole.

Cornap's tabulated output format (Fig. 3b) for theregulator's frequency -domain transfer function andpole -zero locations lists the potentially troublesomepole (outlined in color) as having its real part located at1,021 hertz and its imaginary part at 13,869 Hz. Ananalysis of this pole location reveals that the pole'sphase angle is approximately 86°, which implies ex-treme sensitivity to ringing and probable oscillation ifparameter values change even slightly. 1:1

The author wishes to admovAedge J.E. Hooper's help in developing the Hypi program

162

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Use the attached order card or write to:

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