circuit representations. boolean functions boolean algebra deals with binary variables and logic...

CIRCUIT REPRESENTATIONS

Boolean Functions

Boolean algebra deals with binary variables and logic operations.

Function results in binary 0 or 1

x00001111

y00110011

z01010101

F00001011 F = x(y+z’)

xy

zz’

y+z’ F = x(y+z’)

Boolean Functions

x00001111

y00110011

z01010101

xy00000011

x

y

z

G = xy +yz

yz

xy

We will learn how to transition between equation, symbols, and truth table.

yz00010001

G00010011

Representation Conversion

Need to transition between boolean expression, truth table, and circuit (symbols).

TruthTable

Circuit BooleanExpression

Truth Table to Expression

Converting a truth table to an expression Each row with output of 1 becomes a product term Sum product terms together.

x00001111

y00110011

z01010101

G00010011

xyz + xyz’ + x’yz

Any Boolean Expression can be represented in sum of products form!

Equivalent Representations of Circuits All three formats are equivalent Number of 1’s in truth table output column equals AND terms

for Sum-of-Products (SOP)

x y z

x00001111

y00110011

z01010101

G00010011

G = xyz + xyz’ + x’yz

G

x x x

x xx

xx x

Reducing Boolean Expressions Is this the smallest possible implementation

of this expression? No! Use Boolean Algebra rules to reduce

complexity while preserving functionality. Step 1: Use Theorem 1 (a + a = a)

So xyz + xyz’ + x’yz = xyz + xyz + xyz’ + x’yz

Step 2: Use distributive rule a(b + c) = ab + ac So xyz + xyz + xyz’ + x’yz = xy(z + z’) + yz(x + x’)

Step 3: Use Postulate 3 (a + a’ = 1) So xy(z + z’) + yz(x + x’) = xy · 1 + yz · 1

Step 4: Use Postulate 2 (a · 1 = a) So xy · 1 + yz · 1 = xy + yz = xyz + xyz’ + x’yz


Minterms and Maxterms

Each variable in a Boolean expression is a literal Boolean variables can appear in normal (x) or complement form

(x’) Each AND combination of terms is a minterm Each OR combination of terms is a maxterm

For example: Minterms

x y z Minterm0 0 0 x’y’z’ m0

0 0 1 x’y’z m1

…1 0 0 xy’z’ m4

…1 1 1 xyz m7

For example: Maxterms

x y z Maxterm0 0 0 x+y+z M0

0 0 1 x+y+z’ M1

…1 0 0 x’+y+z M4

…1 1 1 x’+y’+z’ M7

Representing Functions with Minterms

Minterm number same as row position in truth table (starting from top from 0)

Shorthand way to represent functions

x00001111

y00110011

z01010101

G00010011


G = m7 + m6 + m3 = Σ(3, 6, 7)

Complementing Functions

Minterm number same as row position in truth table (starting from top from 0)

Shorthand way to represent functions

x00001111

y00110011

z01010101

G00010011


G’ = (xyz + xyz’ + x’yz)’ =

G’11101100

Can we find a simpler representation?

Complementing Functions Step 1: assign temporary names

b + c -> z

(a + z)’ = G’

Step 2: Use DeMorgans’ Law (a + z)’ = a’ · z’

Step 3: Resubstitute (b+c) for z a’ · z’ = a’ · (b + c)’

Step 4: Use DeMorgans’ Law a’ · (b + c)’ = a’ · (b’ · c’)

Step 5: Associative rule a’ · (b’ · c’) = a’ · b’ · c’

G’ = (a + b + c)’

G = a + b + c

G’ = a’ · b’ · c’ = a’b’c’

G = a + b + c

Complementation Example

Find complement of F = x’z + yz F’ = (x’z + yz)’

DeMorgan’s F’ = (x’z)’ (yz)’

DeMorgan’s F’ = (x’’+z’)(y’+z’)

Reduction -> eliminate double negation on x F’ = (x+z’)(y’+z’)

This format is called product of sums

Conversion Between Canonical Forms

Easy to convert between minterm and maxterm representations

For maxterm representation, select rows with 0’sx

00001111

y00110011

z01010101

G00010011


G = m7 + m6 + m3 = Σ(3, 6, 7)

G = M0M1M2M4M5 = Π(0,1,2,4,5)

G = (x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)(x’+y+z’)

Representation of Circuits

All logic expressions can be represented in 2-level format Circuits can be reduced to minimal 2-level representation Sum of products representation most common in industry.

VERILOG HDL

16

Why do we need HDLs ?

HDL can describe both circuit structure and behavior Schematics describe only circuit structure C language describes only behaviors

Provide high level abstraction to speed up design

High portability and readability Enable rapid prototyping Support different hardware styles

Verilog Overview

A Hardware Description Language (HDL) for describing & testing logic circuits. text based way to talk about designs easier to simulate before silicon translate into silicon directly

Logic synthesis - automatic generation of lower-level logic circuit designs from high-level specifications

Why Verilog?

Verilog: Similar to C, with some changes to account for time

Widely used in industry VHDL is alternative; similar and can pick it up

easily. Verilog simpler to learn!

We employ only a simple subset of Verilog.

Verilog Overview

Verilog is only a hardware description language Although it looks like a general purpose language

Describing circuits is not equivalent to programming

Need to figure out the circuit first and then how to use Verilog to describe it.

Verilog Overview

Verilog description composed of modules:

module Name ( port list ) ;Declarations and Statements;

Endmodule

Modules can have instantiations of other modules, or use primitives supplied by language

Verilog Overview

Verilog has 2 basic modes

1. Structural composition: describes the structure of the hardware components, including how ports of modules are connected together module contents are builtin gates (and, or, xor, not, nand, nor, xnor, buf) or other modules previously declared

2. Behavoral: describes what should be done in a module module contents are C-like assignment

statements, loops

Example: Structural XORmodule xor(X, Y, Z);

input X, Y;output Z;

wire notX, notY, XnotY, YnotX;

not (notX, X), (notY, Y);

and (YnotX, notX, Y), (XnotY, X, notY);

or (Z, YnotX, XnotY);endmodule

XY

XY

Z

XnotY

YnotXnotX

notY

Example: Structural XORmodule xor(X, Y, Z);

input X, Y;output Z;

wire notX, notY, XnotY, YnotX;

not (notX, X), (notY, Y);

and (YnotX, notX, Y), (XnotY, X, notY);

or (Z, YnotX, XnotY);endmodule

XY

XY

Z

XnotY

YnotXnotX

notY

which “ports” input, output

Default is 1 bit wide data

“ports” connect components

Note: order of gates doesn’t matter, since structure determines relationship

Example: Behavoral XOR in Verilogmodule xorB(X, Y, Z);

input X, Y;output Z;reg Z;always @ (X or Y)

Z = X ^ Y;endmodule Unusual parts of above Verilog

“always @ (X or Y)” => whenever X or Y changes, do the following statement

“reg” is only type of behavioral data that can be changed in assignment, so must redeclare Z

Default is single bit data types: X, Y, Z

Verilog: replication, hierarchy

Often in hardware need many copies of an item, connected together in a regular way Need way to name each copy Need way to specify how many copies

Specify a module with 4 XORs using existing module example

Example: Replicated XOR in Verilogmodule 4xor(A, B, C);

input[3:0] A, B;output[3:0] C;

xorB My4XOR[3:0] (.X(A), .Y(B), .Z(C) );

endmodule

Note 1: can associate ports explicitly by name,

(.X (A), .Y(B), .Z(C) )

or implicitly by order (as in C)

(A, B, C)

Note 2: must give a name tonew instance of xors (My4XOR) C[0]

A[0]B[0]

A[0]B[0]

C[1]A[1]B[1]

A[1]B[1]

C[2]A[2]B[2]

A[2]B[2]

C[3]A[3]B[3]

A[3]B[3]

Verilog big idea: Time

Difference from normal prog. lang. is that time is part of the language part of what trying to describe is when things occur,

or how long things will take In both structural and behavoral Verilog,

determine time with #n : event will take place in n time units structural: not #2(notX, X) says notX does not

change until time advances 2 ns behavoral: Z = #2 A ^ B; says Z does not change

until time advances 2 ns Default unit is nanoseconds; can change

Example:

“Initial” means do this code once

Note: Verilog uses begin … end vs. { … } as in C

#2 stream = 1 means wait 2 ns before changing stream to 1

Output called a “waveform”

module test(stream);output stream;reg stream;initial

beginstream = 0;#2 stream = 1;#5 stream = 0;#3 stream = 1;#4 stream = 0;

endendmodule

stream0

1 time

2 7 10 14

Testing in Verilog

Need separate code to test the module (just like C/Java)

Since hardware is hard to build, major emphasis on testing in HDL

Testing modules called “test benches” in Verilog; like a bench in a lab dedicated to testing

Can use time to say how things change

Testing Verilog

Create a test module that instantiates xor:module testxor;

reg x, y, expected; wire z;

xor myxor(.x(x), .y(y), .z(z));

/* add testing code */

endmodule Syntax: declare registers, instantiate module.

Testing continued

Now we write code to try different inputs by assigning to registers:…

initial

begin

x=0; y=0; expected=0;

#10 y=1; expected=1;

#10 x=1; y=0;

#10 y=1; expected=0;

end

Testing continued

Pound sign syntax (#10) indicates code should wait simulated time (10 nanoseconds in this case).

Values of registers can be changed with assignment statements.

So far we have the xor module and a testxor module that iterates over all the inputs. How do we see if it is correct?

Testing continued

Use $monitor to watch some signals and see every time they change:…initial$monitor(“x=%b, y=%b, z=%b, exp=%b, time=%d”,x, y, z, expected, $time);

Our code now iterates over all inputs and for each one: prints out the inputs, the gate output, and the expected output.

$time is system function gives current time

Output

x=0, y=0, z=0, exp=0, time=0

x=0, y=1, z=1, exp=1, time=10

x=1, y=0, z=1, exp=1, time=20

x=1, y=1, z=0, exp=0, time=30 Expected value matches actual value, so

Verilog works

Example 1// Test bench for 2-input multiplexor.

// Tests all input combinations.

module testmux2;

reg [2:0] c;

wire f;

reg expected;

mux2 myMux (.select(c[2]), .in0(c[0]), .in1(c[1]), .out(f));

initial

begin

c = 3'b000; expected=1'b0; ...

•Verilog constants syntax N’Bxxx where N is size of constant in bits B is base: b for binary, h for hex, o for octal xxx are the digits of the constant

Example 2… begin

c = 3'b000; expected=1'b0;

repeat(7)

begin

#10 c = c + 3'b001;

if (c[2]) expected=c[1];

else expected=c[0];

end

#10 $finish;

end

•Verilog if statement, for and while loops like C•repeat (n) loops for n times (restricted for)• forever is an infinite loop

•Can select a bit of variable (c[0] )• $finish ends simulation

KARNAUGH MAPS

Overview

K-maps: an alternate approach to representing Boolean functions

K-map representation can be used to minimize Boolean functions

Easy conversion from truth table to K-map to minimized SOP representation.

Simple rules (steps) used to perform minimization Leads to minimized SOP representation.

Much faster and more more efficient than previous minimization techniques with Boolean algebra.

x y F

0 0 1

0 1 1

1 0 0

1 1 0

Karnaugh maps

0 1y

x

0

1

1

0 0

1

0 1y

x

0

1

x’y’

xy’ xy

x’y

x

y

F = Σ(m0,m1) = x’y + x’y’

x y F

0 0 1

0 1 1

1 0 0

1 1 0

Karnaugh maps Alternate way of representing Boolean function

All rows of truth table represented with a square Each square represents a minterm

Easy to convert between truth table, K-map, and SOP Unoptimized form: number of 1’s in K-map equals

number of minterms (products) in SOP Optimized form: reduced number of minterms

0 1y

x

0

1

1

0 0

1

0 1y

x

0

1

x’y’

xy’ xy

x’y

x

yF = Σ(m0,m1) = x’y + x’y’

Karnaugh Maps

A Karnaugh map is a graphical tool for assisting in the general simplification procedure.

Two variable maps.

0A

1 01

B 0 101

F=AB +A’B 0A

1 11

B 0 101

°Three variable maps.

0A

1 11

0001

01

BC

01 1

11110

F=AB’C’ +AB C +ABC +ABC + A’B’C + A’BC’

F=AB +AB +AB

A B C F0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 11 0 1 11 1 0 11 1 1 1

+

Rules for K-Maps We can reduce functions by circling 1’s in the K-

map Each circle represents minterm reduction Following circling, we can deduce minimized and-

or form.

Rules to consider

1.Every cell containing a 1 must be included at least once.

2.The largest possible “power of 2 rectangle” must be enclosed.

3.The 1’s must be enclosed in the smallest possible number of rectangles.

Karnaugh Maps

A Karnaugh map is a graphical tool for assisting in the general simplification procedure.

Two variable maps.

0A

1 01

B 0 101

F=AB +A’B 0A

1 11

B 0 101 F=A+B

°Three variable maps.

F=A+B C +BC 0

A

1 11

0001

01

BC

01 1

11110

F=AB +AB +AB

F=AB’C’ +AB C +ABC +ABC + A’B’C + A’BC’

Karnaugh maps

Numbering scheme based on Gray–code e.g., 00, 01, 11, 10 Only a single bit changes in code for adjacent map cells This is necessary to observe the variable transitions

00 01AB

C

0

1

11 10

C

B

A

F(A,B,C) = m(0,4,5,7)

G(A,B,C) = 0 0

0 0

1 1

1 1C

B

A

1 0

0 0

0 1

1 1C

B

A

A

= AC + B’C’

More Karnaugh Map Examples

Examples

g = b'

0 101

ab

cab

0001111001

0 101

ab

cab

0001111001

0 10 1

f = a

0 0 1 00 1 1 1

cout = ab + bc + ac

1 10 0

0 0 1 10 0 1 1

f = a

1. Circle the largest groups possible.2. Group dimensions must be a power of 2. 3. Remember what circling means!

Application of Karnaugh Maps: The One-bit Adder

Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

S = A’B’Cin + A’BCin’ + A’BCin + ABCin

Cout = A’BCin + A B’Cin + ABCin’ + ABCin

= A’BCin + ABCin + AB’Cin + ABCin + ABCin’ + ABCin

= BCin + ACin + AB

= (A’ + A)BCin + (B’ + B)ACin + (Cin’ + Cin)AB= 1·BCin + 1· ACin + 1· AB

How to use a KarnaughMap instead of the

Algebraic simplification?


Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

Karnaugh Map for Cout

Now we have to cover all the 1s in theKarnaugh Map using the largestrectangles and as few rectanglesas we can.

A

B

Cin

0

0

0

1 1 1

01

A

B

Cin


Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

0

0 01

1 1 1



Cout = ACin

A

B

Cin


Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

0

0 01

1 1 1



Cout = Acin + AB

A

B

Cin


Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

0

0 01

1 1 1



Cout = ACin + AB + BCin

A

B

Cin


Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

1

1 10

0 1 0

Karnaugh Map for S

S = A’BCin’

A

B

Cin


Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

1

1 10

0 1 0

Karnaugh Map for S

S = A’BCin’ + A’B’Cin

A

B

Cin


Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

1

1 10

0 1 0

Karnaugh Map for S

S = A’BCin’ + A’B’Cin + ABCin

A

B

Cin


Adder

Cin

Cout

SB

AA B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

1

1 10

0 1 0

Karnaugh Map for S

S = A’BCin’ + A’B’Cin + ABCin + AB’Cin’

No Possible Reduction!

Can you draw the circuit diagrams?

Karnaugh Maps for Four Input Functions

Represent functions of 4 inputs with 16 minterms Use same rules developed for 3-input functions Note bracketed sections shown in example.

C + B’D’

Karnaugh map: 4-variable example

F(A,B,C,D) = m(0,2,3,5,6,7,8,10,11,14,15)F =

D

A

B

A

B

CD

0000

1111

1000

01111 0

0 1

0 1

0 0

1 1

1 1

1 1

1 1C

+ A’BD

A' B' D + A' C + B' C D

B C' D' + A C' + A B D'

LT =

EQ =

GT =

K-map for LT K-map for GT

Design examples

0 0

1 0

0 0

0 0D

A

1 1

1 1

0 1

0 0

B

C

K-map for EQ

1 0

0 1

0 0

0 0D

A

0 0

0 0

1 0

0 1

B

C

0 1

0 0

1 1

1 1D

A

0 0

0 0

0 0

1 0

B

C

Can you draw the truth table for these examples?

A'B'C'D' + A'BC'D + ABCD + AB'CD’

A B C D

EQ

Physical Implementation

°Step 1: Truth table

°Step 2: K-map

°Step 3: Minimized sum-of-products

°Step 4: Physical implementation with gates

K-map for EQ

1 0

0 1

0 0

0 0D

A

0 0

0 0

1 0

0 1

B

C

Karnaugh Maps

Four variable maps.

F=BC +CD + AC+ AD

0AB

1 10

0001

00

01

CD

00 1

11110

F=ABC +ACD +ABC +AB CD +ABC +AB C

11 0

111

1011 1

1

°Need to make sure all 1’s are covered

°Try to minimize total product terms.

°Design could be implemented using NANDs and NORs

Karnaugh maps: Don’t cares

In some cases, outputs are undefined We “don’t care” if the logic produces a 0 or a 1 This knowledge can be used to simplify functions.

0 0

1 1

X 0

X 1D

A

1 1

0 X

0 0

0 0

B

C

CDAB

00

01

11

10

00 01 11 10

- Treat X’s like either 1’s or 0’s- Very useful- OK to leave some X’s uncovered

+ C’D

Karnaugh maps: Don’t cares

f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13) without don't cares

f =

0 0

1 1

X 0

X 1D

A

1 1

0 X

0 0

0 0

B

C

A’D

CDAB

00

01

11

10

00 01 11 10

C f0 00 11 01 10 00 11 X100110011

D0101010101010101

10100XX00

A0000000011111111

+

B0000111100001111

+

Don’t Care Conditions In some situations, we don’t care about the value of a function

for certain combinations of the variables. these combinations may be impossible in certain contexts or the value of the function may not matter in when the combinations

occur In such situations we say the function is incompletely specified

and there are multiple (completely specified) logic functions that can be used in the design. so we can select a function that gives the simplest circuit

When constructing the terms in the simplification procedure, we can choose to either cover or not cover the don’t care conditions.

Map Simplification with Don’t Cares

F=ACD+B+AC0

AB

x x1

0001

00

01

CD

0x 1

01110

1x 0

111

1011 1

x

0AB

x x1

0001

00

01

CD

0x 1

01110

1x 0

111

1011 1

xF=ABCD+ABC+BC+AC

°Alternative covering.

Karnaugh maps: don’t cares (cont’d)

f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13) f = A'D + B'C'D without don't cares f = with don't cares

don't cares can be treated as1s or 0s

depending on which is more advantageous

0 0

1 1

X 0

X 1D

A

1 1

0 X

0 0

0 0

B

C

A'D

by using don't care as a "1"a 2-cube can be formed rather than a 1-cube to coverthis node

+ C'D

Definition of terms for two-level simplification

Implicant Single product term of the ON-set (terms that create a logic

1) Prime implicant

Implicant that can't be combined with another to form an implicant with fewer literals.

0 X

1 1

1 0

1 0D

A

1 0

0 0

1 1

1 1

B

C

5 prime implicants:BD, ABC', ACD, A'BC, A'C'D

Examples to illustrate terms

0 0

1 1

1 0

1 0D

A

0 1

0 1

1 1

0 0

B

C

6 prime implicants:A'B'D, BC', AC, A'C'D, AB, B'CD

minimum cover: AC + BC' + A'B'D

Prime Implicants

Any single 1 or group of 1s in the Karnaugh map of afunction F is an implicant of F.A product term is called a prime implicant of F if itcannot be combined with another term to eliminate avariable.

B

C

A

1

1

1

1 1

1 1

1

D

Example:

If a function F is represented bythis Karnaugh Map. Which of thefollowing terms are implicants ofF, and which ones are primeimplicants of F?

(a) AC’D’(b) BD(c) A’B’C’D’(d) AC’(e) B’C’D’

Implicants:(a),(c),(d),(e)

Prime Implicants:(d),(e)

Definition of terms for two-level simplification

Essential prime implicant Prime implicant is essential if it alone covers a minterm in

the K-map, the minterm does not belong to other prime implicats

Remember that all squares marked with 1 must be covered

2023.04.21

Example

Consider function f(a,b,c,d) whose K-map is shown at right.

a’b’ is not a prime implicant because it is contained in b’.

acd is not a prime implicant because it is contained in ad.

b’, ad, and a’cd’ are prime implicants.

111111

111111

111111

1111

b’

cd abad

a’cd’

a’b’

acd

0 X

1 1

1 0

1 0D

A

1 0

0 0

1 1

1 1

B

C

5 prime implicants:BD, ABC', ACD, A'BC, A'C'D

Examples to illustrate terms

0 0

1 1

1 0

1 0D

A

0 1

0 1

1 1

0 0

B

C

6 prime implicants:A'B'D, BC', AC, A'C'D, AB, B'CD

minimum cover: AC + BC' + A'B'D

essential

minimum cover: 4 essential implicants

essential

Essential Prime ImplicantsA product term is an essential prime implicant if there is a minterm that is not covered by other prime implicant.

- The minimal sum-of-products form of F must includeall the essential prime implicants of F.

2023.04.21 PJF - 72

Another Example

Consider f2(a,b,c,d), whose K-map is shown below.

The only essential PI is b’d.

11

11 11 11

11 11

11 11 11

cdab

Objective

Grow implicants into prime implicants (minimize literals per term)

Cover the K-map with as few prime implicants as possible(minimize number of product terms)

2023.04.21

Systematic Procedure for Simplifying Boolean Functions

1. Generate all PIs of the function.

2. Include all essential PIs.

3. For remaining minterms not included in the essential PIs, select a set of other PIs to cover them, with minimal overlap in the set.

4. The resulting simplified function is the logical OR of the product terms selected above.

2023.04.21

Example

f(a,b,c,d) = ∑m(0,1,2,3,4,5,7,14,15).

Five grouped terms, not all needed.

3 shaded cells covered by only one term

3 EPIs, since each shaded cell is covered by a different term.

F(a,b,c,d) = a’b’ + a’c’ + a’d + abc

1111

111111

11111111ab

cd

2023.04.21

Product of sums simplification

NAND AND XOR IMPLEMENTATIONS

NAND-NAND Networks

Mapping from AND/OR to NAND/NAND

ab

cd

a) b)

c) d)

Implementations of Two-level Logic

Sum-of-products AND gates to form product terms

(minterms) OR gate to form sum

Product-of-sums OR gates to form sum terms

(maxterms) AND gates to form product

Two-level Logic using NAND Gates

Replace minterm AND gates with NAND gates Place compensating inversion at inputs of OR gate

Two-level Logic using NAND Gates (cont’d)

OR gate with inverted inputs is a NAND gate de Morgan's:A' + B' = (A • B)'

Two-level NAND-NAND network Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed

Conversion Between Forms Convert from networks of ANDs and ORs to

networks of NANDs and NORs Introduce appropriate inversions ("bubbles")

Each introduced "bubble" must be matched by a corresponding "bubble" Conservation of inversions Do not alter logic function

Example: AND/OR to NAND/NAND

A

B

C

D

Z

A

B

C

D

Z

NAND

NAND

NAND

Z = [ (A • B)' • (C • D)' ]'

= [ (A' + B') • (C' + D') ]'

= [ (A' + B')' + (C' + D')' ]

= (A • B) + (C • D)

Conversion Between Forms (cont’d)

Example: verify equivalence of two forms

A

B

C

D

Z

A

B

C

D

Z

NAND

NAND

NAND

Conversion to NAND Gates Start with SOP (Sum of Products)

circle 1s in K-maps Find network of OR and AND gates

ABC

DE

FG

X

Multi-level Logic x = A D F + A E F + B D F + B E F + C D F + C E F + G

Reduced sum-of-products form – already simplified 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!) 25 wires (19 literals plus 6 internal wires)

x = (A + B + C) (D + E) F + G Factored form – not written as two-level S-o-P 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate 10 wires (7 literals plus 3 internal wires)

Level 1 Level 2 Level 3 Level 4

originalAND-OR network

A

CD

B

BC’

F

introduction andconservation of

bubblesA

CD

B

BC’

F

redrawn in termsof conventional

NAND gates A

CD

B’

BC’

F

Conversion of Multi-level Logic to NAND Gates

F = A (B + C D) + B C'

A

XBC

D

F(a)

Original circuit

A

XBC

D

F(b)

Add double bubbles at inputs

D’

A

X’

BC

F(c)

Distribute bubblessome mismatches

D’

AX

BC

FX’

(d)

Insert inverters to fix mismatches

Conversion Between Forms

Example

Exclusive-OR and Exclusive-NOR CircuitsExclusive-OR (XOR) produces a HIGH output whenever the two inputs are at opposite levels.

Exclusive-NOR (XNOR) :

Exclusive-NOR (XNOR) produces a HIGH output whenever the two inputs are at the same level.

Exclusive-NOR Circuits

XNOR gate may be used to simplify circuit implementation.

Exclusive-NOR Circuits

XOR Function XOR function can also be implemented with AND/OR gates (also

NANDs).

XOR Function Even function – even number of inputs are 1. Odd function – odd number of inputs are 1.

FIGURE 4-25 XOR gates used to implement the parity generator and the parity checker for an even-parity system.

Parity Generation and Checking

FIVE-VARIABLE K-MAPS

95

Five-variable K-maps – f(V,W,X,Y,Z)

V= 0 V= 1

Y

m0 m1 m3 m2

m4 m5 m7 m6

m12 m13 m15 m14X

Wm8 m9 m11 m10

Z

Y

m16 m17 m19 m8

m20 m21 m23 m22

m28 m29 m31 m30X

Wm24 m25 m27 m26

Z

96

Simplify f(V,W,X,Y,Z)=Σm(0,1,4,5,6,11,12,14,16,20,22,28,30,31)

V= 0 V= 1

1 1

1 1 1

1

1 1

1

1 1

1 11

f = XZ’ Σm(4,6,12,14,20,22,28,30) + V’W’Y’ Σm(0,1,4,5) + W’Y’Z’ Σm(0,4,16,20) + VWXY Σm(30,31) + V’WX’YZ m11

Example 1

Example 2

D E

A B C

1

0 0 0 0 0 1 0 1 1 0 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0

0 1

1 1

1 0

1

1

1

1

B

D

1 0 0 1 0 1 1 1 1 1 1 01 6 2 0 2 8 2 4

1 7 2 1 2 9 2 5

1 9 2 3 3 1 2 7

1 8 2 2 3 0 2 6

C

E

1

B

(a ) (b )

1

1

1

1

1

1

C

A

CIRCUIT ANALYSIS

Overview

Important concept – analyze digital circuits Given a circuit

Create a truth table Create a minimized circuit

Approaches Boolean expression approach Truth table approach

The Problem

°How can we convert from a circuit drawing to an equation or truth table?

°Two approaches

°Create intermediate equations

°Create intermediate truth tables

ABC

A

B

C’

Out

Label Gate Outputs

1. Label all gate outputs that are a function of input variables.

2. Label gates that are a function of input variables and previously labeled gates.

3. Repeat process until all outputs are labelled.

ABC

A

B

C’

Out

R

S T

Approach 1: Create Intermediate Equations

Step 1: Create an equation for each gate output based on its input.

• R = ABC

• S = A + B

• T = C’S

• Out = R + T

ABC

A

B

C’

Out

R

S T

Approach 1: Substitute in subexpressions

Step 2: Form a relationship based on input variables (A, B, C)

• R = ABC

• S = A + B

• T = C’S = C’(A + B)

• Out = R+T = ABC + C’(A+B)

ABC

A

B

C’

Out

R

S T

Approach 1: Substitute in subexpressions

Step 3: Expand equation to SOP final result

• Out = ABC + C’(A+B) = ABC + AC’ + BC’

A

C’

Out

B

C’

ABC

Approach 2: Truth Table

Step 1: Determine outputs for functions of input variables. A

00001111

B00110011

C01010101

R00000001

S00111111

ABC

A

B

C’

Out

R

S T

Approach 2: Truth Table

Step 2: Determine outputs for functions of intermediate variables.

A00001111

B00110011

C01010101

T = S * C’

R00000001

S00111111

T00101010

C’10101010A

BC

A

B

C’

Out

R

S T

Approach 2: Truth Table Step 3: Determine outputs for function.

A00001111

B00110011

C01010101

R00000001

S00111111

T00101010

Out 0 0 1 0 1 0 1 1

R + T = Out

ABC

A

B

C’

Out

R

S T

TIMING ANALYSIS

Overview

Circuits do not respond instantaneously to input changes

Predictable delay in transferring inputs to outputs Propagation delay

Even after inputs change, output signal of circuit maintains original output for short time Contamination delay

Combinational Logic Timing: Inverter

° Combinational logic is made from electronic circuits

• An input change takes time to propagate to the output

° The output remains unchanged for a time period equal to the contamination delay, tcd

° The new output value is guaranteed to valid after a time period equal to the propagation delay, tpd

A Y

A

Y

tpd

tcd

Combinational Logic Timing: XNOR Gate

A

B C

A

B

C

tpd

tcd

° The output is guaranteed to be stable with old value until the contamination delay

• Unknown values shown in waveforms as Xs

° The output is guaranteed to be stable with the new value after the propagation delay

Combinational Logic Timing: complex circuits

° Propagation delays are additive • Locate the longest combination of tpd

° Contamination delays may not be additive• Locate the shortest path of tcd

° Find propagation and contamination delay of new, combined circuit

A

B

C A

BC

Circuit X

Circuit X

Tpd = 5nsTcd = 1ns

Tpd = 2nsTcd = 1ns

Tpd = 3nsTcd = 1ns

COMBINATIONAL DESIGN PROCEDURE

Design Procedure (Mano) Design a circuit from a specification.

1. Determine number of required inputs and outputs.

2. Derive truth table

3. Obtain simplified Boolean functions

4. Draw logic diagram and verify correctness A

00001111

B00110011

C01010101

R00000001

S01111111

S = A + B + CR = ABC

BCD to Seven Segment Display Used to display binary coded decimal (BCD)

numbers using seven illuminated segments. BCD uses 0’s and 1’s to represent decimal

digits 0 - 9. Need four bits to represent required 10 digits.

Binary coded decimal (BCD) represents each decimal digit with four bits

a

b

c

g

e

d

f

10019

00018

11107

01002

10001

00000

BCD to seven segment display

0 a,b,c,d,e,f1 b,c2 a,b,d,e,g3 a,b,c,d,g4 b,c,f,g5 a,c,d,f,g6 a,c,d,e,f,g7 a,b,c8 a,b,c,d,e,f,g9 a,b,c,d,f,g

a

b

c

g

e

d

f

List the segments that should be illuminated for each digit.


.0111110019

.1111100018

.0011111107

.

.1101101002

.0011010001

.1111100000

.edcbazyxwDec

Derive the truth table for the circuit. Each output column in one circuit.

Inputs Outputs


1 0

10

1 1

1 1

11

yz

wx

10

11

01

00

10110100

For segment “a” :

Note: Have only filled in ten squares, corresponding to the ten numerical digits we wish to represent.

Find minimal sum-of-products representation for each output

Don’t care conditions (BCD display) ...

1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100


Put in “X” (don’t care), and interpret as either 1 or 0 as desired ….

Fill in don’t cares for undefined outputs. Note that these combinations of inputs should

never happen. Leads to a reduced implementation



yFa1 1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100

Circle biggest group of 1’s and Don’t Cares. Leads to a reduced implementation

Don’t care conditions (BCD display)


wFa2 1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100

Circle biggest group of 1’s and Don’t Cares. Leads to a reduced implementation



zxFa3

1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100

xzFa4

1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100

Circle biggest group of 1’s and Don’t Cares. All 1’s should be covered by at least one

implicant



xzzxwyF 1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100

Put all the terms together Generate the circuit


.0111110019

.1111100018

.0011111107

.

.1101101002

.0011010001

.1111100000

.edcbazyxwDec

Derive the truth table for the circuit. Each output column in one circuit.

Inputs Outputs


1 1

01

1 1

1 0

11

yz

wx

10

11

01

00

10110100

For segment “b” :

See if you complete this example.

Find minimal sum-of-products representation for each output

BINARY ADDERS/ SUBSTRUCTORS

Overview Addition and subtraction of binary data is fundamental

Need to determine hardware implementation Represent inputs and outputs

Inputs: single bit values, carry in Outputs: Sum, Carry

Hardware features Create a single-bit adder and chain together

Same hardware can be used for addition and subtraction with minor changes

Dealing with overflow What happens if numbers are too big?

Half Adder

C A B S 0 0 0 1 A 0 B 0

S 0

C 1

0 0 0 00 1 1 01 0 1 01 1 0 1

Dec Binary

1 1+1 +1 2 10

Add two binary numbers

• A0 , B0 -> single bit inputs

• S0 -> single bit sum

• C1 -> carry out

Multiple-bit Addition

A3 A2 A1 A0

0 1 0 1A 0 1 1 1B3 B2 B1 B0

B

0 1 0 10 1 1 1

A

B

0

1

0

1

1

1

1

Ai

+Bi

Ci

Si

Ci+1

Consider single-bit adder for each bit position.

Each bit position creates a sum and carry

Full Adder

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Ci Ai Bi Si Ci+1

1 1

1 1

Ci

AiBi

00 01 11 10

0

1

Si

Full adder includes carry in Ci

Notice interesting pattern in Karnaugh map.

Full Adder

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Ci Ai Bi Si Ci+1 Si = C’i · A’i · Bi+

+ C’i · Ai · B’i+

+ Ci · A’i · B’i+ + Ci · Ai · Bi

Full adder includes carry in Ci

Alternative to XOR implementation

Full Adder

Si = C’i · A’i · Bi

+ C’i · Ai · B’i

+ Ci · A’i · B’i

+ Ci · Ai · Bi

Si = C’i · (A’i · Bi + Ai · B’i)

+ Ci · (A’i · B’i + Ai · Bi)

Si = C’i · (Ai Bi)

+ Ci · (Ai Bi)’

Si = Ci (Ai Bi)

Reduce and/or representations into XORs

Full Adder

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Ci Ai Bi Si Ci+1

1

1 11

Ci

AiBi

00 01 11 10

0

1

Ci+1

Now consider implementation of carry outTwo outputs per full adder bit (Ci+1, Si)

Note: 3 inputs

Full Adder

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Ci Ai Bi Si Ci+1 Ci

AiBi

00 01 11 10

0

1

1

1 11

Ci+1

Ci+1 = Ai · Bi

+ Ci · Bi

+ Ci · Ai

Now consider implementation of carry outMinimize circuit for carry out - Ci+1

Full Adder

Ci+1 = Ai · Bi

+ Ci A’i · Bi

+ Ci · Ai · !Bi

Ci+1 = Ai · Bi

+ Ci · (A’i · Bi + Ai · Bi’)

Ci+1 = Ai · Bi + Ci · (Ai Bi)

Recall:Si = Ci (Ai Bi)


Full Adder

A

B

S

C

C i+1

i

i

i

i

Si = Ci (Ai Bi)

Half-adder Half-adder


Full adder made of several half adders

Full Adder

half-adder

half-adderA

B

i

i

C i

C i+1

S i

S

C

C

A full adder can be made fromtwo half adders (plus an OR gate).

Hardware repetition simplifies hardware design

Full Adder

Full Adder

A B

C C

S

i i

i+1 i

i

Block Diagram

Putting it all together

• Single-bit full adder

• Common piece of computer hardware

4-Bit Adder

Full Adder

A B

0 C

S

0 0

1

0

Full Adder

A B

C

S

1 1

2

1

Full Adder

A B

C

S

2 2

3

2

Full Adder

A B

C S

3 3

4 3

C 1 1 1 0A 0 1 0 1B 0 1 1 1S 1 1 0 0

Chain single-bit adders together.What does this do to delay?

Negative Numbers – 2’s Complement.

110 = 0116 = 00000001-110 = FF16 = 11111111

12810 = 8016 = 0010000000-12810 = 8016 = 1110000000

Subtracting a number is the same as:

1. Perform 2’s complement

2. Perform additionIf we can augment adder with 2’s complement hardware?

4-bit Subtractor: E = 1

Full Adder

A B

C

0 0

1

0

Full Adder

A B

C

1 1

2

1

Full Adder

A B

C

2 2

3

2

Full Adder

A B

C SD

3 3

4 3 SD SD SD

E

+1

Add A to B’ (one’s complement) plus 1

That is, add A to two’s complement of BD = A - B

Adder- Subtractor Circuit

+1

Add A to B’ (one’s complement) plus 1

That is, add A to two’s complement of BD = A - B

Overflow in two’s complement addition

Definition: When two values of the same signs are added: Result won’t fit in the number of bits provided Result has the opposite sign.

Overflow?

CN-1

BN-1

AN-1

Assumes an N-bit adder, with bit N-1 the MSB

10 1101 1010-------- 0111

11 1110 1101-------- 1011

01 0011 0110-------- 1001

00 0010 0011-------- 0101

00 0010 1100-------- 1110

11 1110 0100-------- 0010

Addition cases and overflow

OFL OFL

235

3 6-7

-2-3-5

-3-6 7

2-4-2

-2 4 2

Summary

Addition and subtraction are fundamental to computer systems

Key – create a single bit adder/subtractor Chain the single-bit hardware together to create bigger

designs The approach is call ripple-carry addition

Can be slow for large designs Overflow is an important issue for computers

Processors often have hardware to detect overflow Next time: encoders/decoder.

MAGNITUDE COMPARATORS AND MULTIPLEXERS

Overview

Discussion of two digital building blocks Magnitude comparators

Compare two multi-bit binary numbers Create a single bit comparator Use repetitive pattern

Multiplexers Select one out of several bits Some inputs used for selection Also can be used to implement logic

Magnitude Comparator

The comparison of two numbers outputs: A>B, A=B, A<B

Design Approaches the truth table

22n entries - too cumbersome for large n use inherent regularity of the problem

reduce design efforts reduce human errors

MagnitudeCompare

A[3..0]

B[3..0]A = B

A < B

A > B


A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

D01

D23

How can we find A > B?

How many rows would a truth table have?

28 = 256


A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

D01

D23

If A = 1001 and B = 0111is A > B?Why?

Because A3 > B3i.e. A3 B3’ = 1

Therefore, one term in thelogic equation for A > B isA3 B3’

Find A > B

Magnitude ComparatorIf A = 1010 and B = 1001is A > B?Why?

Because A3 = B3 and A2 = B2 and A1 > B1i.e. C3 = 1 and C2 = 1 and A1 B1’ = 1

Therefore, the next term in thelogic equation for A > B isC3 C2 A1 B1’

A > B = A3 B3’ + C3 A2 B2’ + …..

Magnitude Comparison

Algorithm -> logic A = A3A2A1A0 ; B = B3B2B1B0

A=B if A3=B3, A2=B2, A1=B1and A1=B1

Test each bit: equality: xi= AiBi+Ai'Bi'

(A=B) = x3x2x1x0

More difficult to test less than/greater than (A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'

(A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0

Start comparisons from high-order bits Implementation

xi = (AiBi'+Ai'Bi)’

Magnitude Comparison

Hardware chips


Real-world application

• Thermostat controller

Multiplexers

Select an input value with one or more select bits

Use for transmitting data Allows for conditional transfer of data Sometimes called a mux

4– to– 1- Line Multiplexer

Quadruple 2–to–1-Line Multiplexer

Notice enable bitNotice select bit4 bit inputs

Multiplexer as combinational modules Connect input variables to select inputs of multiplexer

(n-1 for n variables) Set data inputs to multiplexer equal to values of function

for corresponding assignment of select variables Using a variable at data inputs reduces the size of the

multiplexer

Implementing a Four- Input Function with a Multiplexer

Typical multiplexer uses

Summary

Magnitude comparators allow for data comparison Can be built using and-or gates

Greater/less than requires more hardware than equality

Multiplexers are fundamental digital components Can be used for logic Useful for datapaths Scalable

ENCODERS AND DECODERS

Overview

Binary decoders Converts an n-bit code to a single active output Can be developed using AND/OR gates Can be used to implement logic circuits.

Binary encoders Converts one of 2n inputs to an n-bit output Useful for compressing data Can be developed using AND/OR gates

Both encoders and decoders are extensively used in digital systems

Binary Decoder

Black box with n input lines and 2n output lines Only one output is a 1 for any given input

BinaryDecoder

ninputs 2n outputs

2-to-4 Binary Decoder2-to-4 Binary Decoder

From truth table, circuit for 2x4 decoder is:

Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY)

X Y F0 F1 F2 F3

0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

F0 = X'Y'

F1 = X'Y

F2 = XY'

F3 = XY

X Y

Truth Table:

2-to-4Decoder

X

Y

F0

F1

F2

F3

3-to-8 Binary Decoder3-to-8 Binary Decoder

x y z F0 F1 F2 F3 F4 F5 F6 F7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

F1 = x'y'z

x zy

F0 = x'y'z'

F2 = x'yz'F3 = x'yz

F5 = xy'z

F4 = xy'z'

F6 = xyz'

F7 = xyz

Truth Table:

3-to-8Decoder

X

Y

F0

F1

F2

F3

F4

F5

F6

F7

Z

Implementing Functions Using Implementing Functions Using DecodersDecoders

Any n-variable logic function can be implemented using a single n-to-2n decoder to generate the minterms OR gate forms the sum. The output lines of the decoder corresponding to

the minterms of the function are used as inputs to the or gate.

Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder with m OR gates.

Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

Example: Full adderS(x, y, z) = (1,2,4,7)

C(x, y, z) = (3,5,6,7)

3-to-8Decode

rS2

S1

S0

x

y

z

01234567

S

C

x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Implementing Functions Using Implementing Functions Using DecodersDecoders

Standard MSI Binary Decoders ExampleStandard MSI Binary Decoders Example74138 (3-to-8 decoder)

(a) Logic circuit. (b) Package pin configuration. (c) Function table.

Building a Binary Decoder with NAND Gates

Start with a 2-bit decoder Add an enable signal (E) Note: use of NANDs

only one 0 active! if E = 0

Use two 3 to 8 decoders to make 4 to 16 decoder Enable can also be active high In this example, only one decoder can be

active at a time. x, y, z effectively select output line for w

Three-state gates A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts) If the select input (E) is 0, the three-state gate has no

output

Opposite true here,No output if E is 1

Three-state gates A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts) If the select input is low, the three-state gate has no output

Three-state gates

Encoders If the a decoder's output code has fewer bits

than the input code, the device is usually called an encoder.

e.g. 2n-to-n

The simplest encoder is a 2n-to-n binary encoder One of 2n inputs = 1 Output is an n-bit binary number

.

.

.

.

.

.

2n

inputsn outputs

Binaryencoder

8-to-3 Binary Encoder8-to-3 Binary EncoderAt any one time, only one input line has a value of 1.

Inputs Outputs

I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0

1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1

I0

I1

I2

I3

I4

I5

I6

I7

y0 = I1 + I3 + I5 + I7

y1 = I2 + I3 + I6 + I7

y2 = I4 + I5 + I6 + I7

8-to-3 Priority Encoder8-to-3 Priority Encoder• What if more than one input line has a value of 1?• Ignore “lower priority” inputs.• Idle indicates that no input is a 1.• Note that polarity of Idle is opposite from Table 4-8 in Mano

Inputs Outputs

I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0 Idle

0 0 0 0 0 0 0 0 x x x 11 0 0 0 0 0 0 0 0 0 0 0X 1 0 0 0 0 0 0 0 0 1 0X X 1 0 0 0 0 0 0 1 0 0X X X 1 0 0 0 0 0 1 1 0X X X X 1 0 0 0 1 0 0 0X X X X X 1 0 0 1 0 1 0X X X X X X 1 0 1 1 0 0X X X X X X X 1 1 1 1 0

Priority Encoder (8 to 3 encoder) Priority Encoder :

H7=I7 (Highest Priority) H6=I6·I7’ H5=I5·I6’ ·I7’ H4=I4·I5’ ·I6’·I7’ H3=I3.I4’·I5’ ·I6’·I7’ H2=I2.I3’·I4’ ·I5’·I6’ ·I7’ H1=I1· I2’ ·I3’·I4’ · I5’·I6’ ·I7’ H0=I0·I1’ ·I2’·I3’ ·I4’ ·I5’ ·I6’ ·I7’ IDLE= I0’ ·I1’ · I2’ ·I3’ ·I4’ ·I5’ ·I6’ ·I7’

Inputs Outputs

I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0 Idle0 0 0 0 0 0 0 0 x x x 11 0 0 0 0 0 0 0 0 0 0 0X 1 0 0 0 0 0 0 0 0 1 0X X 1 0 0 0 0 0 0 1 0 0X X X 1 0 0 0 0 0 1 1 0X X X X 1 0 0 0 1 0 0 0X X X X X 1 0 0 1 0 1 0X X X X X X 1 0 1 1 0 0X X X X X X X 1 1 1 1 0

I1

I2

I3

I4

I5

I6

I0

I7

H1

H2

H3

H4

H5

H6

H0

H7

IDLE

Priority Encoder (8 to 3 encoder) Assign priorities to the inputs When more than one input are asserted, the output generates the code

of the input with the highest priority Priority Encoder :

H7=I7 (Highest Priority) H6=I6·I7’ H5=I5·I6’ ·I7’ H4=I4·I5’ ·I6’·I7’ H3=I3.I4’·I5’ ·I6’·I7’ H2=I2.I3’·I4’ ·I5’·I6’ ·I7’ H1=I1· I2’ ·I3’·I4’ · I5’·I6’ ·I7’ H0=I0·I1’ ·I2’·I3’ ·I4’ ·I5’ ·I6’ ·I7’ IDLE= I0’ ·I1’ · I2’ ·I3’ ·I4’ ·I5’ ·I6’ ·I7’

Encoder Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7

Y1

Y2

Y0

IDLE

I1

I2

I3 Y1

Y2I4

I5

I6

I0

Y0

I7

Binary encoder Priority Circuit

I1

I2

I3

I4

I5

I6

I0

I7

H1

H2

H3

H4

H5

H6

H0

H7

IDLE

I1

I2

I3

I4

I5

I6

I0

I7

Priority encoder

Encoder Application (Monitoring Unit)

Action

Encoder Controller

Machine Code

Machine 1

Machine 2

Machine n

Alarm Signal

Contoller Response

Encoder identifies the requester and encodes the valueController accepts digital inputs.

Summary

Decoder allows for generation of a single binary output from an input binary code For an n-input binary decoder there are 2n outputs

Decoders are widely used in storage devices (e.g. memories) We will discuss these in a few weeks

Encoders all for data compression Priority encoders rank inputs and encode the highest

priority input Next time: storage elements!

circuit representations. boolean functions boolean algebra deals with binary variables and logic...

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