class 0 who’s at risk - ieee entity web...
TRANSCRIPT
• Client Locations
Professional Services Only
No Product Sales!
Ted Dangelmayer
www.dangelmayer.com
Class 0 – Who’s at Risk &
How to Avoid Quality and Reliability Failures
Copyright © 2013 Dangelmayer Associates 2
Agenda
• Preliminaries
• Class 0 Definition
• Brief Review: CDM & CBE
• Who’s At Risk
• Class 0 Technologies
• Class 0 Failure Mitigation
Copyright © 2013 Dangelmayer Associates 3
ESD Acronyms • EPM:
• ESD Program Management:
A Total EPM Quality System
• Best Practices Benchmarking™
• Relative Compliance to Best Practices
• Quantifies Yield Improvement Opportunity
• EOS – Electrical Overstress
• IC Damage due to Electrical Over Voltage or Current
• HBM – Human Body Model
• CDM – Charged Device Model
• CBE – Charged Board Event
• CDE – Cable Discharge Event
Copyright © 2013 Dangelmayer Associates 4
DA ESD Class 0 Definition
• Class 0
• Withstand Voltages Less than 250 volts HBM or CDM
• Class 00
• Withstand Voltages Less than 125 volts HBM or CDM
• Class 000
• Withstand Voltages Less than 50 volts HBM or CDM
Note: Class 0 Devices Prone To Higher Levels of
Test Failures, Test Escapes and Latent Failures
Copyright © 2013 Dangelmayer Associates 5
IC Design Target Levels
Model 2009 2010
HBM 2000V 500V
CDM 500V 250V
Average Device Thresholds
Model 1992 1998 2003 2007 2013 2014
HBM 3800V 3000V 2200V 1500V 1000V 750V
CDM 800V 700V 675V 625V 325V 240V
ESDA Technology Roadmap
Device Thresholds Are Declining
Copyright © 2013 Dangelmayer Associates 6
• Catastrophic
• Device failure that is both
sudden and complete. It
involves complete loss of the
required function
• Cumulative
• Device failure resulting from
multiple sub-threshold
exposures to ESD
• Latent
• Device failure over time
due to prior ESD damage
ESD Damage
A Quality & Reliability Issue
Copyright © 2013 Dangelmayer Associates 10
Brief Review: CDM – CBE
Copyright © 2013 Dangelmayer Associates 11
Charged Device Model
Conductive Surface
CDM Video
Device Contact Resistance
Capacitance of
Device
Charge
“Flow” Q
Ground
“99.9% of ESD Failures are CDM/CBE/CDE!”
Andrew Olney, Analog Devices, Quality Director
& Industry Council, TI, Intel, etc.
Copyright © 2013 Dangelmayer Associates 13
S20.20 - Class 0 and CDM/CBE Limitations
Yield Improvements by Adding CDM & CBE Best Practices
0
5
10
15
20
25
1 5 9 13 17 21 25 29 33 37 41 45 49 1 5 9 13 17 21 25 29 33 37 41 45 49
Week
CDM & CBE
Controls Added
22%
ESD
Yield
Loss
S20.20 Program
(HBM Focused)
39% Best
Practices
Benchmarking™
Note: Courtesy Herald Datanetics Itd. - 1st Class 0 Certified Manufacturing Operation
http://www.dangelmayer.com/class-0-certification.php Each data point is confirmed ESD damage
during production (typically 65 volt CDM/HBM ESD sensitivity) and different colors represent
different products.
P
E
R
C
E
N
T
D
E
F
E
C
T
I
V
E
94% Best
Practices
Benchmarking
Copyright © 2013 Dangelmayer Associates 14
CBE (Charged Board Event) Test Set-Up
Olney et al (Analog Devices)
Field Plate
Thin Dielectric
Film
Sensitive Device Pin
Copyright © 2013 Dangelmayer Associates 15 Courtesy: Andrew Olney, Quality Director, Analog Devices
Charged Board Event ESD Damage
Most FA Experts Misdiagnose as EOS!!!!
Up to 50% of EOS Failures are CBE ESD! (2008)
CDM Device Damage CBE Device Damage on Circuit Board
X200 X4000
Peak Currents of 25 amps Have Been Measured!
video
Copyright © 2013 Dangelmayer Associates 16
How to Classify Circuit Boards
• Based on Most Sensitive Component
• Class I, 0, 00, 000
• Must Have Both HBM & CDM Thresholds
• Estimates Are Not Sufficient • W/O Data You are At Risk
• Consider Class 0 For Boards Due to CBE
• Based on Criticality of Application
• 25 Amp Discharge Currents Possible
Copyright © 2013 Dangelmayer Associates 18 p18
Are You On
A Collision Course Too?
“The Perfect Storm”
Entire East Coast of USA
October 1991
• Without Typical “Hurricane Warnings”!
• Fishermen At Sea Caught Off-guard
• 2000 Miles of Hurricane Like Conditions
• ESD Analogy:
• CDM Generally Not Understood
• Class 0 Trend Approaching Now
• A Very ESD Real Threat!
• More Dangerous than Individually
CDM
+ Class 0
= The Perfect ESD Storm!
Copyright © 2013 Dangelmayer Associates 19
Class 0 - Who’s At Risk
Copyright © 2013 Dangelmayer Associates 20
Best Practices Benchmarking™
0
20
40
60
80
100
17 12 6 4 21 11 8 5 2 26 25 19 15 24 37 20 10 29 14 28 18 32 31 33 42 16 3 36 27 7 13 38 41 1 34 30 9 40 37 35 12 44
EP
M P
erf
orm
an
ce
Preferred
Acceptable
Conditional
Unacceptable
Defense
Aerospace
Manufacturing Sites Contract
None of the Sites Assessed Since 2001 had adequate
CDM/CBE Controls in place initially!
High
Risk
Zone
Copyright © 2013 Dangelmayer Associates 21
Class 0 - CDM Threshold Dependencies
Ref: Industry Council WPII 2009
Larger Device Package Size
Higher
Operating
Speeds
Copyright © 2013 Dangelmayer Associates 22
Class 0 Technologies
• ICs
• Nanoscale CMOS
• RF
• GaAs
• Optoelectronics
• Lasers
• LEDs
• Detectors (PIN, APD)
• MEMS
• MR Heads Sylvania
Application
Notes
Copyright © 2013 Dangelmayer Associates 23
Class 0:
Who’s At Risk
• Semiconductor Backend
• Automation
• HBM Programs
• S20.20 Programs
• Manufacturing w/o
• HBM & CDM Thresholds
• CDM Best Practices
• CBE Best Practices
• Circuit Board Manufacturing & Integration
• Contract Manufacturing
• Defense Manufacturing
• Aerospace Manufacturing
• NASA
• Consumer Electronics Manufacturing
• Medical Manufacturing
• Automotive Manufacturing
• Wafer Fabrication & Wafer Saw
• New Construction & Outfitting New Lines
Copyright © 2013 Dangelmayer Associates 24
Circuit Board Manufacturing & Integration
• Myth:
Circuit Boards are Less Sensitive to ESD than Devices
• Widely Assumed True - False Sense of Security
• Boards Are More Sensitive than Components
• Up To 25 Amp Discharge Currents
• Nokia Asserts All ESD Failures Happen at Board Level
• Rapidly Escalating Probability of at least One Class 0
Component per Board
• 50% of EOS Board Failures are ESD (CBE/CDE)
Copyright © 2013 Dangelmayer Associates 26
Variation in CBE
Waveforms
A - High L, C
B - Lower L, C; higher R
C - Faster discharge (small C)
D - Slower discharge (large C)
E - Two RLC sources
F - High L, R
Data Courtesy Nokia
Copyright © 2013 Dangelmayer Associates 27
At Risk - Contract Manufacturing (CM)
• CM Programs are HBM – S20.20
• On a Collision Course
• Customer Generally Do Not Specify Class 0 Requirements
• Customers Leave CDM & Class 0 Mitigation to CMs
• CMs Require Customers Requirements to Take Action
• Therefore – a Collision Course
Copyright © 2013 Dangelmayer Associates 28
At Risk - Defense & Aerospace Manufacturing
• CDM & CBE Mitigation Not Required
• Generally Not Well Understood at Factories
• Mil Standards 30 Years Outdated
• S20.20 an HBM Standard
• Resistant To Change
Copyright © 2013 Dangelmayer Associates 29
At Risk - Consumer Electronics Manufacturing
• Often Performance & Cost Driven
• High Speed
• Technology Node Feature Sizes
• Circuit Functionality
• I/O Density
• Combination Prone to Class 0 Thresholds
Copyright © 2013 Dangelmayer Associates 30
At Risk - Medical Manufacturing
• FDA Recognizes S20.20
• CDM & CBE Not Recognized
• Failures Life Threatening
Copyright © 2013 Dangelmayer Associates 31
At Risk - Automotive Manufacturing
• Expanding Application of Electronics
• Less Experience with Electronics Manufacturing
• Transitions from Mechanical to Electronic Difficult
• ESD Controls New to Automotive Repair Operations
• Often Insufficient Controls
Copyright © 2013 Dangelmayer Associates 32
At Risk - New Construction & Outfitting New Lines
• Class 0 Often Overlooked for New Construction
• ESD Engineers Often not Involved Early
• Architects & Facility Engineers Make Decisions without ESD Input
• Can Result in Significant Cost Penalties to Correct Errors
• e.g. - Segregation of Class 0 Lines May be Necessary
• Class 0 Material Properties Generally Not Considered
• Flooring
• High vs. Low Charging Selection
• Conveyors, Material Transports, Automation & Workstations etc.
• Can Result in Replacement of Costly Items for Class 0 Applications
Copyright © 2013 Dangelmayer Associates 33
At Risk - Wafer Fabrication &
Wafer Saw Operations
Copyright © 2013 Dangelmayer Associates 34
Wafer ESD Model
Field plate at V
Arc model, I(t)- Includes
inductance
Small features Large
bus
Bulk resistance
V(t)
surface resistance
small cap large cap
neglected
neglected
Are ESD failures
happening at
wafer level?
Copyright © 2013 Dangelmayer Associates 35
Typical Wafer Potential Difference Distributions
Difference in potential from zap point
5000 volt zap
-250
-200
-150
-100
-50
0
0 0.001 0.002 0.003 0.004 0.005
position (mm)
vo
ltag
e
Potential differences between neighboring points
-80
-60
-40
-20
0
20
40
60
80
0 0.001 0.002 0.003 0.004 0.005
wafer position (mm)
po
int-
to-p
oin
t vo
ltag
e (
v)
Copyright © 2013 Dangelmayer Associates 36
Class 000 – Wafer Saw Example
Unexpected Results!
• CDM Threshold – 35 Volts
• 92.2% Defective at Wafer Saw
• Failure Analysis
• CDM Damage
Copyright © 2013 Dangelmayer Associates 39
Class 0 Failure Mitigation
Copyright © 2013 Dangelmayer Associates 40
Class 0 Mitigation Considerations
• Industry Standards Do Not Include CDM For Class 0!
• Unlikely They Will in Foreseeable Future
• Not Conducive to Standardization
• Customization Essential
• CDM Mitigation Techniques Not Well Known
• Not Planned for 2014 Issue of S20.20
• 99.9% of ESD Component Failures are CDM/CBE/CDE
• CDM & CBE Techniques Virtually the Same
• Therefore:
• Class 0 Controls ~ CDM Controls
• CDM Mitigation Techniques Must Be Fully Understood
• Proven CDM Best Practices Requirements
• In Private Sector – Limited Access by Public
• Class 0, 00, 000 Requirements
• Escalate at 250 V, 125 V, 50 V
Copyright © 2013 Dangelmayer Associates 41
Best Industry
Manufacturing Standard
ANSI/ESDA S20.20
Scope: HBM >100V
Thus:
S20.20 Customization
is Essential for :
Class 0, CBE, CDE &
CDM
Industry Standards
Lag Technology
10 to 15 years
Copyright © 2013 Dangelmayer Associates 42
CDM Mitigation Two Strategies – Which One is S20.20?
Lower device voltage or higher surface resistance in the
discharge path can reduce discharge current.
Solder
Video
Copyright © 2013 Dangelmayer Associates 44
S20.20 - Class 0 and CDM/CBE Limitations
Yield Improvements by Adding CDM & CBE Best Practices
0
5
10
15
20
25
1 5 9 13 17 21 25 29 33 37 41 45 49 1 5 9 13 17 21 25 29 33 37 41 45 49
Week
CDM & CBE
Controls Added
22%
ESD
Yield
Loss
S20.20 Program
(HBM Focused)
39% Best
Practices
Benchmarking™
Note: Courtesy Herald Datanetics Itd. - 1st Class 0 Certified Manufacturing Operation
http://www.dangelmayer.com/class-0-certification.php Each data point is confirmed ESD damage
during production (typically 65 volt CDM/HBM ESD sensitivity) and different colors represent
different products.
P
E
R
C
E
N
T
D
E
F
E
C
T
I
V
E
94% Best
Practices
Benchmarking
Copyright © 2013 Dangelmayer Associates 45
Questions?
Ted Dangelmayer
Dangelmayer Associates, LLC
www.dangelmayer.com
978 282 8888