class-d audio power amplifier - msic d&t...

Class-D Audio Power Amplifier

Chun Wei Lin

2015/2/11

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin

2

Outline

Introduction & background

Linear control v.s Switching control class-D audio amplifier

Modulator designs

Power stage designs

Low-pass (LC) filter designs

OC/OV/OT protections

Four switching power amplifier designs & results

Conclusions

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3

Overview of Audio Systems

Technology trends

Compact and portable

High power efficiency

High fidelity (Hi-Fi)

Higher sampling frequency

Various digital media

Audio compression algorithms

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Objective of Audio Amplifier

Goal :

Reproducing input audio signals at sound-producing

output elements (i.e. loudspeakers, headphones)

with desired volume and power level.

Golden guidelines to designer

Efficient power delivery

Linear signal reproduction

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5

Class-A audio amplifier (High-end audio system - expensive)

Advantage: Low distortion（fully linear amplifier）

Disadvantage: Quiescent power dissipation,

poor efficiency, large heat-sink area

Class-A Audio Amplifier

refI

refILR

Iv

Ov1Ei

1Q

2Q

Li

CCV

CCV

2 3 4 t0

CQI

Ci

%254

1

4

2

CCLref

m

VRI

V

Duty Ratio=100%

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6

Class-B Audio Amplifier

Class-B audio amplifier

Advantage: No quiescent power dissipation,

up to 78.5% power efficiency!

Disadvantage: Crossover distortion

Iv Ov

LR

CCV

CCV

NQ

PQ Li

2 3 4 t0

Ci

%5.7844

CC

m

V

V

Duty Ratio=50%

B

E

B

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7

Class-AB Audio Amplifier

Class-AB audio amplifier

Advantage: up to 78.5% power efficiency and low distortion

2 3 4 t0

Ci

CQI

Iv

Ov

LR

refI

NQ

PQ Li

Ni

Pi

CCV

CCV

%5.7844

CC

m

V

V

50%<Duty Ratio<100%

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8

Switching Amp. v.s Linear Amp.

In today’s applications, the switching amplifier

is widely used because it features …

Theoretically 100% power efficiency

Less heat

Low cost

Hi-Fi (reach the industry standard of class AB )

Suitable for portable, fairy and quality device

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9

+𝑉𝑆

Class-D (switching) audio amplifier

Advantage: high power efficiency (up to 90%), no heat sink

Disadvantage: large distortion originated from fast two-level

switching

Class-D Audio Amplifier

Gate

Drivers 𝑉𝑖𝑛

𝑉𝑠𝑤

𝑉𝑜𝑢𝑡

−𝑉𝑆

𝐿𝑜

𝐶𝑜 𝑅𝐿

Power Stage Modulator Low-Pass Filter

Modulator

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Power Efficiency v.s Output Power

0

20

40

60

80

100

0.0 0.2 0.4 0.6 0.8 1.0

Class-A ideal Class-B ideal Class-D simulated

Normalized output power (PL / PLMAX)

Po

wer

E

ffic

ien

cy (%

) Class-D audio amplifier features high power efficiency over a wide

range of power demand.

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The switching operation of power amplifier brings undesired

distortion originated from I. the sudden request of two-level

control signal and II. the nonlinearities of power transistors.

Distortion Sources

Gate

Drivers

Low-pass

Filter 𝑉𝑜𝑢𝑡

𝑉𝑠𝑤

𝑅𝐿 𝐶𝑜

𝐿𝑜

+𝑉𝑠

−𝑉𝑠

tD,ON tD,OFF

RDS,ON

finite dV/dt

I

II

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12

Outline


Linear control v.s Switching control class-D amplifier (CDA)

Modulator designs PWM, SDM, SMC

Power stage designs




Conclusions

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I. Pulse-Width Modulation (PWM) CDA 1/6

PWM

modulator

Low-pass

filter (LC) VIN VOUT

∆𝐼

Distortion

sources

𝑅𝐿

+

–

VIN

VC

VIN

VC

VPWM

VPWM

+𝑉𝑠

−𝑉𝑠

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PWM

modulator

Switching

power stage

Low-pass

filter (LC) VOUT

∆𝐼

𝑅𝐿

Verr VIN

+

Feedback compensation for minimizing the difference between

input and output signals.

– +

Loop

Filter

Feedback

compensation

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M.A. Telechuk, A. Gribben, and C. Amadi, “True Filterless Class-D Audio Amplifier,” IEEE J. Solid-State

Circuits (JSSC), vol. 46, no. 12, pp. 2784 - 2793, Dec. 2011.

Feedback compensation, loop filter, Uniform PWM sampling

UPWM

modulator

+

–

+ –

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I. Feedback, II. loop filter, III. Uniform PWM sampling

I II III

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Two poles and one zero of loop filter

for higher audio band gain and better

distortion compensation.

147k 110k 221k

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Transfer function of loop filter:

Transfer function of amplifier:

Poles:

Zero:

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II. Sigma Delta Modulation (SDM) CDA

SDM

modulator

Switching

power stage

Low-pass

filter (LC) Verr VOUT

+ VIN

+ -

Feedback

compensation

SDM applies feedback compensation inside modulator to

reduce the difference between input and output signals.

𝑅𝐿

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20

II.A Delta Modulation (DM) 1/6

A digital audio processing system includes a delta modulator

(DM) which is first proposed in 1952.

A 1-bit quantizer and a integrator are used in the feedback

path to reduce the difference, e, between input signal Si

and output signal So.

integrator

e

quantizer

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Two disadvantages limit its application. First, output signal

So can not follow if input signal Si changes fast.

Secondly, the value of output signal So is unknown if the

value of input signal Si is DC voltage.


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1-bit quantizer Integrator Delta modulator


Si

So

SΔ

require pulse streams

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1-bit quantizer Integrator Delta modulator


Si

So

SΔ

Si

SΔ

So

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Si & SΔ

e

So


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Input signal Modulated signal after filtering


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Sigma delta modulator (SDM) is proposed by moving the

output filter of the delta modulator in front of the subtraction.

Thus, the two integrator can be shared as shown below.

Those problems of delta modulator (DM) can be resolved

in sigma delta modulator because the input signal changes

slowly and smoothly by the integrator.

II.B Sigma Delta Modulation (SDM) 1/6

Si So

SΔ

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A general 1st-order sigma-delta modulator

A general n-th order sigma delta modulator


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1-bit quantizer Integrator First-order SDM


Si

So

SΔ

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1-bit quantizer Integrator First-order SDM


Si

So

SΔ

Si

So

SΔ

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Si

e

So


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Input signal Modulated signal after filtering


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II. Design of 7-th SDM CDA

E. Gaalaas, B.Y. Liu, N. Nishimura, R. Adams, and K. Sweetland, “Integrated Stereo ΔΣ Class D

Amplifier,” IEEE J. Solid-State Circuits (JSSC), vol. 40, no. 12, pp. 2288 - 2397, Dec. 2005.

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III. Sliding-Mode Controller (SMC) CDA 1/6

SMC

controller

Switching

power stage

Low-pass

filter (LC) Verr VOUT

+ VIN

+ -

Feedback

compensation

𝑅𝐿

SMC implements error function and switching function into

controller for reducing distortion without raising sampling

frequency.

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SMC controller

error function

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SMC controller

switching function

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2 adder

1 adder

simplify

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Feedback compensation

SMC

= 𝑬𝟏 + α𝒔𝑬𝟏 = 𝑬𝟏 + α𝑬𝟐

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M.A. Rojas-Gonzalez and E. Sanchez-Sinencio, “Low-Power High-Efficiency Class D Audio Power

Amplifiers,” IEEE J. Solid-State Circuits (JSSC), vol. 44, no.12, pp. 3272 - 3284, Dec. 2009.

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Outline


Linear control v.s Switching control class-D amplifier (CDA)

Modulator designs

Power stage designs SE, BTL / finger, waffle layout




Conclusions

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40

Single-End (SE) Power Stage

VOUT VPWM

+VS

-VS

SH

SL

VPWM

VOUT

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Bridge-Tied-Load (BTL) Power Stage

VOUT+ VPWM+

VOUT- VPWM-

+VS

-VS

+VS

-VS

SH

SL

SH

SL

VPWM+

VPWM-

VPWM+

VPWM- VPWM+ - VPWM-

VOUT+ - VOUT-

VPWM+ - VPWM-

VOUT+ - VOUT-

3 levels 2 levels

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Layouts of Power Stage

I. finger

II. waffle

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Designs of Power Stage

The operation of power stage is simply turning on/off

power transistors.

But the design of power stage affects the efficiency on

power delivery because it is in charge to delivery heavy

current into speaker.

How to design the aspect ratio of power inverter for

higher power efficiency is very important.

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Outline


Linear control v.s PWM control Class-D amplifier (CDA)

Modulator designs

Power stage designs

Low-pass (LC) filter design Butterworth filter



Conclusions

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45

LPF Design for CDAs 1/5

12

1)(

2 sssH

LCs

RCs

LC

sQ

ssV

sVsH

i

o

11

1

)(

)()(

22

002

2

0

Butterworth

Filter

𝐿

C R

Frequency (hz)

Frequency response curve

Gai

n (

dB

)

Bessel

Butterworth

Chebyshev

Elliptic

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RC

RC

2

12

1

LCs

RCs

LC

sQ

ssV

sVsH

i

o

11

1

)(

)()(

22

002

2

0

LPF Design of CDAs 2/5

12

1)(

2

sssH

LC

10

LCf

2

10

RCQ 0

Rf

Q

R

QC

QRC

00

0

2

1

RC

LLC

21

11

Qf

R

Q

R

CL

LC

00

2

0

2

02

11

LCff oc

2

12

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Fig. 2.5b LPF Design of CDAs 3/5

12

1)(

2

sssH

LCs

RCs

LC

sQ

ssV

sVsH

i

o

4

1

4

14

1

)(

)()(

22

002

2

0

Butterworth

Filter

𝐿

C R

𝐿 C

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LCs

RCs

LC

sQ

ssV

sVsH

i

o

4

1

4

14

1

)(

)()(

22

002

2

0


12

1)(

2

sssH

LC4

10

LCf

42

10

RCQ 40

RC

RC

24

12

4

1

Rf

Q

R

QC

QRC

00

0

2444

1

RC

LLC

244

11

4

1

Qf

R

Q

R

CL

LC

00

2

0

2

024

1

4

1

LCff oc

22

12

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Choice of inductance

DC resistance Efficiency

Maximum peak current prevent short-circuit

EMI Shielding inductance

Choice of capacitance

Effective series resistance Q=Xc/ESR Q varies with freq.

))(2(2

2

LINDDSON

L

in

out

RRRI

RI

P

P

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Outline


Linear control v.s PWM control Class-D amplifier (CDA)

Modulator designs

Power stage designs

Low-pass (LC) filter design

OC/OV/OT protections Detections, protections


Conclusions

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51

Safe Operation Area (SOA)

IMAX

+ BVDS

-

M. Berkhout, “Integrated overcurrent protection system for class-D audio power amplifiers,” IEEE J.

Solid-State Circuits, vol. 40, no. 11, pp. 2237–2245, 2005.

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Over-Current (OC) Condition 1/3

B. Krabbenborg, “Protection of audio amplifiers based on temperature measurements in power

transistors,” Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 374–375, 2003.

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Series resistors & comparators

If or

Over-current (OC)

condition happens!

Over-Current (OC) Detection 1/3

VRH VREF > VRL



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Parallel MOS & comparators

If

or

Over-current (OC)

condition happens!

VOUT

>

< VRH

VOUT VRL



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VSL VRL >

Over-current

condition

happens!

Parallel sensing



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Over-Current (OC) Protection

Turning opposite power transistor when OC happens

Current limiting at 4Ω and 2Ω



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Over-Voltage (OV) Protections

𝑉𝑖𝑛

𝑉 𝑜𝑢𝑡

𝑉 𝑈𝐿1 𝑉 𝑈

𝐿2

𝑉𝑇𝐻1 𝑉𝑇𝐻2

Soft-clip Clip rate

= 0.7

Clip rate (hard-clipping)

= 0.9

Voltage-clipping

+ VDD

− VDD

C.-W. Lin and B.-S. Hsieh, An anti-clipping protection system for multilevel class-D amplifier, Proc.

IEEE Int. Conf. on Electr. Eng./Electron., Comput., Telecommun. and Inf. Technol., pp.129–133, 2011.

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Over-Temperature (OT) Detection 1/2



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Over-Temperature (OT) Detection 2/2

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Over-Temperature (OT) Detection & Protection

Tchip (°C)

VCTAT1

Vout (V)

VCTAT2

VZTC

25 125 100

CTAT

Bandgap

Zero TC

Bandgap

IZTC

ICTAT VCTAT1

VCTAT2

VZTC

VZTC

Thermal

Shutdown

(125°C)

Thermal

Protection

(100°C)

+

+

-

-

* CTAT: output current reduces with increasing temperature

* Zero TC: zero temperature coefficient

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Outline

Induction & background


High-fidelity multilevel filterless class-D audio amplifier

Multilevel amplifier with integrated protections

High-efficiency class-D amplifier power stages

Continuous-time LED dimming controller

Conclusions

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64

𝑉𝑝𝑤𝑚 (𝐼𝑝𝑤𝑚)

PWM Class-D Amplifier

𝑉𝑝𝑤𝑚 NPWM

modulator

Low-Pass Filter 𝑉𝑖𝑛 𝑉𝑜𝑢𝑡

𝑉𝑖𝑛

𝑉𝑐

𝑉𝑐

charging time ∆𝐼

∆𝑡↑

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Concept of proposed multilevel technique

PWM modulator

Multilevel

Signal

Generator

(MLSG)

1 0 0

0 0 0

1 0 0

0 1 0

Encoder

Multilevel

Converter

(MLC)

1 0 0

0 0 0

1 0 0

0 1 0

audio pulse width

control code

Bin

ary

nu

me

ric

audio

I II

III Chun-Wei Lin, Bing-Shiun Hsieh, “The multilevel technique for improving filterless class-D audio

amplifiers,” J. of Circuits Systems and Computers (JCSC), under-review 2012.

∆𝐼

∆𝑡

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66

I. Natural PWM Sampling

𝑉𝑖𝑛

𝑉𝑐

𝑉𝑝𝑤𝑚

𝑉1 𝑉2

𝑇𝑠

𝑡𝑛

𝑡𝑛1 𝑡𝑛2

𝑉𝑖𝑛_𝑎𝑣𝑔 =𝑉1 + 𝑉2

2=

1

2∙𝐴 ∙ 𝑡𝑛1 + 𝑡𝑛2

0.5𝑇𝑠 = 𝐴 ∙

𝑡𝑛𝑇𝑠

= 𝐴 ∙ 𝐷

= 𝑉𝑃𝑊𝑀(𝐷)

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II. Multilevel signal generator (MLSG) 1/3

Delay Cell

Adder

DFF

DFF

DFF

𝑽𝑷𝑾𝑴(𝒕)

𝑐𝑙𝑜𝑐𝑘

𝑽𝑴𝑳𝑺𝑮(𝒕)

𝑉𝑃𝑊𝑀 (𝑡 − 𝟏 · Δ𝑇)

𝑉𝑃𝑊𝑀(𝑡 − 𝟐 · Δ𝑇)

𝑉𝑃𝑊𝑀(𝑡 − 𝒌 · Δ𝑇)

= 𝑉𝑃𝑊𝑀 𝑡 − 𝑘 ∙𝑇𝑠

𝑀

𝑀

𝑘=1

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𝑽𝑷𝑾𝑴 (𝒕 − 𝟏 · 𝚫𝑻)

𝑻𝑺 𝑻𝑺

𝒕𝒏

𝑨′

ΔT

ΔT

𝑽𝑷𝑾𝑴 (𝒕 − 𝟐 · 𝚫𝑻)

𝑽𝑷𝑾𝑴 (𝒕 − 𝒌 · 𝚫𝑻)

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𝑉𝑀𝐿𝑆𝐺 𝑡 = 𝑉𝑃𝑊𝑀 𝑡 − 𝑘 ∙𝑇𝑠

𝑀

𝑀

𝑘=1

𝑉𝑀𝐿𝑆𝐺 𝑡 𝑎𝑣𝑔 =1

𝑇𝑠 𝑉𝑀𝐿𝑆𝐺 𝑡

𝑇𝑠

0

𝑑𝑡 =1

𝑇𝑠 𝑉𝑃𝑊𝑀 𝑡 − 𝑘 ∙

𝑇𝑠

𝑀

𝑀

𝑘=1

𝑇𝑠

0

𝑑𝑡

=1

𝑇𝑠 𝐴′

𝑡𝑛

0

𝑀

𝑘=1

𝑑𝑡 = 𝐴′ ∙ 𝑀 ⋅𝑡𝑛

𝑇𝑠= 𝐴′ ∙ 𝑀 ⋅ 𝐷

MLSG output is:

Taking the average value within one period of carrier:

,where D is the duty ratio of PWM-modulated signal

The proposed MLSG is very simple and effective because it expresses

multilevel signal by all digital binary-weighted codes.

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III. Multilevel converter (MLC) 1/2

𝑉𝑝𝑤𝑚+ 𝑉𝑝𝑤𝑚−

V32 2 VVoV22 1 VVo

+𝑉2 +𝑉1 +𝑉2 +𝑉1

+𝑉2 +𝑉1 +𝑉2 +𝑉1

𝑆1

𝑆2

𝑆3

𝑆4

𝑆5

𝑆6

𝑆7

𝑆8

𝑆9

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III. Multilevel converter (MLC) 2/2

TDA

output

SA 1 1 1 1 1 0 0 0 0 0 0 0 0

SB 1 0 0 0 0 1 1 1 1 0 0 0 0

SC 0 1 1 0 0 1 1 0 0 1 1 0 0

SD 0 1 0 1 0 1 0 1 0 1 0 1 0

MLC output +3 +2.5 +2 +1.5 +1 +0.5 0 -0.5 -1 -1.5 -2 -2.5 -3

= VPWM+ – VPWM– a

a V1=1.0V, V2=1.5V.

Use 12 D flip-flops in MLSG for driving MLC

to output 13 voltage levels

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+

-

𝑉𝑖𝑛

𝑉𝑐 NPWM

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

12 DFFs

Encoder

𝑆𝐴 𝑆𝐵 𝑆𝐶 𝑆𝐷

𝑆1 𝑆2 𝑆3 𝑆4 𝑆5 𝑆6 𝑆7 𝑆8 𝑆9

MLSG

MLC

+ output -

Adder

+𝑉2 +𝑉1 +𝑉2 +𝑉1

+𝑉2 +𝑉1 +𝑉2 +𝑉1

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Large capacitor (i.e. larger )

for linear integration

Triangular Waveform Generator - I

+

-

𝑉𝑖𝑛

𝑉𝑐

NPWM

+𝑉𝑆

−𝑉𝑆

𝐶𝑜

𝜏=RC

𝜏

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Triangular Waveform Generator - II

Cascade connection (m1 & m2)

for larger on-resistance and larger

and enhancing the integration

𝜏

+𝑉𝑆

−𝑉𝑆

𝐶𝑜

𝜏=roC

𝑚1

𝑚2

+

-

𝑉𝑖𝑛

𝑉𝑐

NPWM

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Comparison of Output Waveform – I & II

Cascade connection can improve the

linearity of triangular generator!!

With output cascade Without output cascade

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Output Waveform – II

Amplitude Variation due to

Process Variation!!

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Comparator (modulator) Design

MP1 MP2

MN3 MN4

MP5

R1

MN8

MP9MP10

MP11

CcVin- Vin+

Vout

1 2

3

4

5

35/1 35/1

30/1 30/1

40/240/2

6/1

30/1

M=12

40/1

M=6

3k

0.4pF

+

-

modulator

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Comparator Design

*********************************************************************************

* PROCESS : 0.35um MIXED MODE (2P4M,3.3V/5.0V) POLYCIDE *

*********************************************************************************

* Specifications :

* Open loop gain 98.0dB

* CMRR 117.5dB

* PSRR+- 115.0dB / 100.4dB

* PM 57.1deg

* Maximum output voltage swing 0.35V ~ 4.7V

* Power supply voltage +5.0V

* Unit gain frequency 81.3MHz (CL=2pf)

* Slew rate 103.0 V/us - 171.0V/us (CL=2pf)

* Settling time 50nsec

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DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

12 DFFs

𝑆𝐴 𝑆𝐵 𝑆𝐶 𝑆𝐷 MLSG

Adder

D

CLK

C_B C_D

C_D

C_B

C_DC_B

C_B

C_DC_D C_B

Q QBD

CLK Q

QB

D-FF

1

4

3 5

6

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DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

12 DFFs


Adder

3bit

FA

2bit

FA

HA

HA

HA

HA

2bit

FA

(LSB)1A

(MSB)2A

1B

2B

1C

2C

1D

2D

(MSB)13S

12S

(LSB)11S

(MSB)23S

22S

(LSB)21S

(MSB)4S

(LSB)1S

2S

3S

1d

2d

3d

4d

5d

6d

7d

8d

Pad

Pad

Pad

Pad

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81

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

12 DFFs


Adder

1( )S LSB

HA

HA

HA 2A

2B

1A

1B

2S

3( )S MSB

2-bits FA

2 1 2

1 1 2

S d d

S d d

1-bit HA: 1( )S LSB

2S

1d

2d

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82

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

DFF

𝑐𝑙𝑘

12 DFFs


Adder

1( )S LSB

4 ( )S MSB

HA

HA

HA 2A

2B

1A

1B

2S

3-bits FA

HA HA 3A

3B

3S

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83

Encoder & MLC

Encoder


𝑆1 𝑆2 𝑆3 𝑆4 𝑆5 𝑆6 𝑆7 𝑆8 𝑆9

MLC

+ output -

+𝑉2 +𝑉1 +𝑉2 +𝑉1

+𝑉2 +𝑉1 +𝑉2 +𝑉1

1

2

3

4

5

6

7

8

9

A B B C A D

A B C D A B C D

B C D A B D

A B C D A B C D A B C D

A B C D B C D

A C

A B C B C D B C D

A B

A B C D A B C D

S S S S S S S

S S S S S S S S S

S S S S S S S

S S S S S S S S S S S S S

S S S S S S S S

S S S

S S S S S S S S S S

S S S

S S S S S S S S S S

A B CS S

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84

Chip photograph

III II

I

I. NPWM modulator

II. Multilevel Signal

Generator & Encoder

III. Multilevel Converter

TSMC 5V-0.35um

Area = 2.25mm2 with

40-pin DIP package

RL = 8Ω, Lo = 33uH

2015/2/11


85

Triangular Generator 1/3

Use guard-ring to block noise bypassing from substrate.

2015/2/11


86


The same current direction for current source matching.

2015/2/11


87


Power planning circles entire circuit.

VDD

Gnd

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88

Modulator (Two-stage amp.) 1/2

Common centroid matching of double poly capacitor.

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89

Modulator (Two-stage amp.) 2/2

Snake routing of poly resistor.

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90

Stick diagram for simplifying routing path of signals.

D-type Flip-Flop

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91

Well clock matching for minimizing timing delay.

Chains of D-type Flip-Flop 1/2

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92

72 DFFs within proposed MLSG.

Chains of D-type Flip-Flop 2/2

DFF

2015/2/11


93

4-bits Digital Adder

3bit

FA

2bit

FA

HA

HA

HA

HA

2bit

FA

(MSB)4S

(LSB)1S

2S

3S

1d

2d

3d

4d

5d

6d

7d

8d

Matching

sub-circuit

placement

and routing.

2015/2/11


94

Encoder

Encoder


𝑆1 𝑆2 𝑆3 𝑆4 𝑆5 𝑆6 𝑆7 𝑆8 𝑆9 Minimize layout into a square

for saving chip area.

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95

Share “Drain” or “Source” area between two transistor for

saving chip area.

Tapered Buffer

D D D D D S S S

2015/2/11


96

Whole Chip Plan

Power planning for well supplying entire chip

2015/2/11


97

Board Measurement

noise

source

2015/2/11


98

PCB Measurement

Supplies filter B

NC

co

nn

ecto

r for

hig

h fre

q. c

arrie

r, CL

Ks

BNC for output

BNC for input

2015/2/11


99

PCB Measurement

Less

noise

2015/2/11


100

Multilevel and PWM Signals

PWM signal

Multilevel signal

𝑚𝑢𝑙 𝑡 𝑎𝑣𝑔 = 𝐴′ ∙ 𝑀 ⋅ 𝐷

∝ 𝑉𝑃𝑊𝑀(𝑡)

2015/2/11


101

Multilevel and Filtering Signals

Multilevel signal

Recovered audio signal

2015/2/11


102

Spectrum of PWM amplifier without filter

0 2 4 6 8 10 12 14 16 18 20-120

-100

-80

-60

-40

-20

0

Frequency (kHz)

Mag

nit

ude

(dB

)

Freq. (kHz)

Mag

nit

ud

e(dB)

THD=50dB

≈0.316%

Vin = 1kHz, Vtri = 250kHz

RL = 8Ω, Lo = 33uH

SNR=70dB

2015/2/11


103

0 2 4 6 8 10 12 14 16 18 20-120

-100

-80

-60

-40

-20

0

Frequency (kHz)

Mag

nit

ude

(dB

)

Freq. (kHz)

Mag

nit

ud

e(dB)

Spectrum of PWM amplifier with filter


RL = 8Ω, Co = 2.0uF, Lo = 127uH

THD=57dB

≈0.141%

SNR=72dB

BW = 10kHz, Q = 1

2015/2/11


104

0 2 4 6 8 10 12 14 16 18 20-120

-100

-80

-60

-40

-20

0

Frequency (kHz)

Mag

nit

ud

e (

dB

)

Freq. (kHz)

Mag

nit

ud

e(dB)

Spectrum of multilevel amplifier without filter


RL = 8Ω, Lo = 33uH

THD=73dB

≈0.02%

SNR=85dB

2015/2/11


105

THD performance versus power delivery

0.01

0.1

1

10

1 50 100 150 200 250 300 350 400 450 500 550

Output power (mW)

TH

D (

%)

(100%) (55%) (18%)

(0.12%)

(0.02%)

(0.035%)

2015/2/11


106

Power efficiency versus power delivery

0

20

40

60

80

100

0 50 100 150 200 250 300 350 400 450 500 550

Output power (mW)

η (

%)

(100%) (27%)

(85%)

* PLoss = 150mW ∙ 20% = 30mW/2.4mW (8%, TDA&encoder)

2015/2/11


107

EMI Spectrum of Multilevel Class-D Amplifier

0 250 500 750 1000

-100

-80

-60

-40

-20

0

Frequency (kHz)

Mag

nit

ude

(dB

)

0 250 500 750 1000

-100

-80

-60

-40

-20

0

Frequency (kHz)

Mag

nit

ude

(dB

) Conventional PWM Class-D Amplifier

Proposed Multilevel Class-D Amplifier

fc

fc

fc-2fsig fc+2fsig

fc-2fsig fc+2fsig

250

250

2015/2/11


108

Comparison to prior class-D audio amplifiers

Design [53] [54]§ [55] [56]§ [21] [22]

BMA/TMA [24] [57]

Proposed

Amplifier

CMOS

Process

(μm)

0.09 0.35 0.5 0.35 0.5 0.5 0.5 0.5 0.35

Supply

(V) 4.2 5.0 5.0 5.0 2.7 2.7 2.7 2.5 5.0

Load (Ω) 8 8 8 8 8 8 8 8 8

fs (kHz) 410 250 1000 280 380 450 500 >200 250

η (%) 76 88 70 89 84 89 / 90 91 92 85

Po,max

(mW) 700 1000 1000 1000 410 250 200 450 550

SNR (dB) 98 97 94 98 100 94 / 92 65 80 85

THD (%) 0.03 0.18 0.02 0.02 0.02 0.02 / 0.03 0.08 0.3 0.02

Area(mm²) 0.44 2.1 10.5 9.0 1.65 1.49 / 1.31 4.7 0.6 2.25

Levels 3 3 2 2 3 2 / 3 3 2 13

FOM 35.5 7.9 15.7 17.0 52.2 35.1 / 26.3 1.6 9.2 30.9

Topology PWM PWM ΔΣ ΔΣ SMC SMC SMC RWDM PWM

2015/2/11


109

Outline

Induction & background


High-fidelity multilevel filterless class-D audio amplifier




Conclusions

2015/2/11


110

Multilevel Amplifier with Integrated Protections

Over-current (OC)

Over-voltage (OV)

Multilevel Technique

I. Pulse Density

Adjustment MLC

II. OC& OV & OT

Detection

III.

Control Logic

OV OC

+ ILim

− ILim

+ VLim

− VLim Adaptive Power Control Loop

MLSG

Chun-Wei Lin, Bing-Shiun Hsieh, “Multilevel filterless class-D amplifier with adaptive power control

protection,” Microelectronics Journal, under-review 2013.

The relationship between power loss PLoss and relative temperature difference ΔT

( ) ( )J A Loss Static DynamicH k T T W P t P P t

* k is heat coefficient of packages usually cause by OC or OV conditions

2015/2/11


111

Multilevel Amplifier Design

PWM modulator

Multilevel

Signal

Generator

(MLSG)

1 0 0

0 0 0

1 0 0

0 1 0

Encoder

Multilevel

Converter

(MLC)

1 0 0

0 0 0

1 0 0

0 1 0

audio pulse width

control code

Bin

ary

nu

meric

audio

I II

III

2015/2/11


112

before after pulse density adjustment

I. Pulse Density Adjustment Circuits 1/2

TS

PWM pulse width Multilevel output

2015/2/11


113

I. Pulse Density Adjustment Circuits 2/2

PWM

Modulator

Pre-amplifier

K ≥ 1

Pre-amplifier

K ≤ 1

Pulse-Adjustment

Control

2015/2/11


114

MXS

II. Over-Current (OC) Detection Circuits

–

+

OPA

…

MX

IOut

= N∙ ISense

ISense MFS

VTh

VDD VDD

VDD

Reset

CLK

D Q

𝐼𝑀𝑋

𝐼𝑀𝑋𝑆

= (𝑊

𝐿)𝑀𝑋

(𝑊

𝐿)𝑀𝑋𝑆

= N

𝑉𝐺𝑆,𝑀𝑋= 𝑉𝐺𝑆,𝑀𝑋𝑆

𝑉𝐷𝑆,𝑀𝑋= 𝑉𝐷𝑆,𝑀𝑋𝑆

Chun-Wei Lin, Bing-Shiun Hsieh, Chih-Wei Chung, “PWM-based multilevel class-D amplifier with

integrated over-current protection system,” IEEE ICIEA, pp.1394 - 1398, June 2010.

2015/2/11


115

II. Over-Voltage (OV) Detection Circuits

Multilevel output

t

LPF output

The maximum

output level

clock

MLS

G

Encoder

Flip

Flop

Counter

Ι

Previous

state

Present

state

Clipping

Chun-Wei Lin, Bing-Shiun Hsieh, “An anti-clipping protection system for multilevel class-D amplifier,”

IEEE ECTI-CON, pp.129 - 132, May 2011.

2015/2/11


116

II. Over-Temperature (OT) Detection

Tchip (°C)

VCTAT1

Vout (V)

VCTAT2

VZTC

25 125 100

CTAT

Bandgap

Zero TC

Bandgap

IZTC

ICTAT VCTAT1

VCTAT2

VZTC

VZTC

Thermal

Shutdown

(125°C)

Thermal

Protection

(100°C)

+

+

-

-

* CTAT: output current reduces with increasing temperature

* Zero TC: zero temperature coefficient

2015/2/11


117

III. Pulse Density Adjustment Control Logic

S 0

K = 1

S 1

K = 1 - 2/12 S 2

K = 1 - 4/12

S 3

K = 1 - 6/12

S 4

K = 1 - 8/12

S 5

K = 1 - 10/12

S 6

K = 0, PWM out = 0

( Short Circuit )

OC/OV/OT

= 0 OC/OV/OT = 1 OC/OV/OT = 1 OC/OV/OT = 1 OC/OV/OT = 1 OC/OV/OT = 1

OC/OV/OT = 1 OC/OV/OT = 0

OC/OV/OT = 0 OC/OV/OT = 0 OC/OV/OT = 0 OC/OV/OT = 0 OC/OV/OT = 0

2015/2/11


118

Output Signals before and after Protection

0 0.25 0.5 0.75 1-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

Time (ms)

Vo

lta

ge

(V

)

After 6-levels reduction

Before over-current protection

2015/2/11


119

10%

0

20

40

60

80

100

0 2 4 6 8 10

Po

wer

Eff

icie

ncy

(%

)

Reduced levels

0.01

0.1

1

10

0 2 4 6 8 10

TH

D (

%)

(RL=8Ω) (RL=4Ω)

fSIG = 1kHz

fTRI = 250kHz,

IO,MAX = 0.35mA

17dB

2015/2/11


120

Transient Response of OV Protections

0 0.5 1 1.5 2 2.5 3-15

-10

-5

0

5

10

Time (ms)

Ou

tpu

t V

olta

ge

(V

)

I

I II

II

Audio signal

Hard clipping

Soft clipping

Proposed anti-clipping

0 0.5 1 1.5 2 2.5 3-15

-10

-5

0

5

10

Time (ms)

Ou

tpu

t V

olta

ge

(V

)

I

I II

II

Audio signal

Hard clipping

Soft clipping

Proposed anti-clipping

2015/2/11


121

Representation of OV Condition

Expected sinusoidal signal

Clipping sinusoidal signal

II

2/sT

sV

tI

max_oV

III

IT IIT IIIT

2015/2/11


122

Clipping Ratio and Weight

0

20

40

60

80

100

0 10 20 30 40 50 60 70 80 90 100

Cli

pp

ing w

eigh

t (%

)

Clipping ratio (%)

Hard-Clipping

Soft-Clipping

Anti-Clipping

35%

2015/2/11


123

Clipping Ratio and Weight

0

20

40

60

80

100

0 10 20 30 40 50 60 70 80 90 100

Heat

Fact

or

(%

)

Clipping ratio (%)

Hard-Clipping

Soft-Clipping

Anti-Clipping

60 %

2015/2/11


124

Temperature estimation qJA : Junction-to-Ambient resistance

* TJ: temperature of chip junction

* TA: temperature of ambient

* PLoss: power-loss of chip

Thermal Resistance of Chip Packages 1/2

J AJA

Loss

T T

Pq

TJ

case

chip

board

TA

TA

θJC

θCA

θBA

≡

TA

TJ

θJA

(option)

Heat spreader

θJB

Radiation Convection Conduction

25 / 2( ) 4 (1 0.85%) 0.47W

4LossP

0.47 65 30

J A Loss JAT T T P

C

q

* Temperature difference on package!

2015/2/11


125

Thermal Resistance of Chip Packages 2/2

t (s)

TJ (°C)

100

25

TJ

TA

ΔTOT

ΔTOTP

OT condition after power-loss reduction (OTP)

( )J AJA

Loss

T T

Pq

2015/2/11


126

Control of OT Protection

PLoss (W)

TJ (°C)

25

125

100

PStatic ↓

2015/2/11


127

Speaker

output

Transient Response of OT Protection

Multilevel

output

VMLT (V)

PLoss (W)

TJ (oC)

100

125

t OTP

t (ms)

t (ms)

t (ms)

… …

…

25

2015/2/11


128

Simulation Results

0 2 4 6 8 10

0 2 4 6 8 10

IO,RMS = 0.88mA

PO,MAX = 3.1W

PLoss,MAX = 0.47W

ΔTpackage ≒ 30°C

100

80

60

40

20

0

PL

oss

Red

uct

ion

(%

) P

ow

er E

ffic

ien

cy (

%)

100

80

60

40

20

0

Over-temperature Protection

Reduced levels

(15%

)

(50%)

2015/2/11


129

Outline



High-fidelity filterless class-D audio amplifier




Conclusions

2015/2/11


130

Design of full-bridge power stage 1/2

PWM

Modulator c(t)

s(t)

LC

filter

Gate

drivers

Full-bridge

power inverters

The power stage of class-D amplifier consume most of total

power loss because they are in charge to delivery heavy current

into speaker.

Proposed control method is applied to dynamically reduce the

power loss of power stages and enhance the power efficiency

of PWM class-D amplifier over a wide range of power demand.

Full-bridge Power stage

2015/2/11


131

Design of full-bridge power stage 2/2

0

20

40

60

80

100

0.0 0.2 0.4 0.6 0.8 1.0

Modulation index, D

Pow

er

loss

(m

W)

PS, D=0.1

PS, D=0.9

PS, D=0.3

PD, D=0.9

PD, D=0.3

PD, D=0.1

2015/2/11


132

Optimal design of efficient power stages 1/9

Chains of gate drivers CMOS inverters

The total power loss of power stages comprise the switching loss

on parasitic capacitance CSW of gate drivers and conduction loss

on on-resistance ron of inverter transistors.

Switching Power Stages

𝑻−(𝑵−𝟐)𝑪𝒑 𝑻−(𝑵−𝟏)𝑪𝒑 𝑻𝟎𝑪𝒑 𝑻−𝟏𝑪𝒑

𝑪𝑺𝑾

𝒓𝒐𝒏

𝒓𝒐𝒏

PWM

Modulator V𝐂

VS LC

Filter

𝒊𝒐𝒖𝒕

𝑻−(𝑵−𝟐)𝑪𝒑 𝑻−(𝑵−𝟏)𝑪𝒑 𝑻𝟎𝑪𝒑 𝑻−𝟏𝑪𝒑

2015/2/11


133


𝑃𝐿𝑜𝑠𝑠 = 𝑃𝑐 + 𝑃𝑟 → 𝜂 % =𝑃𝑜𝑢𝑡

𝑃𝑜𝑢𝑡 + 𝑃𝐿𝑜𝑠𝑠⋅ 100% ≥ 85% 1.

1.1 𝑃𝑐 =1

2𝑉𝐷𝐷

2 ⋅ 𝑓𝑆𝑊 ⋅ 𝐶𝑆𝑊

=1

2𝑉𝐷𝐷

2 ⋅ 𝑓𝑆𝑊 ⋅ 2 𝑪𝒑 ⋅ 𝑇−𝑖

𝑁−1

𝑖=0

=1

2𝑉𝐷𝐷

2 ⋅ 𝑓𝑆𝑊 ⋅ 2 (𝑘1 + 𝑘2)𝒘𝒑 ⋅ 𝑇−𝑖

𝑁−1

𝑖=0

,where k1 and k2 are parasitic capacitance of Gate-Source and

Drain-Source in adjacent stages of gate driver chains.

minimization

2015/2/11


134

Cg,pi

Cg,ni

Cdb,pi

Cdb,ni

stage i stage i+1 stage i-1

k1 ∙ wp k2 ∙ wp


T T

2015/2/11


135

𝑘1 = 2 1 +1

𝛼𝑪𝒐𝒙𝐿 + 𝐶𝐺𝐷𝑂 + 𝐶𝐺𝑆𝑂

𝑘2 = 2 𝐶𝐽𝑃 +𝐶𝐽𝑁

𝛼𝑳𝑫𝑺 + 1 +

1

𝛼𝐶𝐺𝐷𝑂 + 2𝐶𝐽𝑆𝑊

2015/2/11


136


Full- (H-) bridge power inverters

𝑃𝑜𝑢𝑡 = 𝑖𝑜𝑢𝑡2 ⋅ 𝑅𝐿

𝑃𝑟= 𝑖𝑜𝑢𝑡2 ⋅ 2𝑟𝑜𝑛

𝑉𝑝𝑤𝑚+ 𝑉𝑝𝑤𝑚−

k4 / wp

k3 / wp

k3 / wp

4𝑘3 + 2𝑘4

𝒘𝒑 =

2015/2/11


137

1.2 𝑃𝑟 =1

𝑇𝑆 𝑖𝑜𝑢𝑡

2(𝑡) ⋅ 2𝒓𝒐𝒏𝑑𝑡

𝑇𝑆

0

≈1

2(𝐼𝑂𝑈𝑇 ⋅ 𝐷)2⋅ 2𝑟𝑜𝑛

𝑠𝑖𝑛𝑒

=1

2(

𝑉𝐷𝐷

𝑅𝐿 + 2𝑟𝑜𝑛⋅ 𝐷)2⋅ 2𝑟𝑜𝑛

≈1

2(𝑉𝐷𝐷

𝑅𝐿⋅ 𝐷)2⋅ 2𝒓𝒐𝒏

=1

2(𝑉𝐷𝐷

𝑅𝐿⋅ 𝐷)2⋅ 2

4𝑘3 + 2𝑘4

𝒘𝒑

,where k3 and k4 are contact resistances of Drain-Source diffusion

and on-resistance of power transistors.

→ 𝑅𝐿≫ 2𝑟𝑜𝑛


2015/2/11


138

𝑘3,𝑝 = 𝑙1 + 2𝑙3 𝑅𝑝 + 2 𝑙1 + 𝑙2 𝑅𝑐𝑡𝑝

𝑘4 =𝐿

𝜇𝑝𝐶𝑜𝑥 𝑉𝐷𝐷 − 𝑉𝑡ℎ

𝑘3,𝑛 = 𝑙1 + 2𝑙3 𝑅𝑛 + 2 𝑙1 + 𝑙2 𝑅𝑐𝑡𝑛

: Contact resistances

of Drain-Source diffusion

: On-resistance of power transistors

2015/2/11


139

⇒ 𝑃𝐿𝑜𝑠𝑠 =1

2𝑉𝐷𝐷

2 ⋅ 𝑓𝑆𝑊 ⋅ 2 (𝑘1 + 𝑘2)𝒘𝒑 ⋅ 𝑇−𝑖

𝑁−1

𝑖=0

+

1

2(𝑉𝐷𝐷

𝑅𝐿⋅ 𝐷)2⋅ 2

4𝑘3 + 2𝑘4

𝒘𝒑

⇒𝜕𝑃𝐿𝑜𝑠𝑠

𝜕𝑤𝑝=

1

2𝑉𝐷𝐷

2 ⋅ 𝑓𝑆𝑊 ⋅ 2 (𝑘1 + 𝑘2) ⋅ 𝑇−𝑖

𝑁−1

𝑖=0

+

1

2(𝑉𝐷𝐷

𝑅𝐿⋅ 𝐷)2⋅ 2

0 ⋅ 𝑤𝑝 − 4𝑘3 + 2𝑘4 ⋅ 1

𝒘𝒑2

= 0


𝑷𝑫,𝑮𝑫

𝑷𝑺,𝑻𝒓

2015/2/11


140

⇒ 𝑤𝑝 = 𝐷 ⋅4𝑘3 + 2𝑘4 /𝑅𝐿

2

𝑓𝑆𝑊 ⋅ 𝑘1 + 𝑘2 ⋅ 𝑇−𝑖𝑁−1𝑖=0

= 𝐷 ⋅𝐹1

𝐹2

The optimal design of driving capability wp of power stages

is proportional to current delivery by modulation index D.

The wp should be optimized to fit every D for minimal

average power loss and higher power efficiency

over a wide range of power demand!


2015/2/11


141

Surface plot of total power loss

2015/2/11


142 5

10

15

15

20

20

25

25

25

30

30

30

30

35

35

35

3535

40

40

40

40

40

45

45

45

45

4545

50

50

50

50

50

5050

55

55

55

55

55

55

55

60

60

60

6060

60

60

60

65

65

65

6565

65

65

65

70

70

70

7070

70

70

70

75

75

75

75

75

80

80

80

85

85

90

90

95

95

100

100

105

105

110

110

115

115

120

120

125

125

130

130135140145 150

155160165170

175180 185190195200205210

Modulation Index (D)

wp

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

200

400

600

800

1000

1200

1400

Contour plot of total power loss 1/2

(0.9, 550)

(0.8, 490)

(0.7, 430)

(0.6, 370)

(0.5, 310)

(0.4, 250)

(0.3, 190)

(0.2, 130)

(0.1, 70)

2015/2/11


143 5

10

15

15

20

20

25

25

25

30

30

30

30

35

35

35

3535

40

40

40

40

40

45

45

45

45

4545

50

50

50

50

50

5050

55

55

55

55

55

55

55

60

60

60

6060

60

60

60

65

65

65

6565

65

65

65

70

70

70

7070

70

70

70

75

75

75

75

75

80

80

80

85

85

90

90

95

95

100

100

105

105

110

110

115

115

120

120

125

125

130

130135140145 150

155160165170

175180 185190195200205210

Modulation Index (D)

wp

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

200

400

600

800

1000

1200

1400

Contour plot of total power loss 2/2

Pc↑

Pr↑

2015/2/11


144

The power stage of amplifier is segmented into several small

stages and selectively enabled according to the optimal designs

respecting to different modulation indexes (i.e. power demands).

The driving capability of power stage is dynamically adjusted to

minimize the power loss and improve the power efficiency,

especially for small modulation index.

Control of efficient power stages

Dynamic Adjustment Unit

𝑉𝑀𝐿𝑆𝐺(𝑡) PWM

modulator Vc(t)

Vs(t)

LC

filter

proposed MLSG

Segmented

Power Inverters

𝑉𝑃𝑊𝑀(𝑡)

Segmented

Gate Drivers

Chun-Wei Lin, Bing-Shiun Hsieh, “Dynamic power efficiency improvement for PWM class-D amplifier,”

IEICE Electron. Express Letter (ELEX), vol. 10, no. 6, 2013.

2015/2/11


145

Control of segmented power stages 1/2

Up-PMOS

Up-NMOS

Dn-PMOS

Dn-NMOS


Thermometer

decoder

𝑽𝑴𝑳𝑺𝑮′(𝒕)

𝑑𝑒(𝑡)

𝒕𝒄𝒉


1100

0111


For VMLSG’(t) varies between 11 and 12, means large duty ratio of

PWM signal and great power demand from input signal.

The 6 segmented gate drivers and power inverters are all on duty.

2015/2/11


146

Control of segmented power stages 2/2

If 1≤VMLSG(t)≤(M+1)/2, VMLSG’=i, for VMLSG (t) varies between i and i+1

If (M+1)/2 ≤VMLSG (t)≤M, VMLSG’=i+1, for VMLSG (t) varies between i and i+1

1100

1011

0001

0000

1100

…..

0000

Up-PMOS

Up-NMOS

Dn-PMOS

Dn-NMOS


Thermometer

decoder


𝑑𝑒(𝑡)

𝑽𝑴𝑳𝑺𝑮(𝒕) 𝑽𝑴𝑳𝑺𝑮′(𝒕)

2015/2/11


147

Transient Response

I o,max I o,min

Vsig

Ven5

Ven4

Ven3

Ven2

Ven1

Vpwm

Vout

I o,max

2015/2/11


148

Total Power Loss Reduction

0

10

20

30

40

50

0.0 0.2 0.4 0.6 0.8 1.0

I. Proposed method II. D = 0.9 III. [36]

Modulation Index, D

To

tal

po

wer

loss

(m

W)

Pavg = 23mW 28 mW 24.5 mW

2015/2/11


149

Power Efficiency Enhancement

0

20

40

60

80

100

0.0 0.2 0.4 0.6 0.8 1.0

I. Proposed method II. D = 0.9 III. [36]

Modulation Index, D

Po

wer

Eff

icie

ncy

(%

)

0.26 0.16

0

10

20

30

0.0 0.1 0.2 0.3 0.4 0.5

Diff1 = I - II Diff2 = I - III

Modulation Index, D

Pow

er E

ffic

ien

cy (

%)

27

13

13.5%

2015/2/11


150

0.01

0.1

1

10

TH

D (

%)

Output power (mW)

500 750 1000 1250

Proposed method + 1st feedback compensation

Conventional optimization of D=0.9

THD comparison

∆𝒓𝒐𝒏↑

2015/2/11


151

Outline







Conclusions

2015/2/11


152

• Applications: Display backlight, indoor lighting, home theater…

• Techniques: I. linear and II. PWM dimming

• I. linear: simple structure, continuous-time control,

but its bad linearity results in “Hue shift”.

• II. PWM: precise adjustment of illuminations,

switching control,

but faster switching

increases PD & reduces

the life of LED devices.

• III. Continuous-time PWM dimming:

8-bits PWM control.

Voltage

Supply

Current

regulator

ILED

LED dimming techniques

I. Linear dimming

II. PWM dimming

2015/2/11


153

Driving

buffer

𝑉𝑠𝑖𝑛

ILED

• ΔILED is determined by ∆(VGS – VTn)

ILED is dimmable with Vsin (assume from light sensor)

• offset effect of current regulator and driving buffer

brings variation on bias current of LED

leads in “Hue shift (色相偏移)”.

“Color temperature (色溫)” v.s.“Hue”.

∆𝑉𝐺𝑆

+𝑉𝐷𝐷

−𝑉𝐷𝐷

I. Linear LED dimming technique 1/4

Amp.

Voltage

Supply

2015/2/11


154

“Color Temperature” v.s. “Hue” 1/2

2015/2/11


155

“Color Temperature” v.s. “Hue” 2/2

10°

11°

2015/2/11


156

1 1.5 2 2.5 3 3.5 40

2

4

6

8

10

V DIM

(V)

I L

ED

(m

A)

0.85 4.25


2015/2/11


157

I. Linear LED dimming technique – 8bits 3/4

1 1.5 2 2.5 3 3.5 4-1

-0.5

0

0.5

1

DN

L

(LS

B)

1 1.5 2 2.5 3 3.5 4-10

-5

0

5

10

V DIM

(V)

INL

(L

SB

)

0.85 4.25

8.2

2015/2/11


158


1 1.5 2 2.5 3 3.5 40

5

10

15

20

25

30

Po

wer

(m

W)

1 1.5 2 2.5 3 3.5 40

10

20

30

40

50

60

70

80

90

100

V DIM

(V)

Po

wer

Eff

icie

ncy

(%

)

Pavg of LED

Pavg of current regulation

0.85 4.25

2015/2/11


159

• Current regulator is switched on or off.

• TS ≥ 1/24s ~ 1/16s for “Persistence of Vision(視覺暫留)”

• Luminous intensity can be changed

by adjusting the duration of ton

(ILED is constant!)

• Precise control of luminous

intensity than linear

dimming control

• Large switching loss may

reduce the power efficiency

& life of LED devices.

Voltage

Supply

ILED

𝑽𝒔𝒊𝒏 +

– 𝑽𝒕𝒓𝒊

PWM modulator

𝑇𝑆

𝑡𝑜𝑛

𝑪𝒔𝒘

II. PWM LED dimming technique 1/4

2015/2/11


160

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

2

4

6

8

10

V DIM

(D : duty ratio, %)

I L

ED

(m

A)

(100%)(80%)(40%) (60%)(20%)(0%)


2015/2/11


161


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

5

10

15

20

25

30

35

40

Po

wer

(m

W)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

10

20

30

40

50

60

70

80

90

100

V DIM

(D: duty ratio, %)

Po

wer

Eff

icie

ncy

(%

)

Pavg of LED

Pavg of current regulator

(40%) (60%) (80%) (100%)(20%)(0%)

ILED = C

2015/2/11


162


* fPWM = 1kHz fPWM ≥ 200Hz

2015/2/11


163

PWM signal

Binary-weighted

current regulation

Proposed dimming

scheme

𝒘:𝟐𝟎 𝒘:𝟐𝟏 𝒘:𝟐𝒏−𝟏

III. Continuous-time LED dimming 1/12

4-bits

8-bits Digital

Filter

ILED ≠ C

1-bit Voltage

Supply

Chun-Wei Lin, Bing-Shiun Hsieh, Ying-Xu Tsai, “A continuous-time LED dimming technique,” IEICE

Electron. Express Letter (ELEX), vol. 10, no. 4, 2013.

Multilevel

Signal

Generator

(MLSG)

2015/2/11


164


Multilevel:

M levels

Interpolation:

n levels

𝑡𝑟

𝑇𝑆

𝑡𝑝

Ramp signal

rts

KsH

2

210

)(

• Transfer function of 1st order digital filter

• In discrete domain, ptzs /)1(

rp tt

z

KzH

2

210

)1()(

• If tr = 30ms, M = 12, n = 15 ( 180 levels)

4

1

1

1

1

1

1

0625.01

21047.01)(

i

i

z

Kzz

Kz

z

KzzH

, the multiplication can be implemented

by a simple right shift register.

2015/2/11


165


Subtractor Add/Sub

Delay

Shift

Register

Complement

Turn to

Binary

MSB

LSB

TDA Signal

8bits output

8bits 4bits

𝟏

𝟏 = 𝟎. 𝟎 𝟐

4

1

1

0625.01][

][)(

iz

Kz

nX

nYzH

z -1 X [n] Y [n] = a∙Y[n-1] + X[n]

-0.0625

integration

I II

2015/2/11


166


Multilevel

Signal

Generator

output

filter output

2015/2/11


167

FP

GA

8 p

ow

er

MO

S

mo

un

ted

on

PC

B

Proposed

MLSG

PWM signal from

Agilent 81110A (FPAA)

binary-weighted

current regulation

𝒘:𝟐𝟎 𝒘:𝟐𝟏 𝒘:𝟐𝟕

Digital

Filter

ILED

2015/2/11


168

0 100 200 3000

2

4

6

8

10

Time (ms)

I L

ED

(m

A)


2015/2/11


169

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

2

4

6

8

10

V DIM

(D : duty ratio, %)

I L

ED

(m

A)

(100%)(80%)(40%) (60%)(20%)(0%)


2015/2/11


170

III. Continuous-time LED dimming – 8-bits 9/12

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

DN

L

(LS

B)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

V DIM

(V)

INL

(L

SB

)

2.2

2015/2/11


171

III. Continuous-time LED dimming – 8-bits 10/12

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1D

NL

(L

SB

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-10

-8

-6

-4

-2

0

2

4

6

8

10

V DIM

(V)

INL

(L

SB

) Proposed method

Linear dimming

2.2

8.2

2015/2/11


172

1 1.5 2 2.5 3 3.5 40

2

4

6

8

10

V DIM

(V)

I E

RR

(%

)

0.01%

4.250.85

proposed Proposed LED dimming

Linear LED dimming


2015/2/11


173


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

5

10

15

20

25

30

35

Po

wer

(m

W)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

10

20

30

40

50

60

70

80

90

100

V DIM

(D: duty ratio, %)

Po

wer

Eff

icie

ncy

(%

)

Pavg of LED

Pavg of current regulator

(40%) (60%)(0%) (20%) (80%) (100%)

2015/2/11


174

Outline

Motivation & background






Conclusions

2015/2/11


175

Conclusions 1/4

The features of proposed multilevel class-D audio

amplifier

filterless

reduce distortion & noise

improve electromagnetic interference (EMI)

keep high power efficiency

2015/2/11


176

Conclusions 2/4

The features of proposed integrated protections for

multilevel audio amplifier

reduce excessive power consumption

prevent overheated damage (chip & PCB)

without shutting amplifier down

or involving in large signal distortion

2015/2/11


177

Conclusions 3/4

The features of proposed efficient class-D amplifier

power stages

less power consumption

higher power efficiency over a wide range of modulation

index (i.e. power demand)

without using complex package or extra heat-sink

2015/2/11


178

Conclusions 4/4

The features of proposed LED dimming controller

linear luminous intensity adjustment

luminous efficiency enhancement

extend the life of LED devices

class-d audio power amplifier - msic d&t...

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