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Clockless LogicClockless Logic oror

How do I make hardware fast, How do I make hardware fast, power-efficient, less noisy, and easy-power-efficient, less noisy, and easy-

to-design?to-design?

Montek SinghMontek SinghTue, Jan 14, 2003Tue, Jan 14, 2003

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Course Information (1)Course Information (1)Course Number: COMP290-084Course Number: COMP290-084Time and PlaceTime and Place

Tue/Thu 3:30-4:45pm, Sitterson Hall 325Tue/Thu 3:30-4:45pm, Sitterson Hall 325InstructorInstructor

Montek SinghMontek Singh montek@cs.unc.edumontek@cs.unc.edu (not singh@cs!)(not singh@cs!) SN 245, 962-1832SN 245, 962-1832 Office hours: most afternoons/by appointmentOffice hours: most afternoons/by appointment

Teaching AssistantTeaching Assistant NoneNone

Course Web PageCourse Web Page http://www.cs.unc.edu/~montekhttp://www.cs.unc.edu/~montek

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Course Information (2)Course Information (2)Prerequisites:Prerequisites:

undergraduate knowledge of: digital logic, undergraduate knowledge of: digital logic, algorithms, discrete math (sets and graphs)algorithms, discrete math (sets and graphs)

no knowledge of advanced circuit design or of VLSI is no knowledge of advanced circuit design or of VLSI is assumedassumed relevant topics will be covered in class as neededrelevant topics will be covered in class as needed

you are assumed to know the following topics:you are assumed to know the following topics:digital logic: Boolean algebra, logic gates, and latches and digital logic: Boolean algebra, logic gates, and latches and

registersregistersalgorithms: search techniques, enumeration, divide and algorithms: search techniques, enumeration, divide and

conquer, and time complexityconquer, and time complexitydiscrete math: elementary set theory and graph theorydiscrete math: elementary set theory and graph theory

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Course Information (3)Course Information (3)Reading Material:Reading Material:

Papers and technical reports supplied by instructorPapers and technical reports supplied by instructorCourse Content:Course Content:

The following topics will be covered:The following topics will be covered: Introduction to clockless logicIntroduction to clockless logicGraphical representation of asynchronous systemsGraphical representation of asynchronous systemsAlgorithms for logic synthesisAlgorithms for logic synthesis

– CombinationalCombinational– SequentialSequential

Design techniquesDesign techniques– High-performanceHigh-performance– Low-powerLow-power

Formal methods (performance analysis and verification)Formal methods (performance analysis and verification)Case studies of real-world asynchronous processorsCase studies of real-world asynchronous processors

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Course Information (4)Course Information (4)GradingGrading

30% homework assignments30% homework assignments 35% class project35% class project

your choice of topic: from pure algorithms to VLSI designyour choice of topic: from pure algorithms to VLSI design 30% exams 30% exams 5% class participation5% class participation

Honor Code is in effectHonor Code is in effect encouraged to discuss ideas/conceptsencouraged to discuss ideas/concepts work handed in must be your ownwork handed in must be your own

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Lecture 1: IntroductionLecture 1: Introduction

What is asynchronous design?What is asynchronous design? Why do we want to study it?Why do we want to study it? How is data represented in an asynchronous How is data represented in an asynchronous system?system? How is information exchanged?How is information exchanged?

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Introduction: Clocked Digital Introduction: Clocked Digital DesignDesignMost current digital systems are Most current digital systems are synchronous:synchronous:

Clock:Clock: a global signal that paces operation of all a global signal that paces operation of all componentscomponents

clockclockBenefit of clocking: Benefit of clocking: enables discrete-time enables discrete-time

representationrepresentation all components operate exactly once per clock all components operate exactly once per clock

ticktick component outputs need to be ready by next component outputs need to be ready by next

clock tickclock tickallows “glitchy” or incorrect outputs between clock ticksallows “glitchy” or incorrect outputs between clock ticks

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Microelectronics TrendsMicroelectronics TrendsCurrent and Future Trends: Current and Future Trends: Significant Significant

ChallengesChallenges Large-Scale “Systems-on-a-Chip” (SoC)Large-Scale “Systems-on-a-Chip” (SoC)

100 Million ~ 1 Billion transistors/chip100 Million ~ 1 Billion transistors/chip Very High SpeedsVery High Speeds

multiple GigaHertz clock ratesmultiple GigaHertz clock rates

Explosive Growth in Consumer ElectronicsExplosive Growth in Consumer Electronicsdemand for ever-increasing functionality …demand for ever-increasing functionality …… … with very low power consumption (limited battery life)with very low power consumption (limited battery life)

Higher Portability/Modularity/ReusabilityHigher Portability/Modularity/Reusability““plug ’n play” components, robust interfacesplug ’n play” components, robust interfaces

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Challenges to Clocked DesignChallenges to Clocked DesignBreakdown of Single-Clock Paradigm:Breakdown of Single-Clock Paradigm:

Chip will be partitioned intoChip will be partitioned into multiple timing domainsmultiple timing domainschallenge: gluing together multiple timing domainschallenge: gluing together multiple timing domains

– glue logic is susceptible to “metastability” (=incorrect values glue logic is susceptible to “metastability” (=incorrect values transferred) and latency overheadstransferred) and latency overheads

Increasing Difficulties with Clocked Design:Increasing Difficulties with Clocked Design: Clock distribution: requires Clock distribution: requires significantsignificant designer effort designer effort Performance bottleneck: a single slow componentPerformance bottleneck: a single slow component Clock burns large fraction of chip power (~40-70%)Clock burns large fraction of chip power (~40-70%) Fixed clock rate: poor match forFixed clock rate: poor match for

designing designing reusable componentsreusable components interfacing with interfacing with mixed-timing environmentsmixed-timing environments

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What is Asynchronous Design?What is Asynchronous Design? Digital design with Digital design with no centralized clockno centralized clock Synchronization using local Synchronization using local “handshaking”“handshaking”

Asynchronous SystemAsynchronous System(Distributed Control)(Distributed Control)

handshakinghandshakinginterfaceinterface

Synchronous SystemSynchronous System(Centralized Control)(Centralized Control)

clockclock

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Why Asynchronous Design? (1)Why Asynchronous Design? (1) Higher PerformanceHigher Performance

May obtain “average-case” operation (not “worst-case”)May obtain “average-case” operation (not “worst-case”)not limited by slowest componentnot limited by slowest component

Avoids overheads of multi-GHz clock distributionAvoids overheads of multi-GHz clock distribution Lower PowerLower Power

No clock power expendedNo clock power expended Inactive components consume negligible powerInactive components consume negligible power

Better Electromagnetic CompatibilityBetter Electromagnetic Compatibility Smooth radiation spectra: Smooth radiation spectra: no clock spikesno clock spikes Much less interference with sensitive receivers Much less interference with sensitive receivers [e.g., [e.g.,

Philips pagers, smartcards]Philips pagers, smartcards] Greater Flexibility/ModularityGreater Flexibility/Modularity

Naturally adapt to variable-speed environmentsNaturally adapt to variable-speed environments Supports reusable componentsSupports reusable components

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Why Asynchronous Design? (2)Why Asynchronous Design? (2) The world already is mostly asynchronous!The world already is mostly asynchronous!

Events at the level of (or in between) large-scale systems are Events at the level of (or in between) large-scale systems are asynchronousasynchronous several seconds to several millisecondsseveral seconds to several milliseconds e.g., PC-printer communication, keyboard inputs, network comm.e.g., PC-printer communication, keyboard inputs, network comm.

Events at the board level (or between chips) are often Events at the board level (or between chips) are often asynchronousasynchronous milliseconds to 100 nanosecondsmilliseconds to 100 nanoseconds e.g., CPU-memory interface, interface with I/O subsystem (interrupts)e.g., CPU-memory interface, interface with I/O subsystem (interrupts)

Events within a chip, at the level of functional units (e.g., Events within a chip, at the level of functional units (e.g., adders, control logic) are currently synchronousadders, control logic) are currently synchronous several nanoseconds to 100 picosecondsseveral nanoseconds to 100 picoseconds

Events at the level of a single logic gate are asynchronousEvents at the level of a single logic gate are asynchronous 10 picoseconds10 picoseconds

Events at the quantum level are asynchronousEvents at the quantum level are asynchronous picoseconds to femtosecondspicoseconds to femtoseconds

So, why bother with clocks at all?!So, why bother with clocks at all?! make everything asynchronous make everything asynchronous greater elegance and greater elegance and

robustnessrobustness

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Challenges of Asynchronous Challenges of Asynchronous DesignDesign

communication must be hazard-free!communication must be hazard-free! special design challenge =special design challenge = “hazard-free synthesis”“hazard-free synthesis”

Testability Issues:Testability Issues: absence of clock means no “single-stepping”absence of clock means no “single-stepping”

Lack of Commercial CAD Tools:Lack of Commercial CAD Tools: chicken-and-egg problemchicken-and-egg problem

Hazards: Hazards: potential “glitches” on wirepotential “glitches” on wire

clean signalsclean signals

hazardous signals

clockclock tick tick

no problemno problemfor for clockclockededsystemssystems

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Asynchronous Design: Past & Asynchronous Design: Past & PresentPresentAsync Design: Async Design: In existence for 50 years, but … In existence for 50 years, but … … … many recent technical advances:many recent technical advances:

Hazard-Free Circuit Design:Hazard-Free Circuit Design:several practical techniques for controllers several practical techniques for controllers

[Stanford/Columbia][Stanford/Columbia] Design for Testability:Design for Testability:

several test solutions, e.g. Philips Researchseveral test solutions, e.g. Philips Research Maturing Computer-Aided-Design (“CAD”) Tools:Maturing Computer-Aided-Design (“CAD”) Tools:

software tools for automated design software tools for automated design [Philips,Columbia,Manchester][Philips,Columbia,Manchester]

Successful Fabricated Chips:Successful Fabricated Chips:embedded processors, high-speed pipelines, consumer embedded processors, high-speed pipelines, consumer

electronics…electronics…

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Recent Commercial InterestRecent Commercial InterestSeveral commercial asynchronous chips:Several commercial asynchronous chips:

Philips: Philips: asynchronous 80c51 microcontrollersasynchronous 80c51 microcontrollersused in commercial pagers [1998] and smartcards [2001]used in commercial pagers [1998] and smartcards [2001]

Univ. of Manchester: Univ. of Manchester: async ARM processor [2000]async ARM processor [2000] Motorola: Motorola: async divider in PowerPC chip [2000]async divider in PowerPC chip [2000] HAL: HAL: async floating-point dividerasync floating-point divider

in HAL-I and II processors [early 1990’s]in HAL-I and II processors [early 1990’s]

Recent experimental chips:Recent experimental chips: IBM, Sun and Intel:IBM, Sun and Intel:

fast pipelines, arbiters, instruction-length decoder…fast pipelines, arbiters, instruction-length decoder… IBM/Columbia/UNC: IBM/Columbia/UNC: asynchronous digital FIR filterasynchronous digital FIR filter

Several recent startups:Several recent startups: Theseus Logic, Fulcrum, Self-Timed Solutions…Theseus Logic, Fulcrum, Self-Timed Solutions…

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A 5-minute Homework ProblemA 5-minute Homework ProblemAliceAlice and and BobBob live on opposite sides of a wide river: live on opposite sides of a wide river:

AliceAlice is supposed to send a message (say, a “Yes”/”No”) is supposed to send a message (say, a “Yes”/”No”) across to across to Bob Bob around midnight. Both have flashlights, around midnight. Both have flashlights, but neither owns a watch. What should they do?but neither owns a watch. What should they do?

Suggest several strategies, and discuss pros and cons of Suggest several strategies, and discuss pros and cons of each.each.

AliceAlice

BobBob

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got itgot it

Solution 1Solution 1AliceAlice uses 2 lamps:uses 2 lamps:

1 to indicate that she is ready with the message, and1 to indicate that she is ready with the message, and 1 for the message itself1 for the message itself

BobBob uses 1 lamp:uses 1 lamp: to indicate that he has received the messageto indicate that he has received the message

AliceAlice

BobBobreadyready

yes/noyes/no

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Solution 2Solution 2AliceAlice uses 2 lamps:uses 2 lamps:

GreenGreen lamp to indicate “yes” lamp to indicate “yes” Red Red lamp to indicate “no”lamp to indicate “no”

BobBob uses 1 lamp:uses 1 lamp: to indicate that he has received the messageto indicate that he has received the message

got itgot it

AliceAlice

BobBobnono

yesyes

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Solution 3Solution 3What if Alice and Bob could keep time?What if Alice and Bob could keep time?

AliceAlice uses 1 lamp uses 1 lamp for the message:for the message: At 12 midnight: turns on lamp At 12 midnight: turns on lamp if message = “yes”if message = “yes” At 12:01: turns lamp offAt 12:01: turns lamp off

BobBob needs no lamps!needs no lamps! Takes down the message between 12 and 12:01Takes down the message between 12 and 12:01

Pros:Pros: Fewer signals, lesser processing needed Fewer signals, lesser processing neededCons:Cons: Alice and Bob must keep their clocks closely Alice and Bob must keep their clocks closely

synchronizedsynchronized If Bob’s watch is off by a minute, incorrect communication If Bob’s watch is off by a minute, incorrect communication

possiblepossible

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Data Representation Styles: “Bundled Data Representation Styles: “Bundled Data”Data”Single-rail “Bundled Datapath”: Single-rail “Bundled Datapath”: simplest approach simplest approach

widely usedwidely usedFeatures:Features:

datapath: datapath: 1 wire per bit (e.g. standard sync blocks)1 wire per bit (e.g. standard sync blocks) matched delay: matched delay: produces delayed produces delayed “done”“done” signal signal

worst-case delay: longer than slowest pathworst-case delay: longer than slowest path

+ Practical style: can reuse sync componentsPractical style: can reuse sync components; ; small areasmall area

– Fixed (worst-case) completion timeFixed (worst-case) completion time

donedone indicatesindicates valid datavalid data

bit 1bit 1

requestrequest

bit nbit n

bit 1bit 1

bit mbit m

donedonematchedmatcheddelaydelay

functionfunctionblockblock

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+provides provides robustrobust data-dependent completion data-dependent completion– needs completion detectorsneeds completion detectors

Data Representation Styles: Data Representation Styles: Dual-RailDual-Rail Dual-rail: Dual-rail: uses 2 wires per data bituses 2 wires per data bit

Dual-rail code

Meaning

00 “reset” value 01 0 value 10 1 value 11 unused

bit nbit n

bit 1bit 1

bit mbit m

bit 1bit 1

Each Dual-Rail Pair:Each Dual-Rail Pair: provides both provides both data valuedata value and and validityvalidity

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Dual-Rail (contd.)Dual-Rail (contd.)Dual-Rail Completion Detector:Dual-Rail Completion Detector:

combines dual-rail signalscombines dual-rail signals indicates when all bits are valid (or reset)indicates when all bits are valid (or reset)

CC DoneDoneORORbitbit00

ORORbitbit11

ORORbitbitnn

OROR together 2 rails per bit together 2 rails per bit Merge results using a Müller Merge results using a Müller “C-element”“C-element”

C-element:C-element:if all inputs=1, output if all inputs=1, output 1 1if all inputs=0, output if all inputs=0, output 0 0else, maintain output valueelse, maintain output value

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4-Phase: 4-Phase: requires 4 events per handshakerequires 4 events per handshakeHandshaking Styles: Handshaking Styles: 4-phase4-phase

RequestRequest

AcknowledgeAcknowledge

startevent

eventdone

get ready fornext event

ready fornext event

+ ““Level-sensitive”Level-sensitive” simpler logic simpler logic implementationimplementation

– Overhead of Overhead of “return-to-zero”“return-to-zero” (RTZ or (RTZ or resetting)resetting) extra events which do no useful computationextra events which do no useful computation

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+ Elegant: Elegant: no return-to-zerono return-to-zero– Slower logic implementation:Slower logic implementation:

logic primitives are inherently level-sensitive, not event-logic primitives are inherently level-sensitive, not event-based (at least in CMOS)based (at least in CMOS)

Handshaking Styles: Handshaking Styles: 2-phase2-phase2-Phase: 2-Phase: requires 2 events per handshakerequires 2 events per handshake

RequestRequest

AcknowledgeAcknowledge

startevent

eventdone

start nextevent

next eventdone

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Handshaking + Data Handshaking + Data RepresentationRepresentationSeveral combinations possible:Several combinations possible:

dual-rail 4-phase, single-rail 4-phase, dual-rail 2-phase, and dual-rail 4-phase, single-rail 4-phase, dual-rail 2-phase, and single-rail 2-phasesingle-rail 2-phase

Example:Example: dual-rail 4-phase dual-rail 4-phase

dual-rail data: dual-rail data: functions as anfunctions as an implicit implicit “request”“request” 4-phase cycle: between 4-phase cycle: between acknowledgeacknowledge and and implicit requestimplicit request

bit mbit m

bit 1bit 1

ackackAA BB

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Other Data Representation StylesOther Data Representation Styles Level-Encoded Dual-Rail (LEDR)Level-Encoded Dual-Rail (LEDR)

2 wires per bit: 2 wires per bit: “data”“data” and and “phase”“phase” exactly one wire per bit changes valueexactly one wire per bit changes value

if new value is different, if new value is different, “data”“data” wire changes value wire changes valueelse else “phase”“phase” wire change value wire change value

M-of-N CodesM-of-N Codes N wires used for a data wordN wires used for a data word M wires (M <= N) change valueM wires (M <= N) change value Values of N and M: have impact on…Values of N and M: have impact on…

information transmitted, power consumed and logic information transmitted, power consumed and logic complexitycomplexity

Knuth codes, Huffman codes, …Knuth codes, Huffman codes, …

datadataphasephase

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Which to use?Which to use?Depends on several performance parameters:Depends on several performance parameters:

speedspeedsingle-rail vs. dual-railsingle-rail vs. dual-rail

– single-rail may be faster (if designed aggressively)single-rail may be faster (if designed aggressively)– dual-rail may be faster (if completion times vary widely)dual-rail may be faster (if completion times vary widely)

2-phase vs. 4-phase2-phase vs. 4-phase– 2-phase may be faster (if logic overhead is small)2-phase may be faster (if logic overhead is small)– 4-phase may be faster (if overhead of return-to-zero is small)4-phase may be faster (if overhead of return-to-zero is small)

power consumptionpower consumption2-phase typically has fewer gate transitions (2-phase typically has fewer gate transitions ( lower power) lower power)

amount of logic used (#gates/wires/pins amount of logic used (#gates/wires/pins chip area) chip area)single-rail needs fewer gates/wires/pinssingle-rail needs fewer gates/wires/pins

design and verification effortdesign and verification effortdual-rail, 1-of-N, M-of-N, Knuth codes…:dual-rail, 1-of-N, M-of-N, Knuth codes…:

– delay-insensitive: robust in the presence of arbitrary delaysdelay-insensitive: robust in the presence of arbitrary delayssingle-rail: requires greater timing verification effortsingle-rail: requires greater timing verification effort

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Sutherland’s MicropipelinesSutherland’s Micropipelines

Seminal PaperSeminal Paper

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Focus of Sutherland’s Turing Focus of Sutherland’s Turing Award Lecture: PipeliningAward Lecture: PipeliningMotivation:Motivation: Pipelining is at the heart of nearly allPipelining is at the heart of nearly all high-performance digital systemshigh-performance digital systems

Additional Benefits:Additional Benefits: Low powerLow power Interfacing with mixed systemsInterfacing with mixed systems Modular and scalable designModular and scalable design

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A “coarse-grain” pipeline (e.g. simple processor)A “coarse-grain” pipeline (e.g. simple processor)

A “fine-grain” pipeline (e.g. pipelined adder)A “fine-grain” pipeline (e.g. pipelined adder)

fetchfetch decodedecode executeexecute

Background: PipeliningBackground: PipeliningWhat is Pipelining?: What is Pipelining?: Breaking up a complex Breaking up a complex

operation on a stream of data into simpler operation on a stream of data into simpler sequential operationssequential operations

++ Throughput: Throughput: significantly increasedsignificantly increased–– Latency:Latency: somewhat degradedsomewhat degraded

Storage elementsStorage elements(latches/registers)(latches/registers)

Throughput = #data items Throughput = #data items processed/secondprocessed/second

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Focus of Async CommunityFocus of Async CommunityOur Focus:Our Focus: Extremely fine-grain pipelines Extremely fine-grain pipelines

““gate-level”gate-level” pipelining = use narrowest possible stages pipelining = use narrowest possible stages each stage consists of only a each stage consists of only a single levelsingle level of logic gates of logic gates some of the fastest existing digital pipelines to datesome of the fastest existing digital pipelines to date

Application areas:Application areas: multimedia hardware (graphics accelerators, video DSP’s, multimedia hardware (graphics accelerators, video DSP’s,

…)…)naturally pipelined systems, throughput is criticalnaturally pipelined systems, throughput is critical input is often “bursty”input is often “bursty”

optical networkingoptical networkingserializing/deserializing FIFO’sserializing/deserializing FIFO’s

genomic string matching?genomic string matching?KMP style string matching: KMP style string matching: variablevariable skip lengths skip lengths