cm19 vassil verguilov daq status progress daq next steps summary
DESCRIPTION
CM19 Vassil Verguilov DAQ Status Progress since CM18 DAQ Workshop in RAL –DAQ System requirements –Data unpacking discussed –DATE Tutorial Installation and configuration Implementation of readout code Shaper production in progress in Sofia –First commissioning done in Sofia –Full test started in Geneva Splitter production finished in Geneva New hardware –Spare VME Interface and VME Power Supply –Second Event builder PC –3 LDC PCsTRANSCRIPT
CM19 Vassil Verguilov
DAQ Status
Progress DAQ Next steps Summary
CM19 Vassil Verguilov DAQ Status
Progress since CM18
• DATE readout code completed for the following modules– VME-PCI interface (CAEN V2718)– IO Register (trigger receiver) (CAEN V977)– TDC (CAEN V1290)– Scaler (CAEN V830)
• DAQ test bench completed in Geneva (milestone for Feb. 2007) and RAL– 2PCs (LDCs + GDC, LDC)– 2 Independent VME crates– Private network
• DAQ installation in RAL– 2 VME crates– 2 PCs– 1 Router
CM19 Vassil Verguilov DAQ Status
Progress since CM18
• DAQ Workshop in RAL– DAQ System requirements– Data unpacking discussed– DATE Tutorial
• Installation and configuration• Implementation of readout code
• Shaper production in progress in Sofia– First commissioning done in Sofia– Full test started in Geneva
• Splitter production finished in Geneva• New hardware
– Spare VME Interface and VME Power Supply– Second Event builder PC– 3 LDC PCs
CM19 Vassil Verguilov DAQ Status
Shaper
• Third version of the shaper– DC Gain for the most of the channels is 2.9– Added jumpers to select the desired gain (per channel) - total gain
can be raised to 14.4– Jumper selection between single-ended or differential input– Mechanical support for the splitter– Different channels have different gain and different shapping
constants • Final production ready to start in Sofia, waiting for
precise tests
CM19 Vassil Verguilov DAQ Status
Splitter
• Production completed in Geneva– 4 Layers PCB design– Added shielding
CM19 Vassil Verguilov DAQ Status
General Purpose VME Logic Board
• Started working on CAEN V1495– Implement trigger logic in VHDL
CM19 Vassil Verguilov DAQ Status
Next Steps
• DAQ data unpacking• Readout code for the fADC module• Precise tests of the shaper• Implementing trigger logic in VHDL• Preparation for the cosmic test in November 2007• Preparing for the DAQ review in January 2008
CM19 Vassil Verguilov DAQ Status
Summary
• DAQ is installed and tested in RAL• DAQ test bench is completed• DATE readout code is almost completed• Splitter production completed• Shaper is ready for production, awaiting precise testing