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3-1

3CMOS AmplifierDesign

3.1 Introduction ........................................................................3-1

3.2 Biasing Circuits....................................................................3-7

3.3 Amplifiers...........................................................................3-15

Operational-Amplifier Considerations

3.1 Introduction

This chapter discusses the design, operation, and layout of CMOS analog amplifiers and subcircuits

(current mirrors, biasing circuits, etc.). To make this discussion meaningful and clear, we need to define

simplified schematic representations of n- and p-channel MOSFETs. We say simplified because, when

these symbols are used, it is assumed that the fourth terminal of the MOSFET (i.e., the body connection)

is connected to either the lowest potential on the chip (V SS or ground for the NMOS) or the highest

potential (V DD for the PMOS). Figure 3.1(b) shows the more general schematic representation of n- andp-channel MOSFETs. We are assuming that, although the drain and source of the MOSFETs are inter-

changeable, drain current flows from the top of the device to the bottom. Because of the assumed direction

of current flow, the drain terminal of the n-channel is on the top of the symbol, while the drain terminal

of the p-channel is on the bottom of the schematic symbol. The following are short descriptions of some

important characteristics of MOSFETs that will be useful in the following discussion.

The Threshold Voltage

Loosely defined, the threshold voltage, V THN or V THP , is the minimum gate-to-source voltage (V GS for then-channel or V SG for the p-channel) that causes a current to flow when a voltage is applied between the

drain and source of the MOSFET. As shown in Fig. 3.1(c) the threshold voltage is estimated by plotting

the square root of the drain current against the gate-source voltage of the MOSFET and looking at the

intersection of the line tangent with this plot with the x -axis (V GS for the n-channel). As seen in the

figure, a current does flow below the threshold voltage of the device. This current is termed, for obvious

reasons, the subthreshold current . The subthreshold current is characterized by plotting the log of the

Harry W. LiUniversity of Idaho at Moscow

R. Jacob BakerUniversity of Idaho at Boise

Donald C. Thelen Analog Interfaces

© 2003 by CRC Press LLC

The Threshold Voltage • The Body Effect • The Drain Current • Short-Channel MOSFETs • MOSFET Output Resistance • MOSFET Transconductance • MOSFET Open-

Circuit Voltage Gain • Layout of the MOSFET

The Current Mirror • Simple Current Mirror Biasing

Circuits • The Self-Biased Beta Multiplier Current Reference

The Simple Unbuffered Op-Amp • High-Performance

some important variables related to the DC operation of MOSFETs (Fig. 3.1). Figure 3.1(a) shows the



3-2 Analog Circuits and Devices

drain current against the gate-source voltage. The slope of the curve in the subthreshold region (some-

times also called the weak inversion region) is used to specify how the drain current changes with V GS. A

typical value for the reciprocal of the slope of this curve is 100 mV/dec. An equation relating the drain

current of an n-channel MOSFET operating in the subthreshold region to V GS is (assuming V DS > 100 mV):

FIGURE 3.1 MOSFET device characteristics.




CMOS Amplifier Design 3-3

(3.1)

where W and L are the width and length of the MOSFET, I D0 is a measured constant, k is Boltzmann’s

constant (1.38 ¥ 10–23 J/K), T is temperature in Kelvin, q is the electronic charge (1.609 ¥ 10–23 C), and

N is the slope parameter. Note that the slope of the Log I D vs. V GS curve in the subthreshold region is

(3.2)

The Body Effect

The threshold voltage of a MOSFET is dependent on the potential between the source of the MOSFET

and its body. Consider Fig. 3.2, showing the situation when the body of an n-channel MOSFET isconnected to ground and the source of the MOSFET is held V SB above ground. As V SB is increased (i.e.,

the potential on the source of the MOSFET increases relative to ground), the minimum V GS needed to

cause appreciable current to flow increases (V THN increases as V SB increases). We can relate V THN to V SB

using the body-effect coefficient, g , by

(3.3)

where V THN 0

is the zero-bias threshold voltage when V SB

= 0 and fF

is the surface electrostatic potential1

with a typical value of 300 mV. An important thing to notice here is that the threshold voltage tends to

change less with increasing source-to-substrate (body) potential (increasing V SB).

The Drain Current

In the following discussion, we will assume that the gate-source voltage of a MOSFET is greater than the

threshold voltage so that a reasonably sized drain current can flow (V GS > V THN or V SG > V THP ). If this is

drain current of a long L n-channel MOSFET operating in the triode region, is given by

(3.4)

FIGURE 3.2 Illustration of the threshold voltage dependence on body-effect.

I D I D0

W

L-----

q V GS V TH N –( )kT N ◊

----------------------------------exp◊ ◊=

I DlogDV GS

----------------q elog◊ N kT ◊-----------------=

V TH N V TH N 0 g 2fF V SB+ 2fF –+=

I D b V GS V TH N –( )V DS

V DS2

2--------–=


the case, the MOSFET operates in either the triode region or the saturation region [Fig. 3.1(d)]. The




assuming long L with V DS £ V GS – V THN . Note that the MOSFET behaves like a voltage-controlled resistor

when operating in the deep triode region with a channel resistance (the resistance is measured between

the drain and source of the MOSFET) approximated by

(3.5)

When doing analog design, it is often useful to implement a resistor whose value is dependent on a

controlling voltage (a voltage-controlled resistor). When the NMOS device is operating in the saturation

region, the drain current is given by

(3.6)

assuming long L with V DS ≥ V GS – V THN , where V DS,sat = V GS V THN .The transconductance parameter , b, is given by

(3.7)

where mn,p is the mobility of either the electron or hole and C ox is the oxide capacitance per unit area

[eox/t ox , the dielectric constant of the gate oxide (35.4 aF/µm) divided by the gate oxide thickness]. Typical

values for KP n, KP p, and C ox for a 0.5-µm process are 150 µA/V2, 50 µA/V2, and 4 fF/µm2, respectively.

Also, an important thing to note in these equations for an n-channel MOSFET, is that V GS, V DS, and V THN

can be directly replaced with V SG, V SD, and V THP , respectively, to obtain the operating equations for thep-channel MOSFET (keeping in mind that all quantities under normal conditions for operation are

positive.) Also note that the saturation slope parameter l (also known as the channel length/mobility

modulation parameter) determines how changes in the drain-to-source voltage affect the MOSFET drain

current and thus the MOSFET output resistance.

Short-Channel MOSFETs

As the channel length of a MOSFET is reduced, the electron and hole mobilities, mn and m p, start to get

smaller. The mobility is simply a ratio of the electron or hole velocity to the applied electric field. Reducing

the channel length increases the applied electric field while at the same time causing the velocity of the

electron or hole to saturate (this velocity is labeled v sat ). This effect is called mobility reduction or hot-

carrier effects (because the mobility also decreases with increasing temperature). The result, for a MOSFET

with a short channel length L, is a reduction in drain current and a labeling of short-channel MOSFET .

A short-channel MOSFET’s current is, in general, linearly dependent on the MOSFET V GS or

(3.8)

To avoid short-channel effects (and, as we shall see, increase the output resistance of the MOSFET

when doing analog design), the channel length of the MOSFET is made, generally, 2 to 5 times largerthan the minimum allowable L. For a 0.5-µm CMOS process, this means we make the channel length of

the MOSFETs 1.0 to 2.5 µm.

MOSFET Output Resistance

An important parameter of a MOSFET in analog applications is its output resistance. Consider the

the saturation region, the slope of I D , because of changes in the drain current with changes in the

RCH 1b V GS V TH N –( ) bV DS–

----------------------------------------------------- or 1b V GS V TH N –( )----------------------------------- if V DS V GS V TH N –«=

I D b V GS V TH N –( )21 l V DS V DS sat ,–( )+[ ]=

b KP W

L-----◊ mn p, C ox

W

L-----◊= =

I D W v sa t C ox V GS V TH N – V DS sat ,–( )◊ ◊=


portion of a MOSFET’s I-V characteristics shown in Fig. 3.3(a). When the MOSFET is operating in




drain-source voltage, is relatively small. If this change were zero, the drain current would be a fixed

value independent of the voltage between the drain and source of the MOSFET (in other words, theMOSFET would act like an ideal current source.) Even with the small change in current with V DS, we

can think of the MOSFET as a current source. To model the changes in current with V DS, we can simply

place a resistor across the drain and source of the MOSFET [Fig. 3.3(b)]. The value of this resistor is

(3.9)

where l is in the range of 0.1 to 0.01 V–1.

At this point, several practical comments should be made: (1) in general, to increase l, the channellength is made 2 to 5 times the minimum allowable channel L (this was also necessary to reduce the

short-channel effects discussed above); (2) the value of l is normally determined empirically; trying to

determine l from an equation is, in general, not too useful; (3) the output resistance of a MOSFET is a

function of the MOSFET’s drain current. The exact value of this current is not important when estimating

the output resistance. Whether I D,sat (the drain current at V D,sat ) or the actual operating point current, I D ,

is used is not practically important when determining r o.

MOSFET Transconductance

It is useful to determine how a change in the gate-source voltage changes the drain current of a MOSFEToperating in the saturation region. We can relate the change in drain current, id , to the change in gate-

source voltage, v gs, using the MOSFET transconductance, g m, or

(3.10)

Neglecting the output resistance of a MOSFET, we can write the sum of the DC and AC (or changing)

components of the drain current and gate-source voltage using

(3.11)

If we hold the DC values constant and assume they are large compared to the AC components, then by

simply taking the derivative of iD with respect to v gs, we can determine g m. Doing this results in

(3.12)

FIGURE 3.3 Output resistance of a MOSFET.

r o1

lI D--------ª

g miDD

v GSD---------- idfi g mv gs= =

iD id AC( ) I + D DC( ) b2--- V GS DC( ) v gs AC( ) V TH N –+( )2

= =

g m b V GS V TH N –( ) 2bI D= =





Following this same procedure for the MOSFET operating in the subthreshold region results in

(3.13)

Notice how the change in transconductance is linear with drain current when the device is operating in

the subthreshold region. The larger incremental increase in g m is due to the exponential relationship

between I D and V GS when the device is operating in the weak inversion region (as compared to the square

law relationship when the device is operating in the strong inversion region).

MOSFET Open-Circuit Voltage Gain

At this point, we can ask, “What’s the largest possible voltage gain I can get from a MOSFET under ideal

biasing conditions?” Consider the schematic diagram shown in Fig. 3.4(a) without biasing circuitry shown

and with the effects of finite MOSFET output resistance modeled by an external resistor. The open-circuitvoltage gain can be written as

(3.14)

which increases as the DC drain biasing current is reduced (and the MOSFET intrinsic speed decreases)

until the MOSFET enters the subthreshold region. Once in the subthreshold region, the voltage gain

flattens out and becomes

(3.15)

Layout of the MOSFET

that a p-type substrate is used for the body of the NMOS (the body connection for the n-channel MOSFET

is made through the p+ diffusion on the left in the layout). An n-well is used for the body of the PMOS

devices (the connection to the n-well is made through the n+

diffusion on the right in the layout). Animportant thing to notice from this layout is that the intersection of polysilicon (poly for short) and n+

(in the p-substrate) or p+ (in the n-well) forms a MOSFET. The length and width of the MOSFET, as

seen in Fig. 3.5, is determined by the size of this overlap. Also note that the four metal connections to

the terminals of each MOSFET, in this layout, are floating; that is, not connected to anything but the

FIGURE 3.4 Open-circuit voltage gain (DC biasing not shown).

g mI D q◊kT

------------=

Av ou t

v gs

------- g mr o2bI DlI D

---------------2b

l I D------------ (for normal operation)= = = =

Av

g mr oI D q◊kT

------------1

lI D--------◊ q

l kT ◊-------------- (in the subthreshold region)= = =


Figure 3.5 shows the layout of both n-channel and p-channel devices. In this layout, we are assuming




Notice that we have neglected the finite output resistance of the MOSFETs in this equation. If we

include the effects of finite output resistance, and assume M1 and M2 are sized the same, we see from

Fig. 3.6 that the only time I REF and I OUT are equal is when V GS = V OUT = V DS2.

Design Example

Design a 100-µA current sink and a 200-µA current source assuming that you are designing with a 0.5-

µm CMOS process with KP n = 150 µA/V2, KP p = 50 µA/V2, V THN = 0.8 V, and V THP = 0.9 V. Assume lwas empirically determined (or determined from simulations) to be 0.05 V–1 with L = 2.0 µm. Assume

that an I REF of 50 µA is available for the design. Determine the output resistance of the current source/sinkand the minimum voltage across the current source/sink.

is 300

mV, the width of M1, W 1, is 15 mm (KP n = 150 µA/V2, L = 2 mm). The MOSFET, M1, has a gate-source

voltage 300 mV in excess of the threshold voltage, or, in other words, the MOSFET V GS is 1.1 V. For M2

and M3 to sink 100 mA (twice the current in M1), we simply increase their widths to 30 mm for the same

V GS bias supplied by M1. Note the minimum voltage required across M3, V DS3, in order to keep M3 out

of the triode region (V DS3 V GS - V THN ), is simply the excess gate voltage, , or, for this example,

300 mV. (Note: simply put, 300 mV is the minimum voltage on the drain of M3 required to keep it in

the saturation region.) Increasing the widths of the MOSFETs lowers the minimum voltage required

across the MOSFETs (lowers the excess gate voltage) so they remain in saturation at the price of increasedlayout area. Also, differences in MOSFET threshold voltage become more significant, affecting the match-

ing between devices.

The purpose of M2 should be obvious at this point; it provides a 100-mA bias for the p-channel current

mirror M4/M5. Again, if we set M4’s excess gate voltage to 300 mV (so that the V SG of the p-channel

MOSFET is 1.2 V), the width of M4 can be calculated (assuming that L is 2 mm and KP p = 50 µA/V2)

to be 45 mm (or a factor of 3 times the n-channel width due to the differences in the transconductance

parameters of the MOSFETs). Since the design required a current source of 200 mA, we increase the width

of the p-channel, M5, to 90 mm (so that it mirrors twice the current that flows in M4). The output

resistance of the current source, M5, is 100 kW, while the maximum voltage on the drain of M5 is 3 V(in order to keep M5 in saturation).

Layout of Current Mirrors

In order to get the best matching between devices, we need to lay the MOSFETs out so that differences

(15/2) and M2 (30/2) MOSFETs of Fig. 3.7. Notice how, instead of laying M2 out in a fashion similar to

M1 (i.e., a single poly over active strip), we split M2 into two separate MOSFETs that have the same

shape as M1.

FIGURE 3.6 Basic CMOS current mirror.

2I RE F ( ) b1 §

2I RE F ( ) b1 §


The schematic of the design is shown in Fig. 3.7. If we design so that the term

in the mirrored MOSFETs’ widths and lengths are minimized. Figure 3.8 shows the layout of the M1




with position on the wafer. This may be the result of varying temperature on the top of the wafer during

processing, or fluctuations in implant dose with position. If we lay MOSFETs M2 and M1 out as shownin Fig. 3.9(a) (which is the same way they were laid out in Fig. 3.8), M1 has a “weight” of 1 while M2

has a weight of 5. These numbers may correspond to the threshold voltages of three individual MOSFETs

with numerical values 0.81, 0.82, and 0.83 V. By using the layout shown in Fig. 3.9(b), M1’s or M2’s

average weight is 2. In other words, using the threshold voltages as an example, M1’s threshold voltage

is 0.82 V while the average of M2’s threshold voltage is also 0.82 V. Similar discussions can be made if

the transconductance parameters vary with position. Figure 3.9(c) shows how three devices can be

matched using a common-centroid layout (M2 and M1 are the same size while M3 is 4 times their size.)

A good exercise at this point is to modify the layout of Fig. 3.9(c) so that M2 is twice the size of M1 and

one half the size of M3.The Cascode Current Mirror

We saw that in order to improve the matching between the two currents in the basic current mirror of

of M1 (which is also V GS in Fig. 3.6). This can be accomplished using the cascode connection of MOSFETs

a common-cathode amplifier driving a common-grid amplifier was used to increase the speed and gain

of an overall amplifier design.

FIGURE 3.7 Design example.

FIGURE 3.8 Layout of MOSFET mirror M1/M2 in Fig. 3.7.


The matching between current mirrors can also be improved using a common-centroid layout (Fig.

3.9). Parameters such as the threshold voltage and KP in practice can have a somewhat linear change

Fig. 3.6, we needed to force the drain-source voltage of M2 to be the same as the drain-source voltage

shown in Fig. 3.10. The term “cascode” comes from the days of vacuum tube design where a cascade of




Using the cascode configuration results in higher output resistance and thus better matching. For

the following discussion, we will assume that M1 and M3 are the same size, as are M2 and M4. Again,

remember that M1 and M2 form a current mirror and operate in the same way as previously discussed.

The addition of M3 and M4 helps force the drain-source voltages of M1/M2 to the same value. The

minimum V OUT allowable, in order to keep M4 out of the triode region, across the current mirror

increases to

(3.18)

which is basically an increase of V GS

Here, we assume that the gates of M4 and M2 are at fixed DC potentials (which are set by I REF flowing

through M1/M3). Since the source of M2 is held at ground, we know that the AC component of v gs2 is

0. Therefore, we can replace M2 with a small-signal resistance r o = (1/lI OUT ). To determine the output

resistance of the cascode current mirror, we apply an AC test voltage, v test , and measure the AC test current

that flows into the drain of M4. Ideally, only the DC component will flow through v test . We can write the

AC gate-source voltage of M4 as v gs4 = –itest ·r o. The drain current of M4 is then g m4v gs4 = –itest · g m4r o while

FIGURE 3.9 Common-centroid layout used to improve matching.

FIGURE 3.10 Basic cascode CMOS current mirror.

V OUT min, 22I RE F

b1 3,------------ V TH N +=


over the basic current mirror of Fig. 3.6.

The output resistance of the cascode configuration can be derived with the circuit model of Fig. 3.11.




the current through the small-signal output resistance of M4, r o, is (v test – (–itest r o))/r o. Combining theseequations yields the cascode output resistance of

(3.19)

The cascode current source output resistance is g mr o (the open-circuit voltage gain of a MOSFET) times

larger than r o (the simple current mirror output resistance.) The main drawback of the cascode config-

uration is the increase in the minimum required voltage across the current sink in order for all MOSFETs

to remain in the saturation region of operation.

Low-Voltage Cascode Current Mirror

potential as the drain of M1, that is, VGS or . We know that the voltage on the drain

of M2 can be as low as before it starts to enter the triode region. Knowing this, consider the

wide-swing current mirror shown in Fig. 3.12. Here, “wide-swing” means the minimum voltage across

the current mirror is , the sum of the excess gate voltages of M2 and M4. To understand

the operation of this circuit, assume that M1 through M4 have the same W /L ratio (their bs are all equal).

We know that the V GS of M1 and M2 is . It is desirable to keep M2’s drain

at for wide-swing operation. This means, since M3/M4 are the same size as M1/M2, the gate

voltage of M3/M4 must be or . By sizing M5’s channel width so

FIGURE 3.11 Determining the small-signal output resistance of the cascode current mirror.

FIGURE 3.12 Wide-swing CMOS cascode current mirror.

Rout cascode,v test

itest

-------- r o 1 g mr o+( ) r o g mr 2

oª+= =

2I RE F ( ) b § V TH N +

2I RE F ( ) b §

2 2I RE F ( ) b §

2I RE F ( ) b §

V TH N

+

2I RE F ( ) b § V GS 2I RE F ( ) b § + 2 2I RE F ( ) b § V TH N +


If we look at the cascode current mirror of Fig. 3.10, we see that the drain of M2 is held at the same




that it is one fourth of the size of the other transistor widths and forcing I REF through the diode connected

M5, we can generate this voltage. We should point out that the size (its W /L ratio) of M5 can be further

decreased, say to 1/5, in order to keep M1/M2 from entering the triode region (and the output resistance

from decreasing). The cost is an increase in the minimum allowable voltage across M2/M4, that is, V OUT .

Simple Current Mirror Biasing Circuits

Figure 3.13 shows two simple circuits useful for generating the reference current, I REF , used in the current

mirrors discussed in the previous section. The circuit shown in Fig. 3.13(a) uses a simple resistor with

a gate-drain connected MOSFET to generate a reference current. Note how, by adding MOSFETs mir-

roring the current in M1 or M2, we can generate any multiple of I REF needed. The reference current, of

Fig. 3.13(a), can be determined by solving

(3.20)

Figure 3.13(b) shows a MOSFET-only bias circuit. Since the same current flows in M1 and M2, we

can mirror off of either MOSFET to generate our bias currents. The current flowing in M1/M2 is designed

using

(3.21)

Notice in both equations above that the reference current is a function of the power supply voltage.Fluctuations, as a result of power supply noise, in VDD directly affect the bias currents. In the next

section, we will present a method for generating currents that reduces the currents’ sensitivity to changes

in VDD.

Temperature Dependence of Resistors and MOSFETS

ature coefficient is used to relate the value of a resistor at room temperature, or some known temperature

T 0, to the value at a different temperature. This relationship can be written as

(3.22)

where TCR is the temperature coefficient of the resistor ppm/°C (parts per million, a multiplier of 10–6,

per degree C). Typical values for TCRs for n-well, n+, p+, and poly resistors are 2000, 500, 750, and 100

ppm/°C, respectively.

FIGURE 3.13 Simple biasing circuits.

I RE F

VDD V GS–

R---------------------------

b2---

V GS V TH N –

( )

2= =

I RE F

b1

2----- V GS V TH N –( )2 b2

2----- VDD V GS V – TH N –( )2

= =

R T ( ) R T 0( ) 1 TCR T T 0–( )+[ ]◊=


Figure 3.14 shows how a resistor changes with temperature, assuming a linear dependence. The temper-




Figure 3.15 shows how the drain current of a MOSFET changes with temperature. At low gate-source

voltages, the drain current increases with increasing temperature. This is a result of the threshold voltage

decreasing with increasing temperature which dominates the I-V characteristics of the MOSFET. Thetemperature coefficient of the threshold voltage (NMOS or PMOS), TCV TH , is generally around –3000

ppm/°C. We can relate the threshold voltage to temperature using

(3.23)

At larger gate-source voltages, the drain current decreases with increasing temperature as a result of

the electron or hole mobility decreasing with increasing temperature. In other words, at low gate-source

voltages, the temperature changing the threshold voltage dominates the I-V characteristics of the MOS-

FET; while at larger gate-source voltages, the mobility changing with temperature dominates. Note thatat around 1.8 V, for a typical CMOS process, the drain current does not change with temperature. The

mobility can be related to temperature by

(3.24)

The Self-Biased Beta Multiplier Current Reference

with a gain less than one, to reduce the sensitivity of the reference current to power supply changes.

MOSFET M2 is made K times wider than MOSFET M1 (in other words, b2 = K b1; hence, the name beta

multiplier). We know from this figure that , where

and ; therefore, we can write the current in the circuit as

FIGURE 3.14 Variation of a resistor with temperature.

FIGURE 3.15 Temperature characteristics of a MOSFET.

V TH T ( ) V TH T 0( ) 1 TCV TH T T 0–( )+[ ]=

m T ( ) m T 0( ) T

T 0-----Ë ¯

Ê ˆ 1.5–

=

V GS 1 V GS 2 I RE F R+= V GS 1 2I RE F ( ) b1 § V TH N +=

V GS 2 2I RE F ( ) K b1 § V TH N +=


Figure 3.16 shows the self-biased beta multiplier current reference. This circuit employs positive feedback,




(3.25)

which shows no first-order dependence on the power supply voltage.

Start-up Circuit

One of the drawbacks of using the reference circuit of Fig. 3.16 is that it has two stable operating points

[Fig. 3.17(a)]. The desirable operating point, point A, occurs when the current flowing in the circuit isI REF . The undesirable operating point occurs when zero current flows in the circuit, point B. Because of

the possibility of zero current flowing in the reference, a start-up circuit should always be used when

using the beta multiplier. The purpose of the start-up circuit is to ensure that point B is avoided. When

designed properly, the start-up circuit [Fig. 3.17(b)] does not affect the beta multiplier operation when

I REF is non-zero (M3 is off when operating at point A).

A Comment about Stability

Since the beta multiplier employs positive feedback, it is possible that the circuit can become unstable

and oscillate. However, with the inclusion of the resistor in series with the source of M2, the gain aroundthe loop, from the gate of M2 to the drain/gate of M1, with the loop broken between the gates of M1

and M2, is less than one, keeping the reference stable. Adding a large capacitance across R, however, can

increase the loop gain to the point of instability. This situation could easily occur if R is bonded out to

externally set the current.

FIGURE 3.16 Beta multiplier current reference.

FIGURE 3.17 Start-up circuit for the beta multiplier circuit shown in Fig. 3.16.

I RE F

2

R2b1

----------- 11

K ---–

2

=





3.3 Amplifiers

Now that we have introduced biasing circuits and MOS device characteristics, we will immediately dive into

the design of operational amplifiers. Since space is very limited, we will employ a top-down approach in

which a series of increasingly complex circuits are dissected stage by stage and individual blocks analyzed.

Operational amplifiers typically are composed of either two or three stages consisting of a differentialamplifier, a gain stage and an output stage as seen in Fig. 3.18. In some applications, the gain stage and

the output stage are one and the same if the load is purely capacitive. However, if the output is to drive

a resistive load or a large resistive load, then a high current gain buffer amplifier is used at the output.

Each stage plays an important role in the performance of the amplifier.

The differential amplifier offers a variety of advantages and is always used as the input to the overall

amplifier. Since it provides common-mode rejection, it eliminates noise common on both inputs, while

at the same time amplifying any differences between the inputs. The limit for which this common mode

rejection occurs is called common-mode range and signifies the upper and lower common mode signal

values for which the devices in the diff-amp are saturated. The differential amplifier also provides gain.The gain stage is typically a common-source or cascode type amplifier. So that the amplifier is stable, a

compensation network is used to intentionally lower the gain at higher frequencies. The output stage

provides high current driving capability for driving either large capacitive or resistive loads. The output

stage typically will have a low output impedance and high signal swing characteristics. In some cases, it

may be advantageous to add bipolar devices to improve the performance of the circuitry. These will be

presented as the block level circuits are analyzed.

The Simple Unbuffered Op-Amp

a biasing block, a differential input stage, an output stage, and a compensation capacitor.

The biasing circuit is a simple current mirror driver, consisting of the resistor Rbias and the transistor

M8. The current through M8 is mirrored through both M5 and M7. Thus, the current through the entire

circuit is set by the value of Rbias and the relative W /Ls of M8, M5, and M7. The actual values of this

current will be discussed a little bit later on. When designing with Rbias, one must be careful not to ignore

the effect of temperature on Rbias , and thus the values of the currents through the circuit. We will see

later on how the bias current greatly affects the performance of the amplifier. For the commercial

FIGURE 3.18 Block diagram for a generic op-amp.


Examine the simple operational amplifier shown in Fig. 3.19. Here, the amplifier can be segregated into




temperature range of 0°C to 125°C, the current through M8 should be simulated with Rbias at values of

±30% of its nominal value. Other, more sophisticated voltage references (as discussed earlier) can be

used in place of the resistor reference, and will be presented as we progress.

The Differential Amplifier

The differential amplifier is composed of M1, M2, M3, M4, and M5, with M1 matching M2 and M3matching M4. The transistor M5 can be replaced by a current source in the ideal case to enhance one’s

understanding of the circuit’s functionality. The node labeled as node A can be thought of as a virtual

ground, since the current through M5 is constant and thus the voltage at node A is also constant.

Now assume that the gate of M2 is tied to ground as seen in Fig. 3.20. Any small signal on the gate

of M1 will result in a small signal current id1, which will flow from drain to source of M1 and will also

be mirrored from M3 to M4. Note that since M5 can be thought of as an ideal current source, it can be

replaced with its ideal impedance of an open circuit. Therefore, id1 will also flow from source to drain

of M2. Remember that the small signal current is different from the DC current flowing through M2.

The small signal current can be thought of as the current generated from the instantaneous (AC + DC)

voltage at the output. If the instantaneous voltage at the output node swings up, then the small signalcurrent through M2 will flow from drain to source. However, if the instantaneous voltage swings down,

FIGURE 3.19 Basic two-stage op-amp.

FIGURE 3.20 Pseudo-AC circuit showing small signal currents.





the change in voltage will be considered negative and thus the small signal current will assume an identical

polarity, thus flowing from source to drain of M2. The small signal voltage produced at the output node

will then be 2id1 times the output impedance of the amplifier. In this case, Rout is simply r o2||r o4. The value

of the small signal current, id1, is simply

(3.26)

and the differential voltage, v d = v gs1 + v sg 2. Therefore, since v gs1 = v gs2, then,

(3.27)

the small signal output voltage is simply

(3.28)

and the small signal voltage gain can then be easily derived as

(3.29)

Now let us examine this equation more carefully. Substituting the expressions for g m and r o , the previousequation becomes

(3.30)

where K ¢ is a constant, which is uncontrollable by the designer. When designing analog circuits, it is just

as important to understand the effects of the controllable variables on the specification as it is to know

the absolute value of the gain using hand calculations. This is because the hand analysis and computer

simulations will vary a great deal because of the complex modeling used in today’s CAD tools. Examining

Eq. (3.30), and knowing that the effect of l on the gain diminishes as L increases such that 1/l is directly

proportional to channel length. Then, a proportionality can be established between W /L1,2 and the drain

current vs. the small signal gain such that

(3.31)

Notice that the constant was not included since the value is not dependent on anything the designer can

adjust. The importance of this equation tells us that the gain is proportional to the square root of the

product of W and L and inversely proportional to the square root of the drain current through M1 and

M2, which is also 1/2 I D6. So to increase the gain, one must increase W or L or decrease the value I D6,

which is dependent on the value of Rbias.

The Gain Stage

Now examine the output stage consisting of M6 and M7. Here, the driving transistor, M6, is a simple

of the small signal current is defined by the AC signal v o1, which is equal to v sg 6. Therefore,

id1 g m1v gs 1=

id1

v d-----

g m1

2-------=

v o1 2 id1 r o2 r o4◊ ◊=

v o1

v d------ g m1 2, r o2 r o4( )=

v o1

v d------ 2b1 2, I D1 2,

1

2lI D1 2,-----------------◊ª K

¢ W 1 2,

L1 2, I D1 2,-------------------

1

l---◊ ◊=

v o1

v d------

W 1 2, L1 2,◊I D1 2,

------------------------µ


inverting amplifier with a current source load as seen in equivalent circuit shown in Fig. 3.21. The value




(3.32)

and the gain of the stage is simply

(3.33)

Again, we can write the gain in terms of the designer’s variables, so that the gain of the amplifier can be

expressed as a proportion of

(3.34)

Therefore, overall, the gain of the entire amplifier is

(3.35)

or as the proportionalities

(3.36)

So, the key variables for adjusting gain are the drain currents (the smaller the better) and the W and L

ratios of M1, M2, and M6 (the larger the better). Of course, there are lower and upper limits to the drain

currents and the W /Ls, respectively, that we will examine as we analyze other specifications that will

ultimately determine the bounds of adjustability.

Frequency Response

capacitor, C C , is removed and will be re-added shortly. The capacitors C 1 and C 2 represent the totallumped capacitance from each ground. Since the output nodes associated with each output is a high

FIGURE 3.21 Output stage circuit.

id6

v o1

------ g – m6=

id6

v o1

------v oid6

-----◊ v ov o1

------ g –= m6r o6 r o7◊=

v o

v o1

------W 6 L6 7,◊

I D6 7,

--------------------µ

v ov d---- g m1 2, r o2 r o4( ) g –◊= m6

r o6 r o7( )

v ov d---- W 1 2, L1 2,◊I D1 2,

------------------------ W 6 L6 7,◊I D6 7,--------------------◊µ


Now examine the amplifier circuit shown in Fig. 3.22. In this particular circuit, the compensation




impedance, these nodes will be the dominant frequency-dependent nodes in the circuit. Since each node

in a circuit contributes a high-frequency pole, the frequency response will be dominated by the high-

impedance nodes.

An additional capacitor could have been included at the gate of M4 to ground. However, the equivalent

impedance from the gate of M4 to ground is approximately equal to the impedance of a gate-drain

connected device or 1/ g m3 as seen in Fig. 3.23 (a)–(c). If a controlled source has the controlling voltage

directly across its terminals [Fig. 3.23(b)], then the effective resistance is simply the controlling voltage(in this case, v gs) divided by the controlled current ( g mv gs), which is 1/ g m||r o or approximately 1/ g m if r o is

much greater than 1/ g m [Fig. 3.23(c)]. Therefore, the impedance seen from the gate of M4 to ground is

low, and the pole associated with the node will be at a much higher frequency than the high-impedance

nodes. The same holds true for the node associated with the drain of M5. That node is considered an

AC ground, so it has no effect on the frequency response of the small signal circuit. The only remaining

node is the node which defines the current mirrors (the gate of M8). Since this node is not in the small

signal path, and is a DC bias voltage, it can also be considered an AC ground.

One can approximate the frequency response of the amplifier by examining both the effective imped-

ance and parasitic capacitance at the output of each stage. The parasitic capacitances can be seen in the

gb , C sb , and C db represent the bulk depletioncapacitors of the transistors, while C gd and C gs represent the overlap capacitances from gate to drain and

FIGURE 3.22 Two-stage op-amp with lumped parasitic capacitors.

FIGURE 3.23 Equivalent resistance for a gate-drain connected MOSFET device.


small signal model of a MOSFET in Fig. 3.24. The capacitors C




gate to source, respectively. Referring to Fig. 3.25, which shows the parasitic capacitors explicitly, C 1 can

now be written as

(3.37)

Note that C gd4 is included as capacitor to ground since the low impedance caused by the gate-drain device

of M3 can be considered equivalent to an AC ground. The capacitor C db2 is also connected to AC groundat the source-coupled node consisting of M1 and M2.

Miller’s theorem was used to determine the effect of the bridging capacitor C db6, connected from the

gate to the drain of M6. Miller’s theorem approximates the effects of the gate-drain capacitor by replacing

the bridging capacitor with an equivalent input capacitor of value C db6·(1 – A2) and an equivalent output

capacitor with a value of C db6·(1 – 1/ A2). The term A2 is the gain across the original bridging capacitor

and is – g m6·r o6||r o7. The reader should consult Ref. 2 for a proof of Miller’s theorem.

FIGURE 3.24 High-frequency, small signal model with parasitic capacitors.

FIGURE 3.25 Two-stage op-amp with parasitics shown explicitly.

C 1 C db 4 C gd 4 C db 2 C gd 2 C gs 6 C gd 6 1 A2+( )+ + + + +=





2

(3.38)

Now assume that C 1 is greater than C 2. This means that the pole associated with the diff-amp output

will be lower in frequency than the pole associated with the output of the output stage. Thus, a good

model for the op-amp can be seen in Fig. 3.26. The transfer function, ignoring C C , will then become

(3.39)

where

(3.40)

response, the phase margin is virtually zero. Remember that phase margin is the difference between phase

at the frequency at which the magnitude plot reaches 0 dB (also known as the gain-bandwidth product)

and the phase at the frequency at which the phase has shifted –180°. It is recommended for stability

reasons that the phase margin of any amplifier be at least 45° (60° is recommended). A phase marginbelow 45° will result in long settling times and increased propagation delays. The system can also be

thought of as a simple second-order linear controls system with the phase margin directly affecting the

transient response of the system.

Compensation

Now we will include C C in the circuit. If C C is much greater than C gd6, then the C C will dominate the

value of C 1 [especially since it is multiplied by (1 – A2)] and will cause the pole, f p1, to roll off much

earlier than without C C to a new location, f ¢ p1. One could solve, using circuit analysis, the circuit shown

in Fig. 3.26 with C C included to also prove that the second pole, f p2, moves further out3 to a higher

frequency, f ¢ p2. Ideally, the addition of C C will cause an equivalent single pole roll off of the overallfrequency response. The second pole should not begin to affect the frequency response until after the

magnitude response is below 0 dB. The new values of the poles are

FIGURE 3.26 Model used to determine the frequency response of the two-stage op-amp.

C 2 C db 6 C db 7 C gd 7 C gd 6 11

A2

-----+Ë ¯ Ê ˆ C L+◊+ + +=

v o s( )v d1 s( )------------- g – m1 r o2 r o4( ) g m6 r o6 r o7( ) 1

jf

f p1

----- 1+Ë ¯ Ê ˆ f

f p2

----- 1+Ë ¯ Ê ˆ

-------------------------------------------◊◊=

f p1

1

2pRou t 1C 1------------------------ f p2, 1

2pRou t C 2----------------------= =


The capacitor C can also be determined by examining Fig. 3.25,

The plot of the transfer function can be seen in Fig. 3.27. Note that in examining the frequency




(3.41)

If the previously discussed analysis was performed, one would also see that by using Miller’s theorem,

we are neglecting a right-hand plane (RHP) zero that could have negative consequences on our phasemargin, since the phase of an RHP zero is similar to the phase of a left-hand plane (LHP) zero. An RHP

zero behaves similarly to an LHP zero when examining the magnitude response; however, the phase

response will cause the phase plot to shift –180° more quickly. The RHP zero is at a value of

(3.42)

To avoid effects of the RHP zero, one must try to move the zero out well beyond the point at which

the magnitude plot reaches 0 dB (suggested rule of thumb: factor of 10 greater). The comparison of thefrequency response of the two-stage op-amp with and without C C can be seen in Fig. 3.27.

One remedy to the zero problem is to add a resistor, Rz , in series with compensation capacitor as seen

(3.43)

and the zero can be pushed into the LHP where it adds phase shift and increases phase margin if Rz >1/ g m6

4z z

is on the RHP real axis. As Rz increases in value, the zero gets pushed to infinity at the point at which

Rz = 1/ g m6. Once Rz > 1/ g m6, the zero appears in the LHP where its phase shift adds to the overall phase

response, thus improving phase margin. This type of compensation is commonly referred to as lead

compensation, and is commonly used as a simple method for improving the phase margin. One should

be careful about using Rz , since the absolute values of the resistors are not well predicted. The value of

the resistor should be simulated over its maximum and minimum values to ensure that no matter if the

FIGURE 3.27 Magnitude and phase of the two-stage op-amp with and without compensation.

f ¢

p11

2p g m6Rou t ( )C C Rou t 1

----------------------------------------------- f ¢

p2

g m6C C

2p C 2C 1 C 2C C C C C 1+ +( )◊------------------------------------------------------------------

g m6

2p C 2◊-----------------ª ª,ª

f z 1

g m6

C C

-------=

f z 11

C C 1

g m6

------- R Z –Ë ¯ Ê ˆ

--------------------------------=


in Fig. 3.28. The expression of the zero after adding the resistor becomes

. Fig. 3.29 shows the root locus plot for the zero as R is introduced. With R = 0, the zero location




zero is pushed into the LHP or the RHP, the value of the zero is always 10 times greater than the gain-

bandwidth product.

Other AC Specifications

Referring back to the equations for gain and the first pole location, we can now see adjustable parametersfor affecting frequency response by plugging in the proportionalities for their corresponding factors. The

values of the resistors are directly proportional to the length of L (the longer the L, the higher the

resistance, since longer channel lengths diminish the effects of channel length modulation, l).

The gain-bandwidth product for the compensated op-amp is the open-loop gain multiplied by the

bandwidth of the amplifier (as set by f ¢ p1). Therefore, the gain-bandwidth product is

(3.44)

Or we can write the expression as

(3.45)

FIGURE 3.28 Compensation including a nulling resistor.

FIGURE 3.29 Root locus plot of how the zero shifts from the RHP to the LHP as Rz increases in value.

GBW g m1 r o2 r o4◊( ) g m6 r o6 r o7◊( ) 1

2

pg

m6

Rou t ( )

C C R

ou t 1

-----------------------------------------------Ë ¯ Ê ˆ g m1

2

pC

C

-------------= =

GBW

W

L-----

1 2,I D1 2,

C C

--------------------------µ





which shows that the most efficient way to increase GBW is to decrease C C . One could increase the W /L1,2

ratio, but its increase is only by the square root of W /L1,2. Increasing I D1,2 will also yield an increase (also

to the square root) in GBW , but one must remember that it simultaneously decreases the open-loop gain.

The value of C C must be large enough to affect the initial roll-off frequency as a larger C C improves phase

margin. One could easily determine the value of C C by first knowing the gain-bandwidth specification,

then iteratively choosing values for W /L1,2 and I D1,2 and then solving for C C .

One other word of warning: the designer must not neglect the effects of loading on the circuit.

2

value of the load capacitor directly affects the phase shift through the amplifier by changing the pole

location associated with the output node. The second pole has a value of approximately g m6/2pC L as was

seen earlier. Since the second pole needs to be greater than the gain-bandwidth product, the following

relationship can be deduced:

(3.46)

or

(3.47)

Thus, one can see the effect of C L on phase margin in that the minimum size of the compensation

capacitor is directly dependent on the size of the load capacitor. For a phase margin of 60°, it can beshown3 that the second pole must be 2.2 times greater than the GBW .

The common-mode rejection ratio (CMRR) measures how well the amplifier can reject signals common

to both inputs and is written by

(3.48)

where V cm is a common mode input signal, which in this case is composed of an AC and a DC component

(the higher the value of CMRR, the better the rejection). The circuit for calculating common mode gain

Ad , and the common-mode gain, Acm. The last stage will cancel itself out in the expression for CMRR; thus,

the differential amplifier will determine how well the entire amplifier rejects common mode signals. This

rejection is one of the most advantageous reasons for using a diff-amp as an input stage. If the inputs are

subjected to the same noise source, the diff-amp has the ability to reject the noise signal and only amplify

the difference in the inputs. For the diff-amp used in this example, the common-mode gain is

(3.49)

This equation bears some explanation. Since the inputs are tied together, the source-coupled node can

no longer be considered an AC ground. Therefore, the resistance of the tail current device, M5, must be

considered in the analysis. The AC currents flowing through both M1 and M2 are equal and v gs3 = v gs4.

The output impedance of the diff-amp will drop considerably when using a common-mode signal due

to the feedback loop consisting of M1, M3, M4, and M2. As a result, the common-mode signal appearing

on the drains of M3 and M4 will be identical.

g m6C L

------- g m1 2,C C

----------->

C C

g m1 2,

g m6

----------- C L◊>

CMRR 20 Ad

Acm

--------log 20 v o v d § v o v cm § ---------------log= =

v o1

v cm

-------1

2 g m4r o5

-----------------–=


Practically speaking, the load capacitor usually dominates the value of the capacitor, C in Fig. 3.22. The

can be seen in Fig. 3.30. The gain through the output stage will be the same for both the differential gain,




One can determine this gain by using half-circuit analysis (Fig. 3.31). This is equivalent to a common

source amplifier with a large source resistance of value 2r o5. When using half-circuit analysis, the current

source resistance doubles because the current through the driving device M1 is one half of the original

tail current. Therefore, the gain of this circuit can be approximately determined as the negative ratio

between the resistance attached to the drain of M1 divided by the resistance attached to the source of M1, or

(3.50)

Adding the expression for the differential gain of the diff-amp, v o1/v d, we can write the expression for the

CMRR as

FIGURE 3.30 Circuit used to determine CMRR and PSRR.

FIGURE 3.31 Half-circuit used to determine the common-mode gain.

v o1

v cm

-------1 g m3 4, §

2r o5

------------------–=





(3.51)

or as a proportion,

(3.52)

So, it can be seen that the most efficient manner in which to increase the CMRR of this amplifier is to

increase the channel length of M5 (the tail current device). This, too, has a large signal implication that

we will discuss later in this section.

The power supply rejection ratio (PSRR) measures how well the amplifier can reject changes in the

power supply. This is also a critical specification because it would be desirable to reject noise on the

power supply outright. PSRR from the positive supply is defined as:

(3.53)

where the gain v o /v dd is the small signal gain from v dd

with the input signal, v d, equal to zero. PSRR can also be measured from V SS by inserting a small signal

source in series with ground. One should be careful, however, when simulating this specification to make

sure that the inputs are properly biased so as to ensure that they are in saturation before simulating. It

is best to use a fully differential (differential input and differential output) to most effectively reject powersupply noise (to be discussed later).

Large Signal Considerations

Other considerations that must be discussed are the large signal tradeoffs. One cannot ignore the effects

of adjusting the small signal specifications on the large signal characteristics. The large signal character-

istics that are important include the common-mode range, slew rate, and output signal swing.

Slew rate is defined as the maximum rate of change of the output voltage due to a change in the input

voltage. For this particular amplifier, the maximum output voltage is ultimately limited by how fast the

tail current device (M5) can charge and discharge the compensation capacitor. The slew rate can then

be approximated as

(3.54)

Typically, the diff-amp is the major limitation when considering slew rate. However, the tradeoff issues

again come into play. If I D5 is increased too much, the gain of the diff-amp may decrease below a

satisfactory amount. If C C is made too small, then the phase margin may decrease below an acceptable

amount.The common-mode range is defined as the range between the maximum and minimum common-mode

voltage is DC value and that the differential signal is also as shown. If the common-mode voltage is swept

from ground to V DD , there will be a range for which the amplifier will behave normally and where the

gain of the amplifier is relatively constant. Above or below that range, the gain drops considerably because

the common-mode voltage forces one or more devices into the triode region.

The maximum common-mode voltage is limited by both M1 and M2 going into triode. This point

can be defined by a borderline equation in which V DS1,2 = V GS1,2 – V THN or, in this case, V D1,2 = V G1,2 –

CMRR 20 2 g m1 2, g m3 4, r o2 r o4( )r o5( )log=

CMRR 20W 1 2, L1 2,◊

I D1 2,------------------------

W L § ( )3 4,

2I D5

----------------------- L5◊ ◊Ë ¯ Ê ˆ logµ

PSRR v dd v o v d §

v o v dd § ---------------=

SRdVo

dt ----------

I D5

C C

------ª=


(refer back to Fig. 3.30) to the output of the amplifier

voltages for which the amplifier behaves linearly. Referring to Fig. 3.32, suppose that the common-mode




V THN . Substituting V DD – V SG3 for V D1,2, and solving for VG1,2, which now represents the maximum com-

mon-mode voltage, the expression becomes

(3.55)

where the value of V SG3 is written in terms of its drain current using the saturation equation. If thethreshold voltages are assumed to be approximately the same value, then the equation can be written as

(3.56)

The minimum voltage is limited by M5 being driven into nonsaturation by the common-mode voltage

source. The borderline equation (V D5 = V G5 – V THN ) for this transistor can then be used with V D5 = V G1,2 –

V GS1,2 and writing both V G5 and V GS1,2 in terms of its drain current yields

(3.57)

Now notice the influencing factors for improving the common-mode range (V G1,2(max ) is increased and

V G1,2(min) is decreased). Assume that V DD and V SS are defined by the circuit application and are not

adjustable. To make V G1,2(max ) as large as possible, I D5 and L3 should be made as small as possible while

W 3 is made as large as possible. And to make V G1,2(min) as small as possible, L5, I D5, and L1,2 should be

made as small as possible while increasing W 5 and W 1,2 as large as possible. Making the drain current as

small as possible is in direct conflict with the slew rate. Decreasing L5 will also degrade the common-mode rejection ratio, and increasing W 3 will affect the pole location of the output node associated with

the diff-amp, thus altering the phase margin. All these tradeoffs must be considered as the designer

chooses a circuit topology and begins the process of iterating to a final design.

The output swing of the amplifier is defined as the maximum and minimum values that can appear

on the output of the amplifier. In analog applications, we are concerned with producing the largest swing

possible while keeping the output driver, M6, in saturation. This can be determined by inspecting the

output stage. If the output voltage exceeds the gate voltage of M6 by more than a threshold voltage, then

M6 will go into triode. Thus, since the gate voltage of M6 is defined as V DD – V SG3,4, the maximum output

FIGURE 3.32 Determining the CMR for the two-stage op-amp.

V G1 2 ma x ( ), V DD

I D5

b3

------ V TH P +– V TH N +=

V G1 2 ma x ( ), V DD

I D5

b3

------– V DD

L3 I ◊ D5

W 3 K 3◊-----------------–= =

V G1 2 mi n( ), V SS

2I D5

b5

----------I D5

b1 2,--------+ + V SS

2L5 I ◊ D5

W 5 K 5◊-------------------

L1 2, I ◊ D5

W 1 2, K 1 2,◊-------------------------+ += =





voltage will be determined by the size of M3 and M4. The larger the channel width of M3 and M4, the

smaller the value of V SG3,4 and the higher the output can swing. However, again the tradeoff of making

M3 and M4 too large is the reduction in bandwidth due to the increased parasitic capacitance associated

with the output of the diff-amp.

The minimum value of the output swing is limited by the gate voltage of M7, which is defined by

biasing circuitry. Again using the borderline equation, the drain of M7 may not go below the gate of M7

by more than a V THN . Thus, to improve the swing, the value of V GS7 must be made small, which implies

that the value of V GS8 and V GS5 also be made small, resulting in large values of M5, M8, and M7. This is

not a very wise option because increasing M5 causes all the PMOS devices to increase by the same factor,

resulting in large devices for the entire circuit. By carefully designing the bias device M8, one can design

V GS8 to be around 0.3 V above VTHN. Thus, the output can swing to within 0.3 V of V SS.

Tradeoff Example

When designing amplifiers, the tradeoff issues that occur are many. For example, there are many effects

that occur just by increasing the drain current through the diff-amp: the open-loop gain goes down (by the square root of I D) while the bandwidth increases (by I D) due to the fact that the resistors r o2 and r o4

decrease by 1/I D. The overall effect is an increase (by the square root of I D) in GBW, as predicted earlier.

A table summarizing the various tradeoffs that occur from attempting to increase the DC gain can be

seen in Table 3.1. It is assumed that if a designer only takes the one action listed that the following

secondary effects will occur. In fact, the designer should understand the secondary effects well enough

to take a counteraction to offset the secondary effects.

The key for the entire circuit design is the size of M5; the remaining transistors can be written as

factors of W5. The minimum amount of current flowing through M5 is determined by the slew rate.

Since M3 and M4 carry half the current of M5, then the widths of M3 and M4 can be determined by

assuming that V SG3 = V SG4 = V GS5.

(3.58)

and since L3 = L5, and K n = 3K p, then that leads to the conclusion that W 3,4 = 1.5·W 5. If the nulling resistor

is used in the compensation network, the values for M6 and M7 are determined by the amount of load

capacitance attached to the output. If a large capacitance is present, the widths of M6 and M7 will need

to be large so as to provide enough sinking and sourcing current to and from the load capacitor. Suppose

TABLE 3.1 Tradeoff Issues for Increasing the Gain of the Two-Stage Op-Amp

Desire Action(s) Secondary effects

Increase DC gain Increase W/L1,2

Decrease ID5

Increase W/L6

Decrease ID6

Decreases phase marginIncreases GBW

Increases CMRRDecreases CMR

Decreases SR

Increases CMRIncreases CMRRIncreases phase margin

Increases phase marginIncreases output swing

Decreases output current drive

Decreases phase margin

2I D3 4,

I D5

-------------2K P W L § ( )3 4, V SG 3 4, V TH P –( )2◊ ◊

K n W L § ( )5 V GS 5 V TH N –( )2◊ ◊-----------------------------------------------------------------------------------

2K P W L § ( )3 4,◊K n W L § ( )5◊

-------------------------------------ª ª





it was decided that the amount of current needed for M6 and M7 was twice that of M5. Then, W 7 would

be twice as large as W 5, and W 6 would be six times larger than W 5 to account for the differing K values.

Alternatively, if everything is saturated, then I D3 = I D4, and the drain voltage at the output of the diff-

amp is identical to the drain voltage of M3. This implies that under saturation conditions, the gate of

M6 is at the same potential as the gate of M4; thus, again it must be emphasized that we are talking

about quiescent conditions here, and the current through M6 will be defined by the ratio of M6 to M4.

Therefore, since M6 is carrying four times as much current as M3, then W 6 = 4W 3,4, which is six times

the value of W 5. Thus, every device except M1 and M2 is written in terms of M5.

The sizes of M1 and M2 are the most critical of the amplifier. If W 1,2 are made too large, then C C will

be large due to its relationship with C L and the ratio of g m1 and g m6 [Eq. (3.48)]. However, if W 1,2 is made

too small, the gain may not meet the requirements needed.

One word about high-impedance nodes. If two current sources are in a series as shown in Fig. 3.33(a),

then the value of the voltage between them is difficult to predict. In the ideal case, both current sources

have infinite impedances, so any slight mismatch between I 1 and I 2 will result in large swings in v A. The

same holds true for Fig. 3.33(b). Since the two devices form a high impedance at the output, and eachdevice can be considered a current source, any mismatches in the currents defined by b2(V SG2 – V THP )

2

and b1(V GS1 – V THN )2 will result in large voltage offsets at the output, with the device with the larger

defined current being driven into triode. Thus, the smaller of the two defined currents will be the one

flowing through both devices. Another way to visualize this condition is to place a large resistor repre-

senting the output impedance from v o to ground. Any difference between the two transistor currents will

flow into or out of the resistor, creating a large voltage offset. Feedback is typically used around the op-

amp to stabilize the DC output value.

A Word about Circuit Simulation

Circuit simulators have become powerful design tools for analysis of complicated analog circuits. How-

ever, the designer must be very careful about the role of the simulator in the design. When simulating

high-gain amplifier circuits, it is important to understand the trends and inner working of the circuit

before simulations begin. One should always interpret rather than blindly trust the simulation results

(the latter is a guaranteed recipe for disaster!). For example, the previously mentioned high-impedance

nodes should always be given careful consideration when simulating the circuit. Because these nodes are

highly dependent on l, predicting the actual DC value of the nodes either throughsimulation or hand

analysis is a near impossibility. Before any AC analysis is performed, check the values of the DC points

in the circuit to ensure that every device is in saturation. Failure to do so will result in very wrong answers.

FIGURE 3.33 Illustration of a high-impedance node.





Other Output Stages

With the preceding design, the output stage was a high-impedance driver, capable of handling only

capacitive loads. If a resistive load is present, an additional stage should be added that has a low output

impedance and high current drive capability. An example of the output stage can be seen in Fig. 3.34.

Here, the output impedance is simply 1/ g m9||1/ g m10. Since we do not wish to have a large output impedance,the values for L9 and L10 should be made as small as possible. The transistors M11 and M12 are used to

help bias the output devices such that M9 and M10 are just barely on under quiescent conditions. This

kind of amplifier is known as a class AB output stage and has limitations in CMOS due to the body effect.

In some cases, it is advantageous to use a bipolar output driver as seen in Fig. 3.35. Since most BiCMOS

processes provide only one flavor of BJT (an npn), the transistor Q1 can be used for extra current drive.

This results in a dual-sloped transfer curve characteristic as the output stage goes from sourcing to

sinking. It should be noted that one could use this output stage with the complementary version of the

two-stage amplifier previously discussed.5 This is known as a “pseudo-push-pull” output

stage. M6 and M7 can be output of the previously discussed two-stage op-amp. With the new pseudo-push-pull output attached, the amplifier is able to achieve high output swing with large current drive

FIGURE 3.34 A low-impedance output stage.

FIGURE 3.35 Using an npn BJT as an output driver.


Another BiCMOS output stage can be seen in Fig. 3.36.




capability using very little silicon area. The transistor MQ1 is for level shifting purposes only. When the

output signal needs to swing in the positive direction, Q2 behaves just like the BJT output driver shown

increasing I D9. The increase in current is mirrored via M10 to M11, which is able to sink a large amount

of current. The output voltage at its lowest is approximately the same as the emitter voltage of Q2. The

transistor Q2 provides the needed low output impedance.

Another advantage of using BJT devices in the design is to provide large g ms as compared to the MOS

counterpart. BiCMOS circuits can be constructed, which offer high input impedance and gain bandwidth

products. If both npn and pnp devices are available in the BiCMOS process, then the output stage seenin Fig. 3.37 can be used. This circuit functions as a buffer circuit with very low output impedance.

High-Performance Operational-Amplifier Considerations

In the commercial world, it seems there are not many applications that require simple, easy-to-design

op-amps. High bit rate communication systems and over-sampled data converters push the bandwidth

and slew rate capabilities of CMOS op-amps, while battery-powered systems are required to squeeze just

enough performance out of micro-amps of current, and a volt or two of power supply. Sensor interfaces

and audio systems demand low noise and distortion. To further complicate things, CMOS analog circuits

are often integrated with large digital circuits, making isolation from switching noise a major concern.

FIGURE 3.36

A “pseudo” push-pull npn only output driver.

FIGURE 3.37 A low-impedance output stage using both npn and pnp devices.


in Fig. 3.35. When the output swings in the negative direction, Q1 drives the gate of M9 down, thus




This section will present solutions to some of the problems faced by op-amp designers who, because of

budget constraints or digital compatibility, do not have the option to use bipolar junction transistors in

their design. We will then give some hints on where the designer might use bipolar transistors if they are

available.

Power Supply RejectionFully differential circuits like the OTA shown in Fig. 3.38 are used in mixed signal circuits because

they provide good rejection of substrate noise and power supply noise. As long as the noise coupled

from the substrate or power supply is equal for both outputs, the difference between the two signals

traces in Fig. 3.39 are a differential signal corrupted with common-mode noise. The bottom trace is

the difference between these two noisy signals. If the next circuit in the path has good common-mode

rejection, the substrate and power supply noise will be ignored. In practical circuits, mismatches

between the transistors of symmetrical halves of the differential circuit will lead to imperfect matching

of noise on the outputs, and therefore reduced rejection of power supply noise. Common centroidlayouts and large geometry transistors are necessary to minimize mismatches. Differential circuits are

capable of twice the signal swing of single-ended circuits, making them especially welcome in low-

voltage and low-noise applications.

Single-stage or multiple-stage op-amps can be made differential, but each stage requires a common-

mode feedback circuit to give the differential output a common-mode reference. Consider the folded

cascode OTA shown in Fig. 3.38. If the threshold voltage of M5A is slightly larger than the threshold

voltage of M5B and M5C, the pull-down currents will be larger than the pull-up currents. This small

current difference, in combination with the very high output impedance of the cascode current mirrors,

will cause the output voltages to be pegged at the negative power supply. This common-mode error

cannot be corrected by applying feedback to the differential pair. A common-mode feedback circuit isneeded to find the average of the output voltages, and control the pull-up or pull-down current in the

outputs to maintain this average at the desired reference. A center-tapped resistor between the outputs

could be used to sense the common-mode voltage if the outputs were buffered to drive such a load. Since

a folded cascode OTA cannot drive resistors, a switched capacitor would be a better choice to sense the

FIGURE 3.38 Folded cascode OTA.


is noise-free (differential component of the noise is zero). This is illustrated in Fig. 3.39. The top two

common-mode voltage as shown in Fig. 3.40. The PH1 and PH2 clock signals must be non-overlapping.




When the PH1 switches are closed, C 1 A and C 1B are discharged to zero, while C 2 A and C 2B provide feedback

to the common-mode amplifier. The PH1 switches are then opened, and a moment later, the PH2 switches

closed. The charge transfer that takes place moves the center tap between C 2 A and C 2B toward the average

of the two output voltages. After many clock cycles, the input to the common-mode feedback amplifier

will be the average of the two voltages. C 1 A and C 1B can be precharged to a bias voltage to provide a level

6

that only npn devices are available. Note that to best utilize the npn devices, the folded cascode uses a

diff-amp with P-channel input devices. The amplifier also uses the high swing current mirror presented

in Section 3.2.

FIGURE 3.39 Simulation output illustrating the difference between single-ended and fully differential signals.

FIGURE 3.40 Folded cascode OTA using switched capacitor common mode feedback.


shift. This allows direct feedback from the common-mode circuit to the pull-up bias as shown in Fig. 3.41.

A BiCMOS version of the folded cascode amplifier can be seen in Fig. 3.42. Here, it is again assumed




Slew Rate

The slew rate of a single-stage class A OTA is the maximum current the output can source or sink, dividedby the capacitive load. The slew rate is therefore proportional to the steady-state power consumed. Class

AB amplifiers give a better tradeoff between power and slew rate. The amplifier’s maximum output

current is not the same as the steady-state current. An example of a class AB single-stage op-amp is

consisting of M3A, M3B, M4A, and M4B couples the input signal to M2A and M2B, and sets up the

zero input bias current. If the width of M2A and M2B are three times the width of M1A and M1B, the

small signal voltage on the nodes between M1 and M2 will be approximately zero. The current available

from one of the input transistors is approximately

FIGURE 3.41 Using a bias voltage to precharge the switched capacitor common mode feedback capacitors.

FIGURE 3.42 BiCMOS folded cascode amplifier.


shown in Fig. 3.43. The differential pair is replaced by M1A, M1B, M2A, and M2B. A level shifter




(3.59)

The differential current from the input stage is

(3.60)

It is interesting to note that the non-linearities cancel. The output current becomes non-linear again

as soon as one of the input transistors turns off. The maximum current available from the input transistorsis not limited by a current source as is a differential pair. It should be noted that it is impossible to keep

all transistors saturated for low power supplies and large input common-mode swings. A similar BiCMOS7

Adaptive bias is another method to reduce the ratio of supply current to slew rate. Adaptive bias senses

the current in each side of a conventional differential pair, and increases the bias current when the current

on one side falls below a preset value. This guarantees that neither side of the differential pair will turn

off. The side that is using most of the current must therefore be supplied with much more than the zero

input amount. The differential pair current can be sensed by measuring the gate-to-source voltages as

bias schemes depend on a feedback loop to control the current in the differential pair. These circuits

improve settling time for low power, low bandwidth circuits, but the delay in the feedback path is a

problem for high-speed circuits.

A second form of adaptive bias can be used when it is known that increased output current is needed

just after clock edges, such as in switched capacitor filters. This type of adaptive bias can be realized using

D1·L1/W 1 > I D2·L2/W 2, which makes

V 1 > V 2. When the PH1 switches are closed, the steady-state voltage across the capacitor is V 1 – V 2, and

the current in M3 is set by I D2. When the PH2 switches close, V 2 is momentarily increased, while V 1 is

FIGURE 3.43 A class AB single stage op-amp with high slew rate capability.

I ou t

KP W

L----- V in V bias V TH N + +( )2

=

I OUTP I OUTN – 2 b V in V BIAS V TH N + +( )◊=


circuit with high slew rate can be seen in Fig. 3.44.

shown in Fig. 3.45, or by measuring the current in the load as shown in Fig. 3.46. Both of these adaptive

the switched capacitor bias boost shown in Fig. 3.47. In this circuit, I




decreased. The transient is repeated when the PH1 switches close. The net effect of the switched capacitor

bias boost is that the current in M3 increases after both clock edges. Notice that the current is increased,

whether it is needed or not. This circuit is fast because there is no feedback loop, but it is not the most

efficient because it does not actually sense the current in the differential pair.

In all three approaches, the quiescent current is less than the current when the output is required to

slew. Therefore, output swing and gain are not degraded when the bias current returns to its quiescent

value. All three adaptive bias circuits will cause larger current spikes to be put on the supplies by the op-

amps. The width of the power supply lines should be increased to compensate for the increased IR drop

FIGURE 3.44 A BiCMOS class AB input stage.

FIGURE 3.45 Adaptive biasing scheme for improved slew rate performance.





and crosstalk. Enhanced slew rate circuits are not linear time invariant systems because the transconduc-

tance and output impedance of the transistors are bias current dependent, and the bias is time varying.A transient analysis is the most dependable way to evaluate settling time in this case.

Output Swing

Decreasing power supply voltages put an uncomfortable squeeze on the design engineer. To maintain

the desired signal-to-noise ratio with a smaller signal swing, circuit impedances must decrease, which

often cancels any power savings that may be gained by a lower supply voltage. To get the best signal

swing, differential circuits are used. If the output stages use cascode current mirrors, bias voltages must

be generated, which keep both the mirror and cascode transistors in saturation with the minimum voltage

FIGURE 3.46 Another adaptive biasing circuit.

FIGURE 3.47 Adaptive biasing using a switched capacitor circuit.





mirror is shown in Fig. 3.48. First, let the W /L ratio of M2, M4, and M6 be equal, and the W /L ratio of

M3 and M5 be equal. Now recall that to keep a MOSFET in saturation

(3.61)

The minimum output voltage that will keep both M5 and M6 in saturation with proper biasing is

(3.62)

ignoring the bulk effects. For a given current, the minimum drain voltage can be rewritten as

(3.63)

The equation for the minimum V OUT can be rewritten as

(3.64)

The trick to making this bias generator work is setting V DS of M1 equal to the minimum V DS required

by M3 and M5. M1 is biased in the linear region, while we wish to keep M3 and M5 saturated. It is agood idea to set L1 = L3 = L5 to match etching tolerances. A second trick is to make sure M3 and M4

stay saturated. M4 is inserted between the gate and drain connections of M3 to make V DS3 = V DS5. If the

W /L ratio of M3 is too small, M3 will be forced out of saturation by the source of M4. If the W /L3 is too

large, the gate voltage of M3 will not be large enough to keep M4 in saturation.

DC Gain

of the n-channel cascode current mirror is much greater than the output impedance of the individual

transistors, then the DC gain is approximately

FIGURE 3.48 A high swing biasing circuit for low power supply applications.

V DS V GS V TH N –

≥

V ou t V GS 6 2V TH N – V GS 5+≥

V DS I D L◊K W ◊-------------≥

V OU T

I OU T L6◊K 6 W 6◊

-------------------I OU T L5◊K 5 W 5◊

-------------------+≥


Start by calculating the DC gain of the folded cascode OTA in Fig. 3.38. If we assume the output impedance

on the output. Another example of a high swing bias circuit (refer also to Section 3.2) and a current




(3.65)

If we assume that the current from the M3 splits equally to M1 and M2, the gain can be written as

(3.66)

We can see that the gate area of the differential pair and cascode transistors must both double each time

current is doubled to maintain the same gain. We also note that it is desirable to make L3 > L1. If the

current in the amplifier were raised to increase gain-bandwidth, or slew rate, it would be desirable to

increase the widths of the transistors by the same factor to maintain output swing.

Regulated gate cascode outputs increase the gain of the OTA by effectively multiplying the g m of M4

by the gain of the RGC amplifier. The stability of the RGC amplifier loop must be considered. An exampleof a gain boosted output stage is shown in Fig. 3.49.

Gain Bandwidth and Phase Margin

impedances of the n-channel cascode current mirrors are very large, and the gain of M2 is much greater

than one, we have

(3.67)

FIGURE 3.49 OTA with regulated gate cascode output.

v ov in----- g m1– r o1 r o3◊= g m2 r o2◊ ◊

v ov in-----

W 1L1W 2L2

I D1

------------------------------L3

2L1 L3+

--------------------◊µ

v ov in-----

g m1r o1 g m2r o2

C 1 C ou t r o1 r o2◊ ◊ ◊( ) s

2 g m2

C 1-------

1

C 1 r o1◊----------------

1

C 1 r o2◊----------------

1

C ou t r o2◊-------------------+ + +

Ë ¯ Ê ˆ

s

1

C 1 C ou t r o1 r o2◊ ◊ ◊----------------------------------------+ +

Ë ¯ Ê ˆ

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=


Again, start with the transfer function for the folded cascode OTA of Fig. 3.38. If we assume the output




where ro1 is now the parallel combination of r o1 and r o3. If we further assume that the poles are spaced

far apart, and that g m2 is much larger than 1/r o1 and 1/r o2, then the gain-bandwidth product is g m1/C load.

The second pole, which will determine phase margin, is approximately

The depletion capacitance of the drains of M1 and M3 will also add to this capacitance. As a first cut,

let C 1 = K c·W 2·L2. Now the equation for the second pole boils down to

To get maximum phase margin, we clearly want to use as short a channel length as the gain specificationwill allow. The folded cascode OTA and two-stage OTA both have n-channel and p-channel transistors

in the signal path. Since holes have lower mobility than electrons, it is necessary to make a silicon p-

channel transistor about three times wider than an n-channel transistor of the same length to get the

same transconductance. The added parasitic capacitance of the wider p-channel transistor is a hindrance

for high-speed design. The telescopic OTA shown in Fig. 3.50 has only n-channel transistors in the signal

path, and can therefore achieve very high bandwidths with acceptable phase margin. Its main drawback

is that the output common-mode voltage must be more positive than the input common-mode voltage.

This amplifier can achieve even wider bandwidth with acceptable phase margin if M2 is replaced by an

npn bipolar transistor.

FIGURE 3.50 A telescopic OTA.

wg

m2

C 1-------

1

C ou t r o2◊-------------------+=

w K I D2◊

K C L2 W 2 L2◊◊ ◊-----------------------------------------ª I D2

L2 C ou t ◊------------------+





References

1. R. J. Baker, H. W. Li, and D. E. Boyce, CMOS: Circuit Design, Layout, and Simulation, IEEE Press,

1998.

2. A. S. Sedra and K. C. Smith, Microelectronic Circuits, fourth edition, Oxford University Press,

London, 1998.3. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Saunders College Publishing, Phila-

delphia, 1987.

4. P. R. Gray, Basic MOS Operational Amplifier Design — An Overview, Analog MOS Integrated Circuits,

IEEE Press, 1980.

5. H. Qiuting, A CMOS power amplifier with a novel output structure, IEEE J. Solid-State Circuits,

vol. 27, no. 2, pp. 203-207, Feb. 1992.

6. M. Ismail, and T. Fiez, Analog VLSI: Signal and Information Processing , McGraw-Hill, Inc., New

York, 1994.

7. S. Sen and B. Leung, A class-AB high-speed low-power operational amplifier in BiCMOS technol-

ogy, IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1325-1330, Sept. 1996.

cmos amplifier

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