cmos circuit design

8/14/2019 CMOS Circuit Design

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08/09/09 NERIST 2009 1

CMOS Circuit Design:

Challenges of Nano Electronics

Susanta SenInstitute of Radio Physics and Electronics

University of Calcutta


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08/09/09 NERIST 2009 2

Review of

MOS Transistor


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The MOS Transistor


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MOS Transistor

Depletion Inversion


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MOS Transistor (contd.)

VDS

ID

Channel Pinches off Current Saturates

VG

Saturation Current increases with VG

Vt

Threshold Voltage Vt Device Turns ONMOS can be used as SWITCH


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MOS as SWITCH

Designing Logic Circuits

Logic 0 = 0V : Logic 1 = VDD

n-MOS :VG VtOFF : VG = VDDON

p-MOS :VG VDD VtOFF : VG = 0ON

Gate Voltage Negative w.r.t. Channel


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n-MOS SWITCHTransferring Logic 1 (VDD):

VDD

Vin = VDD VtVDD

Vo

t

Transistor

OFFSource

Impedance

High

Weak 1

Transistor

ON

Source

ImpedanceLow

Strong 0VDD

Vin = 0 V Vo

t

VDD

Transferring Logic 0 (0 V):


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p MOS Switch

Transferring Logic 1 (VDD):

VDD

Vo

t

0V

VDD Strong 1

Transferring Logic 0 (0 V):

0V

0 V

t

Vo

VDD

Vt

Weak 0


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08/09/09 NERIST 2009 9

CMOS Logic

Use n-MOS to produce Logic 0 Pull DOWN

Use p-MOS to produce Logic 1 Pull UP

The CMOS Inverter

Equivalent

Circuit

Logic 1

Output

Logic 0

Output


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08/09/09 NERIST 2009 10

Review of Switching Theory

C

A B

F = C and (A and B)

Switches in Series

A

B

C F = C and (A or B)

Switches in Parallel


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Using n-MOS Switch

Constraint : C = 0

A B

Series Connection

C = 0 F = 0 and (A . B) = A nand B

A

B

C = 0 F = 0 and (A or B) = A nor B

Parallel Connection


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Using p-MOS Switch

Constraint : C = 1

A B

C = 1 F = 1 and ( A . B) = A + B

Series Connection

C = 1

A

B

F = 1 and ( A + B) = A . B

Parallel Connection


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CMOS Logic Design

Pull UP Network

Build using p-MOS

Turns ON when Function is TRUE

Pull DOWN Network

Build using n-MOS

Turns ON when Function is FALSE

Operationally Complement

Topologically Dual


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CMOS Logic (contd.)

A

A

B

BA

A

B

B

F F

NAND GateNOR Gate


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CMOS Design Example

Consider the Function

f = A . (B + C)

f = 0. [A . (B + C)]

Design the

Pull Down

Network

A

B CPullUp

F

B

A

C


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CMOS Design Example

Consider the Functionf = A . (B + C)

Design the

Pull Down

Network first

A

B CPullUp

F

B

A

Cf = [A . (B + C)] is true

The Pull Down Network connects

f to ground when

Connect Ground


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Power DissipationNo Static Dissipation

Except leakage currentDynamic Dissipation

Charging and discharging load capacitor

Direct Path Dissipation

During switching


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Dynamic Dissipation (0 1)

P-MOS On

N-MOS

Off

Vo

IL

IL= CL.dVo/dt

Edrawn= VDDILdt = VDDCLdVo = CLVDD2

Ediss(in Rp) = (VDD- Vo) ILdt= CL(VDD- Vo)dVo = CLVDD2 Estored (in CL)= CLVDD2


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Dynamic Dissipation (1 0)

VoEdiss(in Rn) = Estored=CLVDD2


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CMOS Logic Circuit

Advantages

Low Power Dissipation in Steady State Either Pull-up OR Pull-down ON

No direct path current from VDD Gnd

No (negligible) Steady State Dissipation

High Packing Density

Large Circuits on single chip billion devices

Significant Static Dissipation


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VDD

VOVi

(=VG)

MOS Amplifier

VDS

ID

VDD

VG

Vi

VO

Load Line

RL

ID

VO = VDD ID.RL

VDD


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08/09/09 NERIST 2009 24

The CMOS InverterAmplifier or Inverter ?

Vi VO

VO

Vi

Gate Bias of PMOS changes with

Input Voltage

VDD

VDDVDS

ID

VDD


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A Closer Look

In presence of Noise

VO = f(Vi + vn)

= f(Vi) + vn(VO/Vi) + vn2(2VO/Vi2)+VO

Vi

noisy_output = noiseless_output +

noise x gain + higher order terms

VO= f(Vi)

Gain =

VO/

Vi

ViHViL

VOL

VOH

Digital Noise immunity Analog High Gain


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VG

VDD

VOVi

VDS

ID

VQ

Q

VDD

id= gmvi

+vi+vo

vo = - gmviRL

+id

Gain = vo/vi = - gmRL

VO = VDD ID.RL

The Amplifier : A Closer LookSlope = - 1/RL

iORL


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Small vs Large Signal

Where is the Q-point

VO

Vi

Large Signal limits

Cut off & Saturation

Q-point

Middle of range

Signal will be distorted

Specify limits

Small Signal Q-point

Maximum gain

Linear region

Minimize Distortion


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A Closer Look at the Characteristics

VDS

ID

Gain = gm RL

ID = (k'/2)(W/L) (VGS VT)2(1 + VDS)

= L/(LVDS) Channel Length Modulation Coefficient

RL||rO


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The Analytical Approach

ID

VD

VGv

i

v

o

dID = dVG+ dVDIDVG

IDVDIDVG =gm TransconductanceIDVD=go O/P Conductance

The current source load keeps drain current const. So,

dID

=0 = gm

.vi

+ go

.vo

Hence, Voltage Gain (Ao) is

Ao= vo/vi = gm / go = gm ro


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The Equivalent Circuit

G

D

S

G D

S

The 3 terminals

gOvDS

Current source dependent

on output voltage gOvDS Current source dependent on its

terminal voltage rO= 1/gO

rO= 1/gOgmvGS

Current source dependent oninput voltage (gmvGS)


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The Transistor Parameters: gm & go

In saturationID= (k'/2)(W/L)(VG VT)

2

where, k'= Cox and VT = VT0 Vsb ,

VT0 is the threshold voltage without substrate bias and

is the parameter that accounts for the effect ofsubstrate bias Vsb.

Let VG VT = VGT ID= (k'/2)(W/L) VGTgm = (ID/VG) = k'(W/L) VGT

2


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Transconductance (contd.)

gm = 2ID/VGT

gm = k'(W/L)VGT

Also, k'(W/L) = 2ID/VGT2

2IDk'(W/L)But

VGT=

Three Formulae (!!!)

Is gm linearly dependent onTransistor size ?

gm = 2k'(W/L)IDOr dependent on its

square root ?

Or independent of (W/L) ?

To increase gm

Shall we increase VGT?

Or decrease it ?


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Which Formula ?

Depends on how the Transistor is

BIASED and SIZED

If Size and VGTare known

Use the first one

If Drain Current and Size are known Use thesecond

If the Drain Current and Gate Voltage are given

and the Transistor is accordingly sized Usethe third


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Output Resistance (ro)

ID = (k'/2)(W/L)VGT(1 + VDS)2

gO= (ID/VDS) ID= 'ID /LDefining, ' = L = (L/V

DS)

A technology dependentparameter

Also, at VDS = 1/ =VAID = 0VAEarly voltage

gO=ID/VA


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Amplifier Gain

In terms of Geometry and VGT

AO= (2L/'VGT)In terms of Drain Current and Geometry

AO= (1/') 2k(W L)/IDThus if the Transistor is biased at a constant current,

the DC Gain is determined by the square root of the

Gate Area.


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1 + srO(Cgd+ CO)

The AC Behaviour

gmvi rO

G

Cgd

Cg CO

vOvi

S

sCgd(vi vO) gmvi (vO/rO) sCOvO= 0

vi(sCgd gm) vO(sCgd+ 1/rO+ sCO)= 0

1 + srO(Cgd+ CO)1 + srO(Cgd+ CO)1 + srO(Cgd+ CO)1 + srO(Cgd+ CO)1 + srO(Cgd+ CO)1 + srO(Cgd+ CO)1 + srO(Cgd+ CO)

So the AC Gain

A1 = vO/vi= gm rO1 sCgd/ gm

1 + srO(Cgd+ CO)


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Bandwidth

A1 = gm rO

1 sCgd/ gm

1 + srO(Cgd+ CO)

Let Ctot= Cgd+ CO

Therefore, A1 AO/(1 + srOCtot)

Then ,A1 = gm rO1 sCgd/ gm

1 + srOCtotNormally, Cgd/gm


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Gain Bandwidth Product

GBW= (gm

rO

)/(rO

Ctot

) = gm

/Ctot

The Gain-Bandwidth product (or the cutoff frequency)

is independent ofrO

Ga

in(dB)

AO

(AO 3 dB)

BW GBW Frequency


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The Current Source

IOIref

Q2

Q1

ID1 = (k'/2)(W/L)1(VGS VT)2

ID1 =Iref= (VDD VGS)/R

IO = ID2 = (k'/2)(W/L)2(VGS VT)2

IOIref

(W/L)2(W/L)1

=

R

VDD


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Current Steering

IOIref

Q2Q1

I2 I1

Q3

Q4Q5


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Attention to Speed / BW

Req Transistor (W/L) ratiop-MOS slower than n-MOSHole mobility < Electron mobility

Pull-UP Higher Resistance

Rise time longer

Make p-MOS widerResistance W/L Ratio

Wp= 2. Wn

Delay Req.CL

CL Transistor Area (W.L)


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SCALING

Reduce Transistor Dimensions (W and L)by a factors

Req unaltered W/L

CL reduced by factors2

Improves Speed

Reduces Dissipation per Signal Transition

Reduce device size Towards nano-MOS


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CHALLENGES OF SCALING

Device Technology

Fabrication Lithography, Etching New Device Configuration

Material Limitations Thin Oxides

Gate Oxide Large Leakage

High-k dielectric

Inter-layer Large parasitic capacitance

Low-k dielectric


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CHALLENGES OF SCALING

Interconnect Technology Line delay limits circuit speed

Optical interconnect Silicon Photonics

Device Physics

Quantum Size Effect

Ballistic Transport Develop New Models


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cmos circuit design

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