cmos design objective questions

7/26/2019 Cmos Design Objective Questions

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OBJECTIVE QUESTIONS

1.Which of the material used as gate

[]

a). photoresistiveb). polysilicon c). metald). glass

2.The ---------- of the V!" chip ranges from pre-assembly #afer preparation tofabricationtechni$ues

for the pac%ages that provide electrical connections and mechanical andenvironmental

protection [

]

a). placement b). &loorplanningc). 'ac%agingd). (one

.------------------ is the electrical consideration for V!" pac%ages []

a) lo# ground resistance . b) short signal leads c) minimum po#er supply spi%ing d)*ll


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+.* ,! transistor #hich has conducting channel region at ero gate bias is called []a) /epletion mode b) 0nhancement mode c) !aturated mode d) (on- saturatedmode

."f pac%ing density area and performance are the constraints2 po#er dissipation is nota constraint2 thetechnology you prefer []

a).34Tb) 5,!c). (,-!d). ',!

6.The speed of the 5,! logic is less #hen compared to other technologies due to []

a) 7igh noise immunityb) 7igh input capacitancec) 7igh driven current d) *ll

*. sin% current is obtained under #hich condition.[]

a.)ogic high inputb) ogic lo# inputc) ogic high outputd) ogic lo# output8.Which logic family has highest speed of operation []

a) TT


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b) /Tc) 05d) *ll the above

9.The partial current :o#ing through p and n channels is called []

a) Voltage spi%esb) current spi%esc) both a and b

d) none of the above1;. -------------- is the non-saturated digital logic family [ ]

a) TTb) 05c) ,! d)


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The di>erent integrator resistance is ?????????????

The di>erent integrator capacitance is ?????????????

The fabrication of 5,! is done by ??????????

/i>usion process is carried out in a ???????????

"on implantation is performed at ????????? temperature

The ions in ion implementation process are accelerated ??????

"on implantation is other techni$ue is ????????????

*bbreviation of 5,! is ????????????

*luminum is used for metalliation of most "5 because ?????????

21.The body e>ect #ill be ??????? if the substrate is /5

22.The e$uation of @mis ????????

2.The output conductance @dsis ???????

2+.The polarities of voltage and current in ',! circuits ??????????

2.The polarities of voltage and current in (,! circuits ??????????

26.5harge moves from ?????? to ??????? #hen Vdsis applied

"dsis dependent on ???????? and ???????????

When voltage is applied on the gate of a ,! transistor channel bet#een source anddrain ????

0lectron transit time is denoted by ????????

The e$uation for velocity V is???????

"n a (,! "nverter the depletion mode transistor ????????

The depletion mode transistor is called ??????????? in (,! inverter

The enhancement mode transistor is called ??????????? in (,! inverter

!lope of the transistor characteristic determines the ????????


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When Vin???????? the './ threshold voltage current

The e$uation for "dsin saturation mode is ????????

The e$uation for "dsin non-saturation mode is ????????

The condition in saturated region is ?????????

The condition in non-saturated region is ?????????

"n 5,! inverter the pull up transistor is ????

,! circuits are formed from the follo#ing basic layers ????????

The layers of the ,! circuits are isolated from each other by ???????.When 'olysilicon and thinoA regions cross each other forms

??????????

@reen colour is used in !tic% diagrams in (,! design for ?????????


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The sheet resistance


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*rea capacitance is given by ???????????

'ermittivity of frees space?????????

!tandard unit of capacitance is denoted by ?????????

!heet resistance is ????????

Enit of sheet resistance is ?????

Typical value of


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logical operations b . test ability c . to%ologial %ro%erties & (nature ofarchitecture+"y bit shifte& out at o"e e"& of &ata or& ill be shifte& i" at theother e"& of the or& is alle&


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e"&-arou"& b( end-o> c. end-less d. end-onI" the V.SI &esig" the &ata a"& o"trol sig"als of a shift register /oi"

hori0o"tally a"& !ertially b( vertically and horiontally c. bothhoriontally d .bothvertically

The subsyste' &esig" is lassi*e& as

a( Frst level b. top level c. bottom level d.leaf-ell le!elThe larger syste' &esig" 'ust be %artitio" i"to a sub syste's&esig" suh that

'i"i'u' i"ter&e%e"&e"e a"& i"ter o"etio" b(compleAity ofinterconnectionc.maAimum interdependence d. arbitarily chosenTo si'%lify the subsyste' &esig", e ge"erally use& the

interdependence b. compleA interconnections c. regular structures d.

sta"&ar& ellsSyste' &esig" is ge"erally i" the 'a""er of

a. do#n-top b. to%-&o" (bottom level only d. top level onlyStruture& &esig" begi"s ith the o"e%t of

hierarhy b( do#n-top design c. bottom level design d. compleA functiondesign+"y ge"eral %ur%ose "-bit shifter shoul& be able to shift i"o'i"g&ata by u% to "u'ber of %laes are

n b. 2n c. "-# &(2n-1

For a four bit or&, a o"e-bit shift right is e1ui!ale"t to a

t#o bit shift left b. three-bit shift left (one bit shift left d. four-bit shift leftThe ty%e of sith use& i" shifters is

line s#itch b. transistor type s#itch c. rossbar sith &(gate s#itch

The lin%ed imagecannot be

displayed. TheFle may havebeen

moved renamed ordeleted.Verify

that thelin% points tothe correct

Fleandlocation.

24( The re%rese"tatio" of basi ell use& i" 'ulti%lier is


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3 lath F+ 3 gate& full a&&er

5 i3 %artial %ro&ut su' i" ,5 3 %artial %ro&ut su' out ,Ci3 arryi",C 3 arry out & 3 li"e re1uire& for to6s o'%le'e"t o%eratio"

he arry hai" i" a&&er is o"sist ith

cross-bar s#ith b. transmission gate c. bus interconncection d. %asstra"sistorsV.SI &esig" of a&&er ele'e"t basially re1uires

0G-< gate (ot and < gates b. 'ulti%le7ers, i"!erter iruit a"&o''u"iatio" %aths

multipleAers 0G-< and (*(/ gates d. inverter circuits and communicationpaths

The heart of the +.U is


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fast response of parallel pass transistors d. fast response of series line

The +.U logial fu"tio"s a" be obtai"e& by a suitable sithi"g ofthe

arry li"e betee" a&&er ele'e"ts b( sum line bet#een adder elements

carry line bet#een shifter H bu>ersum line bet#een shifter H bu>erTo fast a" arith'eti o%eratio"s, the 'ulti%liers a"& &i!i&ers is to usearhiteture of

parallel b. serial c. %i%eli"e& &(s#itched

#9#( 5ro%er %lae'e"t of 'e'ory ele'e"ts 'a)es 'a7i'u' use ofthe

a. a!ailable lo) %erio& b(cost of area c. po#er dessipation d. parasitics+ &esig" that re1uires high &e"sity 'e'ory is usually

a single ship b. on chip c. %artitio"e& i"to se!eral hi%s &(/


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more po#er and slo#ermore po#er and fasterS:+< has a

faster, 'ore %oer a"& larger

slo#er more po#er and largerfaster less po#er and smallerfaster less po#er and largerO" hi% 'e'ory is o'es u"&er the ategory of


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high density memory

'e&iu' &e"sity 'e'ory

lo# density memorylarge density memoryO" hi% 'e'ory usually i" the or&er of

1;% bytes;% bytes#) bytes

1;; % bytesThe si'%lest a"& safest ay to use 'e'ory i" a syste' is to treat it asa

se1ue"tial o'%o"e"t

combinational componentdecoders(< gatesSerial aess 'e'ory at the hi% le!el is lasse& as 'e'ory that has

shift registers

countersaccesstime is independent of location of datainternally stored data is usedThe 5.+ %ro!i&es a syste'ati a"& regular ay of i'%le'e"ti"g

'ulti%le out%ut fu"tio"s of " !ariables i"

'! formSO5 for'

compleA formsimple formV=i"%ut !ariables> X 5=%ro&ut ter's> 5.+ is to 'ai"tai" ge"eralityithi" the o"strai"ts of its &i'e"sio"s the" for

+N; gate ha!e " i"%uts a"& out%ut O: gate 'ust ha!e 5 i"%uts

*(/ gate have ' inputs and output < gate must have n inputs3oth *(/ gate and < gate have n inputsboth *(/ and or gates have ' inputs+


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NO:+ C


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&'@*5'5/standard cells5.+The ge"eral arra"ge'e"t of 5.+ is

+N;?O: struture


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Standard cell areas in CBIC area ___________

Power busses are also known as ___________

Inter connections are ___________ in FPGA.

Device sizes in gate array are ___________.

The small squares on the edge of the cell are raised for ___________


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Connecting data path element to form a data path results in ___________ and

___________ layout than using standard cells

Cross talk results from ___________

Silicon circuitry is connected to outside world by ___________

LUT is used in ___________

In full custom ASIC design all the layers are ___________

FPGA is a ___________

PAL and PLA are known as ___________

The output of a physical design is ___________

IN a PLA ___________ are programmable

The size of an IC is generally measured by ___________

CLB are used In___________

The example of physical defect is ___________

___________ technology is not used in FPGA.

The important design points about SOC are ___________.

Design quality of chip is measured on ___________

The example of electrical fault is ___________

In a post silicon validation testing is done on ___________

In structured gate array ___________ is customized?

The objectives of floor planning are___________

Some VLSI test procedures used are ___________

To increase observability techniques used are___________


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Typical manufacturing defects in IC fabrication are___________

Logical faults generated by electrical faults are ___________

___________ is no used for testing of combinational logic.

Timing failure resulting from delay faults arises due to ___________

The disadvantage of the scan based techniques are___________

Boundary scan techniques used for ___________

The scan based technique ___________ is race and hazard free.

Signature analysis is used In ___________

BIST techniques suffers from ___________

In a BIST technique ORA and PSBRG uses ___________

cmos design objective questions

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