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CMOS High Frequency Circuits for Spin Torque Oscillator Technology TINGSU CHEN Licentiate Thesis School of Information and Communication Technology KTH Royal Institute of Technology Stockholm, Sweden 2014

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CMOS High Frequency Circuits for Spin TorqueOscillator Technology

TINGSU CHEN

Licentiate ThesisSchool of Information and Communication Technology

KTH Royal Institute of TechnologyStockholm, Sweden 2014

TRITA-ICT/MAP AVH Report 2014:01ISSN 1653-7610ISRN KTH/ICT-MAP/AVH-2014:01-SEISBN 978-91-7501-972-7

KTH School of Information andCommunication Technology

SE-164 40 KistaSWEDEN

Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framläggestill offentlig granskning för avläggande av teknologie licentiatexamen i Mikro- ochnanoelektronik torsdagen den 30 jan 2014 klockan 13.00 i Sal E, Forum, KunglTekniska högskolan, Isafjordsgatan 39, Kista.

© Tingsu Chen, Jan 2014

Tryck: Universitetsservice US AB

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Abstract

Spin torque oscillator (STO) technology has a unique blend of features,including but not limited to octave tunability, GHz operating frequency, andnanoscaled size, which makes it highly suitable for microwave and radar appli-cations. This thesis studies the fundamentals of STOs, utilizes the state-of-artSTO’s advantages, and proposes two STO-based microwave systems targetingits microwave applications and measurement setup, respectively.

First, based on an investigation of possible STO applications, the mag-netic tunnel junction (MTJ) STO shows a great suitability for microwaveoscillator in multi-standard multi-band radios. Yet, it also imposes a largechallenge due to its low output power, which limits it from being used as amicrowave oscillator. In this regard, different power enhancement approachesare investigated to achieve an MTJ STO-based microwave oscillator. Theonly possible approach is to use a dedicated CMOS wideband amplifier toboost the output power of the MTJ STO. The dedicated wideband amplifier,containing a novel Balun-LNA, an amplification stage and an output buffer,is proposed, analyzed, implemented, measured and used to achieve the MTJSTO-based microwave oscillator. The proposed amplifier core consumes 25.44mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nmCMOS process. The measurement results show a S21 of 35 dB, maximumNF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as themeasurement results of the proposed MTJ STO-based microwave oscillator,show that this microwave oscillator has a highly-tunable range and is able todrive a PLL.

The second aspect of this thesis, firstly identifies the major difficulties inmeasuring the giant magnetoresistance (GMR) STO, and hence studying itsdynamic properties. Thereafter, the system architecture of a reliable GMRSTO measurement setup, which integrates the GMR STO with a dedicatedCMOS high frequency IC to overcome these difficulties in precise characteriza-tion of GMR STOs, is proposed. An analysis of integration methods is givenand the integration method based on wire bonding is evaluated and employed,as a first integration attempt of STO and CMOS technologies. Moreover, adedicated high frequency CMOS IC, which is composed of a dedicated on-chipbias-tee, ESD diodes, input and output networks, and an amplification stagefor amplifying the weak signal generated by the GMR STO, is proposed, an-alyzed, developed, implemented and measured. The proposed dedicated highfrequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power sup-ply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. Theproposed on-chip bias-tee presents a maximum measured S12 of -20 dB anda current handling of about 25 mA. Additionally, the proposed dedicated ICgives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz.The first attempt to measure the (GMR STO+IC) pair presents no RF signalat the output. The possible cause and other identified issues are given.

Keywords: microwave integrated circuit, CMOS, spin torque oscillator,Balun-LNA, wideband amplifier, on-chip bias-tee, multi-standard multi-bandradios.

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Acknowledgements

My deepest and heartfelt gratitude goes to my supervisor, Prof. Ana Rusu, whohas had the most influence on my ability to do research and to “survive”. Firstly,I appreciate her for providing me the chance to work here as a PhD student underher supervision, bringing me to my favorite field of microwave integrated circuits,and introducing me to Willy Sansen (an exciting moment). I am also deeply grate-ful for her excellent guidance, continuous support, enormous encouragement andimportant advices (and more!) through all the phases of my research. In addition,I am indebted to her for her patience, effort and hundreds of time proofreading mymanuscripts. Her creativity, stringent academic attitude, and profound knowledgemake her an excellent example for me to follow and will have a significant impacton my future career.

I deeply appreciate my co-supervisor, Dr. Saul Rodriguez. I would like to thankhim for all his insightful discussion, valuable advices, and un-ending support. Iappreciate him a lot for sharing with me his knowledge and broadening my mind.This work cannot be completed without his help.

Prof. Johan Åkerman, my other co-supervisor, is warmly thanked for his kindscientific support, valuable discussion and providing me the chance to finish mymeasurement at Göteborgs University.

I gratefully acknowledge Swedish Research Council (VR) for funding my re-search.

I am thankful to all the current and past colleagues in our Electronic Circuits forIntegrated Systems group. Sha Tao and Janko Katic are thanked for their support,encouragement, constructive discussion and all the wonderful moments they shared.I would like to appreciate Dr. Julian Garcia and Vasileios Manolopoulos for theirhelp and support.

A huge thank goes to my officemate and friend, Anders Eklund. Thanks for alldaily discussion related to STO, although it took me quite long time to understandthose physical phenomena. I also want to thank him for his help during the mea-surement and all the time we spent together in the Spincave. Also, tack för brakonserter.

I would also like to thank Prof. Urban Westergren for all the advices relatedto microwave issues and being the internal reviewer of this thesis. Measurementassistance provide by Prof. Gunnar Malm was greatly appreciated. I am gratefulto Prof. Eduard Alarcon for the interesting discussion on circuit design.

I would like to express my appreciation to Prof. Jerzy Dabrowski for the valuablediscussion during the SSOCC conference, and accepting the role as an opponent atmy defense.

I would like to send my warm appreciation to all the persons who help me duringthe measurement. Dr. Fredrik Magnusson, thanks for providing useful suggestion,necessary components and cables. Dr. Sohrab Sani and Philipp Dürrenfeld arethanked for their help and effort. I would also like to thank Fatjon Qejvanaj fordicing the STO samples and the great coffee.

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My appreciation also goes to various people for sharing their helping hands;Dr. Håkan Bengtsson, Dr. Jonas Fritzin and Adam Malmcrona from Ericsson ABfor their valuable discussion and design review; Dr. Martin Gustafsson from TexasInstruments, for his help providing the PLL samples and valuable comments duringthe design.

Gracious appreciation also goes to Prof. Mikael Östling, and Prof. Carl-MikaelZetterling (Bellman), whose brilliant management makes my daily work enjoyableat EKT. Prof Anders Hallén is appreciated for his help with study-related issues.In addition, Gunilla Gabrielsson is thanked for her kindness and help.

I would like to extend my acknowledgement to all my friends in Electrum: YeTian, Jiantong Li, Shi Cheng, Jinghua Xia, Ganesh Jayakumar, Raheleh Hedayati,Saleh Kargarrazi, Maziar Naiini, Markus Soldemo, Xi Chen, Yiting Chen, Yu Xiang,Xinggang Yu, Maryam Olyaei, Yi Feng, Fan Pan, Miao Zhang, Sunjae Chung,Quang Tuan Le and Amir Hossein. I am also thankful to all my other friendsall around the world whose friendship supported and encouraged me during theseyears.

A sincere thank goes to Jie Gao for her support and encouragement all thetime. I would also like to express my appreciation to Kerstin Twardy and MengxueReutelingsperger for being such good friends for 12 years. My special thanks go toAnderson Smith for taking my clouds away and brightening my days.

Ultimately, I would like to acknowledge the people who are the most importantto me, my parents, grandparents, uncles and aunts. Mom and dad, you have beena source of constant support to complete this work. Thank you for standing behindme with your love and support all the time.

Tingsu Chen,Stockholm, Noverber 2013

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Abbreviations and Acronyms

AC Alternating currentASK Amplitude-shift keying

BEOL Back-end-of-line

CCO Current-controlled oscillatorCG Common gateCMOS Complementary metal-oxide semiconductorCoB Chip-on-boardCS Common source

DC Direct current

ESD Electrical static discharge

FF corner Fast-fast cornerFL Free layerFSK Frequency-shift keying

GMR Giant magnetoresistanceGSG Ground-signal-ground

IC Integrated circuitIIP3 Third-order input intercept pointILD Inter-layer dielectricILRO Injection-locked ring oscillatorIR-UWB Impulse radio-UWB

LA Limiting amplifierLLG Landau-Lifshitz-GilbertLNA Low noise amplifierLO Local oscillator

MEMS Microelectromechanical SystemsMIM Metal-insulator-metalMMIC Monolithic microwave integrated circuitMR MagnetoresistanceMTJ Magnetic tunnel junction

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NF Noise figureNM Non-magneticNMOS N-Mental-Oxide-Semiconductor

PA Power amplifierPCB Printed circuit boardPL Polarized layerPLL Phase-locked loopPSRR Power supply rejection ratio

Q Quality factor

RF Radio frequencyRMS Root mean squareRX Receiver

SMA SubMiniature version ASNR Signal-to-noise ratioS-parameters Scattering-parametersSRAM Static random-access memorySRF Self-resonant frequencySS corner Slow-slow cornerSTO Spin torque oscillatorSTT Spin transfer torqueSTT-MRAM Spin transfer magnetoresistive random-access memorySV Spin valve

TMR Tunnel magnetoresistanceTSV Through-silicon viaTX Transmitter

UWB Ultra-wideband

VCO Voltage-controlled oscillatorVDD Power supply voltageVG Voltage gainVSWR Voltage standing wave ratio

Contents

Contents ix

List of Figures xi

List of Tables xiii

1 Introduction 11.1 Background on microwaves . . . . . . . . . . . . . . . . . . . . . . . 11.2 Spin Torque Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.5 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.6 Contributions and Publications . . . . . . . . . . . . . . . . . . . . . 8

1.6.1 Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Spin Torque Oscillators Overview 112.1 Background on STO . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.1 Spin Transfer Torque . . . . . . . . . . . . . . . . . . . . . . . 112.1.2 Magnetoresistance . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3 State-of-the-art MTJ STOs . . . . . . . . . . . . . . . . . . . . . . . 152.4 State-of-the-art GMR STOs . . . . . . . . . . . . . . . . . . . . . . . 172.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 STO-based System Architectures 213.1 STO applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1.1 Current-controlled modulator . . . . . . . . . . . . . . . . . . 223.1.2 Microwave frequency detector . . . . . . . . . . . . . . . . . . 223.1.3 Magnetic field sensor . . . . . . . . . . . . . . . . . . . . . . . 233.1.4 Microwave oscillator . . . . . . . . . . . . . . . . . . . . . . . 24

3.2 MTJ STO-based microwave oscillator architecture . . . . . . . . . . 243.2.1 Impedance matching . . . . . . . . . . . . . . . . . . . . . . . 253.2.2 Bandwidth and gain . . . . . . . . . . . . . . . . . . . . . . . 25

ix

x CONTENTS

3.2.3 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.2.4 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.2.5 System architecture of the MTJ STO-based microwave oscil-

lator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.3 System architecture for GMR STO measurement setup . . . . . . . . 27

3.3.1 Issues in current measurement setup of GMR STO . . . . . . 273.3.2 Circuit requirements for GMR STO measurement setup . . . 293.3.3 System architecture of GMR STO measurement setup . . . . 34

4 CMOS Wideband Amplifier for MTJ STO 354.1 Balun-LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.1 Theoretical Design-Oriented Analysis . . . . . . . . . . . . . 364.1.2 Simulation results of the proposed Balun-LNA . . . . . . . . 404.1.3 Stand-alone Balun-LNA . . . . . . . . . . . . . . . . . . . . . 41

4.2 Wideband Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.3 Measurement Results and Discussion . . . . . . . . . . . . . . . . . . 45

4.3.1 Stand-alone Balun-LNA . . . . . . . . . . . . . . . . . . . . . 454.3.2 Wideband amplifier . . . . . . . . . . . . . . . . . . . . . . . 484.3.3 MTJ STO-based microwave oscillator . . . . . . . . . . . . . 51

5 CMOS Circuits for GMR STO Measurement Setup 555.1 On-chip bias-tee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555.2 On-chip ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . 575.3 Input and Output Networks . . . . . . . . . . . . . . . . . . . . . . . 585.4 Amplification Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595.5 Post-layout Simulation Results . . . . . . . . . . . . . . . . . . . . . 625.6 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.6.1 Dedicated high frequency IC . . . . . . . . . . . . . . . . . . 635.6.2 GMR STO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665.6.3 GMR STO measurement setup . . . . . . . . . . . . . . . . . 67

5.7 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695.7.1 Process variation of STOs . . . . . . . . . . . . . . . . . . . . 695.7.2 Pad structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 695.7.3 Wire bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . 715.7.4 Measurement setup stability . . . . . . . . . . . . . . . . . . . 725.7.5 Bias-tee reliability . . . . . . . . . . . . . . . . . . . . . . . . 72

6 Conclusions and Future Work 75

Bibliography 79

List of Figures

1.1 Illustration of the status and trends in microwave technology. (a) Multi-tasking works on a cell phone using microwave technology (b). World-wide microwave equipment market revenue and forecast . . . . . . . . . 2

1.2 MTJ STO-based receiver (a). MTJ STO as an LO (b). STO as a partof a PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 IC design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 A typical STO structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2 Magnetoresistance effect (a). parallel state; (b). anti-parallel state . . . 132.3 Measured MR in MTJ STO . . . . . . . . . . . . . . . . . . . . . . . . . 142.4 Layouts of (a).pads for MTJ STO and (b).coplanar waveguide for GMR

STO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.5 Operation frequency of MTJ STO as a function of the applied magnetic

field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.6 Operation frequency of MTJ STO as a function of the injected DC current 162.7 Measured MR in GMR STO . . . . . . . . . . . . . . . . . . . . . . . . 182.8 Operation frequency of GMR STO as a function of the DC current and

the magnetic field strength with a fixed magnetic field angle of 85o (a).H = 0.7 T (b). H = 0.8 T (c). H = 0.9 T (d). H = 1 T . . . . . . . . 19

3.1 STO-based non-coherent IR-UWB transceiver . . . . . . . . . . . . . . . 233.2 Power transfer from MTJ STO to amplifier . . . . . . . . . . . . . . . . 263.3 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.4 Current GMR STO measurement setup . . . . . . . . . . . . . . . . . . 283.5 Possible integration methods between STO and CMOS IC . . . . . . . . 303.6 Bond wire (a). the lump model (b). the simulated microwave performance 333.7 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1 Proposed Balun-LNA with capacitive cross-coupling technique . . . . . 364.2 Small signal model of cascoded CS stage . . . . . . . . . . . . . . . . . . 374.3 Relationship between gm1, R1 (gain) and noise . . . . . . . . . . . . . . 394.4 (a). NF as a function of RS ; (b). Input reflection coefficient (Γin) as a

function of time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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xii List of Figures

4.5 Simulation results of the proposed LNA (a).Voltage gain and input re-turn loss (b).Noise Figure (c).Linearity (d).Monte Carlo simulation re-sults for process variation . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.6 Schematic of the stand-alone Balun-LNA with output buffer . . . . . . . 434.7 Block diagram and schematics of the proposed wideband amplifier . . . 434.8 Chip photo of the stand-alone Balun-LNA . . . . . . . . . . . . . . . . . 454.9 Test board for the stand-alone Balun-LNA . . . . . . . . . . . . . . . . 464.10 Post-layout simulated and meausred S21 and S11, simulated and de-

embedded VG of the Balun-LNA core . . . . . . . . . . . . . . . . . . . 464.11 Post-layout simulated, measured and de-embedded NF of the buffered

Balun-LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.12 Die photo of the proposed wideband amplifier IC . . . . . . . . . . . . . 494.13 Test board for the wideband amplifier IC . . . . . . . . . . . . . . . . . 494.14 Measurement results of the proposed wideband amplifier (a). Measured

S11, S22 (b). Measured S21 and De-embedded NF . . . . . . . . . . . . 504.15 Measurement setup of the MTJ STO-based microwave oscillator . . . . 514.16 Measurement results of the MTJ STO-based microwave oscillator . . . . 52

5.1 On-chip Bias-tee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565.2 ZAC and ZOX as a function of Cblock . . . . . . . . . . . . . . . . . . . . 575.3 On-chip ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 585.4 Input network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595.5 Output network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605.6 Amplification stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605.7 Zload as a function of Lln . . . . . . . . . . . . . . . . . . . . . . . . . . 625.8 (a). Die photo of the proposed high frequency IC (b). Test board for

GMR STO measurement setup . . . . . . . . . . . . . . . . . . . . . . . 635.9 Measured S12 of the on-chip bias-tee . . . . . . . . . . . . . . . . . . . . 645.10 Measurement results of the proposed high frequency CMOS IC for GMR

STO: (a). Voltage gain (b). Input referred noise (c). IIP3 . . . . . . . . 655.11 Integration of GMR STO and dedicated high frequency IC . . . . . . . 675.12 Measurement setup of the (GMR STO+IC) pair . . . . . . . . . . . . . 685.13 Pad structures of (a). GMR STO and (b). the dedicated IC . . . . . . 705.14 Issue of wire bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715.15 Resistance increase as a function of time (IDC = 25 mA) . . . . . . . . 73

List of Tables

3.1 Performance metrics of MTJ STO . . . . . . . . . . . . . . . . . . . . . 253.2 GMR STO (70 nm) Summary . . . . . . . . . . . . . . . . . . . . . . . . 293.3 Comparison between different integration methods . . . . . . . . . . . . 32

4.1 Comparison with previous Balun-LNA designs . . . . . . . . . . . . . . 484.2 Performance comparison: MTJ STO+amplifier IC pair . . . . . . . . . . 53

5.1 GMR STO characterization . . . . . . . . . . . . . . . . . . . . . . . . . 66

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Chapter 1

Introduction

1.1 Background on microwaves

Microwave technology has had a dramatic impact on wireless high-speed commu-nications. Microwaves are electromagnetic waves whose frequencies f are usuallydefined from 300 MHz to 300 GHz [1], and their corresponding wavelengths λ arebetween 1m to 1mm according to:

λ = c

f(1.1)

where c is the speed of the light. As the wavelengths of microwaves are rela-tively short, they are named as “micro”waves. Based on Shannon’s Theorem, thelarge bandwidth that can be obtained at microwave frequencies, offers a very largechannel capacity, enabling high-speed communications. In addition, microwave fre-quencies allow high directivity and small antenna sizes [2], which enables compactdesign of microwave devices. Because of these advantages, microwaves were firstlyemployed in the military, for instance, radar communications, astronomy, aerospaceproducts, etc. Nowadays, microwave technology is further integrated into our dailylives. It enables us to simply use smart microwave devices to instantly communicatewith other people or devices all around the world. For instance, people can use cellphones not only for making and receiving global calls, but also for sharing data orcontrolling other devices in different ranges, as illustrated in Figure 1.1(a). More-over, the large bandwidth enables us to communicate with several other devicessimultaneously, which forms a multi-task communication system. This multi-tasksystem is based on building microwave links between microwave devices by access-ing different networks, such as WiFi, bluetooth, cellular and satellite networks andusing different bands and standards. In this multi-task communication system, adata rate of over 1 Gb/s can be currently achieved [3].

In addition to wireless high-speed communications, microwave technology presentsa variety of applications, such as remote sensing and medical treatment. This wideapplication prospect of the microwave technology has stabilized its important posi-

1

2 CHAPTER 1. INTRODUCTION

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2008 2009 2010 2011 2012 2017

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Figure 1.1: Illustration of the status and trends in microwave technology. (a)Multi-tasking works on a cell phone using microwave technology (b). Worldwidemicrowave equipment market revenue and forecast

1.2. SPIN TORQUE OSCILLATOR 3

tion in the modern society. Over the last few years, there was a long-term demandof the microwave technology, which is reflected by the microwave equipment mar-ket given in Figure 1.1(b). By 2017, the latest forecast of Infonetics [4] showsthat the microwave equipment market will remain stable. This steady global mi-crowave equipment market continuously pushes the microwave industry to deliverhigh performance, low-cost and small-size components, which are appropriate formulti-band or multi-standard systems. Among these microwave components, themicrowave oscillator is a key component. It is essential in all communications, testor measurement systems, providing critical clocking or generating the carrier orlocal oscillator (LO) signal [5] for the purpose of converting a signal frequency upand down. In order to satisfy modern applications, a microwave oscillator shouldbe widely tuned to cover a multi-frequency range. At the same time, the desiredmicrowave oscillator should be easily integrated with CMOS technology, which isstill the mainstream integrated circuit (IC) technology. Furthermore, high opera-tion frequency, high quality-factor, high stability, low cost, low power consumptionand miniature size are also requirements of modern microwave oscillators. How-ever, the typical off-chip quartz crystal oscillator is no longer suitable in moderncommunication systems due to its large dimension, high power consumption, lowintegration level, and low quality factor (Q) at high frequencies. CMOS fully inte-grated LC voltage-controlled oscillator (VCO) [6] is widely used for its low phasenoise and low power consumption. However, the integrated oscillators have verypoor quality factor, and their tunability is not sufficient for microwave applications.The monolithic microwave integrated circuit (MMIC) based oscillator is becomingmore and more popular since it offers wide tunability and low phase noise. Never-theless, MMICs consume high power with low efficiency, occupy a large silicon areaand are expensive. Accordingly, there is an urgent need of low cost and low powermicrowave oscillators with high operating frequency and large tunability to coverwide bandwidths.

1.2 Spin Torque Oscillator

Spin torque oscillator (STO) is attracting widespread interest due to its potentialuse as a microwave oscillator. The STO operation is based on two spintronic effects:spin transfer torque (STT) and magnetoresistance (MR). The STT effect generatesa precession of the magnetization in STOs, conducting the oscillation of eithertunneling magnetoresistance (TMR) or giant magnetoresistance (GMR). An STOwith TMR is called magnetic tunnel junction (MTJ) STO and an STO with GMRis named spin valve (SV) STO (or so called GMR STO) [7]. Compared to GMRSTOs, MTJ STOs offer a larger output power thanks to larger MR at the expenseof somewhat lower operation frequencies. Unfortunately, MTJ STOs have widerlinewidth than GMR STOS, hence worse spectrum purity.

STO is a tunable nanoscale microwave integrated current-controlled oscillator(CCO), which offers extremely wide tunability. The operation frequency of STO

4 CHAPTER 1. INTRODUCTION

can be tuned by either the DC current injected into the device, or the magneticfield applied to the device. For instance, a single MTJ STO can be used as an LOcovering 3 GHz - 9 GHz bandwidth (|H| < 1000 Oe) in ultra-wideband (UWB)applications [8]. Obviously, its frequency tunability range of ±50% exceeds that ofLC based oscillators which typically show tunability ranges of around ±10%. Theoperation frequency of a single GMR STO can be tuned by the DC biasing currentbetween 10 GHz - 21 GHz with a tunability range of ±35.5% with a fixed magneticfield of H = 1 T and a magnetic angle of 80. Additional frequency tunability canbe achieved by changing the strength or angle of the applied magnetic field. Theoperation frequency of GMR STOs has been experimentally observed up to 46 GHzand extrapolated to 65 GHz. Besides the wide tunability, STO also has miniaturesize, high operation frequency, high integration level with CMOS technology, lowcost, low power consumption, and high Q (up to 18000), which make it a promisingmicrowave oscillator [9]. However, the immature STO technology has currently twodrawbacks which prevent them from being directly used as LOs. These drawbacksare: low output power and spectrum impurity [9]. The maximum output powerthat can be obtained from a MTJ STO is in the order of microwatts, and is evenless for a GMR STO. The spectrum impurity of STO occurs in terms of substantialfrequency fluctuations, and is not acceptable for most LO applications.

1.3 Motivation

While the STO is a promising technology for low-cost fully integrated microwaveoscillator, its low output power and spectrum impurity are, as described before, twocurrent drawbacks. The aim of this work is to alleviate these drawbacks such thatthe STO technology can be used in real wireless communication systems. To provethat concept, the target of this work is to use the STO in a receiver, as shown inFigure 1.2(a). However, this system is applicable only when the STO is oscillatingwithout frequency fluctuations. One possible solution to this current frequencyfluctuation issue is to lock the frequency and phase of a STO in a Phase-lockedloop (PLL) system, as it can be seen in Figure 1.2(b). To make the PLL systemfunctional, the output power of the STO should be larger than -10 dBm. TheMTJ STO can currently provide a much larger output power than the GMR STO,which makes it more suitable for being used as an LO. A typical state-of-the-artMTJ STO produces an output power of approximately 0.5 µW within a tunableoperation frequency range between 4 GHz - 7 GHz [10], which restricts their directuse as LOs. Consequently, it is of great importance to enhance the output powerof MTJ STOs for future STO-based applications.

One possible approach to improve the output power of MTJ STOs is usinginjection locking. It has been experimentally verified that MTJ STOs can be lockedto an external RF current with a frequency fe, which is close to twice the free-running frequency f0 [7]. By using an external RF current with 2.1 mA RMSamplitude, the output power of the MTJ STO is enhanced by 7 dB while the

1.3. MOTIVATION 5

Filter

Antenna

MixerLNA

STO

Filter

Antenna

MixerLNA

V/IAmplifier

CP/LPFPFD

Freq. Divider

REFinBias-T

STO

(a)

(b)

Bias-T

Figure 1.2: MTJ STO-based receiver (a). MTJ STO as an LO (b). STO as a partof a PLL

phase is locked during injection locking. Nevertheless, this approach cannot beimplemented in real applications since an external RF current is needed, and the 7dB power enhancement is not sufficient for applications.

An alternative approach is to use an external amplifier IC to enhance the outputpower of MTJ STOs and prove their potential use as microwave oscillators [11]. Asshown in Figure 1.2(b), a wideband amplifier, covering the operation frequencyrange of MTJ STO with noise, linearity and matching optimization, is required toamplify the output signal of MTJ STO and make it usable in the receiver system.This alternative is more suitable for the current STO technology since it can offerthe required gain and facilitate the future connection to other CMOS circuits suchas PLL or mixer.

Recently, GMR STOs received a lot of attention thanks to their larger tunabilityrange and higher operation frequencies. Numerous studies of GMR STOs have beendone to explore the phase noise and linewidth, to increase the output power, and toremove the large applied magnetic field. However, the existing measurement setupfor GMR STO is usually built by commercial discrete components, which is notoptimal in terms of power and noise. For instance, the cables and connection loss

6 CHAPTER 1. INTRODUCTION

between STO and bias-tee, bias-tee and amplifier, amplifier and spectrum analyzerat such high frequency is significant. In order to minimize the unwanted signalloss in the measurement setup, the GMR STO needs to be integrated with theCMOS IC to avoid losses from printed circuit board (PCB), external bias-tee andpackaging. As a result, an integrated solution of GMR STOs and their dedicatedhigh frequency CMOS circuits, including a wideband on-chip bias-tee and low-noiseamplification, are urgently required.

As detailed in the following section, proposing high frequency IC solutions forSTO technology, in order to make MTJ STOs usable in applications, and improvethe measurement setup for GMR STOs for future STO studies, have been the maindrivers for this work.

1.4 Objectives

The main focus of this thesis is investigating high frequency IC solutions for STOtechnology. As discussed in Section 1.3, two STO-based systems are proposed inthis work, considering the different properties of the MTJ STO and the GMR STO.

Firstly, the exploration of wideband amplifiers, which enable the use of a sin-gle, highly tunable MTJ STO as an LO in a multi-band, multi-standard receiversystem, is considered. The objective is to propose a wideband amplifier solution tocompensate the low output power of the MTJ STO. To achieve this objective, thecircuit requirements are identified, based on which a wideband low-noise amplifieris proposed, developed and implemented.

Secondly, the integration of CMOS ICs and GMR STOs, which is particularlyimportant for improving the measurement setup and for further studies of STOtechnology, is proposed. Accordingly, the objective is to propose a solution forGMR STO fully integrated with a dedicated CMOS high-frequency IC. To achievethis objective, the following sub-objectives are identified. Firstly, possible integra-tion methods are investigated and the most suitable integration method for thecurrent STO technology is chosen. Second sub-objective is to identify the circuitrequirements for improving the measurement setup for GMR STOs, based on thestate-of-the-art GMR STOs and the proposed integration method. Thirdly, thecomplete IC solution, including the on-chip bias-tee, is implemented to achievefully integration and enhance the low output power of GMR STOs.

The top-down ASIC design flow, illustrated in Figure 1.3, is used to implementthe IC solutions for STO technology. It can be seen in Figure 1.3 that differentcircuit requirements for MTJ and GMR STOs are identified based on separateinvestigations of these two types of STOs and integration methods. Accordingto the identified circuit requirements, ICs are designed by following theoreticalstudies, simulations, anaylses and implementations. Finally, in order to evaluatethe designed ICs and prove the concepts given in Section 1.3, high-frequency test-boards for the IC and STO+IC measurements are developed.

1.5. THESIS OUTLINE 7

ASIC Design Flow

STO Technology

MTJ GMR

MTJ STO performances

System/Architecture Design

Circuit Design

Floor Plan, Layout and Verifications

System Verification

Fabrication and Measurement

GMR STO performances

Inter-connection

System Measurement

Figure 1.3: IC design flow

1.5 Thesis Outline

The thesis is organized in six chapters, by following the design flow mentioned inthe previous section.• Chapter 1 describes the motivation, objectives, outline and contributions of

this work.• Chapter 2 presents the background of this work, including the STO operat-

ing principle, classification and state-of-the-art performance. By investigating thestate-of-the-art STOs, this chapter identifies the superiority of STOs as well as theirmain issues.• Chapter 3 investigates possible microwave applications of STO technology.

The most suitable application is the MTJ STO-based microwave oscillator. Be-sides, in order to build a reliable measurement setup for GMR STOs and henceenable further STO studies, the issues of the existing measurement setup were iden-tified. To achieve the proposed MTJ STO-based microwave oscillator and a reliableGMR STO measurement setup, this chapter further identifies the requirements ofthe dedicated CMOS ICs and proposes the architectures for these two STO-basedmicrowave systems. This chapter provides the circuit design fundamentals for thefollowing two chapters.• Chapter 4 presents the proposed wideband amplifier targeting MTJ STOs.

8 CHAPTER 1. INTRODUCTION

The wideband amplifier design consists of a novel Balun-LNA, limiting amplifier(LA) chain and an output buffer. The detailed development of the novel Balun-LNAis demonstrated in this chapter. Measurement results of the implemented Balun-LNA, complete wideband amplifier, as well as the STO-ASIC pair, are illustrated.• Chapter 5 presents the integration of the GMR STO and high frequency

CMOS ICs. This chapter investigates possible integration methods and proposes amethod for current STO technology. Based on the proposed integration method,this chapter focuses on a dedicated high frequency IC for GMR STOs, consistingof an on-chip bias-tee, ESD protection, input and output networks and an amplifi-cation stage. The detailed development and measurement results of the proposedIC and the entire integrated solution for GMR STO-IC are given in this chapter.• Chapter 6 draws the conclusions and identifies the future work.

1.6 Contributions and Publications

In order to meet the thesis objective of enabling MTJ STOs’ use as microwaveoscillators, possible power enhancement techniques for MTJ STOs have been in-vestigated. Based on this investigation, a wideband amplifier IC solution has beenproposed to enhance the low output power of MTJ STOs, while optimizing thenoise performance within a large portion of its tunability range. This proposedwideband amplifier consists of three stages: a Balun-LNA as input stage, followedby the amplification stage and the output buffer stage. A new Balun-LNA topologytargeting MTJ STOs was proposed and implemented in 65 nm CMOS. The mea-surement results show 20 dB of gain, 2 GHz - 7 GHz bandwidth, and noise figurebelow 5 dB while consuming 3.84 mW from a 1.2 V power supply. This Balun-LNAis highly tolerant to the time-variant impedance changes expected from the MTJSTO devices. Due to the use of inductorless design techniques, the Balun-LNAis very compact and occupies a total area of only 0.0044 mm2. The amplificationstage is realized by cascading five cascode stages to achieve large gain and a CSstage to achieve large output swing. The output buffer employs an adder to com-plete balance-to-unbalance conversion for the measurement purpose. Besides, itprovides a 50 Ω output impedance matching for further connection to other exter-nal blocks. The measured S11 and S22 of the proposed wideband amplifier IC areapproximately -10 dB. The de-embedded S21 is 35 dB, and a maximum NF of 5 dBis achieved in the bandwidth of 2 GHz - 7 GHz. The proposed amplifier has beenconnected to and measured with a MTJ STO. By connecting the proposed amplifierdirectly to a MTJ STO with a maximum output power of -40 dBm, an integratedpower larger than -10 dBm can be obtained at the output of the STO-amplifierchain. The output power of the MTJ STO-amplifier pair can be used to drive aPLL.

To overcome the current difficulties in measuing GMR STOs and to build a reli-able measurement setup for GMR STOs, an efficient approach of integrating GMRSTOs and its dedicated CMOS circuits has been proposed. Possible solutions of

1.6. CONTRIBUTIONS AND PUBLICATIONS 9

integrating GMR STOs and CMOS circuits have been investigated and a wire bond-ing method has been employed in this work since it is flexible, cheap and suitable forthe current STO technology. The dedicated CMOS high frequency ICs for GMRSTOs are determined by the wire bonding integration method, and proposed toprovide on-chip DC biasing, ESD protection and wideband pre-amplification forGMR STOs. The proposed IC is composed of a bias-tee, ESD diodes, input andoutput networks and an amplification stage. It is implemented in 65 nm CMOS,consumes 14.3 mW from a 1.2 V power supply, and occupies a total silicon areaof 0.329 mm2. The on-chip bias-tee is a key component for full integration and ithas a measured isolation of more than 20 dB between the AC port and DC port,covering a bandwidth larger than 17 GHz and handling a maximum DC currentof 25 mA. In addition, measurement results of the fully-ESD protected dedicatedIC show a measured voltage gain of 13 dB with a -3 dB bandwidth of 12.5 GHz -14.5 GHz. These measurement results of the dedicated IC show its potentiality toprovide the required DC biasing, ESD protection and amplification to GMR STOs.

1.6.1 Publications

This thesis is part of a collaboration project on Spin Torque Oscillator (STO)technology. The STO devices have been provided by the partners. The author hasproposed, analyzed, developed and implemented all CMOS circuits, test-boards,and measurement setups, and has performed the necessary chip measurements. Inaddition, the author has measured, together with the partners, the STOs used inthis work and the (STO+CMOS IC) pairs.

This research has resulted in the following publications and manuscripts. Partof the material has been published in peer-reviewed international conference pro-ceedings.• T. Chen, S. Rodriguez, A. Rusu, “Wideband Amplifier Design for Magnetic

Tunnel Junction Based Spin Torque Oscillators”, in Proc. of GigaHertz Symposium2012, Stockholm, Sweden, March 2012.

Author’s contribution: 100% theoretical analysis, 100% IC design, 90% of writ-ing the manuscript.• T. Chen, S. Rodriguez, E. Alarcon, A. Rusu, “A 2 GHz - 8.7 GHz Wideband

Balun-LNA with Noise Cancellation and Gain Boosting”, in Proc. of IEEE PRIME2012, pp. 59-62, Aachen, Germany, June 2012.

Author’s contribution: 100% theoretical analysis, 100% IC design, 70% of writ-ing the manuscript.• T. Chen, P. Dürrenfeld, S. Rodriguez, J. Åkerman, A. Rusu, “A Highly-

Tunable Microwave Oscillator Based on MTJ STO Technology”, manuscript 2013.Author’s contribution: 100% theoretical analysis, 100% IC design, 100% of

the CMOS amplifier IC measurement, 50% of the (MTJ STO+amplifier IC) pairmeasurement, 90% of writing the manuscript.

10 CHAPTER 1. INTRODUCTION

• T. Chen, A. Eklund, S. Rodriguez, J. Åkerman, A. Rusu, “Integration ofHigh Frequency CMOS Circuits and Giant Magnetoresistance-based Spin TorqueOscillator Technology”, manuscript 2013.

Author’s contribution: 100% theoretical analysis, 100% IC design, 100% of thededicated CMOS IC measurement, 50% of the (GMR STO+IC) pair measurement,95% of writing the manuscript.• T. Chen, S. Rodriguez, A. Rusu, “A 2 GHz - 7 GHz Wideband Balun-LNA”,

manuscript 2013.Author’s contribution: 100% theoretical analysis, 100% IC design, 90% of mea-

surement, 80% of writing the manuscript.

Chapter 2

Spin Torque Oscillators Overview

2.1 Background on STO

As described in Chapter 1, STO technology attracted a lot of attention in recentyears since it opened the possibility of a new nanoscale source of microwaves thanksto its advantages. The operation princple of this nanoscaled STO is based on twospintronic effects: spin transfer torque (STT) and magnetoresistance (MR). Theseeffects are detailedly explained in this chapter.

2.1.1 Spin Transfer Torque

The idea of STT has been first predicted by John Slonczewsk [12] and Luc Berger[13] in 1996, which can be explained as: in a magnetic multilayer device, the angularmomentum can be transferred by electron currents from one magnetic layer toanother, which exerts a torque on the local magnetization. By using this transferredtorque, the magnetization can keep sustained oscillation at microwave frequenciesunder specific conditions. This prediction was then experimentally verified by Tsoiin 2000 [14] by detecting microwave oscillations in a magnetic multilayer device. Atypical multilayer structure of STO is shown in Figure 2.1 [9] : it uses two magneticlayers, which are isolated by a thin spacer or so called non-magnetic (NM) layer.The magnetic layer with fixed magnetization is called polarized layer (PL) andthe other magnetic layer whose magnetization is free to rotate is called free layer(FL). With an unpolarized current injected into the sandwich structure illustratedin Figure 2.1, a spin-polarized current is generated on PL, conducting to the STTeffect. This STT effect transfers the spin momentum to FL, applying the torqueon the local magnetization to compensate the magnetization damping precessionin the magnetic thin film device, which is described by the Landau-Lifshitz-Gilbert(LLG) equation [15] :

dMdt = −γM×Heff + αM× dM

dt , (2.1)

11

12 CHAPTER 2. SPIN TORQUE OSCILLATORS OVERVIEW

Free layer (FL)

Polarized layer (PL)

Spacer(NM)

Figure 2.1: A typical STO structure

where γ is the gyromagnetic ratio; α is the damping parameter; M is the magneti-zation with the precessional motion; Heff is the effective magnetic field on FL. Themagnetization can undergo sustained oscillation when the magnetization dampingis balanced out by STT [16]. To conclude, the STT effect consists of keeping the pre-cession of magnetization of a nano-scaled magnetic layer by using a spin-polarizedcurrent. This interesting effect has been used to develop several novel spintronicdevices. For example, the STT effect is employed in the spin transfer magnetore-sistive random access memory (STT-MRAM), which outperforms SRAM in termsof power consumption and cost. In order to develop STO devices, another effect ofmagnetoresistance is necessary to be combined with the STT effect.

2.1.2 Magnetoresistance

In a magnetic thin-film device with alternating ferromagnetic and NM conductivelayers, the electrical resistance of this device is a function of the magnetization ormagnetic field [16]. This effect is called the MR effect. By injecting a DC currentinto the STO sandwich structure, the STT effect, as described above, is conductedto keep the precession of magnetization by changing the orientation of the magne-tization. As a result, this steady-state magnetization precession and the magneticfield applied on STO causes a periodic variation of the MR value. In another words,the value of MR is a function of the DC current injected into STO and a function ofthe applied magnetic field. When the relative magnetization orientations of thesetwo ferromagnetic layers are aligned as shown in Figure 2.2(a) [17], this state iscalled parallel state. In this state, the electrons can pass through the spacer easily

2.1. BACKGROUND ON STO 13

(a) (b)

Free layer (FL)

Polarized layer (PL)

IDC

Unpolarized current

NM

Free layer (FL)

Polarized layer (PL)

IDC

Unpolarized current

NM

Figure 2.2: Magnetoresistance effect (a). parallel state; (b). anti-parallel state

since they do not need to change the form of their wavefunctions [16]. Consequently,STO reveals the lowest resistance value during the magnetization precession, whichis called parallel state and represented by RP . When the relative orientations of themagnetization between the free layer and fixed layer are anti-aligned as shown inFigure 2.2(b), this state is called anti-parallel state. In this state, the highest levelof electrons reflection results in the largest resistance value during magnetizationprecession. RAP is used to represent the resistance value in the anti-parallel state.This periodic variation of the MR value (between RP and RAP ) can be furtherconsidered as an electrical resistance value of STO oscillating around a DC valueRDC . The time-variant part of the resistance, which is caused by the relative ori-entation of magnetization changes, can be regarded as a high frequency term RAC .The electrical resistance of STO, RS , can be then expressed by [17, 18]:

RS = RDC +RAC ·cos(2πf ·t) (2.2)

where f is the operation frequency of STO. The relationships between RDC , RAC

and RAP , RP can be described by:

RDC = RAP +RP

2 (2.3)

andRAC = RAP −RP

2 (2.4)

As it can be seen in Figure 2.3, for a typical MTJ STO measured at KTH, RP andRAP are 38 Ω and 64 Ω, respectively. The calculated RDC and RAC are 51 Ω and13 Ω, respectively.

14 CHAPTER 2. SPIN TORQUE OSCILLATORS OVERVIEW

Figure 2.3: Measured MR in MTJ STO

The output power of STO is a function of RAC/RDC , which is expressed by [9]:

Pout = (RAC

RDC)2· β

(1 + β)2 ·RDC ·I2DC (2.5)

where β is the impedance matching ratio and IDC is the DC current injected intoSTO. The maximum power can be obtained when the impedance seen from theoutput of STO is matched to RDC .

The MR coefficient (or sometimes called “MR ratio”) given by [9]:

MRratio = RAP −RP

RP(2.6)

is also used to characterize the MR effect of STO or to predict the output power ofSTO.

By combining the STT and MR effects, the oscillation of STO can be sustainedat several gigahertz and can be tuned by both IDC and the applied magnetic field.

2.2 Classification

Based on the type of the barrier or the spacer layer, given in Figure 2.2, STOs canbe classified into MTJ STOs and GMR STOs [9, 16]. The spacer layer in MTJ andGMR STOs is thin insulator and thin metallic spacer, respectively. This structuredifference in different STOs determines different biasing conditions and dynamic

2.3. STATE-OF-THE-ART MTJ STOS 15

performances in MTJ and GMR STOs. Detailed RF performances of these twotypes of STO are studied separately in the following section.

For the measurement purpose in this work, the MTJ STO is embedded intosignal-ground RF pads as shown in Figure 2.4(a) and the GMR STO is placed ona ground-signal-ground (GSG) coplanar waveguide as illustrated in Figure 2.4(b).

(b)(a)

G S

SG G

Figure 2.4: Layouts of (a).pads for MTJ STO and (b).coplanar waveguide for GMRSTO

2.3 State-of-the-art MTJ STOs

State-of-the-art MTJ STOs are based on CoFeB/MgO/CoFeB composition struc-ture [8, 9], since MTJ STOs with this structure exhibit relatively large magnetore-sistances, and hence large microwave powers. According to Eq.(2.5), an MTJ STOwith a 51 Ω RDC (given in section 2.1) is able to provide a -12.5 dBm output powerin theory, assuming that the impedance is matched at the output of the STO. Yet,the combination of power losses in the measurement setup and other effects in theSTO [19] causes a large discrepancy between the theoretically calculated outputpower and the measured output power. The experimentally observed output poweris significantly lower than the expected output power, and is usually between -60dBm and -40 dBm. Additionally, the maximum measured output power of the MTJSTO is on the order of microwatts [20]. Accordingly, this low level of the outputpower prevents the MTJ STO being directly used as a microwave oscillator.

As mentioned before, an important advantage of using MTJ STOs as microwaveoscillators is that they can be simply tuned to cover a large part of the UWB fre-quency range. The measured tunability from a circular MTJ STO with an approx-imate diameter of 240 nm, is given in Figure 2.5 [8]. It can be seen from Figure 2.5that by changing the applied magnetic field, the operation frequency of the MTJSTO can be widely and linearly tuned from 3 GHz to 9 GHz. Additional tunabilitycan be achieved by altering the DC current, as illustrated in Figure 2.6. To protectthe tunnel barrier of MTJ STO from being broken by a large DC current, the DCcurrent injected into the MTJ STO should be limited to e.g. 10 mA. Figure 2.6illustrates that an additional 0.5 GHz tunable range can be obtained by tuning the

16 CHAPTER 2. SPIN TORQUE OSCILLATORS OVERVIEW

Figure 2.5: Operation frequency of MTJ STO as a function of the applied magneticfield

0 2 4 6 84

4.5

5

5.5

6

6.5

Current (mA)

f (G

Hz)

5

10

15

20

25

Figure 2.6: Operation frequency of MTJ STO as a function of the injected DCcurrent

DC current from 4 mA to 9 mA. Moreover, it can be calculated from Figure 2.6that the Q of the MTJ STO is on the order of 100, which is much larger than thatof a typical CMOS VCO [21]. Furthermore, it can be observed from Figure 2.6that the linewidth is on the order of 10 MHz and the frequency fluctuations existin this device, indicating that the STO is suffering from limited phase noise. The

2.4. STATE-OF-THE-ART GMR STOS 17

phase noise of the MTJ STO has been measured about -65 dBc/Hz at 1 MHz offset[22, 23], which is not acceptable for most LO applications. As a consequence, thislimited phase noise should be improved in order to enable widespread uses of MTJSTOs in microwave applications.

The power consumption of the MTJ STO is depending on its operation fre-quency. A maximum power of 5.15 mW is consumed when the maximum allowablecurrent of 10 mA is injected into the device. The power consumption of the MTJSTO is slightly lower than that of a state-of-the-art CMOS VCO [24], which is 6.8mW.

2.4 State-of-the-art GMR STOs

Many studies of GMR STOs have recently been performed by varying the mag-netic stack composition [16], device dimensions, and biasing conditions (magneticfield strengh, magnetic field angle and DC current)[25], in order to understand thedifferent dynamic properties of STOs. The GMR STOs used in this work are fab-ricated using a stack composition of Pd8-Cu15-Co8-Cu7-NiFe4.5-Cu3-Pd3 and indifferent dimensions, changing from 30 nm to 100 nm. Due to the fact that themaximum allowable current has a quadratic dependence on the device dimension,smaller GMR STO has much lower current handling capability, and hence muchsmaller current tunabiliy. For example, experiments showed that a 100 nm and a 70nm GMR STO can usually handle a maximum DC current of approximately 45 mAand 28 mA, respectively. To illustrate the general case, 70 nm GMR STOs that areintermediate in sizes, are detailedly discussed in this work. In order to characterizeboth DC and RF performances of the GMR STO, the device is fabricated on thewaveguide (presented in section 2.2), which is probed, and then connected by abias-tee Miteq BT4000− S [26] through a RF cable. The AC port of this bias-teeis further connected to a wideband amplifier Mini−Circuits ZV A− 213+ [27] tobe able to observe the STO signal in the spectrum analyzer.

The GMR STO with a diameter of 70 nm has been measured, and presents atypical RDC of 6.55 Ω and an MR ratio about 1 − 2% [28], as it can be seen inFigure 2.7. In comparison to the MTJ STO, the GMR STO has significantly lowerMR ratio, indicating much lower output power according to Eq.(2.5) and Eq.(2.6).Measurements show that a typical GMR STO can yield a output power of -100 dBmto -80 dBm in reality. The maximum output power found in literatures is about-70 dBm with the out-of-plane configuration of the magnetic field [9]. Accordingly,this low output power of the GMR STO makes it difficult to be observed, whichimpedes the study of its dynamic properties.

GMR STOs have extremely large tunability and high operation frequency. Inorder to show its tunability and operation frequency, typical frequency shifts versusDC current and magnetic field of the 70 nm GMR STO has been measured anddepicted in Figure 2.8. This RF performance measurement has been performed bysweeping the magnetic field strengh from 0.7 T (= 7000 Oe) to 1 T (= 10000 Oe)

18 CHAPTER 2. SPIN TORQUE OSCILLATORS OVERVIEW

Figure 2.7: Measured MR in GMR STO

and the DC current from 10 mA to 30 mA, with a fixed magnetic field angle of 85o.Each sub-figure of Figure 2.8 illustrates that a tunability of 5 GHz can be gainedfrom tuning the DC current. It should be noted that a linear tunable range between11 GHz and 14 GHz with very narrow linewidth can be obtained when applyinga magnetic field of 0.9 T, as illustrated in Figure 2.8(c). In this case, the DCcurrent tuning sensitivity of GMR STO can be calcuated about 0.3 GHz/mA. Themagnetic field tuning sensitivity can be calculated in a similar way by comparingthe frequencies at a fixed DC current, e.g. 20 mA, under different magnetic fieldstrength conditions. As a result, the GMR STO presents a magentic field tuningsensitivity of approximately 0.75 MHz/Oe. To further show its protential tunability,the operation frequency of GMR STOs has been experimentally observed up to 46GHz and extrapolated to 65 GHz [29].

In addition to tunability, Figure 2.8 also gives the information about the linewidthand the threshold current of GMR STO. It can be approximately read from thefigure that the linewidth is on the order of MHz, which is narrower than that ofthe MTJ STO and hence higher Q. At room temperature, a maximum Q of 18000has been found in similar GMR STOs. The threshold current of the GMR STO isa function of the magnetic field strength. For instance, the threshold current variesfrom 16 mA to 20 mA by altering the magnetic field from 0.7 T to 1 T. What’smore, it can be seen from Figure 2.8(c) and (d) that mode transitions happen athigher frequencies in GMR STOs, which is undesired in microwave applications.

The GMR STO with a 70 nm dimension can draw a maximum current of about30 mA. Consequently, the maximum power consumption of this GMR STO is

2.5. SUMMARY 19

(a) (b)

(c) (d)

Figure 2.8: Operation frequency of GMR STO as a function of the DC current andthe magnetic field strength with a fixed magnetic field angle of 85o (a). H = 0.7 T(b). H = 0.8 T (c). H = 0.9 T (d). H = 1 T

around 3.7 mW, which is even lower than that of a MTJ STO.

2.5 Summary

The intriguing properties, especially extremely large tunability, miniature size, andhigh quality factor, of MTJ STO suggest that it is a promising candidate forthe next generation microwave oscillators. However, challenges still remain be-fore widespread applications of STOs are possible. To build the first STO-basedsystem, additional techniques are required to alleviate the current issues of MTJ

20 CHAPTER 2. SPIN TORQUE OSCILLATORS OVERVIEW

STOs.Many dynamic properties of STOs, such as mode structure and phase noise, are

not yet very well understood [16, 30]. To further study these dynamic propertiesof STOs, GMR STOs are widely used because they allow easier and faster fabrica-tion, and larger injected DC currents than MTJ STOs [18]. The larger allowableDC current of GMR STOs indicates a larger achievable tunability range. However,currently, their maximum output power of nano-watt makes GMR STOs less suit-able for any applications. For research purpose, KTH and GU have collaboratedand fabricated GMR STOs. Yet, as mentioned in section 2.4, the existing mea-surement setup is not optimized for noise and power, which brings difficulties inmeasuring the weak signal generated by GMR STOs. To overcome the identifiedissues and build a reliable measurement setup, an approach of integrating GMRSTOs and their dedicated CMOS circuits, which preamplifies the weak GMR STOsignal, are required. A reliable and accurate measurement setup can enable furtherstudies of the emerging STO technology.

Chapter 3

STO-based System Architectures

As discussed in Chapter 2, the MTJ and GMR STOs present different dynamicproperties, such as operation frequency and output power.

MTJ STOs offer larger output power than GMR STOs, due to larger magne-toresistance at the expense of somewhat lower operation frequencies. The relativelyhigher output power of MTJ STOs, as well as the considerably tunable range from3 GHz to 9 GHz, enable their potential microwave uses. This chapter firstly inves-tigates possible applications of MTJ STOs. According to this investigation, thischapter gives the most suitable application for state-of-the-art MTJ STOs. Unfor-tunately, the main limitation of using MTJ STOs in microwave applications is theiroutput power. Possible approaches, which can enhance the output power of MTJSTOs, are then investigated. Currently, using an external amplifier IC to enhancethe output power of MTJ STOs is the only approach to prove their potential usesas microwave oscillators. Thereafter, this chapter identifies the circuit requirementsbased on the state-of-the-art MTJ STOs, and presents the system architecture ofthe MTJ STO-based applications.

In order to further study the dynamic properties of GMR STO technology, dif-ficulties in measuring GMR STOs should be overcome. To reach this goal, possibleintegration methods, which can improve the performance of the current measure-ment setup, are investigated and discussed in this chapter. The most appropriateintegration method of wire bonding, targeting the state-of-the-art GMR STO tech-nology, is chosen. For the selected integration method, the system architecturefor GMR STO measurement setup is determined. The CMOS high frequency IC,that is required to provide the necessary on-chip bias-tee, ESD protection, andamplification for GMR STO, are proposed.

3.1 STO applications

Considering STOs’advantages of high operation frequency and extremely wide tun-ability, potential microwave uses of STOs are modulators [31, 32], frequency detec-

21

22 CHAPTER 3. STO-BASED SYSTEM ARCHITECTURES

tors [33], magnetic field sensors [34], and oscillators [29].

3.1.1 Current-controlled modulator

It is detailedly described in Chapter 2 that by using the DC current-induced STT,the magnetization can undergo sustained oscillation, whose oscillation frequencycan be tuned by the injected DC current. In [31, 32], it was further experimentallyverified that STOs can be used as frequency modulator, by means of injecting ahigh-frequency AC current signal in addition to this DC current. Hence, a mod-ulated microwave signal can be simply obtained at the output of the STO. Thiseffective modulation opens up the possibility of STO-based signal processing: high-frequency signal can be directly fed into the current-controlled STO and modulated.Furthermore, recent study [32] has shown that the DC drive current actually createsa combined nonlinear frequency and amplitude modulation in STOs.

Nonetheless, this STO-based signal processing suffers from the issue of limitedoutput power. Additionally, other nonlinearities such as temperature and dynamic-mode hopping are not yet clearly understood. As a result, STOs are not totallyready for being used as frequency modulators in communication systems.

3.1.2 Microwave frequency detector

It is reported in [33] that a spin-torque diode effect has been discovered in MTJSTOs. This spin-torque diode effect can be explained as: by applying a smallmicrowave AC current to MTJ STO, whose frequency is resonant with the tunableoscillation frequency of STO, a DC voltage can be detected across the device. Thisis based on the fact that the device resistance is alternating between RP and RAP

when an alternating current is injected into the device. Accordingly, the averageof the product of the AC current and the alternating resistance appears as a DCvoltage across the spin-torque diode. This spin-torque diode is noise-tolerant sincethe DC voltage can only be obtained when the frequency of the AC signal is resonantwith the oscillation frequency of STO.

This interesting diode effect found in STOs, along with their wide tunability,fast response and low power consumption, make it possible to build an STO-basednon-coherent IR-UWB transceiver as shown in Figure 3.1. For the transmitter(TX), two different currents I0 and I1 can be used to represent the binary data “0”and “1”, and hence can be alternatively injected into a single STO. STO can quicklyrespond to the different injected currents as altering between different frequencies orswitching between on and off states, according to the desired modulation technique.Possible modulation techniques are frequency-shift keying (FSK) and amplitude-shift keying (ASK) as illustrated in Figure 3.1. For the receiver (RX), STO canbe directly used as a demodulator thanks to its diode effect, enabling a directconversion of the received microwave signals to high and low output voltages. Thesehigh and low output voltages can be directly used to distinguish between binary

3.1. STO APPLICATIONS 23

PASTO

STO

1 0 1 0

1 0 1 0

ASK

FSK

OR

LNA

e.g. I0=3mA → 0 (FSK)

Or I0=0mA → 0 (ASK)I1=1mA → 1

I1=1mA → 1 AntennaASK

FSK

OR1 0 1 0

Figure 3.1: STO-based non-coherent IR-UWB transceiver

data “0” and “1”. This STO-based non-coherent IR-UWB transceiver may fullyutilize STOs’ advantages while being immune to STOs’ limited phase noise [35].

However, the current issue of this possible application is that the DC voltageobtained from the STO diode effect is currently too low. For example, by feeding amicrowave signal with a 10 mW (10 dBm) power, a DC voltage of 250 µV is obtained[36]. As a result, this DC output level is too low to be detected. Therefore, to solvethis low DC voltage problem, extra circuits, such as power amplifier (PA) or chopperamplifier, are required to amplify either the microwave input signal or the outputDC voltage. These extra circuits consume extra power, which is not desired bylow-power applications.

3.1.3 Magnetic field sensor

As illustrated in Figure 2.5 and Figure 2.7, the operation frequency of STO isan approximately linear function of the applied magnetic field. According to thisproperty, STO can be used to sense the magnetic field strength by measuring itsoscillation frequency change. This application is attractive because it avoids mea-suring the signal amplitude, which requires large SNR in order to accurately sensethe magnetic field. In addition, this STO-based magnetic sensor has very high sen-sitivity. The reported sensitivity of STO oscillation frequency to the magnetic fieldstrength is 100 GHz/T - 180 GHz/T [34, 37, 38].

However, in order to use STOs to accurately detect the magnetic field, theircurrently significant process variations, should be overcome. Besides, this STO-based sensor still requires a biasing magnetic field in order to work properly.

24 CHAPTER 3. STO-BASED SYSTEM ARCHITECTURES

3.1.4 Microwave oscillatorWith its intriguing properties, the STO becomes a promising candidate for mi-crowave oscillator, which can be used as LO in STO-based receivers. Before STOcan be widespread used in practical applications, such as STO-based receiver, theissue of very limited output power should be solved. The output power of a singleMTJ STO now reaches 1 µW. By enhancing this output power, the MTJ STOis able to be used as a microwave oscillator. There are several possible solutionsto improve the output power of MTJ STO. Besides injection locking, which is ex-plained in Chapter 1, other possible solutions are synchronization of STO arrays[39, 40] and employment of external CMOS ICs. It has been verified by simulationsin [41] that the output power level can be possibly lifted to 0 dBm by synchronizinghundreds of STOs in parallel. However, power combiners are required between eachSTO pair in order to add up the power at the output (assume the power combinersdon’t introduce extra loss), which is not accepted in applications. Otherwise, STOswill load each other when they are connected in parallel, which results in no powerenhancement. Besides, only two STOs at present can be experimentally synchro-nized in a parallel configuration with the help of separate biasing currents. This isbecause the operation frequencies and phases are not identical in two STOs due toprocess variations. Connecting STOs in series allows improving the output powerwithout using external power combiners. Yet, series connection of STOs increasesthe complexibility of fabrication. Therefore, the only possible solution is applyingan amplifier to alleviate the limited output power issue. It is reported in [9] thatthe maximum power can be obtained by employing a high input impedance ampli-fier. Nevertheless, this is not true when considering the maximum power transferand imperfectly matched load. Accordingly, it is necessary to develop a widebandamplifier targeting MTJ STO with the consideration of power, noise and linearity.

The current issues, including process variation, limited linearity and undevel-oped diode effect, prevent STO being used as modulator, frequency detector andmagnetic field sensor. As a result, the most suitable application for the state-of-the-art MTJ STOs is the microwave oscillator.

3.2 MTJ STO-based microwave oscillator architecture

MTJ STOs used in this work are provided by KTH, and thus the characteristicsof these MTJ STOs are similar to those in [8]. The characteristics of a typicalMTJ STO were discussed in Chapter 2 and are summarized in Table 3.1. Basedon the performance metrics in Table 3.1, key design parameters of the desiredamplifier IC are derived targeting MTJ STO-based microwave oscillator. Thesekey design parameters include impedance matching, bandwidth, gain, linearity andnoise. Considering these design parameters, the most suitable architecture for therequired amplifier IC is proposed. The detailed requirements that are related tothese design parameters, and the entire architecture are discussed in this section.

3.2. MTJ STO-BASED MICROWAVE OSCILLATOR ARCHITECTURE 25

Table 3.1: Performance metrics of MTJ STOSpecificationDC current -10 mA to 10 mATunability range 3 GHz to 9 GHzResistance RS 51 ± 13 ΩOutput power -60 dBm to -40 dBm

3.2.1 Impedance matchingIn order to DC bias the MTJ STO without disturbing its microwave signal, an ex-ternal wideband bias-tee from Mini-Circuits with a coaxial connector was employedin the MTJ STO measurement setup. This bias-tee is connected to MTJ STO pads(given in Figure 2.4(a)) by an RF probe through the RF cable. It has been verifiedin [42] that the wideband on-chip bias-tee with a 10 mA current handling (see Table3.1), cannot be implemented in 65nm CMOS technology due to the limited 1.2 Vpower supply and parasitics at high frequencies. Therefore, an external bias-teeis always required for isolating the DC biasing current from the AC signal. Thiswideband external bias-tee is assumed to be lossless to simplify the following calcu-lation of impedance matching condition for maximum power transfer. Additionally,the MTJ STO pads are much shorter compared to the 1/10 wavelength 1 of theAC signal, and hence can be neglected in the calculation. As a result, the powertransferred from the MTJ STO to the input impedance Zin of the desired amplifier(shown in Figure 3.2) can be written as below:

Pin = ( VS

RDC +RAC + Zin)2Zin (3.1)

This transferred power Pin can be maximized when

Zin = RDC +RAC (3.2)

The AC term RAC cannot be dynamically matched in practice. As a consequence,the desired amplifier should provide a good input impedance matching to RDC =(RP + RAP )/2 ∼50 Ω to achieve maximum power transfer. The impact of theSTO’s periodic variation resistance will be detailedly analyzed in Chapter 4.

The output impedance of the amplifier should be designed to 50 Ω for the samereason, which also eases the further connection with PLL or mixer. Moreover, theimpedance matching at the output can avoid signal reflection [43].

3.2.2 Bandwidth and gainThe typical output power of MTJ STOs, as mentioned before, is between -60 dBmand -40 dBm. In order to further connect the STO in a PLL, such as the wide-

1A rule of thumb is that the wire should be treated as a transmission line if its length is largerthan 1/10 of the wavelength

26 CHAPTER 3. STO-BASED SYSTEM ARCHITECTURES

RDC

VS

RAC

Zin

Input of the amplifier

MTJ STO

Figure 3.2: Power transfer from MTJ STO to amplifier

band PLL LMX2487E [44] which covers a frequency range of 3 GHz - 7.5 GHz, toeliminate its spectrum impurity, the output power of STO should be amplified toat least -15 dBm, which is the minimum input power requirement of LMX2487E.Accordingly, the required gain of the amplifier IC is 30 dB - 50 dB, depending onthe output power level of the STO, and including a margin of other losses due toparasitics. In order to take advantage of the wide tunability of MTJ STOs, thebandwidth of the target amplifier IC should cover the entire tunability range ofMTJ STOs if possible.

3.2.3 Linearity

Since a large gain is required and 65 nm CMOS technology with 1.2 V power supplyare used for the amplifier IC, the output stage of the amplifier should be able tohandle a large output swing in order to prevent signal klipping. What is more,to reject the power ripple and noise, power supply rejection ratio (PSRR) shouldbe larger than 40 dB. In order to obtain a large PSRR, differential signals shouldbe processed in the amplifier. However, the output of STO is unbalanced (single-ended). For this reason, a Balun is required as the first stage of the amplifier toconvert the single-ended STO signal to differential signals. For measurement pur-pose, the output stage of the amplifier is responsible for converting the differentialsignals back to a single-ended output.

3.2.4 Noise

The noise performance of a 50 Ω system is best characterized by the noise figure(NF). According to Friis formulas for noise, the NF of the system is mostly deter-mined by the first stage, which is usually a low noise amplifier (LNA). However, asdiscussed in the previous subsection, the first stage of the desired amplifier shouldbe a Balun. Consequenctly, a Balun-LNA [45] is the most suitable topology forthe first stage in this case, since it avoids using on-chip passive components, which

3.3. SYSTEM ARCHITECTURE FOR GMR STO MEASUREMENT SETUP27

are bulky and lossy, to achieve a Balun. Based on the study of the state-of-the-artwideband CMOS LNAs, noise performance similar or better than [46, 45, 47] hasbeen considered for this frequency range. Therefore, the target NF of the amplifierIC is lower than 5 dB.

3.2.5 System architecture of the MTJ STO-based microwaveoscillator

By considering the impedance matching, amplification, bandwidth, noise and lin-earity as mentioned above, the architecture of the wideband amplifier IC for MTJSTO-based microwave oscillator is given in Figure 3.3. The whole amplifier shouldbe composed of three stages: a Balun-LNA as input stage, followed by the amplifi-cation stage and the output buffer stage. The ampliciation stage is responsible forproviding enough gain. The detailed design of these blocks will be introduced inthe next chapter.

External

Bias-tee

DC current source

MTJSTO

RF cable50 Ω

Input Stage of

Amplifier

ACDC+ACBalun+LNA

Limiting Amplifier

Chain

Output Buffer

GS

Figure 3.3: System architecture

3.3 System architecture for GMR STO measurement setup

3.3.1 Issues in current measurement setup of GMR STOAt present, the microwave power that can be obtained from a typical GMR STO isapproximately 1 nW [41]. As a consequence, this low output power of GMR STOdoes not allow GMR STO to be used in any application. Nevertheless, comparedwith MTJ STO, GMR STO is much easier and faster to be fabricated, and hence alow-loss measurement setup is required to study the dynamic properties of STOs.The dynamic properties of interest are linewidth, phase noise and other nonlinearbehaviors, which are not yet clearly understood. Besides, GMR STO is attractivebecause it allows large DC current, and thus can be widely tuned at extremely high

28 CHAPTER 3. STO-BASED SYSTEM ARCHITECTURES

frequencies, e.g. 12 GHz - 24 GHz [48]. The wide tunability and high operationfrequency enable GMR STO to be potentially practical in applications, such asmagnetic field sensor. Furthermore, a lot of studies on reducing the required highmagnetic field of GMR STO have been carried out in recent years. However, theexisting GMR STO measurement setup, as it is shown in Figure 3.4, is not optimalin terms of power and noise [32], which brings difficulties in characterizing thedynamic properties of GMR STO. It can be seen in Figure 3.4 that the GMR STOis placed on the GSG coplanar waveguide (the characteristic impedance Z0 of thecoplanar waveguide is 50 Ω ), which is probed and connected by an RF cable toan external wideband bias-tee. The AC signal generated by GMR STO is thendelivered to and amplified by a commercial wideband amplifier Mini-Circuits ZVA-213+ [27], which takes 326 mA from a 15 V power supply, and requires a bulkyheatsink. In this measurement setup, the RF cables and external bias-tee introducesignificant power losses during the measurement. In addition, the input impedanceof the commercial amplifier cannot provide a perfect matching to 50 Ω over a widefrequency range. According to the datasheet [27], the amplifier presents a maximumvoltage standing wave ratio (VSWR) of 2.5, which results in considerable signalreflection. As a consequence, the S11 of the amplifier gives an obvious standingwave pattern, causing a large inaccuracy of the linewidth measurement. In orderto improve the measurement setup and reduce the signal degradation, a dedicatedCMOS high frequency IC, which can provide the required bias-tee and amplificationfor GMR STO while considering power transfer and noise, is in urgent need. ThisCMOS high frequency IC for GMR STOs may pave the way for future research onSTO’s dynamic properties and bring STO one step closer to applications.

External

Bias-tee

DC current source

50 Ω

ACDC+AC

Amp

GMR STO

RF cable

Spectrum Analyzer

RF cable

Figure 3.4: Current GMR STO measurement setup

3.3. SYSTEM ARCHITECTURE FOR GMR STO MEASUREMENT SETUP29

Table 3.2: GMR STO (70 nm) Summary

SpecificationDC current 8 mA to 30 mATunability range 10 GHz to 15 GHzResistance ∼6.5 ΩReactance 56 pH to 90 pH (waveguide)Signal level -154 dBm/Hz

3.3.2 Circuit requirements for GMR STO measurement setupIn order to achieve a low-loss reliable measurement setup for GMR STOs, the re-quired CMOS high frequency IC (for simplicity, this IC will be called “the dedicatedIC”), should include the following key blocks: an on-chip bias-tee, ESD protectiondiodes and a wideband amplifier.

As it can be seen in Figure 2.8, the operation frequency of a typical GMRSTO (70 nm diamater) can be continuously tuned between 10 GHz and 15 GHz byvarying the DC current from 7 mA to 30 mA. In this work, the frequency range of10 GHz - 15 GHz is the band of interest since this continuously tunable frequencyrange can be used for both STO studies and microwave applications. Particularly,this frequency range is important to study the linewidth, phase noise, phase lockingand synchronization of STOs. Consequently, the desired bandwidth of the requiredhigh frequency circuits should cover a frequency range of 10 GHz - 15 GHz.

As the desired bandwidth in this work is between 10 GHz - 15 GHz, the per-formance metrics of this 70 nm GMR STO are extracted in Table 3.2. Theseperformance metrics are used to derive other circuit requirements in following sub-sections.

On-chip bias-tee

The on-chip bias-tee design is essential in this work for performance reasons, as anoff-chip bias-tee would introduce significant signal losses on the connection at 10GHz - 15 GHz, while also limiting the integration advantage of nano-sized STOs.A fully-integrated solution can only be achieved with a dedicated on-chip bias-tee for GMR STOs. According to the desired bandwidth and required DC biasingcurrent for GMR STOs, the on-chip bias-tee should handle up to 30 mA DC currentwhile covering a frequency range larger than 15 GHz. Besides, the on-chip bias-teeshould provide sufficient isolation between the DC and AC paths while minimizingthe insertion loss on the AC path.

Integration of STO and the dedicated IC

As mentioned above, the integration of the STO device with the CMOS IC isnecessary and vital for both on-going studies and future applications. One pos-

30 CHAPTER 3. STO-BASED SYSTEM ARCHITECTURES

(b). Flip-chip

MOS transistors

Metal 1

Metal 2

Metal 3

Metal 4

Top Metal

Via1

Via2

Via3

Via4

STO

(a). Monolithic integration

400 um

210 um

Mesa 16 x 8 um40 um

PADPAD PAD

62 um100 um 100 um

(c). Wire bonding

STO

STO

CMOS IC

GSG coplanar waveguide

Figure 3.5: Possible integration methods between STO and CMOS IC

3.3. SYSTEM ARCHITECTURE FOR GMR STO MEASUREMENT SETUP31

sible integration approach is the monolithic integration, which is widely used inCMOS-MEMS systems [49, 50]. This approach can be realized by stacking STOlayers as post-processing steps on top of the CMOS back-end-of-line (BEOL) lay-ers, as illustrated in Figure 3.5(a). This approach minimizes packaging size andsignal degradation at high frequencies. However, it is difficult to implement andit requires a long development time since more process steps are needed. More-over, this approach doesn’t allow independent optimization of the IC and the STOdevice, which is not suitable for the currently early-stage STO technology.

An alternative approach of integration is using flip-chip interconnections be-tween the STO and the CMOS IC, as shown in Figure 3.5(b). Flip-chip is pro-duced by an extra build-up process step that adds bumps to all the pads of theentire wafer [51]. To integrate the nano-scaled STOs with ICs by using flip-chip,STOs are placed on coplanar waveguides. Compared to monolithic integration,flip-chip allows easy implementation and easy measurement. Nevertheless, this ap-proach limits the flexibility as the STO and the IC cannot be easily detached andreused.

Figure 3.5(c) shows a low-cost and flexible approach using chip-on-board (CoB)hybrid integration. CoB employs wire bonding technology to directly connect theGSG pads of the IC to the coplanar waveguide of the STO by gold bond wires. Theapproach of using wire bonding offers independent measurements and optimizationsof the IC and the STO. Besides, this approach allows easy replacement of either theSTO or the IC, which introduces another degree of freedom for research purposes.Nevertheless, this approach introduces significant performance degradation due tolarger parasitics.

A summary of the comparison between these three different integration methodsis given in Table 3.3. By comparing these methods, it can be found that mono-lithic and flip-chip solutions can ultimately result in a higher level of integrationand better performance at high frequencies. However, as a first attempt to proveintegration of STO and CMOS technologies, the wire bonding method can providean easy implementation, measurement and replacement, which is suitable for thecurrently early-phase STO technology. This integration approach introduces moreparasitics as compared to the other integration methods mentioned above. Theseparasitics will bring a non-uniform signal degradation when considering a wide fre-quency range. As a consequence, in order to take advantage of the wide tunabilityof GMR STOs, special considerations are required to deal with these parasitics andto achieve wideband high-frequency operation. A possible approach to compen-sate the bond wire is to use other passive components, so as to build a high-ordernetwork and hence to improve the frequency response.

32 CHAPTER 3. STO-BASED SYSTEM ARCHITECTURES

Table 3.3: Comparison between different integration methods

Chip on board(Bond wire)

Flip-Chip Fully integrated onCMOS

Pros +Flexibility+Easy implementa-tion+Easy measurement+Low cost

+Medium Flexibility+Easy implementa-tion+Easy measurement+Low performancedegradation

+Fully integration+Close-to-zero perfor-mance degradation

Cons -Large performancedegradation (Otherpassive componentsare required to com-pensate the bondwire and improve thefrequency response)

-High cost -No flexibility-Hard implementation-Hard measurement(can not be seperatelymeasured)

On-chip ESD protection

It should be noted that the on-chip ESD protection is also necessary for experi-mental research and practical applications. Specifically, in the STO and the 65 nmCMOS technologies, the GMR STO can only stand several hundred millivolts be-cause of heating and electromigration effects [52], and the CMOS IC has low ESDrobustness [53, 54]. Therefore, the required circuits should offer ESD protection forboth the STO and the CMOS IC.

Input and output networks

The bond wire, on-chip bias-tee and ESD diodes introduce a lot of parasitics athigh frequencies, which results in a non-uniform signal degradation over the widefrequency range. For instance, bond wires, whose lump model is given in Figure3.6(a), with different lengths were simulated in ADS to evaluate their microwaveperformance. By sweeping the length of the wire bond, the simulated results aredepicted in Figure 3.6(b). These simulated results show that the bond wires bringsignificant losses at high frequencies. For example, a 1 mm bond wire yields a 2 dBsignal degradation at 15 GHz. Due to this significant loss, the output of the entirededicated IC for GMR STO will be probed to avoid the lossy wire bonding. Inaddition, the ESD diodes along with the pad may easily introduce a considerableparasitic capacitance, which also limits the IC operation at high frequencies [55].As a result, these parasitcs make the dedicated IC for GMR STO challenging. Inorder to obtain a flat gain within the frequency range of 10 GHz - 15 GHz, inputand output networks are required.

3.3. SYSTEM ARCHITECTURE FOR GMR STO MEASUREMENT SETUP33

Rbond

Lbond

CP Rbond CP

(a)

(b)

Figure 3.6: Bond wire (a). the lump model (b). the simulated microwave perfor-mance

Wideband amplification

As the GMR STO produces an extremely weak output signal, a wideband amplifierwith noise and power optimizations is also needed. It should be considered thatthe coplanar waveguide for GMR STO (Figure 3.5), has a length of 210 um. Thislength is much shorter than the 1/10 wavelength of the STO signal. Accordingly,the impedance mismatch brought by the coplanar waveguide can be neglected.Theoretically, maximum power transfer can be obtained when the input impedanceof the dedicated IC for GMR STO matches the source impedance, which typicallyhas a resistive part of around 6.5 Ω for GMR STOs. At high frequencies, widebandimpedance matching to 6.5 Ω is not feasible since any parasitic will introduce animpedance mismatch much larger than 6.5 Ω. Therefore, the wideband amplifiershould include an LNA, which is able to provide high input impedance to maximizethe voltage delivered by STO, as the input stage. In addition, an extra gain stage isadded for providing additional amplification to the weak output signal of the GMRSTO. To enable the future connections to other RF blocks, the last stage, which isthe output buffer, should be able to load a 50 Ω impedance.

The proposed IC solution with high input impedance (high-Z) can achieve better

34 CHAPTER 3. STO-BASED SYSTEM ARCHITECTURES

noise performance, as compared to the case when input impedance is matched. Thisis based on the fact that the minimum NF can be achieved by maximizing the loadimpedance [21], which is the input impedance of the dedicated IC for GMR STOin this case.

3.3.3 System architecture of GMR STO measurement setup

DC current source

High

Z

ACDC+ACOutput

filterInput filter

On-chip

Bias-tee 50

Ohms

AC

LNA Gain stage Output buffer

GMR STO

IC

Figure 3.7: System architecture

The proposed system architecture of the dedicated IC for GMR STO is presentedin Figure 3.7. The GMR STO, which is placed on the coplanar waveguide, should beconnected to the ESD protected RF pad on the desired IC by bond wires. This RFpad should be followed by the on-chip bias-tee, which provides the DC bias currentfor the GMR STO while feeding the AC signal to the amplifier. The parasitics ofpad, bond wire and other components are used to build networks at both inputand output, which are responsible for flating the gain. The amplification stage ofthe dedicated IC for GMR STO measurement setup consists of an LNA with highinput impedance, followed by a gain stage, and an output buffer. The circuit designwill be discussed in Chapter 5.

Chapter 4

CMOS Wideband Amplifier forMTJ STO

As discussed in Chapter 3, the architecture of MTJ STO-based microwave oscilla-tor, which enables further connection with other RF blocks such as PLL, has beenproposed. In order to achieve the MTJ STO-based microwave oscillator, this chap-ter focuses on the CMOS wideband amplifier for MTJ STO. As explained before,this wideband amplifier should be composed of three stages: the Balun-LNA asinput stage, followed by the amplification stage and the output buffer stage. Itshould be noticed that the Balun-LNA is critical since the input stage should pro-vide good input impedance matching to RDC = (RP +RAP )/2 ∼50 Ω, and shouldachieve low noise performance within the band of interest. Therefore, this chapterwill start from the detailed analysis of the Balun-LNA design.

4.1 Balun-LNA

The topology of the proposed Balun-LNA is depicted in Fig 4.1 [56]. The Balun-LNA consists of a CS stage (M1) combined with a cross-coupled CG stage (M2,M3) [57]. The impedance at the source of M2 is designed to match the source.Biasing ofM2 can be done by using either an NMOS current source or an inductor.The voltage drop at R1 has the same sign as the source and produces the outputvoltage Vout+. The voltage drop at R2 has opposite sign due to inversion caused byM1 and produces the output voltage Vout−. When the amplitudes of the outputsare equal, the amplifier behaves as a single-ended to differential balun converter,allowing differential processing of the signal on the following stages. Transistor M1is cascoded byM3, hence improving its voltage gain. This arrangement also reducesthe Miller effect on M1 and therefore helps to enhance the bandwidth. The cross-coupled transistors introduce a dual feedback loop into the circuit which allowsmore design variables to enter into the expressions of input matching, gain, andnoise performance. The next four subsections describe how these feedback loops

35

36 CHAPTER 4. CMOS WIDEBAND AMPLIFIER FOR MTJ STO

Figure 4.1: Proposed Balun-LNA with capacitive cross-coupling technique

enable more degrees of freedom that can be exploited in order to enhance the LNAperformance.

4.1.1 Theoretical Design-Oriented AnalysisGain Boosting

The voltage gain from VS to Vout− is found by using the small signal equivalentcircuit of Figure 4.2. The effect of channel length modulation of M1 needs to beaccounted in the analysis since the drain-source resistance can be as low as a fewhundred Ohms and therefore not negligible. The voltage gain Vout−/VS can beexpressed as:

Vout−

VS= −A·(gm1·ro1 + 1

gm3·ro1 + 1)·gm3·R2 (4.1)

where gm1, gm3, and ro1 are the transconductance of M1,M3, and the drain-sourceresistance of M1 respectively. A is a factor that accounts for the voltage divider atthe input, and that takes the value of 0.5 when the source impedance is matched.

The voltage gain calculated from VS to Vout+ can be also found using a similarprocedure and its expression is:

Vout+

VS= −A·(gm1·ro1 + 1

gm3·ro1 + 1)·gm2·R1 (4.2)

where gm2 is the transconductance of M2. Compared to the CG stage where thegain is roughly A·gm2·R1, Eq.(4.2) shows that the gain is boosted by a factorgm1·ro1+1gm3·ro1+1 due to the feedback loop.

4.1. BALUN-LNA 37

Figure 4.2: Small signal model of cascoded CS stage

Accordingly, the total voltage gain of the proposed LNA is:

Av = Vout+ − Vout−

VS= A·(gm1·ro1 + 1

gm3·ro1 + 1)·(gm2·R1 + gm3·R2) (4.3)

The condition for balancing the differential outputs can be found by equatingEq.(4.1) and Eq.(4.2), which results in the following relationship:

R1

R2= gm3

gm2(4.4)

When the differential gain is balanced, the total voltage gain can be simplifiedto:

Av = 2A·(gm1·ro1 + 1gm3·ro1 + 1)·gm2·R1 = 2A·(gm1·ro1 + 1

gm3·ro1 + 1)·gm3·R2 (4.5)

where it can be appreciated that the boosting factor increases the total gain withoutrequiring additional power consumption. This factor is one of the main advantagesof this cross-coupled configuration.

Input impedance

The input impedance Rin of the proposed LNA is given by:

Rin = gm3·ro1 + 1(gm1·ro1 + 1)·gm2

(4.6)

Proper matching requires Rin = RS . Under this condition, gm2 can be expressedby:

gm2 = 1gm1·ro1+1gm3·ro1+1 ·gm2

(4.7)

38 CHAPTER 4. CMOS WIDEBAND AMPLIFIER FOR MTJ STO

In this case, gm2 is inversely proportional to the boosting factor. A proper com-bination of gm1, gm3, and ro1 allows small M2 sizes and biasing currents, resultingin small parasitics and low power consumption.

Noise/Distortion Cancellation

In a CG stage which is matched to a given source, half of the drain noise currentflows directly to R1 resulting in a minimum noise factor of (1+γ) where γ representsthe drain noise coefficient. The proposed topology, however, belongs to a familyof CG-CS LNA that provides a cancellation mechanism for suppressing this noise.The differential output noise voltage generated by in,M2, the drain noise current ofM2, is:

Vout+,M2 − Vout−,M2 = −A·(R1 −RS ·gm1·ro1 + 1gm3·ro1 + 1 ·gm2·R2)·in,M2 (4.8)

which can be cancelled, provided that the following condition is satisfied:

R1

R2= gm1·ro1 + 1gm3·ro1 + 1 ·gm3·RS (4.9)

This condition is independent of A. Replacing Eq.(4.9) in Eq.(4.7) it is possibleto obtain the same expression as Eq.(4.4), which means that noise cancellation,matching, and gain balancing are concurrently achieved. Besides, the non-lineardistortion generated by M2 can be cancelled for the same reason [58].

The other noise contributors are M1, load resistors R1 and R2, and the biasingof M2. For simplicity, the following analysis disregards the noise of this biasing;however, its effect will be studied in the next section. The relationship betweengm1, gm2, gm3, R1, R2 and the noise performance can be characterized by the noisefactor F , which is given by:

F = 1 +¯v2

nout,M1 + ¯v2nout,M2 + ¯v2

nout,R1 + ¯v2nout,R2

¯v2n,RS·A2

v

(4.10)

where vnout,M1, vnout,M2, vnout,R1 and vnout,R2, represent the differential outputnoise voltage of M1, M2, R1 and R2. The noise factor as a function of the smallsignal parameters and noise sources can be expressed as:

F = 1 +14 (gm2R1 + gm3R2)2·( ro1

gm3ro1+1 )2·(in,M1)2

¯v2n,RS·A2

v

+14 (R1 −RS · gm1ro1+1

gm3ro1+1 ·gm3R2)2·in,M12 + ¯v2

nout,R1+ ¯v2

nout,R2

¯v2n,RS·A2

v

(4.11)

4.1. BALUN-LNA 39

where in,M1, in,M2 are drain noise currents of M1, M2. When Eq.(4.9) is satisfied,the noise of M2 is cancelled and the total noise factor simplifies to:

F = 1 + γ1·gm1

α·RS(gm11

ro1)2 + RS

R1+ RS ·R2

R21

(4.12)

where γ1 is the drain noise coefficient of M1 and α represents the transconductancedegradation in the short-channel regime. R1 and R2 are chosen much larger thanRS , causing that M1 governs the noise contribution. From Eq.(4.12), it can alsobe seen that as gm1 increases, a lower NF = 10·log(F ) is achieved. Furthermore,according to Eq.(4.5), increasing gm1 also boosts the differential gain simultane-ously. Figure 4.3 illustrates the relationship between gain, noise and gm1, by usingEq.(4.12) and assuming γ1 = 1, α = 0.8, and Ro1 =325 Ω. The gain and noiseimprovement in this case can be concurrently achieved, which is opposite to [59]where larger load resistors degrade the noise performance.

Robustness to the periodic variation of the STO resistance

The periodic variation of RS given in Eq.(2.2) results in time-variant noise andinput impedance matching conditions, which can be characterized by the noisefactor F (Eq.(4.10)) and the input reflection coefficient (Γin) given by:

Γin = ZIN − ZS

ZIN + ZS= ∓14· cos(2πf ·t)

100± 14· cos(2πf ·t) (4.13)

Since (RDC + RAC) takes values within 50 Ω ± 14 Ω, we assume that ZIN is 50Ω. The impact of this assumption on the NF and reflection coefficient is found

Figure 4.3: Relationship between gm1, R1 (gain) and noise

40 CHAPTER 4. CMOS WIDEBAND AMPLIFIER FOR MTJ STO

by evaluating Eq.(4.10) and Eq.(4.13) for RS values ranging from 36 Ω to 64 Ω(Figure 4.4). It can be seen that the NF varies by ± 0.06 dB as the RS valueoscillates around 50 Ω. Likewise, in one oscillation period, the maximum Γin is0.1628, presenting a maximum voltage standing wave ratio (VSWR) of 1.39:1 andindicating that the mismatch loss will be lower than 0.12 dB. Accordingly, theselection of RS =50 Ω as design parameter shows minimal impact on performanceand demonstrates that the proposed Balun-LNA is robust to the periodic variationof the STO resistance.

(a) (b)

Figure 4.4: (a). NF as a function of RS ; (b). Input reflection coefficient (Γin) as afunction of time

4.1.2 Simulation results of the proposed Balun-LNA

In order to validate the previous theoretical analysis, two LNAs were designedusing 65 nm CMOS technology. The first LNA uses an NMOS current sourceM0 to bias M2, whereas the second LNA uses an on-chip inductor. Based onprevious analysis M1, M2, and M3 take the sizes 50.4um/65nm, 20um/65nm, and28um/65nm, respectively. M1, M3 are biased at 1.88 mA which results in gm1,and gm3 of 20 mS and 15 mS, repectively. M2 is biased at 1.22 mA so that gm2is approximately 10 mS. In the case when M2 is biased with a current source, M0has a size of 40um/500nm. R1 and R2 are set to 500 Ω and 325 Ω, respectively.Load capacitances CL equal to 20 fF representing a wideband limiting amplifierstage have been included at the output. Finally, a 1.5 nH bonding wire and 120 fFcapacitances to account for the pads and ESD protection were added at the input.Using the theoretical derivation presented in previous subsections and the designvalues of the proposed LNA, the voltage gain can be calculated as 16.1 dB whenthe input impedance is perfectly matched to RS . The NF can be estimated as 2.26dB.

4.2. WIDEBAND AMPLIFIER 41

Figure 4.5(a) shows the simulated voltage gain Av and return losses S11 forboth LNAs. In both cases, the gain matches very well the theoretical result usingEq.(4.3). For the fast - fast (FF) corner simulation at −25oC and (VDD+10%), theproposed LNA (current source biasing case) exhibits 17.58 dB gain within 2 GHz -8.1 GHz bandwidth. For the slow - slow (SS) corner at 85oC and (VDD-10%), thegain is 14.3 dB and the bandwidth is 2 GHz - 9 GHz. The requirements of gainand bandwidth can still be fulfilled in the worst cases. Moreover, the simulateddifferential gain mismatch is below 0.2 dB over the band of interest. Return lossesfor both circuits show good matching characteristics. The simulated NF is plottedin Figure 4.5(b) Compared to the calculated NF of 2.26 dB, the simulated NF is 0.54dB - 1.54 dB larger. This difference is mainly attributed to other noise sources andnon-idealities not accounted for in the analysis, such as gate resistance, gate-inducednoise, source/drain resistances, larger drain noise coefficient of M1, as well as theeffect of parasitic capacitances which start to shunt signals at high frequencies. Itcan be also observed in Figure 4.5(b) that the worst case of NF is at the SS corner.The NF at SS corner is 4.3 dB - 4.8 dB, which is tolerable for this application.Figure 4.5(c) shows the simulated IIP3 using a two-tone test (5 GHz and 5.02GHz). Addionally, Monte Carlo simulations have been performed considering theMOS threshold voltage variations and resistor mismatches. The results presentedin Figure 4.5(d) show that the process variations have insignificant impact on thegain and NF.

4.1.3 Stand-alone Balun-LNA

As mentioned before, the Balun-LNA is the most critical stage of the entire wide-band amplifier. Accordingly, the Balun-LNA (biased by M0, which is illustrated inFigure 4.6 and will be explained in the next section) should be separately evaluated.In order to measure the Balun-LNA independently, the balanced-to-unbalanced out-put buffer introduced in the previous section is used for measurement purpose, as itis shown in Figure 4.6. In addition, a 1 pF MIM series capacitor for providing ACcoupling is added. The loss on the buffer + capacitor is estimated and subtractedfrom the measurement in order to obtain the performance of the core LNA. Fur-thermore, two small diodes are added at both input and output RF pads in orderto provide ESD protection to the circuitry. The proposed design is implemented in65 nm CMOS technology. The post layout simulations of the Balun-LNA core givea voltage gain of 20 dB with 2 GHz - 8.7 GHz -3 dB bandwidth. The maximumsimulated NF of the buffered Balun-LNA within the band of interest is 4.5 dB.

4.2 Wideband Amplifier

As discussed in Chapter 3, in order to obtain enough gain for the MTJ STO tobe usable as microwave oscillator, the amplifier IC should contain a Balun-LNA,followed by an amplification chain and an output buffer, as given in Figure 4.7. The

42 CHAPTER 4. CMOS WIDEBAND AMPLIFIER FOR MTJ STO

(a)

(b)

(c)

(d)

Figure 4.5: Simulation results of the proposed LNA (a).Voltage gain and inputreturn loss (b).Noise Figure (c).Linearity (d).Monte Carlo simulation results forprocess variation

4.2. WIDEBAND AMPLIFIER 43

M1

M3

R2R1

Rs

Vs

C1 C2

C0

M2

VDD

GND

Vbias

+

-Vin

Vout+

Vout-

M0CPAD

Vout

C3

C4

M4

M5

LNA core

Zin

Vb3

Rb4

Rb5

CAC2VDD

Figure 4.6: Schematic of the stand-alone Balun-LNA with output buffer

External

Bias-tee

DC current source

MTJSTO

RF cable50 Ω

Input Stage of

Amplifier

ACDC+AC

Limiting Amplifier

Chain

Output Buffer

GS

Figure 4.7: Block diagram and schematics of the proposed wideband amplifier

44 CHAPTER 4. CMOS WIDEBAND AMPLIFIER FOR MTJ STO

Balun-LNA has been proposed and analyzed in previous section. The amplificationchain should be realized by cascading five cascode stages to achieve large gain anda CS stage to obtain large output swing. Meanwhile, as descibed in Chapter 3, thetotal bandwidth BWtot of the cascaded stages should be able to cover the entiretunable range of the MTJ STO if possible, and can be written as [60]:

BWtot = BW · m

√2 1

n − 1 (4.14)

where BW is the bandwidth of each stage, n is the number of identical stages, m is2 and 4 for first-order and second-order amplifier stages, respectively. As expressedin Eq.(4.14), a larger n leads to lower BWtot. Hence, as demonstrated in [42], atrade-off between bandwidth and gain exists in the entire amplification chain. Fur-thermore, in practice, extra parasitics within each stage and between stages resultin additional bandwidth shrinkage. Consequently, in order to obtain sufficient gainand bandwidth simultaneously, an approach to enhance the bandwidth is in de-mand. One possible approach to enhance the bandwidth is to use Miller capacitorscompensation [61] in the amplification stage. Yet, this approach suffers from in-stability and capacitance mismatch. Another possible approach is active feedback[62], which has relatively high complexity and hence can be hardly used in cascadedstages. Other approaches, such as capacitive degeneration [63] and Cherry-Hooper[64, 65], introduce gain degradation, and therefore are not accepted. Accordingly,to obtain high gain as well as wide bandwidth, inductive peaking approach [63]is employed in the amplification stage. The drawback of this approach is that alarge silicon area is required for the on-chip inductor. As a result, two differentialinductors are used to obtain the required bandwidth (Figure 4.7), and placed in thefirst and fifth stages so as to accomplish relatively optimal floorplan and layout1.

For measurement purpose, an output buffer is required to complete balance-to-unbalance conversion, as given in Figure 4.7. In addition, this output buffer enablesthe proposed amplifier to drive the 50 Ω impedance.

The block diagram and schematics of the proposed wideband amplifier are de-picted in Figure 4.7. Since inductors are needed in the amplification stage to coverthe required bandwidth, an inductorless Balun-LNA was chosen in order to facili-tate the layout, and hence achieve better performance. As a consequence, the CGstage, shown in Figure 4.6 and Figure 4.7, is biased by M0.

The proposed wideband amplifier for MTJ STO is implemented in a 65 nmCMOS process with a 1.2 V supply. In the band of interest (3 GHz - 8 GHz), post-layout simulation results exhibit a typical S21 of 48 dB, maximum S11 and S22 of-10 dB and -7.5 dB, respectively. In addition, the maximum simulated NF withinthe -3 dB bandwidth is 4.7 dB, and the simulated IIP3 is -40 dBm at 5 GHz. Thewideband amplifier core draws a total current of 21.19 mA from the 1.2 V powersupply. In addition to the low noise performance and the high gain, the simulation

1A common practice is that two inductors should be separated by a distance, which is largerthan two times of the inductor diameter

4.3. MEASUREMENT RESULTS AND DISCUSSION 45

results of the proposed amplifier also exhibit that it has low power consumptionand moderate impedance matching in the frequency range of 3 GHz - 8 GHz, whichis suitable for MTJ STO applications.

4.3 Measurement Results and Discussion

4.3.1 Stand-alone Balun-LNAThe chip photograph of the stand-alone Balun-LNA is shown in Figure 4.8. Theactive area of the Balun-LNA core is 0.0044 mm2 (63 um × 70 um). The Balun-LNA core draws 3.2 mA from a 1.2 V power supply which results in only 3.84 mWpower consumption. To measure the performance of the proposed Balun-LNA, thedie was directly wire bonded on the test board 1, as it is given in Figure 4.9. This isbecause that other pre-molded packages introduce significant signal losses at highfrequencies and thus should be avoided. The RF input and output are connected byusing 50 Ω microstrip transmission lines. In addition, as it can be seen from Figure4.9, all the power supply and current references have been connected by SMAs andcoaxial cables in order to minimize the impact of the external noise.

Balun-

LNA core

63 um

70 um

Buffer

Figure 4.8: Chip photo of the stand-alone Balun-LNA

Figure 4.10 shows the post-layout simulated and measured S21 and S11 of thebuffered Balun-LNA, as well as the simulated and de-embedded voltage gain (VG)of the Balun-LNA (output buffer is de-embedded). The measured S21 follows thepost-layout simulated S21, but it is not flat within the frequency range of interest.

1All the PCBs in this work are fabricated using ROGERS 4350 high-frequency substrate inorder to minimize signal losses within the bands of interest.

46 CHAPTER 4. CMOS WIDEBAND AMPLIFIER FOR MTJ STO

Figure 4.9: Test board for the stand-alone Balun-LNA

Figure 4.10: Post-layout simulated and meausred S21 and S11, simulated and de-embedded VG of the Balun-LNA core

4.3. MEASUREMENT RESULTS AND DISCUSSION 47

This may be caused by the signal discontinuities on PCB traces, SMA connectorsand bond wires. To calculate the voltage gain of the Balun-LNA core, 6 dB areadded to the measured S21 in order to compensate for the loss of the output buffer(it halves the output voltage when matching the load). Beside that, the outputseries AC coupling capacitor forms a voltage divider with the load and introducessome frequency dependent loss that should also be removed from the S21 in orderto estimate the performance of the LNA core. After de-embedding these losses, avoltage gain of around 20 dB is obtained within the -3 dB bandwidth of 2 GHz -7 GHz. Although the frequency bandwidth shrinks with 1.7 GHz, the Balun-LNAcan still cover a large portion of the operation frequency range of MTJ STOs.

The bondwire inductance (∼ 1 nH) along with the capacitances on PCB (∼300 fF) and on-chip (∼ 100 fF) forms a Π-network. As a result, a good impedancematching (S11 < -10 dB) is achieved from 5.25 GHz to 7 GHz. The measured S11degrades below 4 GHz due to the fact that the 1 pF AC coupling capacitor at theRF input has added non-negligible impedance at low frequencies. This capacitorhas been added to the design for measurement purposes and it is unnecessary in thereal application since a wideband bias-tee would directly connect the STO oscillatorto the LNA.

To measure the NF, the Y factor method was used in combination with a Mini-Circuits ZVE-3W-83+ amplifier [66] having 35 dB gain over 2 GHz - 8 GHz band-width. Figure 4.11 plots the simulated, measured and de-embedded NF of thebuffered Balun-LNA. Due to the small total voltage gain of the buffered Balun-LNA,the noise introduced by the Mini-Circuits ZVE-3W-83+ amplifier is significant and

Figure 4.11: Post-layout simulated, measured and de-embedded NF of the bufferedBalun-LNA

48 CHAPTER 4. CMOS WIDEBAND AMPLIFIER FOR MTJ STO

should be de-embedded from the measured NF. For simplicity, it is assumed thatthe impedances at both input and output are matched during de-embedding. Themaximum de-embedded NF of the buffered Balun-LNA is 5 dB within the -3 dB gainbandwidth, which is 0.5 dB larger than the post-layout simulated NF. This noiseperformance degradation comes from the on-chip and off-chip parasitics, impedancemismatch, gain variation, and other losses in the signal path.

Finally, to characterize the linearity of the Balun-LNA, the IIP3 was measuredby using two tones at 3 GHz and 3.02 GHz with 20 MHz frequency spacing. Themeasured IIP3 is +2 dBm. This performance was obtained thanks to the non-lineardistortion cancellation intrinsic in this circuit topology.

Table 4.1 summarizes the performance of the proposed Balun-LNA and givescomparison to other recently published Balun-LNA designs [45, 47, 67]. Amongall the designs present in Table 4.1, the proposed Balun-LNA shows the largestgain and bandwidth product with low power consumption. Moreover, it presentscompetitive linearity and comparable NF within a wider frequency range. Becauseno on-chip inductors are required, this design occupies a very small chip area.

Table 4.1: Comparison with previous Balun-LNA designs

Tech.(nm)

VDD(V)

BW(GHz)

Gain(dB)

NF(dB)

IIP3(dBm)

S11(dB)

Power(mW)

Thiswork

65 1.2 2-7 20 <5 +2 @3GHz

-6 3.84

[45] 65 1.2 0.2-5.2

15.6 <3.5 0 -10 14

[47] 130 1 0.2-3.8

19 <3.4 -4.2 -9 5.7

[47] 130 0.85 0.2-3.8

14.8 <4.1 -3.8 -9 3.2

[67] 130 1.2 0.1-2 16.6 <3.8 +0.5 -10 3

4.3.2 Wideband amplifier

Figure 4.12 presents the die photo of the wideband amplifier IC. The widebandamplifier is fully ESD protected and implemented in 65 nm CMOS process. Itconsumes 25.44 mW from a 1.2 V power supply and occupies a core area of 500 um× 320 um. The amplifier has been wire bonded on a test board for both the stand-lone wideband amplifier IC and the entire MTJ STO-based microwave oscillator(MTJ STO+IC pair) measurements, as given in Figure 4.13.

As a first attempt to connect the MTJ STO to the wideband amplifier IC andhence develop an MTJ STO-based microwave oscillator, the performance of the

4.3. MEASUREMENT RESULTS AND DISCUSSION 49

Figure 4.12: Die photo of the proposed wideband amplifier IC

Figure 4.13: Test board for the wideband amplifier IC

50 CHAPTER 4. CMOS WIDEBAND AMPLIFIER FOR MTJ STO

Figure 4.14: Measurement results of the proposed wideband amplifier (a). Mea-sured S11, S22 (b). Measured S21 and De-embedded NF

wideband amplifier has been evaluated separately. The measurement results ofthe proposed amplifier are plotted in Figure 4.14. The measured S11 and S22 pa-rameters are approximately -10 dB. Due to the fact that the measured S11 andS22 highly depend on the PCB transmission line, which is wire bonded to the im-plemeted IC, this measured S11 and S22 cannot be compared with the simulatedS11 and S22, provided in Section 4.2. The de-embedded S21, as shown in Figure4.14, is approximately 35 dB with a -3 dB bandwidth of 2 GHz - 7 GHz. Com-pared to the simulated S21, the gain degradation, the bandwidth shrinkage and thefluctuations of the measured S21 are mainly caused by SMA connection on PCB,bond wires, and other on-chip and off-chip parasitics. Besides, a maximum mea-sured NF of 5 dB is attained within the -3 dB bandwidth. The 0.3 dB differencebetween the measured NF and simulated NF is related to both on-chip and off-chip parasitics, gain variation and other losses in the signal path. Additionally, themeasured NF of the proposed wideband amplifier matches the simulated NF. Thedescrepancy between the measured NF of the Balun-LNA and the simulated NF isdue to the finite total gain of the Balun-LNA and the Mini-Circuits ZVE-3W-83+amplifier, which limits the accuracy of the NF measurement using Y-method [68].Moreover, due to the limited gain of the buffered Balun-LNA, the noise introducedby the Mini-Circuits ZVE-3W-83+ amplifier contributes significantly to the totalmeasured NF. Finally, to obtain the linearity of the proposed wideband amplifier,two tones at 3 GHz and 3.02 GHz with 20 MHz spacing have been used to measurethe IIP3. The measured IIP3 is -28 dBm, which is higher than the simulated valueowing to the gain degradation.

4.3. MEASUREMENT RESULTS AND DISCUSSION 51

4.3.3 MTJ STO-based microwave oscillatorThereafter, in order to prove MTJ STO’s potential use as a microwave oscillator,an MTJ STO has been connected through a bias-tee to the proposed widebandamplifier, as illustrated in Figure 4.15, forming the MTJ STO-based microwaveoscillator. The MTJ STO used in this work is based on CoFeB/MgO/CoFeB com-position structure [8], has an approximate diameter of 240 nm and consumes amaximum power of 5.15 mW. The MTJ STO presents a measured tunability of 3GHz - 9 GHz [8], as illustrated in Figure 2.5.

Figure 4.15: Measurement setup of the MTJ STO-based microwave oscillator

The measurement of the MTJ STO-based microwave oscillator has been donewith a fixed magnetic field H = 400 Oe and a magnetic angle of 15o (Figure4.16). The measured power spectrum of the MTJ STO-based microwave oscillatorgiven in Figure 4.16 demonstrates the DC current tunability of this oscillator. Byfurther tuning the magnetic field, a large tunability of 3 GHz - 7 GHz can beachieved. Table 4.2 summarizes the performance of the proposed MTJ STO-basedmicrowave oscillator, and gives a comparison to other works. Compared to thesolution in [9], the proposed microwave oscillator gives a much wider tunable range.In comparison toMini-Circuits ZVE-3W-83+, the proposed wideband amplifier hassmaller area, lower power consumption, and hence allows a direct connection to theMTJ STO using chip-on-board technique. Additionally, the proposed microwaveoscillator is able to be directly connected to other RF blocks in multi-standard radio

52 CHAPTER 4. CMOS WIDEBAND AMPLIFIER FOR MTJ STO

Figure 4.16: Measurement results of the MTJ STO-based microwave oscillator

applications, thanks to the good impedance matching, low power consumption,large gain and wide bandwidth of the proposed amplifier.

To conclude, by combining the emerging MTJ STO technology and a dedicatedCMOS wideband amplifier IC, the proposed power enhancement approach booststhe low output power of the highly-tunable MTJ STO to a level that can be directlyused by a PLL. Meanwhile, the proposed wideband amplifier also takes a large partof the extremely wide tunability range of the MTJ STO, while improving the noiseperformance within the band of interest. The (MTJ STO+amplifier IC) pair as anentire microwave oscillator presents a measured Q of about 170 and a tunability of3 GHz - 7 GHz, which is much wider compared to the state-of-the-art CMOS-basedVCO. Consequently, the proposed microwave oscillator opens the possibility of anew microwave source for multi-band, multi-standard radios.

4.3. MEASUREMENT RESULTS AND DISCUSSION 53

Table 4.2: Performance comparison: MTJ STO+amplifier IC pair

This work ZVE-3W-83+ STO+AmplifierISSCC 2009[9]

MTJ STO

STOresistance [Ω] ∼50 (TMR=70%) >200

(TMR=41%)Qualityfactor (Q) ∼170 -

Outputpower [dBm] -60 ∼ -40 -45

Tuningrange [GHz] 3 ∼ 9 4 ∼ 10 (Read

from the figure)STOdiameter [nm] 240 nm 240 nm

Power con-sumption [mW] 3.2 -

Amplifier

Process 65 nm CMOS1.2 V

-15 V

130 nm CMOS-

Gain [dB] 35 (typ.) 35 (typ.) 22Bandwidth[GHz] 2 ∼ 7 2 ∼ 8 <5

S11 [dB] -10 (typ.) -14 (typ.) -0.2 ∼ -1.8S22 [dB] -10 (typ.) -15.5 (typ.) -15NF [dB] 5 5.8 (typ.) 4IIP3 [dBm] -28 7 (typ.) -

Area [mm2] 0.16(LNA: 0.0044)

3013(heat sinkis needed)

-

Power con-sumption [mW]

38(core: 25.44) 12000 -

MTJ STO+ IC pair

Integrationmethod

Chip-on-board/No No Chip-on-board

Bandwidth[GHz] 3 ∼ 7 3 ∼ 8 4 ∼ 5

Chapter 5

CMOS Circuits for GMR STOMeasurement Setup

This chapter firstly focuses on the design of the high frequency circuits for GMRSTO, based on the system analysis and the proposed GMR STO-measurement setupgiven in Chapter 3. Secondly, the chapter presents the stand-alone measurementsof both GMR STO and the proposed CMOS high frequency IC. Thereafter, thechapter presents the measurement results of the (GMR STO+IC) pair and discussesthe issues identified in the measurements.

5.1 On-chip bias-tee

A bias-tee is necessary to supply DC current to the STO, while allowing only theAC signals to pass from the STO to the following stage. A bias-tee is a passivecomponent, which has three ports: an AC port, a DC port and an (AC+DC)port. The bias-tee usually consists of a capacitor (C) between AC and (AC+DC)ports to block the DC signal, and a resistor (R) or an inductor (L) between DCand (AC+DC) ports to provide a DC current without disturbing the AC signal.The topology of the dedicated on-chip bias-tee is determined by the amount ofDC current required for the application. For applications that require small DCcurrents, the RC bias-tee is preferred to offer flat impedance over a wide frequencyrange, while producing only a small voltage drop across the resistor and dissipatinglow power [12]. In this work, the maximum DC current required to be handled bythe bias-tee is about 30 mA. By using the RC bias-tee, a large voltage drop will bedetected across R, as R has to be large enough to block the AC signal from the DCpower supply. As a result, the RC bias-tee topology is not acceptable in this work.Meanwhile, the LC bias-tee is not an optimal solution for wideband operation dueto the parasitics of the on-chip inductors. To overcome these issues of differentbias-tee topologies at high frequencies, a bias-tee combining a capacitor (Cblock),resistor (R1), on-chip inductor (L1) and bond wire (L2), is proposed in this work

55

56CHAPTER 5. CMOS CIRCUITS FOR GMR STO MEASUREMENT SETUP

Cblock

R1

DC port

AC & DC port

L1

L2

Cap to avoid

DC interactions

C0

STORS = 5.5Ω

LS

Zin

AC port

Figure 5.1: On-chip Bias-tee

and is depicted in Figure 5.1.The series impedance ZAC in the signal path can be expressed by

ZAC = Rcap + j

ωCblock(5.1)

where Rcap is the series resistance of the capacitor Cblock. This ZAC should beminimized to avoid AC voltage drop across Cblock. It can be found in Eq.(5.1)that a small ZAC can be achieved by employing a large Cblock. However, a largerCblock has larger undesired fringe capacitance, which degrades the signal at highfrequencies and will be added in parallel to the input impedance of the requiredIC for GMR STOs. In order to minimize the fringe capacitance, a Metal-insulator-Metal (MIM) capacitor will be used as Cblock in this work. ZAC and the parasiticimpedance ZOX introduced by the fringe capacitance of MIM capacitors at 10 GHzcan be then plotted as a function of Cblock, which is given in Figure 5.2. A cornerof Cblock can be seen around 1.3 pF, which is the optimal value for signal deliveryand thus will be used for DC decoupling.

The total impedance ZDC in the DC path can be written as

ZDC = jω(L1 + L2) +R1 (5.2)

L1 can be implemented by either a stack inductor or a spiral inductor. The stackinductor can provide a higher inductance value by taking a smaller silicon area.However, it is implemented by stacking several low-K metal layers, which bringslarge parasitics hence leads to low self-resonant frequency (SRF) and low qualityfactor (Q). A spiral inductor is using high-K top metal layer, which gives a higherQ and lower parasitics than the stack inductor. Consequently, the spiral induc-tor is more suitable for high frequency STO applications and will be employed inthis work. It should be noted that the on-chip inductor design includes trade-offs

5.2. ON-CHIP ESD PROTECTION 57

0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 50

1 02 03 04 05 06 07 08 0

Z A C Z O X

C b l o c k ( p F )

Z AC(Ω

)

5 0 01 0 0 01 5 0 02 0 0 02 5 0 03 0 0 03 5 0 0

Z OX(Ω

)Figure 5.2: ZAC and ZOX as a function of Cblock

between inductance value, SRF or Q, and current handling. These trade-offs are in-volved in selecting the number of turns, separation distance between each turn andwidth of metallization for the inductor. Considering these trade-offs, the designedspiral inductor gives an inductance of 1.6 nH, using 4.5 turns, 2.3 um spacing, 2.5um metallization width, and occupying a total area of 80 um × 80 um.

By using the wire bonding integration method, an inductance L2 of the bondwire is added into the total impedance at high frequencies for free. This bond wireinductance has a high Q, but it cannot totally replace the on-chip inductor. Thisis because the bond wire requires an on-chip pad, which directly acts as a shuntcapacitor to ground and thus would shunt the AC signal at high frequencies.

A resistor R1 is connected in series to the inductor L1 and the bond wire L2, toprovide an extra flat impedance over a wide frequency range. In order to preventlarge voltage drop and power dissipation, R1 is chosen 120 Ω. This R1 is placedclosest to the high frequency signal path for the purpose of isolating parasitic ca-pacitances of the on-chip inductor from the signal path.

5.2 On-chip ESD protection

Heating and electromigration effects are the main concerns that limit the operationof GMR STOs. Our experience with GMR STOs tells us that a maximum currentof 40 mA can be injected into a GMR STO, which has a 100 nm contact and a ∼5Ω resistance. As a result, the breakdown voltage of these devices is low and can becalculated to be approximately 200 mV, which highly requires an ESD protectionfor STO-based applications. Besides, the CMOS RF transistors used in this workhave breakdown voltages around 3 V, where ESD protection is necessary whilechallenging due to the trade-off between the ESD robustness and parasitics [69].

58CHAPTER 5. CMOS CIRCUITS FOR GMR STO MEASUREMENT SETUP

Accordingly, these paths that require ESD protections are considered and illustratedin Figure 5.3. Possible ESD approaches given in [54] are investigated. To achievelarge bandwidth at high frequencies and fully utilize the parasitcs introduced bythe ESD components, the ESD protection is designed to be embedded in the inputand output networks, which will be detailed discussed in the next subsection. ESDprotection diodes are added at both input and output pads to protect both theSTO and the IC. In order to allow a large current (∼ 30 mA) passing through theproposed bias-tee without triggering the clamp circuit, no ESD protection is addedat the pad for IDC . Fortunately, the inductor of the proposed bias-tee shunt theESD current to the ESD protected input pad. The sizes of these diodes are 30um × 2 um, which can provide basic ESD protections while the parasitics can behandled by the intput and output networks.

GMR STO

InternalCircuits C

lam

pC

ircu

its

VDD

GND

IDCESD

event

Pad

RF input

RF output

Figure 5.3: On-chip ESD protection

5.3 Input and Output Networks

As discussed above, a lot of parasitics are introduced by bond wires, on-chip bias-tee and ESD protection diodes. Moreover, other parasitics that should be carefullyconsidered are brought by on-chip and off-chip pads and routing wires. All of theseparasitics make the dedicated IC for GMR STOs challenging to achieve widebandoperation at high frequencies. To relieve the impacts of these parasitics on mi-crowave performances, input and output networks are proposed by utilizing theseparasitics to build input and output filters, so as to trade voltage gain at specificfrequencies for achieving a flat frequency response over the required bandwidth.

To make full use of all parasitics mentioned above, a 5th-order LC low-passfilter can be achieved at the input by adding only an on-chip inductor Lcomp andan auxiliary capacitor Ca, as illustrated in Figure 5.4. Based on the mathematical

5.4. AMPLIFICATION STAGE 59

VDD

Cp1

Lbond

L1

R1

Lcomp Cblock

Cp2

IDC PAD

On-chipOff-chip

Bias-tee

RFPAD

RFPAD

CPAD

CESD

To amplifierFrom STO

Ca

Figure 5.4: Input network

analysis in Matlab, an LC low-pass filter that has the following values for L and C:

Ci1 = 20fF ;Li1 = 0.6nH;Ci2 = 250fF ;Li2 = 0.6nH;Ci3 = 20fF (5.3)

is required to obtain a flat frequency response over the band of interest. Conse-quently, Cp1 and Cp2 are the off-chip and on-chip parasitic capacitances, and canbe simply used as Ci1 and Ci3, respectively. In order to compensate the bond wireas discussed in Chapter 3, two bond wires configured in parallel would act as theLi1 in this LC low-pass filter, since a feasible bond wire with a ∼ 1.2 mm lengthwould introduce ∼ 1.2 nH as a rule of thumb. In addition, the required relativelylarge Ci2 can be implemented by the parasitic capacitances of two RF pads for twobond wires and ESD diodes, which gives a CP AD × 2 +CESD ∼200 fF in total. Asa result, considering the parasitics of routing wires, an additional auxiliary MIMcap Ca =∼50 fF and a small on-chip inductor Lcomp are inserted to complete theLC low-pass filter at the input.

In order to GSG probe the output of the dedicated IC for GMR STOs, GSGpads with a 150 um pad-pitch are required at the output for measurement purpose.To fully utilize the parasitics of the signal pad and ESD diodes at the output, a3rd-order Butterworth bandpass filter (shunt) can be realized, as it is illustratedin Figure 5.5. Again, based on the analysis in Matlab, the desired bandpass filtershould have the following values for L and C:

Co1 = 250fF ;Lo1 = 0.5nH;Co2 = 56fF ;Lo2 = 2.2nH;Co3 = 250fF ;Lo3 = 0.5nH(5.4)

Accordingly, the required corresponding components Co1, Co2 and Lo1 − Lo3 areintroduced to obtain the desired bandpass filter at the output.

5.4 Amplification Stage

The wideband amplifier for the GMR STO measurement setup is depicted in Figure5.6. This wideband amplifier consists of three cascoded CS stages, which bring

60CHAPTER 5. CMOS CIRCUITS FOR GMR STO MEASUREMENT SETUP

DC decoupling

Co1 Lo1

Lo2 Co2

Lo3

CESD

RFPAD

CPAD

VDD

From Amplifier

IC out

Figure 5.5: Output network

Ll1

Rl1

M1

M2

Ll2

Rl2

M3

M4

Ll3

Rl3

M5

M6

Rb1 Rb2 Rb3

VDD

GND

Rb0

Vin

Vout

Vb0

Figure 5.6: Amplification stage

simplicity, high gain and wide bandwidth while reducing the undesired Miller effect.Yet, each stage of the cascoded CS stage can only provide a -3 dB bandwidthof 6 GHz - 8 GHz and a voltage gain of 8 dB - 10 dB roughly. Additionally,considerable parasitics cannot be avoided during physical implementation, causing asignificant impact at high frequencies and therefore extra bandwidth shrinkage. Asa result, bandwidth enhancement is strongly needed in order to fulfill the bandwidthrequirement. Concerning required gain, bandwidth, noise and layout-introducedparasitics, a bandwidth enhancement approach using inductive peaking is used toprovide an impedance component that increases with frequency, compensating thesignificant gain drop at high frequencies. Inductive peaking technique is used ineach stage of the amplifier, where the inductors Lln (n = 1 ∼ 3) are arranged inseries with the load resistor Rln to shunt the total capacitances Cln seen at the

5.4. AMPLIFICATION STAGE 61

output nodes:

Cln = Cdb1 + Cgd1 + Cgs2 + Cp (5.5)

where Cdb1 and Cgd1 are the drain-bulk and gate-drain capacitances of the firststage respectively, Cgs2 is the gate-source capacitance of the next stage, Cp is thetotal parasitic capacitance introduced at that node. The total frequency-dependentload impedance Zload in each stage can be written as:

Zload = ( 1sCln

) ‖ (Rln + sLln) = Rln + sLln

1 + sRlnCln + s2LlnCln(5.6)

Eq.(5.6) indicates that the inductor Lln introduces a zero so that the total Zload

increases with frequency, compensating the impedance drop owing to Cln, and thusextending the bandwidth. In order to choose an optimal value for Lln, the rela-tionship between the frequency-dependent Zload and Lln is desired. To identify thisrelationship, it is assumed that a transistor with a size of 20um/60nm, which gives agm ∼ 15 mS, Cdb ∼ 1 fF, Cgd ∼ 6 fF, and Cgs ∼ 14 fF, will be used. Increasing thetransistor size allows higher gm and thus larger gain, yet, gives narrower bandwidthbecause of larger fringe capacitances. In addition to Cdb1 +Cgd1 +Cgs2 ∼ 20 fF, atotal parasitic capacitance of 40 fF (with margin) is considered due to the routingand interconnection. As a result, Cln ∼ 60 fF is employed to estimate the relation-ship between Zload and Lln. Moreover, Rln =225 Ω is assumed in order to meetthe required gain of ∼10 dB. Thereafter, the absolute value of Zload as a functionof Lln is able to be plotted, as given in Figure 5.7. This figure illustrates that atrelatively low frequencies (10 GHz - 12 GHz), as Lln increases, Zload also increases.Nevertheless, at higher frequencies, for instance, 14 GHz or 15 GHz, Zload doesnot follow the increasing Lln anymore. Instead, at 15 GHz, Zload reaches its peakvalue when the Lln is around 3 nH, and then Zload starts decreasing as Lln fur-ther increases. Besides, considering the fact that larger inductor comes with largerparasitic capacitance and hence lower SRF, a ∼ 2.5 nH inductor, which appearsat 15 GHz as a corner in Figure 5.7, is optimal and selected for the assumed case.Afterwards, based on these assumed parameters, the transistor sizes for M1 −M4were slightly adjusted since smaller M3 and M4 would not bring significant impacton the gain, while bringing lower parasitics. As a consequence, M1 and M3 takethe sizes of 22.4um/60nm, M2 and M4 utilize the sizes of 17.6um/60nm, Rl1 andRl2 are chosen 215 Ω and 227 Ω, respectively. Based on the previous analysis, theLl1 and Ll2 can be optimized as 2.2 nH. These design parameters, however, are notacceptable for the last stage since the last stage is responsible for driving 50 Ω, asexplained in Chapter 3. For this reason, transistorM5 with 32um/60nm size, whichoffers larger gm5, and the resistor Rl3 of 50 Ω, which provides output impedancematching, are employed in the last stage. The required inductor Ll3 is obtained inthe same way based on the chosen transistor size and resistor value, and is 1.25 nH.

62CHAPTER 5. CMOS CIRCUITS FOR GMR STO MEASUREMENT SETUP

1

2

3

4

100

150

200

250

300

350

400

10

12

14

Zload

()

Frequency (GHz)

Lln (nH)

179.0206.3233.5260.8288.0315.3342.5369.8397.0

Figure 5.7: Zload as a function of Lln

5.5 Post-layout Simulation Results

The entire CMOS high frequency IC for GMR STO measurement setup present inFigure 3.7, is designed and implemented in a 65nm CMOS process with a 1.2 Vpower supply. Since its high frequency operation is sensitive to any parasitics thatintroduced by floorplan and layout, special considerations regarding the floorplanand layout, should take account of the following aspects:

1. To enable the on-chip bias-tee to cope with a large DC current up to 30mA, excessiveness of vias and metal widths are necessary to avoid electromigrationproblems.

2. The floorplan and layout should minimize the layout-introduced parasitics,since any parasitic will degrade the performance at such high frequencies.

The post-layout simulated voltage gain of the proposed high-frequency IC forGMR STO is 12 dB with a -3 dB bandwidth of 10 GHz - 15.2 GHz. It should benoted that the transmission line on PCB is considered during this simulation, sincethis transmission line at such high frequencies has significant impact on the overallperformance. Besides, a maximum simulated 1.4 nV/

√Hz input referred noise is

achieved. In addition, the proposed IC has a simulated minimum power supplyrejection ratio (PSRR) of 55 dB. Monte Carlo simulations were performed to verifythe functionality of the proposed IC with extreme process variations.

5.6. MEASUREMENT RESULTS 63

5.6 Measurement Results

Figure 5.8(a) gives the die photo of the implemented high frequency IC for GMRSTO measurement setup. It consumes 14.3 mW from the 1.2 V power supply.In addition, the proposed IC takes a total silicon area of 700 um × 470 um =0.329 mm2. To characterize the proposed high frequency IC separately and thenmeasure it together with the GMR STO, the proposed IC has been wire bonded ona test board shown in Figure 5.8(b). The RF input is connected to 50 Ω microstriptransmission line on the PCB. The RF output of the IC is probed for measurementpurpose.

(a) (b)

700 um

470 um

Figure 5.8: (a). Die photo of the proposed high frequency IC (b). Test board forGMR STO measurement setup

5.6.1 Dedicated high frequency IC

Figure 5.9 presents the measured S12 of the proposed on-chip bias-tee. A maximumS12 of -20 dB indicates that a decent isolation can be achieved between the ACport and the DC port. Moreover, compared to the simulated S12, which does nottake the bond wire into consideration, the measured S12 further demonstrates thatthe bond wire does provide extra impedance at high frequencies for free.

The measurement results of the proposed high frequency IC are plotted in Fig-ure 5.10. Three chips (IC samples) have been wire bonded to the test boards and

64CHAPTER 5. CMOS CIRCUITS FOR GMR STO MEASUREMENT SETUP

Figure 5.9: Measured S12 of the on-chip bias-tee

measured. These chips present de-embedded voltage gains of about 13 dB, as it canbe seen in Figure 5.10(a). However, all of these chips show significant bandwidthshrinkage during measurement. Besides, noticed from Figure 5.10(a), the band-widths of different measured chips vary from each other. The bandwidth shrinkageand bandwidth difference may be mainly caused by bond wires at the RF inputs,because lengths of the wires are not identical on different PCBs.

To characterize the noise performance, the total output noise was measured, andthen referred to the input. Figure 5.10(b) illustrates the measured input referrednoise of the proposed IC. The larger input referred noise at lower frequencies isrelated to the gain degradation. At high frequencies, the measured input referrednoise follows the simulated result.

Figure 5.10(c) shows that the measured IIP3 of the proposed IC is -18 dBm.Since the GMR STO signal is very weak, as mentioned in the previous chapters,this IIP3 is sufficient for the GMR STO measurement setup.

5.6. MEASUREMENT RESULTS 65

(a)

(b)

(c)

Figure 5.10: Measurement results of the proposed high frequency CMOS IC forGMR STO: (a). Voltage gain (b). Input referred noise (c). IIP3

66CHAPTER 5. CMOS CIRCUITS FOR GMR STO MEASUREMENT SETUP

5.6.2 GMR STO

Thereafter, in order to examine the performance of GMR STOs and thus wire bondthe GMR STO to the proposed IC, GMR STOs were characterized separately beforewire bonding. A large number of GMR STOs was necessary for characterization.One reason is that the process varation of GMR STO is non-negligible so that astatistical analysis of the measurement results is highly informative. The otherreason is that the vulnerability of the pad structure, which can be damaged duringmeasurement and wire bonding, requires sufficient GMR STOs for wire bondingattempts. As a consequence, 6 dies of GMR STOs were measured in total. Table5.1 presents the measured results of all 70 nm GMR STOs with single nano-contactstructure on one die. From this table, it should be noticed that there are four issuesidentified during the characterization and therefore should be carefully consideredbefore wire bonding. Due to the required rotation of GMR STO in the electromag-net, pad damaging and probe sliding during GMR STO characterization preventthe microwave signal being detected at the output. Besides, a large number of GMRSTOs, which were placed and measured in the electromagnet with an out-of-plane

Table 5.1: GMR STO characterizationL04 1 Rtotal

2 RST O3 Current

PolarityNote Wire

bondingD1 12 5.14 correct Many RF modes of GMR

STO were detectedOK

D2 11.7 4.84 - RF properties of this GMRSTO was not characterizedfor protecting the pad frombeing damaged

OK

D3 11.6 4.74 - See D2 OKD4 11.75 4.89 wrong Probe slides during magnetic

field rotation, causing wrongcurrent polarity

OK

D5 11.98 5.12 correct The pad (waveguide) of thisGMR STO was broken dur-ing magnetic field rotation

NO

D6 11.8 4.94 - See D2 OKD7 11.73 4.87 - See D2 OKD8 ∝ ∝ - An open circuit was detected

across this GMR STONO

D9 11.78 4.92 correct See D1 OK

1L04DX represents Line #04 Device #X2Rtotal is the total measured resistance including the resistance of the GMR STO and the

resistance in the measurement setup3RST O is the measured RP of the GMR STO

5.6. MEASUREMENT RESULTS 67

angle of 85o, present undesired multi-mode behaviour. Furthermore, some GMRSTOs that show infinite or very low resistances (this case is not shown in the table),are not accepted and should not be wire bonded. Based on numerous measurementsof GMR STOs, the measurement result of a typical MR is provided in Figure 2.7.Besides, 20% of these GMR STOs were RF characterized by sweeping the magneticfield and DC current. The RF characterization results are shown in Figure 2.8. Forthe rest of GMR STOs, only DC characterization and vortex-mode [70] were exam-ined, since the rotation and RF measurement of the probed STO, which introducerisks destroying its pad (waveguide), should be avoided. Especially, experimentsinform that the STO can be hardly wire bonded after RF characterization. As aresult, a GMR STO, which has not been RF characterized, is used for wire bondingand the GMR STO measurement setup.

5.6.3 GMR STO measurement setup

As mentioned above, a GMR STO with a 70 nm dimension, a measured resistanceRP of 6.48 Ω and a clear vortex-mode, which has not been RF characterized in themagnetic field, was selected and wire bonded to the dedicated IC for GMR STOmeasurement setup. Before wire bonding, the die of GMR STO was diced to allowshort bond wires between the GMR STO and the dedicated IC, and hence littlehigh frequency signal degradation. As it can be seen in Figure 5.11, a wedge wirebonding technique was used as the first attempt to integrate the GMR STO withthe dedicated IC.

STO

CMOS IC

PCB

Figure 5.11: Integration of GMR STO and dedicated high frequency IC

68CHAPTER 5. CMOS CIRCUITS FOR GMR STO MEASUREMENT SETUP

Afterwards, to be able to fix the test board (with wire bonded GMR STO andthe dedicated IC) in the electromagnet, bulky SMA connectors and RF cables werereplaced by home-made shielded twisted-pair cables. To be able to observe themicrowave signal at the output of the (GMR STO+IC) pair, the output of the ICwas probed, and connected to the ZVA-213+ amplifier for sufficient gain.

Before rotating the magnetic field and starting the RF measurements, the DCbiasing for both GMR STO and IC was checked. The total impedance seen from thebias-tee was∼140 Ω, which is reasonable considering the combined impedance of theon-chip bias-tee and the GMR STO. Thereafter, in order to verify that the outputof the (GMR STO+IC) pair was properly probed, the dedicated IC was biased anda noise floor change was observed at the output. Then, a three-step probing methodwas developed during the measurement for the purpose of protecting the pads frombeing damaged. The first step is rotating the PCB outside the magnetic field to60o. The second step is placing the pre-rotated PCB into the electromagnet andprobing the output of the (GMR STO+IC) pair at 60o. The last step is rotatingthe PCB in the electromagnet to 85o gradually with a 5o step.

The final measurement setup for characterizing the RF performance of the(GMR STO+IC) pair is given in Figure 5.12. DC biasing and noise floor for the(GMR STO+IC) pair were further examined after rotating the probed PCB in theelectromagnet as shown in Figure 5.12. In order to characterize the RF perfor-mance of the (GMR STO+IC) pair, the current was swept from 0 mA to 25 mA,and the magnetic field was altered from 0.7 T to 1.2 T. However, no microwave

Electromagnet

PCB

RF probe and RF cable

Figure 5.12: Measurement setup of the (GMR STO+IC) pair

5.7. DISCUSSION 69

signal was able to be detected at the output of the (GMR STO+IC) pair. Theissues identified in these experiments and the possible cause of this problem aregoing to be discussed in the next section.

5.7 Discussion

To identify the cause of the problem, which was described above, possible issuesfound in these experiments, are considered in this section. Possible solutions arealso given in this section for future reference.

5.7.1 Process variation of STOs

To examine the impact of the STOs’ process variation on their RF performance,6 GMR STOs from the same batch with identical dimension (70 nm) were RFcharacterized under the same biasing condition: H = 0.9 T, angle (out-of-plane) =85o and IDC = 27 mA. The measurement results show that the operation frequenciesof these GMR STOs vary from 12.61 GHz to 14.31 GHz under the same biasingcondition. Accordingly, this problem with device-to-device reproducibility of GMRSTOs should be solved at device level in order to enable reliable STO-based systems.However, this large process variation is not the cause of the problem of no detectedmicrowave signal in the measurement, since the bandwidth of the dedicated IC isable to cover these different operation frequencies.

5.7.2 Pad structure

Experiments indicate that the pad or waveguide structure of the GMR STO isvulnerable. For example, broken waveguide has been obtained after RF character-ization and is depicted in Figure 5.13(a). It can be observed in Figure 5.13(a) thatthe signal pad lost connection to the GMR STO during measurement. In addition,this problem also occurs during wire bonding. This problem is mainly due to theweak strength of the metal-oxide interface adhesion using copper metallization. Thesolution to this problem is to improve adhesion of the metal-oxide interface dur-ing fabrication. Possible approach is to use platinum or aluminium metallizationinstead of copper metallization [71].

In addition, the pad structure designed for the dedicated IC is not optimal forthe existing measurement setup. This brought another difficulty in measuring the(GMR STO+IC) pair. It can be seen from the probing marks in Figure 5.13(b) thatthe GSG probe slides towards the right side during the rotation in the electromag-net. One possible solution is to design larger pad on the dedicated IC. However,larger pad introduces larger parasitics, which takes a lot of effort to cope with inorder to achieve wideband operation. Another possible solution is to use a self-rotatable electromagnet to provide the required magnetic field for GMR STO. Thissolution would avoid rotating the entire probed test board as given in Figure 5.12.

70CHAPTER 5. CMOS CIRCUITS FOR GMR STO MEASUREMENT SETUP

(a)

(b)

Figure 5.13: Pad structures of (a). GMR STO and (b). the dedicated IC

5.7. DISCUSSION 71

5.7.3 Wire bonding

As it can be seen in Figure 5.14, the power rail (VDD, metal 8) and the die sealring (= grounded through P+ contacts) are located 2.3 um and 10 um away fromthe aluminium pad in the pad ring, respectively. A failed case of wire bondingcan be seen in Figure 5.14, the gold wires are wedge-bonded, and their wedges arepartially overlapped with the power rail, causing short circuits between the padsand the power rail due to the damaged inter-layer dielectric (ILD). The solution tothis wire bonding problem is to use ball bonding instead of wedge bonding.

Figure 5.14: Issue of wire bonding

In addition, failed wire bonding may lead to a short circuit, and hence causethe problem that no RF signal was detected at the output during measurement.However, no short circuit was identified by examining the bond wires after mea-surement.

72CHAPTER 5. CMOS CIRCUITS FOR GMR STO MEASUREMENT SETUP

5.7.4 Measurement setup stability

As shown in Figure 5.12, the probed test board was rotated in the electromagnetin order to achieve the required magnetic field biasing for GMR STO. In additionto the pad structure issue, another issue that was identified in this measurementsetup is the stability of the test board, which was taped on a narrow metal holder,as illustrated in Figure 5.12. A slight offset between the test board and the RFprobe during rotation could lead to an open circuit at the output between the RFprobe and the pads, which further results in no noise floor change at the output.The possible solution to this problem is to rotate the magnetic field using rotat-able electromagnet, instead of rotating the entire measurement setup with probeddevices.

5.7.5 Bias-tee reliability

During the (GMR STO+IC) pair measurement, two times of resistance changeswere observed from the DC port of the bias-tee. The first time was an instantresistance drop from 142 Ω to 125 Ω as the second attempt to inject a DC current(IDC = 25 mA) into the bias-tee. The second time was a gradual resistance increasefrom 125 Ω to 158 Ω as a function of time, when a large current (IDC = 25 mA) wasinjected into the bias-tee. The resistance drop may be explained as the ground andthe signal paths of STO were shorted. The later resistance increase is related tothe on-chip bias-tee. In order to identify the issue in the on-chip bias-tee, a bias-teereliability test was performed. In this reliability test, large currents (IDC > 20 mA)were injected into the on-chip bias-tee and the resistance seen from the DC portof the bias-tee was measured. As a current larger than 24 mA was injected intothe bias-tee, a resistance increase was observed. Thereafter, a 25 mA current wascontinuously injected into the bias-tee, and the resistance as a function of time wasrecorded, as plotted in Figure 5.15. This test result matches the case given in [72],where the resistance increase is caused by the electromigration-induced depletionunder through-silicon via (TSV).

As mentioned in Section 5.5, electromigration rules were considered during cir-cuit design. However, due to the design rule-introduced trade-off between the DCcurrent handling and the RF performance, a total vias (metal 7 - metal 8) numberof 8 was used in the on-chip inductor L1 (Figure 5.1) of the bias-tee. These viaswere designed to be able to handle a total current of 43.52 mA. Yet, it may bepossible that the available number of vias after fabrication is less than 8, for ex-ample, 7 or 6. As a result, when a large current was injected into the bias-tee, thelimited number of available vias may lead to the electromigration-induced depletionunder TSV. The possible solution is to design a dedicated on-chip inductor, whichis optimized for this required bias-tee, instead of using the inductors provided bythe foundry.

To conclude, the measurement results of the dedicated IC show the potentialityto enhance the output power of GMR STOs by means of avoiding probing and

5.7. DISCUSSION 73

130

135

140

145

150

155

160

165

1 2 3 4 5 6 7 8 9

Me

asu

red

Re

sist

ance

Time (minute)

Figure 5.15: Resistance increase as a function of time (IDC = 25 mA)

signal losses on external components and interconnections. As the possible causeand measurement issues have been identified as given above, further attempts tomeasure the (GMR STO+IC) pair will be carried out in the future.

Chapter 6

Conclusions and Future Work

The state-of-the-art STO technology features large tunability, high integration level,superior quality factor, high operating frequency, and miniature size, making it apromising technology for microwave and radar applications. In order to capturemost of the STO’s advantages and capitalize its potential benefits, the workingprinciple of STOs, and the state-of-art MTJ and GMR STOs have been studied.

Based on STOs’ studies, possible applications of the STO technology have beeninvestigated, including but not limited to frequency detector, modulator, magneticfield sensor and microwave oscillator. Most suitable application of the state-of-the-art STO technology is the MTJ STO-based microwave oscillator. Yet, thisSTO-based oscillator cannot realize its application unless its low output powerissue can be solved. Therefore, in order to enhance the output power of STOand hence make it usable as a microwave oscillator, different power enhancementtechniques have been investigated. According to this investigation, the only possibleapproach at present is to use a dedicated amplifier targeting MTJ STO technology.Accordingly, a dedicated wideband amplifier has been proposed and analyzed, tovalidate the proposed approach for the state-of-the-art MTJ STO. Important factorsincluding the required power transfer, gain, bandwidth, noise and linearity havebeen also considered. The proposed wideband amplifier has been implemented byemploying a novel Balun-LNA, an amplification stage and an output buffer. Thisfully-ESD protected amplifier was implemented in 65 nm CMOS technology, usinga 1.2 V power supply. Performance measurements of the stand-alone amplifier andthe (STO+amplifier IC) pair exhibit that the proposed approach enables a directconnection between the (STO+amplifier IC) pair and a PLL in an STO-basedsystem. Consequently, this proposed approach brings STO technology one stepcloser to multi-standard, multi-band radios, while opening the possibility of a newhighly-tunable microwave source.

GMR STO is widely used in the present studies of STO’s dynamic properties.The GMR STO provides a wider tunable range of higher frequencies, yet, withlower output power, compared to MTJ STO. In addition, the current measurement

75

76 CHAPTER 6. CONCLUSIONS AND FUTURE WORK

setup of GMR STO is composed of bulky RF discrete components and lossy RFcables, which is not optimal from power transfer and noise points of view. In orderto overcome the difficulties in measuring GMR STO due to its extremely low out-put power and the non-optimal measurement setup, and therefore facilitate futureSTO’s studies, an efficient approach is to integrate the GMR STO with a dedicatedCMOS high frequency IC, in order to avoid losses in the measurement setup. Tobetter integrate STO and CMOS technologies, multiple integration methods havebeen explored. Based on the examination and evaluation, the integration methodbased on wire bonding has been analyzed and employed, as a first integration at-tempt of STO and CMOS technologies. Based on the chosen integration methodand the state-of-the-art GMR STO, the system architecture of the dedicated highfrequency CMOS IC for GMR STO has been proposed, considering the followingkey factors: full integration, required DC bias current for STO, bandwidth, noise,pre-amplification. The proposed system is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage, which isused to amplify the weak signal generated by the GMR STO. The on-chip bias-teehas been measured, demonstrating that it is able to provide the required isolationand DC current handling. Additionally, measurement results of the dedicated ICshow a low noise amplification of a weak signal. To verify the integration concept,a GMR STO with 70 nm dimension has been wire bonded with the proposed IC.However, the measurement of the (GMR STO+IC) pair has failed in obtaining theamplified STO signal at the output. By debugging, a short circuit has been de-tected at the GMR STO, which results in no detected RF signal. The overall (GMRSTO+IC) pair experiments show that the issues identified in Chapter 5 should besolved, in order to realize a reliable GMR STO measurement setup.

In this thesis, high frequency ICs for the state-of-the-art STO technology havebeen investigated. Both MTJ and GMR STOs have been considered. The achievedresults demonstrate that, by compensating the low output power of the MTJ STOusing the proposed dedicated amplifier, the (MTJ STO+amplifier IC) pair hasgreat potential to be used as a microwave oscillator. Moreover, the fact that the(GMR STO+IC) pair could not be measured successfully, suggested that the STOis still in its early stages and is not yet ready to be packaged. This work is a firstattempt of promoting STO technology toward applications, hence a tremendousamount of work is required before STO technology can be optimized for microwaveapplications. On one hand, external circuitries, which are required to compensatethe STO’s low output power and spectrum impurity, consume extra silicon areaand power. Thus, the (STO+IC) pair does not seem to outperform other maturetechnologies, such as MMIC and CMOS, and hence it is not yet competitive. Onthe other hand, the main obstacles for STO-based applications are their spectrumimpurity and dependence on the external magnetic field.

With respect to the circuit aspect, future research may include investigation ofother circuit solutions for enhancing the output power of the STO and improvingthe dedicated bias-tee for STO. For instance, injection-locked ring oscillator (ILRO)[65] can be used to overcome the low output power issue, by injecting the STO

77

signal to a high power and low spectral purity oscillator, such as a CMOS-basedring oscillator. In addition, an off-chip PCB-based bias-tee, up to 10 GHz, can berealized to provide the required biasing for the STO while avoiding lossy cablesand connectors, and hence allowing better RF performance. Moreover, future workmay consider other possible applications of STO technology, such as frequencydetectors and magnetic sensors, and propose CMOS circuits required to developsuch detectors or sensors.

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