cmos inverter nand nor gates
TRANSCRIPT
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EE1411
D
igital Integrated Circuits2nd Combinational Circ
IntegratedIntegrated
CircuitsCircuits
A DesignA DesignPerspectivePerspective
Designing CombinationalDesigning Combinational
Logic CircuitsLogic Circuits
Jan M. Rabaey
Anantha ChandrakasanBorivoje Nikoli
November 2002.
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EE1412
D
igital Integrated Circuits2nd Combinational Circ
om na ona vs. equen aom na ona vs. equen aLogicLogic
Combinational Sequential
Output =f(In) Output =f(In, Previous In)
CombinationalLogic
Circuit
OutIn
CombinationalLogic
Circuit
OutIn
State
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EE1413
D
igital Integrated Circuits2nd Combinational Circ
Static CMOS CircuitStatic CMOS Circuit
At every point in time (except during the switchingtransients) each gate output is connected to eitherVDDorVssvia a low-resistive path.
The outputs of the gates assumeat all timesthevalueof the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects duringswitching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on thecapacitance of high impedance circuit nodes.
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EE1414
D
igital Integrated Circuits2nd Combinational Circ
a c omp emen ary a c omp emen ary CMOSCMOS
VDD
F(In1,In2,InN)
In1
In2
InN
In1
In2
InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networks
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EE1415
D
igital Integrated Circuits2nd Combinational Circ
NMOS TransistorsNMOS Transistors
in Series/Parallel Connectionin Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X
Y
A
B Y = X if A OR B
NMOS Transistors pass a strong 0 but a weak 1
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EE1416
D
igital Integrated Circuits2nd Combinational Circ
PMOS TransistorsPMOS Transistors
in Series/Parallel Connectionin Series/Parallel Connection
X Y
A B
Y = X if A AND B = A + B
X Y
A
B Y = X if A OR B = AB
PMOS Transistors pass a strong 1 but a weak 0
PMOS switch closes when switch control input is low
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7Digital Integrated Circuits2nd Combinational Circ
Threshold DropsThreshold Drops
VDD
VDD 0PDN
0 VDD
CL
CL
PUN
VDD
0 VDD
- VTn
CL
VDD
VDD
VDD |VTp |
CL
S
D S
D
VGS
S
SD
D
VGS
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8/114EE141
8Digital Integrated Circuits2nd Combinational Circ
StyleStyle
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9Digital Integrated Circuits2nd Combinational Circ
Example Gate: NANDExample Gate: NAND
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EE14110
Digital Integrated Circuits2nd Combinational Circ
Example Gate: NORExample Gate: NOR
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EE14111Digital Integrated Circuits2nd Combinational Circ
Complex CMOS GateComplex CMOS Gate
OUT = D + A (B + C)
D
A
B C
D
A
B
C
C t ti C lC t ti C l
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EE14112Digital Integrated Circuits2nd Combinational Circ
Constructing a ComplexConstructing a Complex
GateGate
C
(a) pull-down network
SN1 SN4
SN2
SN3D
FF
A
DB
C
D
F
A
B
C
(b) Deriving the pull-up networkhierarchically by identifying
sub-nets
D
A
A
B
C
VDD VDD
B
(c) complete gate
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EE14113Digital Integrated Circuits2nd Combinational Circ
Cell DesignCell Design
Standard Cells General purpose logic
Can be synthesized
Same height, varying width
Datapath Cells For regular, structured designs (arithmetic)
Includes some wiring in the cell Fixed height and width
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EE14114Digital Integrated Circuits2nd Combinational Circ
Standard Cell LayoutStandard Cell Layout
Methodology 1980sMethodology 1980s
signals
Routing
channel
VDD
GND
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EE14115Digital Integrated Circuits2nd Combinational Circ
Standard Cell LayoutStandard Cell Layout
Methodology 1990sMethodology 1990s
M2
No Routing
channelsVDD
GNDM3
VDD
GND
Mirrored Cell
Mirrored Cell
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EE14116Digital Integrated Circuits2nd Combinational Circ
Standard CellsStandard Cells
Cell boundary
N Well Cell height 12 metal tracksMetal track is approx. 3 + 3Pitch =repetitive distance between object
Cell height is 12 pitch
2
Rails ~10
InOut
VDD
GND
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EE14117Digital Integrated Circuits2nd Combinational Circ
Standard CellsStandard Cells
InOut
VDD
GND
In Out
VDD
GND
With silicideddiffusion
With minimaldiffusionrouting
OutIn
VDD
M2
M1
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EE14118Digital Integrated Circuits2nd Combinational Circ
Standard CellsStandard Cells
A
Out
VDD
GND
B
2-input NAND gate
B
VDD
A
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EE14119Digital Integrated Circuits2nd Combinational Circ
Stick DiagramsStick Diagrams
Contains no dimensionsRepresents relative positions of transistors
In
Out
VDD
GND
Inverter
A
Out
VDD
GNDB
NAND2
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EE14120Digital Integrated Circuits2nd Combinational Circ
Stick DiagramsStick Diagrams
C
A B
X = C (A + B)
B
A
C
i
j
j
VDDX
X
i
GND
AB
C
PUN
PDNABC
Logic Graph
wo ers ons owo ers ons o +
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EE14121Digital Integrated Circuits2nd Combinational Circ
wo ers ons owo ers ons o +B)B)
X
CA B A B C
X
VDD
GND
VDD
GND
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EE14122Digital Integrated Circuits2nd Combinational Circ
Consistent Euler PathConsistent Euler Path
j
VDDX
X
i
GND
AB
C
A B C
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EE14123Digital Integrated Circuits2nd Combinational Circ
OAI22 Logic GraphOAI22 Logic Graph
C
A B
X = (A+B)(C+D)
B
A
D
VDDX
X
GND
AB
C
PUN
PDN
C
D
D
ABCD
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EE141 24Digital Integrated Circuits2nd Combinational Circ
Example: x = ab+cdExample: x = ab+cd
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}
b
u ngereu ngere
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EE141 25Digital Integrated Circuits2nd Combinational Circ
u - ngereu - ngereTransistorsTransistors
One finger Two fingers (folded)
Less diffusion capacitance
P i f C lP ti f C l t
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EE141 26Digital Integrated Circuits2nd Combinational Circ
Properties of ComplementaryProperties of Complementary
CMOS Gates SnapshotCMOS Gates Snapshot
High noise margins:
VOHand VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:(under appropriate sizing conditions)
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EE141 27Digital Integrated Circuits2nd Combinational Circ
CMOS PropertiesCMOS Properties
Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative
device sizes; ratioless
Always a path to Vdd or Gnd in steady state; low
output impedance Extremely high input resistance; nearly zero
steady-state input current
No direct path steady state between power and
ground; no static power dissipation Propagation delay function of load capacitance
and resistance of transistors
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EE141 28Digital Integrated Circuits2nd Combinational Circ
Switch Delay ModelSwitch Delay Model
AReq
A
Rp
A
Rp
A
Rn CL
A
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
NAND2 INVNOR2
npu a ern ec snpu a ern ec s
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EE141 29Digital Integrated Circuits2nd Combinational Circ
npu a ern ec snpu a ern ec son Delayon Delay
Delay is dependent onthe pattern of inputs
Low to high transition
both inputs go low delay is 0.69 Rp/2 CL
one input goes low delay is 0.69 Rp CL
High to low transition both inputs go high
delay is 0.69 2Rn CL
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
e ay epen ence on npue ay epen ence on npu
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EE141 30Digital Integrated Circuits2nd Combinational Circ
e ay epen ence on npue ay epen ence on npuPatternsPatterns
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=10
A=1, B=10
A=1 0, B=1
time [ps]
Voltage[V]
Input Data
Pattern
Delay
(psec)
A=B=01 67
A=1, B=01 64
A= 01, B=1 61
A=B=10 45
A=1, B=10 80
A= 10, B=1 81
NMOS = 0.5 m/0.25 mPMOS = 0.75 m/0.25 m
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EE141 31Digital Integrated Circuits2nd Combinational Circ
Transistor SizingTransistor Sizing
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
2
2
2 2
1 1
4
4
T i Si i
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EE141 32Digital Integrated Circuits2nd Combinational Circ
Transistor Sizing aTransistor Sizing a
Complex CMOS GateComplex CMOS Gate
OUT = D + A (B + C)
D
A
B C
D
A
B
C
1
2
2 2
4
4
8
8
6
3
6
6
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EE141 33Digital Integrated Circuits2nd Combinational Circ
Fan-In ConsiderationsFan-In Considerations
DCBA
D
C
B
A CL
C3
C2
C1
Distributed RC model(Elmore delay)
tpHL = 0.69 Reqn (C1+2C2+3C3+4CL)
Propagation delay deteriorates
rapidly as a function of fan-in
quadratically in the worst case.
pp
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EE141 34Digital Integrated Circuits2nd Combinational Circ
pp --InIn
tpLH
t p(psec)
fan-in
Gates with a
fan-ingreater than
4 should be
avoided.0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
tpHL
quadratic
linear
tp
pp
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EE141 35Digital Integrated Circuits2nd Combinational Circ
pp --OutOut
2 4 6 8 10 12 14 16
tpNOR2
t p(psec)
eff. fan-out
All gates
have the
same drive
current.
tpNAND2
tpINV
Slope is a
function of
drivingstrength
pp
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EE141 36Digital Integrated Circuits2nd Combinational Circ
pp --and Fan-Outand Fan-Out
Fan-in: quadratic due to increasing resistance
and capacitance
Fan-out: each additional fan-out gate adds two
gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
Fast Complex Gates:Fast Complex Gates:
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EE141 37Digital Integrated Circuits2nd Combinational Circ
Fast Complex Gates:Fast Complex Gates:
Design Technique 1Design Technique 1
Transistor sizing
as long as fan-out capacitance dominates
Progressive sizing
InN CL
C3
C2
C1In1
In2
In3
M1
M2
M3
MNDistributed RC line
M1 > M2 > M3 > > MN
(the fet closest to the
output is the smallest)
Can reduce delay by more than
20%; decreasing gains as
technology shrinks
F t C l G tFast Complex Gates:
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EE141 38Digital Integrated Circuits2nd Combinational Circ
Fast Complex Gates:Fast Complex Gates:
Design Technique 2Design Technique 2
Transistor ordering
C2
C1In1
In2
In3
M1
M2
M3 CL
C2
C1In3
In2
In1
M1
M2
M3 CL
critical path critical path
charged1
01 charged
charged1
delay determined by time to
discharge CL, C1 and C2
delay determined by time to
discharge CL
1
1
01 charged
discharged
discharged
Fast Complex Gates:Fast Complex Gates:
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EE141 39Digital Integrated Circuits2nd Combinational Circ
Fast Complex Gates:Fast Complex Gates:
Design Technique 3Design Technique 3
Alternative logic structures
F = ABCDEFGH
Fast Complex Gates:Fast Complex Gates:
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EE141 40Digital Integrated Circuits2nd Combinational Circ
Fast Complex Gates:Fast Complex Gates:
Design Technique 4Design Technique 4
Isolating fan-in from fan-out using buffer
insertion
CLCL
Fast Complex Gates:Fast Complex Gates:
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EE141 41Digital Integrated Circuits2nd Combinational Circ
Fast Complex Gates:Fast Complex Gates:
Design Technique 5Design Technique 5
Reducing the voltage swing
linear reduction in delay
also reduces power consumption
But the following gate is much slower!
Or requires use of sense amplifiers on thereceiving end to restore the signal level (memorydesign)
tpHL = 0.69 (3/4 (CL VDD )/ IDSATn )
= 0.69 (3/4 (CL Vswing )/ IDSATn )
z ng og c a s orz ng og c a s or
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EE141 42Digital Integrated Circuits2nd Combinational Circ
z ng og c a s or z ng og c a s or SpeedSpeed
Frequently, input capacitance of a logic path isconstrained
Logic also has to drive some capacitance
Example: ALU load in an Intels microprocessoris 0.5pF
How do we size the ALU datapath to achievemaximum speed?
We have already solved this for the inverterchain can we generalize it for any type oflogic?
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EE141 43Digital Integrated Circuits2nd Combinational Circ
Buffer ExampleBuffer Example
( )=
+=N
i
iii fgpDelay1
For given N: Ci+1 /Ci = Ci/Ci-1To find N: Ci+1 /Ci ~ 4
How to generalize this to any logic path?
CL
In Out
1 2 N
(in units of inv)
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EE141 44Digital Integrated Circuits2nd Combinational Circ
Logical EffortLogical Effort
( )fgp
C
CCRkDelay
in
Lunitunit
+=
+=
1
p intrinsic delay (3kRunit Cunit ) - gate parameter f(W)
g logical effort (kRunit Cunit ) gate parameter f(W)f effective fanout
Normalize everything to an inverter:
ginv =1,pinv = 1
Divide everything by inv(everything is measured in unit delays inv)
Assume = 1.
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EE141 45Digital Integrated Circuits2nd Combinational Circ
Delay in a Logic GateDelay in a Logic Gate
Gate delay:
d= h +p
effort delay intrinsic delay
Effort delay:
h = g f
logicaleffort
effective fanout =Cout/Cin
Logical effort is a function of topology, independent of sizing
Effective fanout (electrical effort) is a function of load/gate size
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EE141
46Digital Integrated Circuits2nd Combinational Circ
Logical EffortLogical Effort
Inverter has the smallest logical effort and
intrinsic delay of all static CMOS gates
Logical effort of a gate presents the ratio of its
input capacitance to the inverter capacitancewhen sized to deliver the same current
Logical effort increases with the gate
complexity
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EE141
47Digital Integrated Circuits2nd Combinational Circ
Logical EffortLogical Effort
Logical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output current
g= 1 g= 4/3 g= 5/3
B
A
A B
F
VDDVDD
A B
A
B
F
VDD
A
A
F
1
2 2 2
2
2
1 1
4
4
Inverter 2-input NAND 2-input NOR
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EE141
48Digital Integrated Circuits2nd Combinational Circ
Logical Effort of GatesLogical Effort of Gates
Fan-out (h)
Normaliz e
ddela
y(d)
t
1 2 3 4 5 6 7
pINV
tpNAND
F(Fan-in)
g=p =
d=
g=
p =
d=
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EE141
49
Digital Integrated Circuits2nd Combinational Circ
Logical Effort of GatesLogical Effort of Gates
Fan-out (h)
Normaliz e
ddela
y(d)
t
1 2 3 4 5 6 7
pINV
tpNAND
F(Fan-in)
g= 1p = 1
d= h+1
g= 4/3
p = 2
d= (4/3)h+2
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EE141
50
Digital Integrated Circuits2nd Combinational Circ
Logical Effort of GatesLogical Effort of Gates
IntrinsicDelay
EffortDelay
1 2 3 4 5
Fanoutf
1
2
3
4
5
Inve
rter: g
=1; p
=1
2-in
putNAN
D:g=
4/3;
p=2
NormalizedD
elay
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51
Digital Integrated Circuits2nd Combinational Circ
Add Branching EffortAdd Branching Effort
Branching effort:
pathon
pathoffpathon
C
CCb
+=
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EE141
52
Digital Integrated Circuits2nd Combinational Circ
Multistage NetworksMultistage Networks
Stage effort: hi = gifi
Path electrical effort: F= Cout/Cin
Path logical effort: G = g1g2gN
Branching effort: B = b1b2bN
Path effort: H= GFB
Path delay D = di = pi + hi
( )=
+=N
i
iii fgpDelay1
p mum or perp mum or per
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EE141
53
Digital Integrated Circuits2nd Combinational Circ
p mum or per p mum or per StageStage
HhN =
When each stage bears the same effort:
N
Hh =
( ) PNHpfgD Niii +=+= /1Minimum path delay
Effective fanout of each stage:ii ghf =
Stage efforts: g1f1 = g2f2 = = gNfN
p ma um er op ma um er o
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EE141
54
Digital Integrated Circuits2nd Combinational Circ
p ma um er o p ma um er oStagesStages
For a given load,and given input capacitance of the first gate
Find optimal number of stages and optimal sizing
invN NpNHD += /1
( ) 0ln /1/1/1 =++=
inv
NNN pHHHN
D
NHh/1=Substitute best stage effort
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EE141
55
Digital Integrated Circuits2nd Combinational Circ
Logical EffortLogical Effort
From Sutherland, Sproull
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EE141
56
Digital Integrated Circuits2nd Combinational Circ
Example: Optimize PathExample: Optimize Path
Effective fanout, F=
G =
H=h =
a =
b =
1a
b c
5
g = 1
f= a
g = 5/3
f= b/a
g = 5/3
f= c/b
g = 1
f= 5/c
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EE141
57
Digital Integrated Circuits2nd Combinational Circ
Example: Optimize PathExample: Optimize Path
1a
b c
5
g = 1
f= a
g = 5/3
f= b/a
g = 5/3
f= c/b
g = 1
f= 5/c
Effective fanout, F= 5
G = 25/9
H= 125/9 = 13.9
h = 1.93a = 1.93
b = ha/g2 = 2.23
c= hb/g3 = 5g4/f= 2.59
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EE141
58
Digital Integrated Circuits2nd Combinational Circ
Example: Optimize PathExample: Optimize Path
1
ab c
5
Effective fanout, H= 5
G = 25/9
F= 125/9 = 13.9
f= 1.93a = 1.93
b = fa/g2 = 2.23
c= fb/g3 = 5g4/f= 2.59
g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1
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EE141
59
Digital Integrated Circuits2nd Combinational Circ
Example 8-input ANDExample 8-input AND
e o o og cae o o og ca
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EE141
60
Digital Integrated Circuits2nd Combinational Circ
e o o og cae o o og caEffortEffort
Compute the path effort: F= GBH
Find the best number of stages N~ log4F
Compute the stage effort f= F1/N
Sketch the path with this number of stages
Work either from either end, find sizes:
Cin= C
out*g/f
Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann 1999.
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EE141
61
Digital Integrated Circuits2nd Combinational Circ
SummarySummary
Sutherland,
Sproull
Harris
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62
Digital Integrated Circuits2nd Combinational Circ
RatioedRatioed
LogicLogic
i d iR ti d L i
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63
Digital Integrated Circuits2nd Combinational Circ
Ratioed LogicRatioed Logic
VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT< 0
Goal: to reduce the number of devices over complementary CMOS
R i d L iR ti d L i
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EE141
64
Digital Integrated Circuits2nd Combinational Circ
Ratioed LogicRatioed LogicVDD
VSS
PDN
In1
In2
In3
F
RLLoad
ResistiveN transistors + Load
VOH = VDD
VOL
= RPN
RPN + RL
Assymetrical response
Static power consumption
tpL= 0.69 RLCL
A i L dA ti L d
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65
Digital Integrated Circuits2nd Combinational Circ
Active LoadsActive LoadsVDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
DepletionLoad
PMOSLoad
depletion load NMOS pseudo-NMOS
VT< 0
d OS
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Digital Integrated Circuits2nd Combinational Circ
Pseudo-NMOSPseudo-NMOS
VDD
A B C D
F
CL
VOH= VDD (similar to complementary CMOS)
kn
VDD
VTn
( )VOLV
OL2
2-------------
kp
2------ V
DDV
Tp( )
2=
VOL
VDD
VT
( ) 1 1k
p
kn
------ (assuming that VT
VTn
VTp
)= = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
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Digital Integrated Circuits2nd Combinational Circ
Pseudo-NMOS VTCPseudo-NMOS VTC
0.0 0.5 1.0 1.5 2.0 2.50.0
0.5
1.0
1.5
2.0
2.5
3.0
Vin [V]
Vout
[V]
W/Lp = 4
W/Lp = 2
W/Lp = 1
W/Lp = 0.25
W/Lp = 0.5
I d L dI d L d
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Digital Integrated Circuits2nd Combinational Circ
Improved LoadsImproved Loads
A B C D
F
CL
M1M2 M1 >> M2Enable
VDD
Adaptive Load
d d (2)I d L d (2)
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Digital Integrated Circuits2nd Combinational Circ
Improved Loads (2)Improved Loads (2)
VDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
AABB
M1 M2
Differential Cascode Voltage Switch Logic (DCVSL)
DCVSL E lDCVSL E l
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Digital Integrated Circuits2nd Combinational Circ
DCVSL ExampleDCVSL Example
B
A A
B B B
Out
Out
XOR-NXOR gate
rans enrans en
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Digital Integrated Circuits2nd Combinational Circ
ResponseResponse
0 0.2 0.4 0.6 0.8 1.0-0.5
0.5
1.5
2.5
Time [ns]
Voltage
[V] A B
A B
A,BA,B
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Digital Integrated Circuits2nd Combinational Circ
Pass-Pass-
TransistorTransistorLogicLogic
P T i t L iPass Transistor Logic
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Digital Integrated Circuits2nd Combinational Circ
Pass-Transistor LogicPass-Transistor Logic
Inputs
Switch
Network
OutOut
A
B
B
B
N transistors No static consumption
l GE l AND G t
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Digital Integrated Circuits2nd Combinational Circ
Example: AND GateExample: AND Gate
B
B
A
F= AB
0
NMOS O l L iNMOS O l L i
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Digital Integrated Circuits2nd Combinational Circ
NMOS-Only LogicNMOS-Only Logic
VDD
In
Outx
0.5m/0.25m0.5m/0.25m
1.5m/0.25m
0 0.5 1 1.5 20.0
1.0
2.0
3.0
Time [ns]
Voltage
[V]
x
Out
In
NMOS only SwitchNMOS only Switch
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Digital Integrated Circuits2nd Combinational Circ
NMOS-only SwitchNMOS-only Switch
A = 2.5 V
B
C = 2.5V
CL
A = 2.5 V
C = 2.5 V
B
M2
M1
Mn
Threshold voltage loss causes
static power consumption
VB
does not pull up to 2.5V, but 2.5V -VTN
NMOS has higher threshold than PMOS (body effect)
NMOS Only Logic:NMOS Only Logic:
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Digital Integrated Circuits2nd Combinational Circ
y gLevel Restoring TransistorLevel Restoring Transistor
M2
M1
Mn
Mr
OutA
B
VDDVDDLevel Restorer
X
Advantage: Full Swing
Restorer adds capacitance, takes away pull down current at X
Ratio problem
R t Si iR t Si i
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Digital Integrated Circuits2nd Combinational Circ
Restorer SizingRestorer Sizing
0 100 200 300 400 5000.0
1.0
2.0
W/Lr=1.0/0.25W/Lr=1.25/0.25
W/Lr=1.50/0.25
W/Lr=1.75/0.25
Voltage[V
]
Time [ps]
3.0Upper limit on restorer sizePass-transistor pull-downcan have several transistors i
stack
Solution 2: Single TransistorSolution 2: Single Transistori h
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Digital Integrated Circuits2nd Combinational Circ
Pass Gate withPass Gate with VVTT=0=0
Out
VDD
VDD
2.5V
VDD
0V 2.5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
Complementary Pass TransistorComplementary Pass TransistorL iL i
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Digital Integrated Circuits2nd Combinational Circ
LogicLogic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=A
F=A
OR/NOR EXOR/NEXORAND/NAND
F
F
Pass-Transistor
Network
Pass-TransistorNetwork
AABB
AAB
B
Inverse
(a)
(b)
o u on : ransm ss ono u on : ransm ss onGateGate
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Digital Integrated Circuits2nd Combinational Circ
GateGate
A B
C
C
A B
C
C
B
CL
C= 0 V
A = 2.5 V
C = 2.5 V
es s ance o ransm ss ones s ance o ransm ss onGateGate
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Digital Integrated Circuits2nd Combinational Circ
GateGate
Vout
0 V
2.5 V
2.5 VRn
Rp
0 . 0 1 . 0 2 . 00
1 0
2 0
3 0
Vout
, V
Resistance,ohm
s
Rn
Rp
Rn
|| Rp
ass- rans s or aseass- rans s or aseMultiplexerMultiplexer
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Digital Integrated Circuits2nd Combinational Circ
MultiplexerMultiplexer
AM
2
M1
B
S
S
S F
VDD
GND
VDD
In
1
In
2
S S
S S
Transmission Gate XORTransmission Gate XOR
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Digital Integrated Circuits2nd Combinational Circ
Transmission Gate XORTransmission Gate XOR
A
B
F
B
A
B
B
M1
M2
M3/M4
Delay in Transmission GateDelay in Transmission GateNetworksNetworks
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Digital Integrated Circuits2nd Combinational Circ
NetworksNetworks
V1 Vi-1
C
2.5 2.5
0 0
Vi Vi+1
CC
2.5
0
Vn-1 Vn
CC
2.5
0
In
V1 Vi Vi+1
C
Vn-1 Vn
CC
In
ReqReq Req Req
CC
(a)
(b)
C
Req Req
C C
Req
C C
Req Req
C C
Req
C
In
m
(c)
Delay OptimizationDelay Optimization
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Digital Integrated Circuits2nd Combinational Circ
Delay OptimizationDelay Optimization
Transmission Gate Full AdderTransmission Gate Full Adder
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Digital Integrated Circuits2nd Combinational Circ
Transmission Gate Full AdderTransmission Gate Full Adder
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
Similar delays for sum and carry
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Digital Integrated Circuits2nd Combinational Circ
DynamicDynamic
LogicLogic
Dynamic CMOSDynamic CMOS
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Digital Integrated Circuits2nd Combinational Circ
Dynamic CMOSDynamic CMOS
In static circuits at every point in time (exceptwhen switching) the output is connected to eitherGND or VDD via a low resistance path.
fan-in ofn requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage ofsignal values on the capacitance of highimpedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors
Dynamic GateDynamic Gate
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Digital Integrated Circuits2nd Combinational Circ
Dynamic GateDynamic Gate
In1
In2 PDN
In3
Me
Mp
Clk
Clk
Out
CL
Out
Clk
Clk
A
B
C
Mp
Me
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)
Dynamic GateDynamic Gate
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Digital Integrated Circuits2nd Combinational Circ
Dynamic GateDynamic Gate
In1
In2 PDN
In3
Me
Mp
Clk
Clk
Out
CL
Out
Clk
Clk
A
B
C
Mp
Me
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
on
off
1
off
on
((AB)+C)
Conditions on OutputConditions on Output
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Digital Integrated Circuits2nd Combinational Circ
Conditions on OutputConditions on Output
Once the output of a dynamic gate isdischarged, it cannot be charged again untilthe next precharge operation.
Inputs to the gate can make at most onetransition during evaluation.
Output can be in the high impedance state
during and after evaluation (PDN off), state isstored on C
L
roper es o ynam croper es o ynam cGatesGates
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Digital Integrated Circuits2nd Combinational Circ
GatesGates
Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (VOL
= GND and VOH
= VDD)
Non-ratioed - sizing of the devices does not affect
the logic levels
Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging C
L
roper es o ynam cGatesGates
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Digital Integrated Circuits2nd Combinational Circ
GatesGates
Overall power dissipation usually higherthan staticCMOS no static current path ever exists between V
DDand GND
(including Psc)
no glitching higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn low noise margin (NM
L)
Needs a precharge/evaluate clock
Design 1: ChargeDesign 1: ChargeL k
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Digital Integrated Circuits2nd Combinational Circ
LeakageLeakage
CL
Clk
Clk
Out
A
Mp
Me
Leakage sources
CLK
VOut
Precharge
Evaluate
Dominant component is subthreshold current
o u on o argeo u on o argeLeakageLeakage
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Digital Integrated Circuits2nd Combinational Circ
LeakageLeakage
CL
Clk
Clk
Me
Mp
A
B
Out
Mkp
Same approach as level restorer for pass-transistor logic
Keeper
Design 2: ChargeDesign 2: ChargeSh iSh i
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Digital Integrated Circuits2nd Combinational Circ
SharingSharing
CL
Clk
Clk
CA
CB
B=0
A
OutMp
Me
Charge stored originally on
CL is redistributed (shared)
over CL and CA leading to
reduced robustness
arge ar ngarge ar ngExampleExample
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Digital Integrated Circuits2nd Combinational Circ
ExampleExample
CL=50fF
Clk
Clk
A A
B B B !B
CC
Out
Ca=15fF
Cc=15fF
Cb=15fF
Cd=10fF
Charge SharingCharge Sharing
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Digital Integrated Circuits2nd Combinational Circ
Charge SharingCharge Sharing
CL
VDD
CL
Vout
t( ) Ca VDD VTn VX( )( )+=
or
Vout Vout t( ) VDD CaCL
-------- VDD VTn VX( )( )= =
Vout VDDCa
Ca CL+----------------------
=
case 1) ifVout< VTn
case 2) ifVout> VTnB = 0
Clk
X
CL
Ca
Cb
A
Out
Mp
Ma
VDD
Mb
Clk Me
o u on o argeo u on o argeRedistributionRedistribution
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Digital Integrated Circuits2nd Combinational Circ
RedistributionRedistribution
Clk
Clk
Me
Mp
A
B
Out
MkpClk
Precharge internal nodes using a clock-driven transistor
(at the cost of increased area and power)
Design 3: BackgateDesign 3: Backgate
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Digital Integrated Circuits2nd Combinational Circ
CouplingCoupling
CL1
Clk
Clk
B=0
A=0
Out1Mp
Me
Out2
CL2 In
Dynamic NAND Static NAND
=1=0
ac ga e oup ngac ga e oup ngEffectEffect
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Digital Integrated Circuits2nd Combinational Circ
EffectEffect
-1
0
1
2
3
0 2 4 6
Voltag
e
Time, ns
Clk
In
Out1
Out2
Design 4: ClockDesign 4: ClockF d h hF dth h
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Digital Integrated Circuits2nd Combinational Circ
FeedthroughFeedthrough
CL
Clk
Clk
B
A
OutMp
Me
Coupling between Out and
Clk input of the precharge
device due to the gate to
drain capacitance. Sovoltage of Out can rise
above VDD . The fast rising
(and falling edges) of the
clock couple to Out.
Cl k d h h
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Digital Integrated Circuits2nd Combinational Circ
Clock FeedthroughClock Feedthrough
-0.5
0.5
1.5
2.5
0 0.5 1
Clk
Clk
In1
In2
In3
In4
Out
In &
Clk
Out
Time, ns
Voltage
Clock feedthrough
Clock feedthrough
Other EffectsOther Effects
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Digital Integrated Circuits2nd Combinational Circ
Other EffectsOther Effects
Capacitive coupling
Substrate coupling
Minority charge injectionSupply noise (ground bounce)
asca ng ynam casca ng ynam cGatesGates
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Digital Integrated Circuits2nd Combinational Circ
GatesGates
Clk
Clk
Out1
In
Mp
Me
Mp
Me
Clk
Clk
Out2
V
t
Clk
In
Out1
Out2 V
VTn
Only 0 1 transitions allowed at inputs!
Domino LogicDomino Logic
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Digital Integrated Circuits2nd Combinational Circ
Domino LogicDomino Logic
In1
In2 PDN
In3
Me
Mp
Clk
ClkOut1
In4 PDN
In5
Me
Mp
Clk
ClkOut2
Mkp
1 11 0
0 00 1
Why Domino?Why Domino?
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Digital Integrated Circuits2nd Combinational Circ
Why Domino?Why Domino?
Clk
Clk
Ini PDN
Inj
IniInj
PDN Ini PDN
Inj
Ini PDN
Inj
Like falling dominos!
roper es o om noroper es o om noLogicLogic
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Digital Integrated Circuits2nd Combinational Circ
LogicLogic
Only non-inverting logic can be implemented
Very high speed
static inverter can be skewed, only L-H transition Input capacitance reduced smaller logical effort
es gn ng w om noes gn ng w om noLogicLogic
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Digital Integrated Circuits2nd Combinational Circ
LogicLogic
Mp
Me
VDD
PDN
Clk
In1
In2
In3
Out1
Clk
Mp
Me
VDD
PDN
Clk
In4
Clk
Out2
Mr
VDD
Inputs = 0
during precharge
Can be eliminated!
Footless DominoFootless Domino
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Digital Integrated Circuits2nd Combinational Circ
Footless DominoFootless Domino
The first gate in the chain needs a foot switch
Precharge is rippling short-circuit current
A solution is to delay the clock for each stage
VDD
Clk M p
Out1
In1
1 0
VDD
Clk M p
Out2
In2
VDD
Clk M p
Outn
InnIn3
1 0
0 1 0 1 0 1
eren a ua aeren a ua aDominoDomino
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Digital Integrated Circuits2nd
Combinational Circ
DominoDomino
A
B
Me
Mp
Clk
Clk
Out = AB
!A !B
MkpClk
Out = ABMkp Mp
Solves the problem of non-inverting logic
1 0 1 0
onoff
np-CMOSnp-CMOS
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Digital Integrated Circuits2nd
Combinational Circ
np CMOSnp CMOS
In1
In2 PDN
In3
Me
Mp
Clk
ClkOut1
In4 PUN
In5
Me
MpClk
Clk
Out2
(to PDN)
1 11 0
0 00 1
Only 0 1 transitions allowed at inputs of PDNOnly 1 0 transitions allowed at inputs of PUN
NORA LogicNORA Logic
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NORA LogicNORA Logic
In1
In2 PDN
In3
Me
Mp
Clk
ClkOut1
In4 PUN
In5
Me
MpClk
Clk
Out2
(to PDN)
1 11 0
0 00 1
to otherPDNs
to otherPUNs