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David J. Allstot, Cameron Charles, Dicle Öziş, Sudip Shekhar and Jeffrey S. Walling

University of Washington

CMOS RF Design Techniques to Mitigate Substrate Parasitic Effects

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Case Studies

• Compensated Quadrature Coupler

• Reflective-Type Phase Shifter Layout

• Stagger-Compensated Wideband Amplifier

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Motivation for Couplers

• Negative Resistance Amplifier

• Image Reject Mixer

• Balanced Amplifiers

• Reflective-type phase shifter (RTPS)

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Hybrid Couplers

• 0°, 180° or 90° phase shifts

• Mutually isolated ports: 1 & 4 and 2 & 3

10 1120 logReturn Loss S= − 10 2120 logInsertion Loss S= −

10 3120Coupling log S= − 10 4120Isolation log S= −

4110

31

20 SDirectivity logS

= −

1 2

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Input port

Isolated port

Direct port

Coupled port

( ) ( )( ) ( )

21 3110

21 31

20S jS

IR .logS jS

ω ωω ω

− = +

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90° Branch-Line Coupler

[ ]

0 00 010 02

0

1

1 0

11

jj

jS

j

− =

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90° Coupled-Line Hybrid

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0 011e

CZ ZC

+ = −

12

0 011o

CZ ZC

− = +

0 0 0e oZ Z Z=0 707C .=

[ ]

0 00 010 02

0

1

1 0

11

jj

jS

j

− =

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90° Lange Coupler

• Mutual capacitance and coupling increased by splitting two lines into four

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Lumped Branch-line Coupler

10 0

1CZω

= 01

0 2ZL

ω=

2 120 1

1C CLω

= −

F. Ellinger, R. Vogt, and W. Bachtold, “Ultracompact reflective-type phase shifter MMIC at C-band with 360° phase-control range for smart antenna combining,” IEEE J. Solid-State Circuits, vol. 37, pp. 481-486, April 2002.

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Lumped Branch-line Coupler Simulation Results

• L=1 nH, C2 = 253 fF and C1 = 612.13 fF

• Narrow bandwidth

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Lumped Lange Coupler

• Both electrical and magnetic coupling

0

0 0 0

and normnorm

Z CL L CZω ω

= =

12

M

G M

C kC C

= =+

R.C. Frye, S. Kapur, and R.C. Melville, “A 2GHz quadrature hybrid implemented in CMOS technology,” IEEE Custom Integrated Circuits Conference, May 2002, pp. 287-290.

• Normalized to unity characteristic impedance and angular frequency

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Lange vs. Branch-Line Coupler

Loss Characteristics Matching & Phase

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Spiral Transformer

• 6M process, top metal is 2 µm thick, min. spacing 3 µm

• Thick metal approximation in MOMENTUM for better edge coupling estimation

• Metal widths 5µm: 5µm :25 µm

• Outer dimensions 100µm:10µm:400µm

V1

V2 V3

V4

L1 L2

R1 R2

i1

i2

i3

i41

3111

14 14

YYk Re ReY Y

− = ×

1 2

3 4

21LLk=M

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Cascading

• Transformers with lower k factors

• Higher bandwidth

• Higher loss

( ) ( )lower path upper path

2 221 1 1CS a a jb jb a b= ⋅ ⋅ + − ⋅ ⋅ − = −

( ) ( )lower path upper path

31 1 1 2CS a jb jb a j ab= ⋅ ⋅ − + − ⋅ ⋅ = −

2 221 1 2CS a b= − =

31 2 2CS j ab j= − = −

21S a=

31S jb= −

a4b4 a3

b3 a4'b4'

b3'a3'

a1b1 a2

b2 a1'b1'

b2'a2'

1

1

-jb

a-jb-jb

a

a

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Phase Response with k Variations

• 15 % reduction in k value • 15 % increase in k value

• Single-stage Lange coupler nominal k= 0.707

• Two-stage Lange coupler nominal k=0.38

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Phase compensation

• Simulated phase responses for different couplers with inductor/transformer Q=10: (a) Ideal, (b) branch-line, and (c) Lange.

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Cascaded Coupler Layout

530 µm

740 µm

• 0.18µ CMOS process – 2 µm top metal

(Branch-line)(Lange)

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Measured Results-I

• Max. Phase error = 0.7°

• Bandwidth = 220 MHz

• 220 MHz / 5.4 GHz → 4 %

• (a) Measurement (b) Simulation

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Measured Results-II

• (S21,S31) = -5 ± 0.2 dB

• Isolation = 21dB

• Return Loss = 18dB

• Directivity = 16 dB

• Bandwidth = 220 MHz

• 220 MHz / 5.4 GHz → 4 %

Measured S-parameters of the phase-compensated two-stage hybrid coupler: (a) Loss: S21 and S31; (b) matching: S11, S22, S33 and S44, and (c) isolation: S41.

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Image Rejection (IR)

( ) ( )( ) ( )

21 3110

21 31

20S jS

IR FOM .logS jS

ω ωω ω

− = = +

• IRmax= 45 dB

• IR > 34.5 dB

• Bandwidth = 220 MHz

• 220 MHz / 5.4 GHz → 4 %

• (a) Measurement (b) Simulation

IR = Figure of Merit (FOM)

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Comparisons with Previous Results

Lumped-Element Quad.Hybrid

Freq. (GHz)

BW (MHz)% f0

Quad.Phase Diff.

Loss (NF)(dB)

IRFOM(dB)

Process

Branch-line

Coupler [1]

5.2 100% 1.9

-90°±3° 3.5 ± 0.3 NAGaAs

6µm each of top

two metalsLange

Coupler[2]

2.0 100% 5

NA 4.7 (ave) 30CMOS

3µm top metal

This work 5.4 220% 4

-90°±0.7° 5 ± 0.2 34.5CMOS

2µm topmetal

[1] F. Ellinger, R. Vogt, and W. Bachtold, “Ultracompact reflective-type phase shifter MMIC at C-band with 360° phase-control range for smart antenna combining,” IEEE J. Solid-State Circuits, vol. 37, pp. 481-486, April 2002.

[2] R.C. Frye, S. Kapur, and R.C. Melville, “A 2-GHz quadrature hybrid implemented in CMOS technology,” IEEE J.

Solid-State Circuits, vol. 38, pp. 550-555, March 2003.

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Reflective Load for RTPS

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Blocking Capacitors

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Reflective Load with Parasitics• Re-examine the reflective load with the

blocking cap parasitics:

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Impact on RTPS Performance (1)

• Parasitic impedance to ground appears in parallel with the inductor

• Reduces the effective Q• Increases phase shifter

losses

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Impact on RTPS Performance (2)• Also affects the phase characteristics• As CP increases, RP decreases, performance

is degraded

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Design Strategies• Minimize CP: Reduce the size of CB2 (7 pF) as

compared to CB1, CB3 (40 pF) Tradeoff: smaller than optimal blocking capacitor

vs. negative effects of parasitics

• Maximize RP: In layout, avoid placing substrate contacts in the proximity of CB2

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Effect of Cgd-Cpar in CS-cascode LNA

Additional noise from the cascode transistor

• Cpar increases, deteriorates Bandwidth

Remedy

• Keep W/L of M1, M2 small

Non-optimal gain, NF

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A typical UWB CSLNA

• Large W/L => Large Cgs, Cpar

• # Inductors = 5

Large Area, Power

A. Bevilacqua, et al., “An Ultrawideband CMOS low-noise amplifier for 3.1-10.6GHz wireless receivers,” JSSC, Dec. 2004, pp. 2259-2268.

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A CG-LNA

• No feedforward path from Cgd

• Rs = 1/gm keeps W/L small

• Simple broadband input match

• Poor noise performance

αγ

+≈ 1F

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Gm-boosted CG-cascode LNA

For Cc>>Cgs

Gm = 2gm

αγ

21 +≈F

• Lower Noise Figure, Power

• Small W/L keeps Cgs, Cpar small

W. Zhuo, et al., “A capacitor cross-coupled common-gate CMOS low noise amplifier,” TCAS-II, Dec. 2005, pp. 875-879.

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Modified-Series Peaking

•Absorb parasitic capacitance to extend bandwidth!•C1 ≡ Cpar

( )( )212 11

1)(RCjLC

ZN ωωω

+−≈Assuming C1<<C1+C2

,

Compensate for Large peakingS. Shekhar, et al., “A CMOS 3.1-10.6GHz UWB LNA employing stagger-compensated series peaking,” RFIC, 2006 (in press).

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Stagger-compensated Series Peaking

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Stagger-compensated Series Peaking

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Stagger-compensated Series Peaking

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Effect of Cgd in CS-LNA

• Feed-through path

• Decreases reverse isolation

• Complicates input matching

Remedy

• Add a cascode transistor?

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A UWB CGLNA

ω1s21

ωs

s11

HN(ω)

Series-Peaked Response

Staggered Response

Overall Compensated

Response

Test Buffer Test Buffer

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Chip Microphotographs

Differential

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Measurement Results & Comparison

[1] A. Bevilacqua, et al., “An ultra-wideband CMOS LNA for 3.1 to 10.6GHz wireless receivers,” ISSCC, 2004, pp. 382, 383, 533.[2] R-C. Liu, et al., “Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode distributed amplifiers,” JSSC, vol. 39, pp. 1370-1374, Aug. 2004.[3] P. Heydari, et al., “Design of CMOS distributed for multiband UWB wireless receivers,” RFIC, 2005, pp. 695-698.[4] A. Yazdi, et al., “A 1.8V three-stage 25GHz 3dB-BW differential non-uniform downsized distributed amplifier,” ISSCC, 2005, pp. 156, 157, 590.