coen 311 computer organization software
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COEN 311Computer Organization & Software
Chapter 3Principle Components of a Computer
(Prof. Sofiène Tahar)
Concordia University Electrical & Computer Engineering
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CPU (Central Processing Unit)• Components of a Computer
– CPU– Memory– I/O devices
• Architectures– Accumulator– General Purpose Register (GPR)
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CPU (Central Processing Unit)• Instruction Execution Steps
– Fetch (read instruction from memory)– Decode (interpret instruction)– Execute (fetch operands and execute operation)– Increment PC (prepare to fetch next instruction)
• Instruction Execution Flow – Microsteps– Time analysis
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CPU (Central Processing Unit)• CPU‐Memory Interface
– Data Bus– Address Bus– Control Bus (memory and I/O control)
• Internal Architecture– Data buses (width of data/registers/buffers)– Address buses (width of address/registers/buffers)– Control signals (select/enable/read/write/op.)
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CPU (Central Processing Unit)• Internal Organization
– Registers (RF/Accu, PC, IR)– Internal busses (address and data)– Buffers (MBR, MAR, Temp)– Units (ALU, decoder, etc.)– Control (muxes, enable, read/write, ALU ops, etc.)
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CPU Internal Organization
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General Purpose Register (GPR) Machine
MBR
MARIR
Interpreter
PC
INC
RF
CPU I/O Control
control bus
data bus
address bus
0
1
63 = 26‐1
Memory(Byte organized)
R0
R1
R2
R3
00
01
10
11
ALU
10
10
6
6
6
10
66
6
6
10
10
10
10
1010
2
2
op
a
b
b
RF: Register FileMBR: Memory Buffer RegisterMAR: Memory Address RegisterIR: Instruction RegisterInterpreter: Control UnitPC: Program CounterINC: Incrementer
10
6
a
10
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GPR (General Purpose Register) CPU
MBR
MARIR
Interpreter
PC
INC
RF
CPU I/O Control
Mem. Control
data bus
address bus
0
1
28‐1 = 255
Memory(Byte organized)
R0
R1
R2
R3
00
01
10
11
ALU
16
16
16
8
8
16
16
88
8
8
16
16
16
16
1616
2
2 a
a
b
b
RF: Register FileMBR: Memory Buffer RegisterMAR: Memory Address RegisterIR: Instruction RegisterInterpreter: Control UnitPC: Program CounterINC: Incrementer
8
16
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MAR PC
MBR M[MAR]
IR MBR
R3 R1 + R2
PC PC + 1
Interpret
Execution steps for “Add” InstructionADD R1, R2,R3
R3 R1 + R2
else
add
Increment PC
addition
decode
fetch
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MBR
MARIR
Interpreter
PC
INC
ACC
Accumulator Machine
0
1
214‐1
16
1616
16
16
14
14
1414
14
161616
16
14
16Data bus
Address bus
R/W
E
ALU
CPU Memory C = 214 Bytes= 16 KB
16
8‐bit
ACC: AccumulatorALU: Arithmetic & Logic UnitMBR: Memory Buffer RegisterMAR: Memory Address Register
IR: Instruction RegisterInterpreter: Control UnitPC: Program CounterINC: Incrementer
14
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MAR PC
MBR M[MAR]
IR MBR
MAR IR[Y]
MBR M[MAR]
ACC ACC + MBR
PC PC + 2
Interpret?
Execution steps for “Add” instruction in Accumulator Machine
ADD YACC ACC + M[Y]
add
else
fetch
Decode/ Interpret
Load operand
addition
PC increment
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91039202A123
$1000$1002$1004
1) Fetch2) Decode
1010 0001 0010 0011ADD R1, R2, R3
3) Execute4) Inc PC
PC
IR
MDRControl
ALU
CPU
R15
Memory
MAR
R1R0
Instruction Execution in GPR Machine ADD R1, R2, R3R3 <‐ R1 + R2
...
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MARPC
MBRM[MAR]
IRMBR
R3R1+R2
PCPC+2
decode decode
execute
Inc PC
0.3ns 1
3+0.3ns 11
0.3ns 1
0.3ns 1
3x0.3ns 3
2x0.3ns 2
5.7 ns 19 clock cycles
Timing Analysis of Instruction Execution
fetch
ADD R1, R2, R3
Processor: 3.3GHzMemory: 333MHz
1/(3.3 x 109) = 0.3 ns1/(333 x 106) = 3 ns
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1010 0100 $2000 $2002
ADD R4 M[$2000] M[$2002]
4 bits 4 bits 16 bits 16 bits
40 bits = 5 Bytes!!
Complex (multiple words) instruction
ADD ($2000), ($2002), R4
R4 <‐M[$2000] + M[$2000]Operation
Assembly
Encodings
1010 XXXX 0100 XXXX $2000 $2002
16 bits16 bits 16 bits
48 bits = 6 Bytes
16‐bit data:
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1010 0000 0100 0000 $2000 $2002
A040
2000
2002
07100311
+
ADD ($2000), ($2002), R4
16 bit data, 16 bit address architecture
16 bits 16 bits 16 bits
48 bits = 3 Words
MAR
MBR
$0311$0710
R4
IR
16 bits
$1000
$1002
$1004
$2000
$2002
16
48PC
Temp 2
Temp 1
Instruction
Data
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MARPC
MBRM[MAR]
IRMBR
interpret
$1000
$A040
$A040
other opcode
add mem1, mem2, reg
Fetch
decode
ADD ($2000), ($2002), R4
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Fetch address of memory operand 1
$1002
$1002
$2000
$2000
$1004
$2002
$2002
PCPC+2
MAR PC
MBRM[MAR]
Temp1 MBR
MAR PC
MBRM[MAR]
Temp2MBR
PCPC+2
$1004
Fetch address of memory operand 2
ADD ($2000), ($2002), R4
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Fetch memory operand 1
$2000
$0710
$0710
$2002
$0311
ADD ($2000), ($2002), R4
Execution
Increment PC
MBR M[MAR]
MBR M[MAR]
Temp 1 MBR
MAR Temp2
MAR Temp 1
R4MBR + Temp1
PCPC+2
($0311+$0710)
$1006
Fetch memory operand 2
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PCPC+2
MAR PC
MBRM[MAR]
Temp1 MBR
MAR PC
MBRM[MAR]
Temp2MBR
PCPC+2
MBR M[MAR]
MBR M[MAR]Temp 1 MBRMAR Temp2
MAR Temp 1
R4MBR + Temp1
PCPC+2
MARPC
MDRM[MAR]
IRMDR
decode
ADD ($2000), ($2002), R4 0.3ns 1
3.3ns 110.3ns 1
0.9ns 3
3.3ns 11
0.9ns 3
3.3ns 1
0.3ns 1
0.3ns 10.3ns 1
0.9ns 3
Processor: 3.3GHzMemory: 333MHz
Memory access: 10ccRegister transfer: 1ccLogical operation: 1ccArithmetic operation: 2cc
71% memory traffic!!
0.3ns 1
3.3ns 110.3ns 1
0.3ns 1
0.3ns 13.3ns 11
0.9ns 11
0.9ns 3Total: 77 cc = 23.1 ns
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MC68000 Computer
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Steps required for execution of add instruction
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We want to compute a (x+y) * (x‐y)
where x, y, a are memory data
1) Write an assembly program for the above task using:a) Accumulator machineb) GPR machine ( 4 registers)
2) Assuming all accumulator instructions take 50 ns; and allGPR instructions take 30ns, except move M‐R/R‐M that take 50nsCompute the total execution of the programs in 1a) and 1b)
Your First Assembly Program
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1) Accumulator MachineADD X ; ACC ACC + M[X]SUB X ; ACC ACC – M[X]MUL X ; ACC ACC * M[X]LD X ; ACC M[X]ST X ; M[X] ACC
x: data in memory. M[X]=xX: addess for Memory
2) GPR MachineADD Ri, Rj, Rk ; Rk Ri + RjSUB Ri, Rj, Rk ; Rk Ri – RjMUL Ri, Rj, Rk ; Rk Ri * RjMOVE Ri, Rj ; Rj RiMOVE Ri, M[X] ; M[X] RiMOVE M[X], Rj ; RiM[X]
xX
address data
....
Instruction Sets
src src dest
ADD Ri, Rj, Rk
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....y Y
addressdata
1) Accumulator Machine
LD X ; ACC M[X]
ADD Y ; ACC x + y
ST T ; temp x + y
LD X ; ACC x
SUB Y ; ACC x‐y
MUL T ; ACC (x‐y)*temp
ST A ; a (x‐y)*(x+y)
x X
temp Ta A
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2) GPR
MOVE x, R0 ; R0 x (=M[X])MOVE y, R1 ; R1 y (=M[Y])ADD R0, R1,R2 ; R2 R0+R1SUB R1, R0, R3 ; R3 R0‐R1MUL R2, R3, R0 ; R0 R2*R3MOVE R0, a ; a R0
R2*R3 (x+y)*(x‐y)
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....y Y
addressdata
1) Accumulator MachineLD X ; ACC M[X]ADD Y ; ACC x + yST T ; temp x + yLD X ; ACC xSUB Y ; ACC x‐yMUL T ; ACC (x‐y)*tempST A ; a (x‐y)*(x+y)
x X
temp Ta A
The Assembly Programs
2) GPRMOVE x, R0 ; R0 x (=M[X])MOVE y, R1 ; R1 y (=M[Y])ADD R0, R1, R2 ; R2 R0+R1SUB R1, R0, R3 ; R3 R0‐R1MUL R2, R3, R0 ; R0 R2*R3MOVE R0, a ; a R0
R2*R3 (x+y)*(x‐y)
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Main Memory• Technologies, RAM, ROM etc.• Hardware (modules, buses, etc.)• Addresses, Organization and Capacity• Content
– Instructions (machine code)– Data
• Integer• Floating point• Char• ASCII• EBCDIC
Code
Code
Data
Data
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Data and address buses width of 8 bits each
CPU‐Memory Interface
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Memory Hierarchy
Level 1 Cache
Level 2 Cache Main
MemoryHard Disk
01...........2n‐1CPU
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Memory Technologies
• Volatile Memory : RAM (Random Access Memory)
• Non‐Volatile Memory : ROM (Read Only Memory)– PROM : Programmable ROM– EPROM : Erasable PROM– EEPROM : Electrically EPROM– EAPROM : Electrically Alterable PROM Can delete
SELCTED Locations
Deletes ALL LocationsUV
Elec.
(‐‐ Flash Memory)
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SRAM vs. DRAM
• Static RAM (SRAM)– Fast but expensive– 5 transistor flip flops (more chip area)
• Dynamic RAM (DRAM)– Relatively slower but less expensive– 1 transistor + 1 Capacitor (less chip area higher density)
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DRAM Technologies
• SDRAM: Synchronous DRAM
• SDR SDRAM: Single Data Rate SDRAM
• DDR SDRAM: Double Data Rate SDRAM
• DDR2 SDRAM: an evolution over DDR SDRAM
• DDR3 SDRAM: improvement over DDR2
• DDR4 SDRAM: improvement over DDR3
• RLDRAM: Reduced‐latency DRAM
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0
1
2
3
4
5
31
Data bus
Address bus
8
5
8 bits
C = 2m x n
Address lines Data lines
C = 25 x 8=32 x 8bit= 32 Bytes
EXAMPLE:
Memory Capacity
Control bus2
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WORD ORGANIZATION
0
1
2
3
4
5
2m‐1
Data bus
Address bus
n
m
n bits
Control bus2
C = 2m x n
Adress Bus Data Bus
C = 2m x n bit= 2m x n/8 Byte
Example:
Note: 210 = 1 K ; 220 = 1 M ; 230 = 1 G ; 240 = 1 T
m = 32, n = 16C = 232 x 16 bit = 232 x 16/8 Byte = 8 GB
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BYTE ORGANIZATION
0
1
2
3
4
5
2m‐1
Data bus
Address bus
n
m
8 bits
Control bus2
C = 2m x n
Address Bus Data Bus
C = 2m x 8 bit= 2m Byte
Example: m = 32, n = 16C = 232 x 8 bit = 232 Byte = 4 GB
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Example of Byte Organized Memory
(a)
(b)
First 24 bytes (a) and first 12 16‐biit words (b)
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Example of Byte Organized Memory
First 12 16‐bit words (a) and three 32‐bit longwords with addresses 0, 2, and 6 (b).
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CPUAddress bus
16 ─ 11 10 7 ─ 19 8 RD WR Data bus
Decoder3 2 1 0
CS1CS2RD
AD7WR
128 x 8 RAM 1 Data
CS1CS2RD
AD7WR
128 x 8 RAM 2 Data
CS1CS2RD
AD7WR
128 x 8 RAM 3 Data
CS1CS2RD
AD7WR
128 x 8 RAM 4 Data
CS1CS2 128 x 8
ROM DataAD9
1 ─ 789
“Real” Memory – CPU Interface
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256 B
0
255
511
767
00 00..0
00 11..1
0 1 00..0 256
512
0
1
2
3
16bits
10111111 0 1
01
253254255
256 B
256 B
256 B
768
1023
01 11..1
10 00..0
10 11..1
11 00..0
11 11..1
8 bits2 bits
Memory Organization: Logical View
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8 bits8 bits
8 bits
16bits
R/W
CS
Address BusData Bus
256 B
256 B
Capacity (word organized):C =28 x 16 bits = 28 x 2 Bytes = 512 B
Memory Organization (Internal Structure) [Word Organized Memory]
8 bitsR/WCS
8 bits
256 B
8 bits16 bits
R/WCS
?
Memory Module(8 bits address & 8 bits data)
Memory System(8 bits address & 16 bits data)
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R/W
CS
8 bits
16 bits
16 bits
16 bits
16 bits
16 bits
10 bits
2 bits
256 B
256 B
256 B
256 B
Address BusData Bus
Capacity (byte organized):C =210 = 1 KB
Memory Organization (Internal Structure)[Byte Organized Memory]
16 bitsR/WCS
8 bits
256 B
10 bits16 bits
R/WCS
?
Memory Module(8 bits address & 16 bits data)
Memory System(10 bits address & 16 bits data)
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Capacity (byte organized):C =210 = 1 KB
Memory Organization: Another Structure[Byte organized Memory]
16 bitsR/WCS
8 bits
256 B
8 bits16 bits
R/WCS
?
Memory Module(8 bits address & 16 bits data)
Memory System(10 bits address & 16 bits data)R/W
CS
16bits
10bits2bits
16bits
16bits
16bits
16bits
8 bits
R/W
R/W
R/W
R/W
CS
CS
CS
CS
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00
23 bits 8 bits
Module8 MB
……
……
……
……
2bit
23 bits
25bits
64bits
8 8 8
23 23 2300
01
10
11
64
C = 256 MB = 32 x 8 MB
Complex Memory Organization [Word Organized Memory]
01
10
11
0
25 bits
System
64 bits
modules
?
C = 225 x 64/8 = 256 MB
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Memory Content
• Contents : strings of bits (bytes, 16‐bit word, 32‐bit word, ...)
• Interpretation– Instruction (Code with fixed format, e.g. MC68000)– Data
• Signed Integer• Unsigned Integer• Floating Point number• BCD number• Character: ASCII, EBCDIC
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CODE
CODE
DATA
DATA
DataSignedInteger
UnsignedInteger
FloatingPointnumber
BCDnumber
Character‐ASCII‐ EBCDIC
BCD : Binary Coded Decimal
ASCII : American Standard Code for Information Interchange (7 bit Code – max 128 characters)
EDCDIC : Extended Decimal Coded Decimal Interchange Code(8 bit Code – max 256 characters)
Memory Content
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EBCDIC and ASCII codes (in Hex) for selected characters
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Example: Two possible representations of “0018” depending on the interpretation: EBCDIC character code or signed integer
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Example: Instruction Encoding
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Class QuizGive an interpretation to the following string of bits
assuming it is:
• Unsigned Integer• Signed Integer• BCD number• String of ASCII charachters• IEEE 754 Floating Point number• MC68000 Instruction
0011001000001011
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0011001000001011
Unsigned Number
= 12811
$ 3 2 0 B
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0011001000001011
Signed Number
$ 3 2 0 B
= 12811
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0011001000001011
BCD Number
3 2 0 NA
Not a BCD number!
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0011001000001011IEEE Float Number
SIGN EXPONENT SIGNIFICANT
FS E
(‐1)s x 2E‐127 x 1.F
(‐1)0 x 250‐127 x 1.00001011= 2‐77 x 1.00001011 = 2‐77 x (1 +2‐5+2‐7+2‐8) = 6.901 x 10‐24
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0011001000001011
ASCII Character
$ 3 2 0 B
$32 $0B = “2” “VT”VT : Vertical Tab
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MC68000 Instructions Encoding(subset)
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0011001000001011
MC68000 Instruction
MOVE Ai , Dj (Di source, Ai: dest.)
MOVE A3 , D1