COM20020D

COM20020 ULANCRevision D

Universal Local Area Network Controllerwith 2K x 8 On-Board RAM

FEATURES

New Features for Rev. D - Data Rates up to 5 Mbps - Programmable Reconfiguration Times 24 Pin DIP, 28 Pin PLCC Package Ideal for Industrial/Factory/Building

Automation and TransportationApplications

Deterministic, (ANSI 878.1), Token PassingARCNET Protocol

Minimal Microcontroller and MediaInterface Logic Required

Flexible Interface For Use With AllMicrocontrollers or Microprocessors

Automatically Detects Type ofMicrocontroller Interface

2Kx8 On-Chip Dual Port RAM Command Chaining for Packet Queuing Sequential Access to Internal RAM Software Programmable Node ID

Eight, 256 Byte Pages Allow Four Pages TXand RX Plus Scratch-Pad Memory

Next ID Readable Internal Clock Scaler and Clock Multiplier for

Adjusting Network Speed Operating Temperature Range of -40oC to

+85oC Self-Reconfiguration Protocol Supports up to 255 Nodes Supports Various Network Topologies (Star,

Tree, Bus...) CMOS, Single +5V Supply Duplicate Node ID Detection Powerful Diagnostics Receive All Packets Mode Flexible Media Interface:

- Traditional Hybrid Interface For LongDistances up to Four Miles at 2.5Mbps.

- RS485 Differential Driver Interface ForLow Cost, Low Power, High Reliability

GENERAL DESCRIPTION

SMSC's COM20020D is a member of the family ofEmbedded ARCNET Controllers from StandardMicrosystems Corporation. The device is ageneral purpose communications controller fornetworking microcontrollers and intelligentperipherals in industrial, automotive, andembedded control environments using anARCNET protocol engine. The small 24 pin

package, flexible microcontroller and mediainterfaces, eight- page message support, andextended temperature range of the COM20020Dmake it the only true network controller optimizedfor use in industrial, embedded, and automotiveapplications. Using an ARCNET protocol engineis the ideal solution for embedded controlapplications because it provides a deterministic

2token-passing protocol, a highly reliable andproven networking scheme, and a data rate of upto 5 Mbps when using the COM20020D.

A token-passing protocol provides predictableresponse times because each network eventoccurs within a predetermined time interval, basedupon the number of nodes on the network. Thedeterministic nature of ARCNET is essential inreal time applications. The integration of the 2Kx8

RAM buffer on-chip, the Command Chainingfeature, the 5 Mbps maximum data rate, and theinternal diagnostics make the COM20020D thehighest performance embedded communicationsdevice available. With only one COM20020D andone microcontroller, a complete communicationsnode may be implemented.

ARCNET is a registered trademark of Datapoint Corporation

3TABLE OF CONTENTSFEATURES .......................................................................................................................................1GENERAL DESCRIPTION ................................................................................................................1PIN CONFIGURATION......................................................................................................................4DESCRIPTION OF PIN FUNCTIONS................................................................................................. 5PROTOCOL DESCRIPTION ..............................................................................................................8

NETWORK PROTOCOL ...............................................................................................................8DATA RATES ...............................................................................................................................8NETWORK RECONFIGURATION................................................................................................. 9BROADCAST MESSAGES..........................................................................................................10EXTENDED TIMEOUT FUNCTION.............................................................................................10LINE PROTOCOL .......................................................................................................................10

SYSTEM DESCRIPTION .................................................................................................................13MICROCONTROLLER INTERFACE ............................................................................................13TRANSMISSION MEDIA INTERFACE.........................................................................................17

FUNCTIONAL DESCRIPTION .........................................................................................................22MICROSEQUENCER ..................................................................................................................22INTERNAL REGISTERS .............................................................................................................25INTERNAL RAM .........................................................................................................................38COMMAND CHAINING...............................................................................................................43INITIALIZATION SEQUENCE......................................................................................................45IMPROVED DIAGNOSTICS........................................................................................................46

OPERATIONAL DESCRIPTION ......................................................................................................49MAXIMUM GUARANTEED RATINGS*........................................................................................49DC ELECTRICAL CHARACTERISTICS .......................................................................................49

TIMING DIAGRAMS........................................................................................................................52APPENDIX A................................................................................................................................... 67APPENDIX B: EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS ................................71APPENDIX C................................................................................................................................... 72SOFTWARE IDENTIFICATION OF THE COM20020 REV B, REV C AND REV D............................72

For more details on the ARCNET protocol engine and traditional dipulse signaling schemes,please refer to the ARCNET Local Area Network Standard, available from Standard MicrosystemsCorporation or the ARCNET Designer's Handbook, available from Datapoint Corporation.

For more detailed information on cabling options including RS485, transformer-coupled RS-485and Fiber Optic interfaces, please refer to the following technical note which is available fromStandard Microsystems Corporation: Technical Note 7-5 - Cabling Guidelines for the COM20020ULANC.

4PIN CONFIGURATION

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

A0/nMUX

A1

A2/ALE

AD0

AD1

AD2

D3

D4

D5

D6

D7

nRD/nDS

nWR/DIR

nCS

nINTR

nRESET IN

nTXEN

RXIN

nPULSE2

nPULSE1

XTAL2

XTAL1

VDD

26

27

28

1

2

3

4

18

17

16

15

14

13

12

25 24 23 22 21 20 19

5 6 7 8 9 10 11

nCS

nIN

TR

nRE

SE

T IN

VS

S

nTX

EN

RX

IN

nPU

LSE

2

AD

1

VS

S

AD

2

D3

D4

D5

D6

nPULSE 1

XTAL2

XTAL1

VDD

VSS

N/C

D7

nWR/DIR

nRD/nDS

VDD

A2/ALE

AD0

A1

Packages: 24-Pin DIP or 28-Pin PLCC

Ordering Information:

COM20020

VSS

A0/nMUX

PACKAGE TYPE: P = Plastic, LJP = PLCC

TEMP RANGE: (Blank) = Commercial: 0C to +70C I = Industrial: -40C to +85C

DEVICE TYPE: 20020 = Universal Local Area Network Controller (with 2K x 8 RAM)

PI

5DESCRIPTION OF PIN FUNCTIONSDIP PIN

NO.

PLCC PIN

NO. NAME SYMBOL DESCRIPTION

MICROCONTROLLER INTERFACE

1-3 1-3 Address

0-2

A0/nMUX,

A1,A2/ALE

Input. On a non-multiplexed mode, A0-A2are address input bits. (A0 is the LSB) On amultiplexed address/data bus, nMUX tiedLow, A1 is left open, and ALE is tied to theAddress Latch Enable signal. A1 isconnected to an internal pull-up resistor.

4-11 4-6,8-12 Data 0-7 AD0-AD2,D3-D7

Input/Output. On a non-multiplexed bus,these signals are used as the data lines forthe device. On a multiplexed address/databus, AD0-AD2 act as the address lines(latched by ALE) and as the low data lines forthe device. D3-D7 are always used for dataonly. These signals are connected to internalpull-up resistors.

23 27 nRead/nData

Strobe

nRD/nDS Input. On a 68XX-like bus, nDS is an activelow signal issued by the microcontroller as thedata strobe signal to strobe the data onto thebus. On a 80XX-like bus, nRD is an activelow signal issued by the microcontroller toindicate a read operation.

22 26 nWrite/

Direction

nWR/DIR Input. On a 68XX-like bus, DIR is issued bythe microcontroller as the Read/nWrite signalto determine the direction of data transfer. Inthis case, a logic "1" selects a read operation,while a logic "0" selects a write operation. Inthis case, data is actually strobed by the nDSsignal. On an 80XX-like bus, nWR is anactive low signal issued by the microcontrollerto indicate a write operation. In this case, alogic "0" on this pin, when the COM20020D isaccessed, enables data from the data bus tobe written to the device.

19 23 nReset in nRESET Input. This active low signal executes ahardware reset.

20 24 nInterrupt nINTR Output. This active low signal is generated bythe COM20020D when an enabled interruptcondition occurs.

21 25 nChip Select nCS Input. This active low signal selects theCOM20020D for an access.

6DIP PIN

NO.

PLCC PIN

NO. NAME SYMBOL DESCRIPTION

TRANSMISSION MEDIA INTERFACE

16,15 19,18 nPulse 2,nPulse 1

nPULSE2,nPULSE1

Output (nPULSE1), Input/Output (nPULSE2).In Normal Mode, these active low signalscarry the transmit data information, encodedin pulse format, as DIPULSE waveform.When the device is in Backplane Mode, thenPULSE1 signal driver is programmable(push/pull or open-drain), while the nPULSE2signal provides a clock with frequency ofdouble the data rate. nPULSE1 is connectedto a weak internal pull-up resistor on theopen/drain driver in backplane mode.

17 20 Receive In RXIN Input. This signal carries the receive datainformation from the line tranceiver.

18 21 nTransmitnEnable

nTXEN Output. This signal is used prior to the Power-up to enable the line drivers for transmission.The polarity of the signal is programmablethrough the nPULSE2 pin.nPULSE2 floating before Power-up: nTXENactive low (Default option)nPULSE2 grounded before Power-up:nTXEN active high (This option is onlyavailable in Backplane Mode)

13,14 16,17 CrystalOscillator

XTAL1,XTAL2

An external crystal should be connected tothese pins. Oscillation frequency range isfrom 10 to 20 MHz. If an external TTL clock isused instead, it must be connected to XTAL1with a 390W pull-up resistor, and XTAL2should be left floating.

24 15,28 PowerSupply

VDD +5 Volt Power Supply pin.

12 7,14,22 Ground VSS Ground pin.

7FIGURE 1 - COM20020 OPERATION

Invitationto Transmit to

this ID?

Y N

Free BufferEnquiry to

this ID?SOH?

Y N

Y N

RI?

Write SIDto Buffer

DID=0?

DID=ID?

Write Bufferwith Packet

CRCOK?

LENGTHOK?

DID=0?

DID=ID?

SEND ACK

N

Y

N

Y

N

Y N

BroadcastEnabled?

N

Y

N

No Activityfor 41uS?

Y

N

Set NID=ID

Start Timer:T=(255-ID)

ActivityOn Line?

Y

N

T=0?

Set RI

RI?Transmit

NAK

TransmitACK

Set NID=ID

Write ID toRAM Buffer

SendReconfigure

Burst

Power On

ReconfigureTimer hasTimed Out

Start ReconfigurationTimer (420 mS)*

TA?

Broadcast?Transmit

Free BufferEnquiry

No Activity

Pass theToken

Set TA

Y

N

ACK?

NAK?

1

NoActivity NYIncrement

NID

SendPacket

Was PacketBroadcast?

NoActivity

N

ACK? Set TMA

Set TA

x 73 us

for 37.4us?

for 37.4us?

for 37.4us?

YN

NY

Y N

NY

N

N

N

N

1

YY

Y

Y Y

Y

Y

N

Y

Read Node ID

ID refers to the identification number of the ID assigned to this node.

NID refers to the next identification number that receives the token after this ID passes it.

-

-

-

-

SID refers to the source identification.DID refers to the destination identification.

SOH refers to the start of header character; preceeds all data packets.

-

Y N

* Reconfig timer is programmable via setup2 register bits 1, 0.

Note - All time values are valid for 5 Mbps.

8PROTOCOL DESCRIPTION

NETWORK PROTOCOL

Communication on the network is based on atoken passing protocol. Establishment of thenetwork configuration and management of thenetwork protocol are handled entirely by theCOM20020D's internal microcoded sequencer. Aprocessor or intelligent peripheral transmits databy simply loading a data packet and its destinationID into the COM20020D's internal RAM buffer,and issuing a command to enable the transmitter.When the COM20020D next receives the token, itverifies that the receiving node is ready by firsttransmitting a FREE BUFFER ENQUIRYmessage. If the receiving node transmits anACKnowledge message, the data packet istransmitted followed by a 16-bit CRC. If thereceiving node cannot accept the packet (typicallyits receiver is inhibited), it transmits a NegativeAcKnowledge message and the transmitterpasses the token. Once it has been establishedthat the receiving node can accept the packet andtransmission is complete, the receiving nodeverifies the packet. If the packet is receivedsuccessfully, the receiving node transmits an

ACKnowledge message (or nothing if it is notreceived successfully) allowing the transmitter toset the appropriate status bits to indicatesuccessful or unsuccessful delivery of the packet.An interrupt mask permits the COM20020D togenerate an interrupt to the processor whenselected status bits become true. Figure 1 is aflow chart illustrating the internal operation of theCOM20020D connected to a 20 MHz crystaloscillator.

DATA RATES

The COM20020D is capable of supporting datarates from 156.25 Kbps to 5 Mbps. The followingprotocol description assumes a 5 Mbps data rate.To attain the faster data rates, the clock frequencymay be doubled by the internal clock multiplier(see next section). For slower data rates, aninternal clock divider scales down the clockfrequency. Thus all timeout values are scaled asshown in the following table:

Example: IDLE LINE Timeout @ 5 Mbps = 41 ms.IDLE LINE Timeout for 156.2 Kbps is 41 ms * 32 =1.3 ms

INTERNALCLOCK

FREQUENCYCLOCK

PRESCALER DATA RATETIMEOUT SCALING

FACTOR (MULTIPLY BY)40 MHz Div. by 8 5 Mbps 120 MHz Div. by 8

Div. by 16Div. by 32Div. by 64Div. by 128

2.5 Mbps1.25 Mbps625 Kbps

312.5 Kbps156.25 Kbps

2481632

9Selecting Clock Frequencies Above 2.5 Mbps

To realize a 5 Mbps network, an external 40 MHzclock must be input. However, since 40 MHz isnear the frequency of FM radio band, it is notpractical for use for noise emission reasons.

Therefore, higher frequency clocks aregenerated from the 20 MHz crystal as selectedthrough two bits in the Setup2 register,CKUP[1,0] as shown below. The selected clockis supplied to the ARCNET controller.

CKUP1 CKUP0 CLOCK FREQUENCY (DATA RATE)0 0 20 MHz (Up to 2.5Mbps) Default (Bypass)0 1 40 MHz (Up to 5Mbps)1 0 Reserved1 1 Reserved

This clock multiplier is powered-down (bypassed)on default. After changing the CKUP1 andCKUP0 bits, the ARCNET core operation isstopped and the internal PLL in the clockgenerator is awakened and it starts to generatethe 40 MHz. The lock out time of the internal PLLis 8uSec typically. After more than 8 msec (thiswait time is defined as 1 msec in this data sheet),it is necessary to write command data '18H' tothe command register to re-start the ARCNETcore operation. This clock generator is calledclock multiplier.

Changing the CKUP1 and CKUP0 bits must beone time or less after releasing hardware reset.

The EF bit in the SETUP2 register must be setwhen the data rate is over 5 Mbps.

NETWORK RECONFIGURATION

A significant advantage of the COM20020D is itsability to adapt to changes on the network.Whenever a new node is activated or deactivated,a NETWORK RECONFIGURATION is performed.When a new COM20020D is turned on (creatinga new active node on the network), or if theCOM20020D has not received an INVITATIONTO TRANSMIT for 420mS, or if a software resetoccurs, the COM20020D causes a NETWORKRECONFIGURATION by sending aRECONFIGURE BURST consisting of eightmarks and one space repeated 765 times. Thepurpose of this burst is to terminate all activity onthe network. Since this burst is longer than anyother type of transmission, the burst will interferewith the next INVITATION TO TRANSMIT,

destroy the token and keep any other node fromassuming control of the line.

When any COM20020D senses an idle line forgreater than 41mS, which occurs only when thetoken Is lost, each COM20020D starts an internaltimeout equal to 73ms times the quantity 255minus its own ID. The COM20020D starts networkreconfiguration by sending an invitation to transmitfirst to itself and then to all other nodes bydecrementing the destination Node ID. If thetimeout expires with no line activity, theCOM20020D starts sending INVITATION TOTRANSMIT with the Destination ID (DID) equal tothe currently stored NID. Within a given network,only one COM20020D will timeout (the one withthe highest ID number). After sending theINVITATION TO TRANSMIT, the COM20020Dwaits for activity on the line. If there is no activityfor 37.4mS, the COM20020D increments the NIDvalue and transmits another INVITATION TOTRANSMIT using the NID equal to the DID. Ifactivity appears before the 37.4mS timeoutexpires, the COM20020D releases control of theline. During NETWORK RECONFIGURATION,INVITATIONS TO TRANSMIT are sent to all NIDs(1-255).

Each COM20020D on the network will finally havesaved a NID value equal to the ID of theCOM20020D that it released control to. At thispoint, control is passed directly from one node tothe next with no wasted INVITATIONS TOTRANSMIT being sent to ID's not on the network,until the next NETWORK RECONFIGURATIONoccurs. When a node is powered off, the previousnode attempts to pass the token to it by issuing an

10

INVITATION TO TRANSMIT. Since this nodedoes not respond, the previous node times outand transmits another INVITATION TOTRANSMIT to an incremented ID and eventually aresponse will be received.

The NETWORK RECONFIGURATION timedepends on the number of nodes in the network,the propagation delay between nodes, and thehighest ID number on the network, but is typicallywithin the range of 12 to 30.5 mS.

BROADCAST MESSAGES

Broadcasting gives a particular node the ability totransmit a data packet to all nodes on the networksimultaneously. ID zero is reserved for thisfeature and no node on the network can beassigned ID zero. To broadcast a message, thetransmitting node's processor simply loads theRAM buffer with the data packet and sets the DIDequal to zero. Figure 4 illustrates the position ofeach byte in the packet with the DID residing ataddress 0X01 or 1 Hex of the current pageselected in the "Enable Transmit from Page fnn"command. Each individual node has the ability toignore broadcast messages by setting the mostsignificant bit of the "Enable Receive to Page fnn"command to a logic "0".

EXTENDED TIMEOUT FUNCTION

There are three timeouts associated with theCOM20020D operation. The values of thesetimeouts are controlled by bits 3 and 4 of theConfiguration Register and bit 5 of the Setup 1Register.

Response Time

The Response Time determines the maximumpropagation delay allowed between any twonodes, and should be chosen to be larger thanthe round trip propagation delay between the twofurthest nodes on the network plus the maximumturn around time (the time it takes a particularCOM20020D to start sending a message inresponse to a received message) which isapproximately 6.4 mS. The round trip propagationdelay is a function of the transmission media and

network topology. For a typical system usingRG62 coax in a baseband system, a one waycable propagation delay of 15.5 mS translates to adistance of about 2 miles. The flow chart in Figure1 uses a value of 37.4 mS (15.5 + 15.5 + 6.4) todetermine if any node will respond.

Idle Time

The Idle Time is associated with a NETWORKRECONFIGURATION. Figure 1 illustrates thatduring a NETWORK RECONFIGURATION onenode will continually transmit INVITATIONS TOTRANSMIT until it encounters an active node. Allother nodes on the network must distinguishbetween this operation and an entirely idle line.During NETWORK RECONFIGURATION, activitywill appear on the line every 41 mS. This 41 mS isequal to the Response Time of 37.4 mS plus thetime it takes the COM20020D to startretransmitting another message (usually anotherINVITATION TO TRANSMIT).

Reconfiguration Time

If any node does not receive the token within theReconfiguration Time, the node will initiate aNETWORK RECONFIGURATION. The ET2 andET1 bits of the Configuration Register allow thenetwork to operate over longer distances than the2 miles stated earlier. The logic levels on thesebits control the maximum distances over which theCOM20020D can operate by controlling the threetimeout values described above. For propernetwork operation, all COM20020D's connected tothe same network must have the same ResponseTime, Idle Time, and Reconfiguration Time.

LINE PROTOCOL

The ARCNET line protocol is consideredisochronous because each byte is preceded by astart interval and ended with a stop interval. Unlikeasynchronous protocols, there is a constantamount of time separating each data byte. On a 5Mbps network, each byte takes exactly 11 clockintervals of 200ns each. As a result, one byte istransmitted every 2.2 mS and the time to transmita message can be precisely determined. The lineidles in a spacing (logic "0") condition. A logic "0"

11

is defined as no line activity and a logic "1" isdefined as a negative pulse of 100nS duration. Atransmission starts with an ALERT BURSTconsisting of 6 unit intervals of mark (logic "1").Eight bit data characters are then sent, with eachcharacter preceded by 2 unit intervals of mark andone unit interval of space. Five types oftransmission can be performed as describedbelow:

Invitations To Transmit

An Invitation To Transmit is used to pass thetoken from one node to another and is sent by thefollowing sequence: An ALERT BURST An EOT (End Of Transmission: ASCII code

04H) Two (repeated) DID (Destination ID)

characters

ALERTBURST

EOT DID DID

Free Buffer Enquiries

A Free Buffer Enquiry is used to ask another nodeif it is able to accept a packet of data. It is sent bythe following sequence: An ALERT BURST

An ENQ (ENQuiry: ASCII code 85H) Two (repeated) DID (Destination ID)

characters

ALERTBURST

ENQ DID DID

Data Packets

A Data Packet consists of the actual data beingsent to another node. It is sent by the followingsequence:

An ALERT BURST An SOH (Start Of Header--ASCII code 01H) An SID (Source ID) character Two (repeated) DID (Destination ID)

characters A single COUNT character which is the 2's

complement of the number of data bytes tofollow if a short packet is sent, or 00Hfollowed by a COUNT character if a longpacket is sent.

N data bytes where COUNT = 256-N (or 512-N for a long packet)

Two CRC (Cyclic Redundancy Check)characters. The CRC polynomial used is:X16 + X15 + X2 + 1.

ALERT

BURSTSOH SID DID DID COUNT data data CRC CRC

12

Acknowledgements

An Acknowledgement is used to acknowledgereception of a packet or as an affirmativeresponse to FREE BUFFER ENQUIRIES and issent by the following sequence: An ALERT BURST An ACK (ACKnowledgement--ASCII code

86H) character

ALERT BURST ACK

Negative Acknowledgements

A Negative Acknowledgement is used as anegative response to FREE BUFFERENQUIRIES and is sent by the followingsequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII

code 15H) character

ALERT BURST NAK

13

SYSTEM DESCRIPTION

MICROCONTROLLER INTERFACE

The top halves of Figures 2 and 3 illustrate typicalCOM20020D interfaces to the microcontrollers.The interfaces consist of a 8-bit data bus, anaddress bus and a control bus. In order to supporta wide range of microcontrollers without requiringglue logic and without increasing the number ofpins, the COM20020D automatically detects andadapts to the type of microcontroller being used.Upon hardware reset, the COM20020D firstdetermines whether the read and write controlsignals are separate READ and WRITE signals(like the 80XX) or DIRECTION and DATASTROBE (like the 68XX). To determine the type ofcontrol signals, the device requires the software toexecute at least one write access to externalmemory before attempting to access theCOM20020D. The device defaults to 80XX-likesignals. Once the type of control signals aredetermined, the COM20020D remains in thisinterface mode until the next hardware resetoccurs. The second determination theCOM20020D makes is whether the bus ismultiplexed or non-multiplexed. To determine thetype of bus, the device requires the software towrite to an odd memory location followed by aread from an odd location before attempting toaccess the COM20020D. The signal on the A0 pinduring the odd location access tells theCOM20020D the type of bus. Since multiplexedoperation requires A0 to be active low, activity onthe A0 line tells the COM20020D that the bus isnon-multiplexed. The device defaults tomultiplexed operation. Both determinations maybe made simultaneously by performing a WRITEfollowed by a READ operation to an odd locationwithin the COM20020D Address space 20020Dregisters. Once the type of bus is determined, theCOM20020D remains in this interface mode untilhardware reset occurs.

Whenever nCS and nRD are activated, the presetdeterminations are assumed as final and will notbe changed until hardware reset. Refer toDescription of Pin Functions section for details onthe related signals. All accesses to the internalRAM and the internal registers are controlled bythe COM20020D. The internal RAM is accessedvia a pointer-based scheme (refer to theSequential Access Memory section), and theinternal registers are accessed via directaddressing. Many peripherals are not fast enoughto take advantage of high-speed microcontrollers.Since microcontrollers do not typically haveREADY inputs, standard peripherals cannotextend cycles to extend the access time. Theaccess time of the COM20020D, on the otherhand, is so fast that it does not need to limit thespeed of the microcontroller. The COM20020D isdesigned to be flexible so that it is independent ofthe microcontroller speed.

The COM20020D provides for no wait statearbitration via direct addressing to its internalregisters and a pointer based addressing schemeto access its internal RAM. The pointer may beused in auto-increment mode for typicalsequential buffer emptying or loading, or it can betaken out of auto-increment mode to performrandom accesses to the RAM. The data withinthe RAM is accessed through the data register.Data being read is prefetched from memory andplaced into the data register for the microcontrollerto read. It is important to notice that only bywriting a new address pointer (writing to anaddress pointer low), one obtains the contents ofCOM20020D internal RAM. Performing only readfrom the Data Register does not load new datafrom the internal RAM. During a write operation,the data is stored in the data register and thenwritten into memory. Whenever the pointer isloaded for reads with a new value, data isimmediately prefetched to prepare for the firstread operation.

14

FIGURE 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE

RXIN

nPULSE1

nPULSE2

TXEN

GND

+5V

100 Ohm

BACKPLANE CONFIGURATION

FIGURE A

RXIN

nPULSE1

FIGURE B

ReceiverHFD3212-002

2+5V

7

6

TransmitterHFE4211-014

+5V

3

2 Fiber Interface (ST Connectors)

267

NOTE: COM20020 must be in backplane mode

AD0-AD7

nINT1

RESET

nRD

nWR

A15

AD0-AD2, D3-D7

nCS

nRESET

nRD/nDS

nWR/DIRnINTR

A2/BALEALE

XTAL1

XTAL2

GND

RXIN

nPULSE1

nPULSE2

nTXEN

8051

COM20020

Differential DriverConfiguration

Media Interfacemay be replacedwith Figure A, B or C.

*

75176B or Equiv.

A0/nMUX

27 pF 27 pF

XTAL2XTAL1

20 MHz XTAL

15

FIGURE 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE

D0-D7

nIRQ1

nRES

nIOS

R/nW

A7

D0-D7

A0/nMUXA0

XTAL1

XTAL2

A1A1

nCS

nRESET

nRD/nDS

nWR/nDIR

nINTR

A2/BALEA2

RXIN

nPULSE1

nPULSE2

TXEN

GND

Differential DriverConfiguration

6801

COM20020

Media Interfacemay be replacedwith Figure A, B or C.

*

75176B or Equiv.

XTAL1 XTAL2

27 pF 27 pF20MHz XTAL

RXIN

nPULSE1

nPULSE2

nTXEN

GND

Traditional HybridConfiguration

RXIN

nPULSE1

nPULSE2

17, 19,4, 13, 14

5.6K1/2W5.6K1/2W

0.01 uF1KV

12

11

-5V0.47

uF10

uF+

3

0.47uF

+

+5V

uF10

6

FIGURE C

HYC9088HYC9068 or

N/C

*Valid for 2.5 Mbps only.

16

High Speed CPU Bus Timing Support

High speed CPU bus support was added to theCOM20020D. The reasoning behind this is asfollows: With the Host interface in Non-multiplexed Bus mode, I/O address and ChipSelect signals must be stable before the readsignal is active and remain after the read signalis inactive. But the High Speed CPU bus timingdoesn't adhere to these timings. For example, aRISC type single chip microcontroller (like theHITACHI SH-1 series) changes I/O address atthe same time as the read signal. Therefore,several external logic ICs would be required toconnect to this microcontroller.

In addition, the Diagnostic Status (DIAG) registeris cleared automatically by reading itself. Theinternal DIAG register read signal is generatedby decoding the Address (A2-A0), Chip Select(nCS) and Read (nRD) signals. The decoder will

generate a noise spike at the above tight timing.The DIAG register is cleared by the spike signalwithout reading itself. This is unexpectedoperation. Reading the internal RAM and NextId Register have the same mechanism asreading the DIAG register.

Therefore, the address decode and hostinterface mode blocks were modified to fit theabove CPU interface to support high speed CPUbus timing. In Intel CPU mode (nRD, nWRmode), 3 bit I/O address (A2-A0) and Chip Select(nCS) are sampled internally by Flip-Flops on thefalling edge of the internal delayed nRD signal.The internal real read signal is the more delayednRD signal. But the rising edge of nRD doesn'tdelay. By this modification, the internal realaddress and Chip Select are stable while theinternal real read signal is active. Refer to figure4 below.

FIGURE 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE

The I/O address and Chip Select signals, whichare supplied to the data output logic, are notsampled. Also, the nRD signal is not delayed,because the above sampling and delaying pathsdecrease the data access time of the read cycle.

The above sampling and delaying signals aresupplied to the Read Pulse Generation logicwhich generates the clearing pulse for the

Diagnostic register and generates the startingpulse of the RAM Arbitration. Typical delay timebetween nRD and nRD1 is around 15nS andbetween nRD1 and nRD2 is around 10nS.

Longer pulse widths are needed due to thesedelays on nRD signal. However, the CPU caninsert some wait cycles to extend the widthwithout any impact on performance.

A2-A0, nCS

nRD

Delayed nRD(nRD1)

Sampled A2-A0, nCS

More delayed nRD(nRD2)

VALID

VALID

17

The RBUSTMG bit was added to Disable/Enablethe High Speed CPU Read function. It is definedas: RBUSTMG=0, Disabled (Default);

RBUSTMG=1, Enabled.

In the MOTOROLA CPU mode (DIR, nDSmode), the same modifications apply.

RBUSTMG BIT BUS TIMING MODE0 Normal Speed CPU Read and Write1 High Speed CPU Read and Normal Speed CPU Write

TRANSMISSION MEDIA INTERFACE

The bottom halves of Figures 2 and 3 illustrate theCOM20020D interface to the transmission mediaused to connect the node to the network. Table 1lists different types of cable which are suitable forARCNET applications.1 The user may interface tothe cable of choice in one of three ways:

Traditional Hybrid Interface

The Traditional Hybrid Interface is that which isused with previous ARCNET devices. The HybridInterface is recommended if the node is to beplaced in a network with other Hybrid-Interfacednodes. The Traditional Hybrid Interface is for usewith nodes operating at 2.5 Mbps only. Thetransformer coupling of the Hybrid offers isolationfor the safety of the system and offers highCommon Mode Rejection. The Traditional HybridInterface uses circuits like SMSC's HYC9068 orHYC9088 to transfer the pulse-encoded databetween the cable and the COM20020D. TheCOM20020D transmits a logic "1" by generating

two 100nS non-overlapping negative pulses,nPULSE1 and nPULSE2. Lack of pulsesindicates a logic "0". The nPULSE1 and nPULSE2signals are sent to the Hybrid, which creates a200nS dipulse signal on the media. A logic "0" istransmitted by the absence of the dipulse. Duringreception, the 200nS dipulse appearing on themedia is coupled through the RF transformer ofthe LAN Driver, which produces a positive pulse atthe RXIN pin of the COM20020D. The pulse onthe RXIN pin represents a logic "1". Lack of pulserepresents a logic "0". Typically, RXIN pulsesoccur at multiples of 400nS. The COM20020Dcan tolerate distortion of plus or minus 100nS andstill correctly capture and convert the RXIN pulsesto NRZ format. Figure 5 illustrates the eventswhich occur in transmission or reception of dataconsisting of 1, 1, 0.

1 Please refer to TN7-5 Cabling Guidelines forthe COM20020 ULANC, available from SMSC, forrecommended cabling distance, termination, andnode count for ARCNET nodes.

18

Backplane Configuration

The Backplane Open Drain Configuration isrecommended for cost-sensitive, short-distanceapplications like backplanes and instrumentation.This mode is advantageous because it savescomponents, cost, and power.

Since the Backplane Configuration encodes datadifferently than the traditional HybridConfiguration, nodes utilizing the BackplaneConfiguration cannot communicate directly withnodes utilizing the Traditional HybridConfiguration. The Backplane Configuration doesnot isolate the node from the media nor protects itfrom Common Mode noise, but Common ModeNoise is less of a problem in short distances.

The COM20020D supplies a programmableoutput driver for Backplane Mode operation. A

push/pull or open drain driver can be selected byprogramming the P1MODE bit of the Setup 1Register (see register descriptions for details).The COM20020D defaults to an open drainoutput.

The Backplane Configuration provides for directconnection between the COM20020D and themedia. Only one pull-up resistor (in open drainconfiguration of the output driver) is requiredsomewhere on the media (not on each individualnode). The nPULSE1 signal, in this mode, is anopen drain or push/pull driver and is used todirectly drive the media. It issues a 200nSnegative pulse to transmit a logic "1". Note thatwhen used in the open-drain mode, theCOM20020D does not have a fail/safe input onthe RXIN pin. The nPULSE1 signal actuallycontains a weak pull-up resistor. This pull-upshould not take the place of the resistor requiredon the media for open drain mode.

19

FIGURE 5 - COM20020 NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS

FIGURE 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0

COM20020

+VCC

RBIAS

+VCC +VCC

RBIAS RBIAS

RT RT

75176B or Equiv.

COM20020 COM20020

20MHZCLOCK(FOR REF.

ONLY)

nPULSE1

nPULSE2

DIPULSE

RXIN

1 0

100ns

100ns

200ns

400ns

1

20

In typical applications, the serial backplane isterminated at both ends and a bias is provided bythe external pull-up resistor.

The RXIN signal is directly connected to the cablevia an internal Schmitt trigger. A negative pulseon this input indicates a logic "1". Lack of pulseindicates a logic "0". For typical single-endedbackplane applications, RXIN is connected tonPULSE1 to make the serial backplane data line.A ground line (from the coax or twisted pair)should run in parallel with the signal. Forapplications requiring different treatment of thereceive signal (like filtering or squelching),nPULSE1 and RXIN remain as independent pins.External differential drivers/receivers for increasedrange and common mode noise rejection, forexample, would require the signals to beindependent of one another. When the device isin Backplane Mode, the clock provided by thenPULSE2 signal may be used for encoding thedata into a different encoding scheme or othersynchronous operations needed on the serial datastream.

Differential Driver Configuration

The Differential Driver Configuration is a specialcase of the Backplane Mode. It is a dc coupledconfiguration recommended for applications likecar-area networks or other cost-sensitiveapplications which do not require directcompatibility with existing ARCNET nodes and donot require isolation.

The Differential Driver Configuration cannotcommunicate directly with nodes utilizing theTraditional Hybrid Configuration. Like theBackplane Configuration, the Differential DriverConfiguration does not isolate the node from themedia.

The Differential Driver interface includes a RS485Driver/Receiver to transfer the data between thecable and the COM20020D. The nPULSE1 signaltransmits the data, provided the Transmit Enablesignal is active. The nPULSE1 signal issues a200nS (at 2.5Mbps) negative pulse to transmit alogic "1". Lack of pulse indicates a logic "0". TheRXIN signal receives the data, the transmitterportion of the COM20020D is disabled duringreset and the nPULSE1, nPULSE2 and nTXENpins are inactive.

Programmable TXEN Polarity

To accommodate transceivers with active highENABLE pins, the COM20020D contains aprogrammable TXEN output. To program theTXEN pin for an active high pulse, the nPULSE2pin should be connected to ground. To retain thenormal active low polarity, nPULSE2 should beleft open. The polarity determination is made atpower on reset and is valid only for BackplaneMode operation. The nPULSE2 pin shouldremain grounded at all times if an active highpolarity is desired.

21

FIGURE 7 - INTERNAL BLOCK DIAGRAM

MICRO-SEQUENCER

ANDWORKING

REGISTERS

STATUS/COMMANDREGISTER

RESETLOGIC

RECONFIGURATIONTIMER

NODE IDLOGIC

OSCILLATOR

TX/RXLOGIC

ADDITIONAL

REGISTERS

ADDRESSDECODINGCIRCUITRY

2K x 8

AD0-AD2,

BUSARBITRATIONCIRCUITRY

nPULSE1nPULSE2nTXEN

nINTR

nRESET

RAM

A0/nMUXA1

A2/BALE

nRD/nDS

nWR/DIR

nCS

D3-D7

RXIN

XTAL1XTAL2

22

Table 1 - Typical Media

CABLE TYPENOMINAL

IMPEDANCEATTENUATION PER 1000 FT.

AT 5 MHzRG-62 Belden #86262 93W 5.5dB

RG-59/U Belden #89108 75W 7.0dB

RG-11/U Belden #89108 75W 5.5dB

IBM Type 1* Belden #89688 150W 7.0dB

IBM Type 3* Telephone TwistedPair Belden #1155A 100W 17.9dB

COMCODE 26 AWG TwistedPair Part #105-064-703 105W 16.0dB

*Non-plenum-rated cables of this type are also available.

Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-485and Fiber Optic interfaces, please refer to TN7-5 Cabling Guidelines for the COM20020 ULANC,available from Standard Microsystems Corporation.

FUNCTIONAL DESCRIPTIONMICROSEQUENCER

The COM20020D contains an internalmicrosequencer which performs all of the controloperations necessary to carry out the ARCNETprotocol. It consists of a clock generator, a 544 x8 ROM, a program counter, two instructionregisters, an instruction decoder, a no-opgenerator, jump logic, and reconfiguration logic.

The COM20020D derives a 10 MHz and a 5 MHzclock from the output clock of the Clock Multiplier.These clocks provide the rate at which theinstructions are executed within the COM20020D.The 10 MHz clock is the rate at which the programcounter operates, while the 5 MHz clock is the rateat which the instructions are executed. Themicroprogram is stored in the ROM and the

instructions are fetched and then placed into theinstruction registers. One register holds theopcode, while the other holds the immediate data.Once the instruction is fetched, it is decoded bythe internal instruction decoder, at which point theCOM20020D proceeds to execute the instruction.When a no-op instruction is encountered, themicrosequencer enters a timed loop and theprogram counter is temporarily stopped until theloop is complete. When a jump instruction isencountered, the program counter is loaded withthe jump address from the ROM. TheCOM20020D contains an internal reconfigurationtimer which interrupts the microsequencer if it hastimed out. At this point the program counter iscleared and the MYRECON bit of the DiagnosticStatus Register is set.

23

Table 2 - Read Register Summary

REGISTER MSBREAD

LSB ADDRSTATUS RI/TRI X/RI X/TA POR TEST RECON TMA TA/

TTA00

DIAG.STATUS

MY-RECON

DUPID RCV-ACT

TOKEN EXC-NAK

TENTID NEWNEXTID

X 01

ADDRESSPTR HIGH

RD-DATA

AUTO-INC

X X X A10 A9 A8 02

ADDRESSPTR LOW

A7 A6 A5 A4 A3 A2 A1 A0 03

DATA D7 D6 D5 D4 D3 D2 D1 D0 04SUB ADR (R/W)* 0 0 0 (R/W)* SUB-

AD2SUB-AD1

SUB-AD0

05

CONFIG-URATION

RESET CCHEN TXEN ET1 ET2 BACK-PLANE

SUB-AD1

SUB-AD0

06

TENTID TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 07-0NODE ID NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 07-1SETUP1 P1

MODEFOURNAKS

X RCV-ALL

CKP3 CKP2 CKP1 SLOW-ARB

07-2

NEXT ID NXTID7

NXTID6

NXTID5

NXTID4

NXTID3

NXTID2

NXTID1

NXTID0

07-3

SETUP2 RBUS-TMG

X CKUP1 CKUP0 EF NO-SYNC

RCN-TM1

RCM-TM2

07-4

Note*: (R/W) This bit can be Written or Read. For more information see Appendix C.

24

Table 3 - Write Register Summary

ADDR MSBWRITE

LSB REGISTER00 RI/TR1 0 0 0 EXCNAK RECON NEW

NEXTIDTA/TTA

INTERRUPTMASK

01 C7 C6 C5 C4 C3 C2 C1 C0 COMMAND02 RD-

DATAAUTO-

INC0 0 0 A10 A9 A8 ADDRESS

PTR HIGH03 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS

PTR LOW04 D7 D6 D5 D4 D3 D2 D1 D0 DATA05 (R/W)* 0 0 0 (R/W)* SUB-

AD2SUB-AD1

SUB-AD0

SUBADR

06 RESET CCHEN TXEN ET1 ET2 BACK-PLANE

SUB-AD1

SUB-AD0

CONFIG-URATION

07-0 TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 TENTID07-1 NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 NODEID07-2 P1-

MODEFOURNAKS

0 RCV-ALL

CKP3 CKP2 CKP1 SLOW-ARB

SETUP1

07-3 0 0 0 0 0 0 0 0 TEST07-4 RBUS-

TMG0 CKUP

1CKUP

0EF NO-

SYNCRCN-TM1

RCN-TM0

SETUP2

Note*:(R/W) This bit can be Written or Read. For more information see Appendix C.

25

INTERNAL REGISTERS

The COM20020D contains 14 internal registers.Tables 2 and 3 illustrate the COM20020D registermap. All undefined bits are read as undefined andmust be written as logic "0".

Interrupt Mask Register (IMR)

The COM20020D is capable of generating aninterrupt signal when certain status bits becometrue. A write to the IMR specifies which status bitswill be enabled to generate an interrupt. The bitpositions in the IMR are in the same position astheir corresponding status bits in the StatusRegister and Diagnostic Status Register. A logic"1" in a particular position enables thecorresponding interrupt. The Status bits capable ofgenerating an interrupt include the ReceiverInhibited bit, New Next ID bit, Excessive NAK bit,Reconfiguration Timer bit, and TransmitterAvailable bit. No other Status or Diagnostic Statusbits can generate an interrupt.

The six maskable status bits are ANDed with theirrespective mask bits, and the results are ORed toproduce the interrupt signal. An RI or TAinterrupt is masked when the corresponding maskbit is reset to logic "0", but will reappear when thecorresponding mask bit is set to logic "1" again,unless the interrupt status condition has beencleared by this time. A RECON interrupt iscleared when the "Clear Flags" command isissued. An EXCNAK interrupt is cleared when the"POR Clear Flags" command is issued. A NewNext ID interrupt is cleared by reading the Next IDRegister. The Interrupt Mask Register defaults tothe value 0000 0000 upon hardware reset.

Data Register

This read/write 8-bit register is used as thechannel through which the data to and from theRAM passes. The data is placed in or retrievedfrom the address location presently specified bythe address pointer. The contents of the DataRegister are undefined upon hardware reset. Incase of READ operation, the Data Register isloaded with the contents of COM20020D InternalMemory upon writing Address Pointer low onlyonce.

Tentative ID Register

The Tentative ID Register is a read/write 8-bitregister accessed when the Sub Address Bits areset up accordingly (please refer to theConfiguration Register and SUB ADR Register).The Tentative ID Register can be used while thenode is on-line to build a network map of thosenodes existing on the network. It minimizes theneed for operator interaction with the network.The node determines the existence of other nodesby placing a Node ID value in the Tentative IDRegister and waiting to see if the Tentative ID bitof the Diagnostic Status Register gets set. Thenetwork map developed by this method is onlyvalid for a short period of time, since nodes mayjoin or depart from the network at any time. Whenusing the Tentative ID feature, a node cannotdetect the existence of the next logical node towhich it passes the token. The Next ID Registerwill hold the ID value of that node. The TentativeID Register defaults to the value 0000 0000 uponhardware reset only.

Node ID Register

The Node ID Register is a read/write 8-bit registeraccessed when the Sub Address Bits are set upaccordingly (please refer to the ConfigurationRegister and SUB ADR Register). The Node IDRegister contains the unique value whichidentifies this particular node. Each node on thenetwork must have a unique Node ID value at alltimes. The Duplicate ID bit of the DiagnosticStatus Register helps the user find a unique NodeID. Refer to the Initialization Sequence section forfurther detail on the use of the DUPID bit. Thecore of the COM20020D does not wake up until aNode ID other than zero is written into the NodeID Register. During this time, no microcode isexecuted, no tokens are passed by this node, andno reconfigurations are caused by this node.Once a non-zero NodeID is placed into the NodeID Register, the core wakes up but will not join thenetwork until the TXEN bit of the ConfigurationRegister is set. While the Transmitter is disabled,the Receiver portion of the device is still functionaland will provide the user with useful informationabout the network. The Node ID Register defaultsto the value 0000 0000 upon hardware reset only.

26

Next ID Register

The Next ID Register is an 8-bit, read-onlyregister, accessed when the sub-address bits areset up accordingly (please refer to theConfiguration Register and SUB ADR Register).The Next ID Register holds the value of the NodeID to which the COM20020D will pass the token.When used in conjunction with the Tentative IDRegister, the Next ID Register can provide acomplete network map. The Next ID Register isupdated each time a node enters/leaves thenetwork or when a network reconfiguration occurs.Each time the microsequencer updates the NextID Register, a New Next ID interrupt is generated.This bit is cleared by reading the Next ID Register.Default value is 0000 0000 upon hardware orsoftware reset.

Status Register

The COM20020D Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and6, are software compatible with previous SMSCARCNET devices. In previous SMSC ARCNETdevices the Extended Timeout status wasprovided in bits 5 and 6 of the Status Register. Inthe COM20020D, the COM20020, theCOM90C66, and the COM90C165, COM20020-5,COM20051 and COM20051+ these bits exist inand are controlled by the Configuration Register.The Status Register contents are defined as inTable 4, but are defined differently during theCommand Chaining operation. Please refer to theCommand Chaining section for the definition ofthe Status Register during Command Chainingoperation. The Status Register defaults to thevalue 1XX1 0001 upon either hardware orsoftware reset.

Diagnostic Status Register

The Diagnostic Status Register contains sevenread-only bits which help the user troubleshootthe network or node operation. Variouscombinations of these bits and the TXEN bit of theConfiguration Register represent differentsituations. All of these bits, except the ExcessiveNAcK bit and the New Next ID bit, are reset tologic "0" upon reading the Diagnostic StatusRegister or upon software or hardware reset. TheEXCNAK bit is reset by the "POR Clear Flags"command or upon software or hardware reset.The Diagnostic Status Register defaults to thevalue 0000 000X upon either hardware orsoftware reset.

Command Register

Execution of commands are initiated byperforming microcontroller writes to this register.Any combinations of written data other thanthose listed in Table 5 are not permitted and mayresult in incorrect chip and/or network operation.

Address Pointer Registers

These read/write registers are each 8-bits wideand are used for addressing the internal RAM.New pointer addresses should be written by firstwriting to the High Register and then writing to theLow Register because writing to the Low Registerloads the address. The contents of the AddressPointer High and Low Registers are undefinedupon hardware reset. Writing to Address Pointerlow loads the address.

Configuration Register

The Configuration Register is a read/write registerwhich is used to configure the different modes ofthe COM20020D. The Configuration Registerdefaults to the value 0001 1000 upon hardwarereset only. SUBAD0 and SUBAD1 point to theselection in Register 7.

27

Sub-Address Register

The sub-address register is new to theCOM20020D, previously a reserved register. Bits2, 1 and 0 are used to select one of the registersassigned to address 7h. SUBAD1 and SUBAD0already exist in the Configuration register on theCOM20020B. They are exactly same as those inthe Sub-Address register. If the SUBAD1 andSUBAD0 bits in the Configuration register arechanged, the SUBAD1and SUBAD0 in the Sub-Address register are also changed. SUBAD2 is anew sub-address bit. It Is used to access the 1new Set Up register, SETUP2. This register isselected by setting SUBAD2=1. The SUBAD2 bitis cleared automatically by writing theConfiguration register.

Setup 1 Register

The Setup 1 Register is a read/write 8-bit registeraccessed when the Sub Address Bits are set upaccordingly (see the bit definitions of theConfiguration Register). The Setup 1 Registerallows the user to change the network speed (datarate) or the arbitration speed independently,invoke the Receive All feature and change thenPULSE1 driver type. The data rate may beslowed to 156.25Kbps and/or the arbitration speedmay be slowed by a factor of two. The Setup 1Register defaults to the value 0000 0000 uponhardware reset only.

Setup 2 Register

The Setup 2 Register is new to the COM20020D.It is an 8-bit read/write register accessed whenthe Sub Address Bits SUBAD[2:0] are set upaccordingly (see the bit definitions of the SubAddress Register). This register contains bits forvarious functions. The CKUP1,0 bits select theclock to be generated from the 20 MHz crystal.The RBUSTMG bit is used to Disable/EnableFast Read function for High Speed CPU bussupport. The EF bit is used to enable the newtiming for certain functions in the COM20020D (ifEF = 0, the timing is the same as in theCOM20020 Rev. B). See Appendix A. TheNOSYNC bit is used to enable the NOSYNCfunction during initialization. If this bit is reset,the line has to be idle for the RAM initializationsequence to be written. If set, the line does nothave to be idle for the initialization sequence tobe written. See Appendix A.

The RCNTM[1,0] bits are used to set the time-out period of the recon timer. Programming thistimer for shorter time periods has the benefit ofshortened network reconfiguration periods. Thetime periods shown in the table on the followingpage are limited by a maximum number of nodesin the network. These time-out period values arefor 5Mbps. For other data rates, scale the time-out period time values accordingly; the maximumnode count remains the same.

RCNTM1 RCNTM0TIME-OUTPERIOD

MAX NODECOUNT

0 0 420 mS Up to 255 nodes0 1 105 mS Up to 64 nodes1 0 52.5 mS Up to 32 nodes1 1 26.25 mS* Up to 16 nodes*

Note*: The node ID value 255 must exist in the network for the 26.25 mS time-out to be valid.

28

Table 4 - Status Register

BIT BIT NAME SYMBOL DESCRIPTION

7 ReceiverInhibited

RI This bit, if high, indicates that the receiver is not enabled becauseeither an "Enable Receive to Page fnn" command was neverissued, or a packet has been deposited into the RAM buffer pagefnn as specified by the last "Enable Receive to Page fnn"command. No messages will be received until this command isissued, and once the message has been received, the RI bit is set,thereby inhibiting the receiver. The RI bit is cleared by issuing an"Enable Receive to Page fnn" command. This bit, when set, willcause an interrupt if the corresponding bit of the Interrupt MaskRegister (IMR) is also set. When this bit is set and another stationattempts to send a packet to this station, this station will send aNAK.

6,5 (Reserved) These bits are undefined.

4 Power On Reset POR This bit, if high, indicates that the COM20020D has been reset byeither a software reset, a hardware reset, or writing 00H to theNode ID Register. The POR bit is cleared by the "Clear Flags"command.

3 Test TEST This bit is intended for test and diagnostic purposes. It is a logic"0" under normal operating conditions.

2 Reconfiguration RECON This bit, if high, indicates that the Line Idle Timer has timed outbecause the RXIN pin was idle for 41mS. The RECON bit iscleared during a "Clear Flags" command. This bit, when set, willcause an interrupt if the corresponding bit in the IMR is also set.The interrupt service routine should consist of examining theMYRECON bit of the Diagnostic Status Register to determinewhether there are consecutive reconfigurations caused by thisnode.

1 TransmitterMessageAcknowledged

TMA This bit, if high, indicates that the packet transmitted as a result ofan "Enable Transmit from Page fnn" command has beenacknowledged. This bit should only be considered valid after theTA bit (bit 0) is set. Broadcast messages are never acknowledged.The TMA bit is cleared by issuing the "Enable Transmit from Pagefnn" command.

0 TransmitterAvailable

TA This bit, if high, indicates that the transmitter is available fortransmitting. This bit is set when the last byte of scheduled packethas been transmitted out, or upon execution of a "DisableTransmitter" command. The TA bit is cleared by issuing the"Enable Transmit from Page fnn" command after the node nextreceives the token. This bit, when set, will cause an interrupt if thecorresponding bit in the IMR is also set.

29

Table 5 - Diagnostic Status Register

BIT BIT NAME SYMBOL DESCRIPTION

7 MyReconfiguration

MY-RECON

This bit, if high, indicates that a past reconfiguration was caused by thisnode. It is set when the Lost Token Timer times out, and should betypically read following an interrupt caused by RECON. Refer to theImproved Diagnostics section for further detail.

6 Duplicate ID DUPID This bit, if high, indicates that the value in the Node ID Registermatches both Destination ID characters of the token and a response tothis token has occurred. Trailing zero's are also verified. A logic "1" onthis bit indicates a duplicate Node ID, thus the user should write a newvalue into the Node ID Register. This bit is only useful for duplicate IDdetection when the device is off line, that is, when the transmitter isdisabled. When the device is on line this bit will be set every time thedevice gets the token. This bit is reset automatically upon reading theDiagnostic Status Register. Refer to the Improved Diagnostics sectionfor further detail.

5 ReceiveActivity

RCVACT This bit, if high, indicates that data activity (logic "1") was detected onthe RXIN pin of the device. Refer to the Improved Diagnostics sectionfor further detail.

4 Token Seen TOKEN This bit, if high, indicates that a token has been seen on the network,sent by a node other than this one. Refer to the Improved Diagnosticsection for further detail.

3 Excessive NAK EXCNAK This bit, if high, indicates that either 128 or 4 NegativeAcknowledgements have occurred in response to the Free BufferEnquiry. This bit is cleared upon the "POR Clear Flags" command.Reading the Diagnostic Status Register does not clear this bit. This bit,when set, will cause an interrupt if the corresponding bit in the IMR isalso set. Refer to the Improved Diagnostics section for further detail.

2 Tentative ID TENTID This bit, if high, indicates that a response to a token whose DIDmatches the value in the Tentative ID Register has occurred. Thesecond DID and the trailing zero's are not checked. Since each nodesees every token passed around the network, this feature can be usedwith the device on-line in order to build and update a network map.Refer to the Improved Diagnostics section for further detail.

1 New Next ID NEWNXTID

This bit, if high, indicates that the Next ID Register has been updatedand that a node has either joined or left the network. Reading theDiagnostic Status Register does not clear this bit. This bit, when set,will cause an interrupt if the corresponding bit in the IMR is also set.The bit is cleared by reading the Next ID Register.

1,0 (Reserved) These bits are undefined.

30

Table 6 - Command RegisterDATA COMMAND DESCRIPTION

0000 0000 ClearTransmitInterrupt

This command is used only in the Command Chaining operation.Please refer to the Command Chaining section for definition ofthis command.

0000 0001 DisableTransmitter

This command will cancel any pending transmit command(transmission that has not yet started) and will set the TA(Transmitter Available) status bit to logic "1" when theCOM20020D next receives the token.

0000 0010 DisableReceiver

This command will cancel any pending receive command. If theCOM20020D is not yet receiving a packet, the RI (ReceiverInhibited) bit will be set to logic "1" the next time the token isreceived. If packet reception is already underway, reception willrun to its normal conclusion.

b0fn n100 EnableReceive toPage fnn

This command allows the COM20020D to receive data packetsinto RAM buffer page fnn and resets the RI status bit to logic "0".The values placed in the "nn" bits indicate the page that the datawill be received into (page 0, 1, 2, or 3). If the value of "f" is alogic "1", an offset of 256 bytes will be added to that pagespecified in "nn", allowing a finer resolution of the buffer. Refer tothe Selecting RAM Page Size section for further detail. If thevalue of "b" is logic "1", the device will also receive broadcasts(transmissions to ID zero). The RI status bit is set to logic "1"upon successful reception of a message.

00fn n011 EnableTransmit fromPage fnn

This command prepares the COM20020D to begin a transmitsequence from RAM buffer page fnn the next time it receives thetoken. The values of the "nn" bits indicate which page to transmitfrom (0, 1, 2, or 3). If "f" is logic "1", an offset of 256 bytes is thestart of the page specified in "nn", allowing a finer resolution of thebuffer. Refer to the Selecting RAM Page Size section for furtherdetail. When this command is loaded, the TA and TMA bits arereset to logic "0". The TA bit is set to logic "1" upon completion ofthe transmit sequence. The TMA bit will have been set by thistime if the device has received an ACK from the destination node.The ACK is strictly hardware level, sent by the receiving nodebefore its microcontroller is even aware of message reception.Refer to Figure 1 for details of the transmit sequence and itsrelation to the TA and TMA status bits.

0000 c101 DefineConfiguration

This command defines the maximum length of packets that maybe handled by the device. If "c" is a logic "1", the device handlesboth long and short packets. If "c" is a logic "0", the devicehandles only short packets.

000r p110 Clear Flags This command resets certain status bits of the COM20020D. Alogic "1" on "p" resets the POR status bit and the EXCNAKDiagnostic status bit. A logic "1" on "r" resets the RECON statusbit.

31

DATA COMMAND DESCRIPTION

0000 1000 ClearReceiveInterrupt

This command is used only in the Command Chaining operation.Please refer to the Command Chaining section for definition ofthis command.

0001 1000 Start InternalOperation

This command restarts the stopped internal operation afterchanging CKUP1 or CKUP0 bit.

Table 7 - Address Pointer High Register

BIT BIT NAME SYMBOL DESCRIPTION

7 Read Data RDDATA This bit tells the COM20020D whether the following accesswill be a read or write. A logic "1" prepares the device for aread, a logic "0" prepares it for a write.

6 Auto Increment AUTOINC This bit controls whether the address pointer will incrementautomatically. A logic "1" on this bit allows automaticincrement of the pointer after each access, while a logic "0"disables this function. Please refer to the SequentialAccess Memory section for further detail.

5-3 (Reserved) These bits are undefined.

2-0 Address 10-8 A10-A8 These bits hold the upper three address bits which provideaddresses to RAM.

Table 8 - Address Pointer Low Register

BIT BIT NAME SYMBOL DESCRIPTION

7-0 Address 7-0 A7-A0 These bits hold the lower 8 address bits which provide theaddresses to RAM.

32

Table 9 - Sub Address Register

BIT BIT NAME SYMBOL DESCRIPTION

7-3 Reserved These bits are undefined.

2,1,0 Sub Address 2,1,0 SUBAD2,1,0

These bits determine which register at address 07 may beaccessed. The combinations are as follows:

SUBAD2 SUBAD1 SUBAD0 Register 0 0 0Tentative ID \ (Same 0 0 1Node ID \ as in 0 1 0Setup 1 / Config 0 1 1Next ID / Register) 1 0 0Setup 2 1 0 1Reserved 1 1 0Reserved 1 1 1ReservedSUBAD1 and SUBAD0 are exactly the same as exist in theConfiguration Register. SUBAD2 is cleared automatically bywriting the Configuration Register.

Table 10 - Configuration Register

7 Reset RESET A software reset of the COM20020D is executed by writing alogic "1" to this bit. A software reset does not reset themicrocontroller interface mode, nor does it affect theConfiguration Register. The only registers that the softwarereset affect are the Status Register, the Next ID Register, andthe Diagnostic Status Register. This bit must be broughtback to logic "0" to release the reset.

6 CommandChaining Enable

CCHEN This bit, if high, enables the Command Chaining operation ofthe device. Please refer to the Command Chaining sectionfor further details. A low level on this bit ensures softwarecompatibility with previous SMSC ARCNET devices.

5 Transmit Enable TXEN When low, this bit disables transmissions by keepingnPULSE1, nPULSE2 if in non-Backplane Mode, and nTXENpin inactive. When high, it enables the above signals to beactivated during transmissions. This bit defaults low uponreset. This bit is typically enabled once the Node ID isdetermined, and never disabled during normal operation.Please refer to the Improved Diagnostics section for detailson evaluating network activity.

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Table 10 - Configuration Register

4,3 ExtendedTimeout 1,2

ET1, ET2 These bits allow the network to operate over longer distancesthan the default maximum 2 miles by controlling theResponse, Idle, and Reconfiguration Times. All nodes shouldbe configured with the same timeout values for propernetwork operation. For the COM20020D with a 20 MHzcrystal oscillator, the bit combinations follow:

ET20011

ET10101

ResponseTime (mS)

596.6298.4149.2 37.4

Idle Time(mS)65632816441

ReconfigTime(mS)840840840 420

Note: These values are for 5Mbps and RCNTMR[1,0]=00.Reconfiguration time is changed by the RCNTMR1 andRCNTMR0 bits.

2 Backplane BACK-PLANE

A logic "1" on this bit puts the device into Backplane Modesignaling which is used for Open Drain and Differential Driverinterfaces.

1,0 Sub Address 1,0 SUBAD1,0

These bits determine which register at address 07 may beaccessed. The combinations are as follows:

SUBAD1 SUBAD0 Register 0 0 Tentative ID 0 1 Node ID 1 0 Setup 1 1 1 Next IDSee also the Sub Address Register.

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Table 11 - Setup 1 Register

BIT BIT NAME SYMBOL DESCRIPTION7 Pulse1 Mode P1MODE This bit determines the type of PULSE1 output driver used

in Backplane Mode. When high, a push/pull output is used.When low, an open drain output is used. The default isopen drain.

6 Four NACKS FOURNACKS

This bit, when set, will cause the EXNACK bit in theDiagnostic Status Register to set after four NACKs to FreeBuffer Enquiry are detected by the COM20020D. This bit,when reset, will set the EXNACK bit after 128 NACKs toFree Buffer Enquiry. The default is 128.

5 Reserved Do not set.4 Receive All RCVALL This bit, when set, allows the COM20020D to receive all

valid data packets on the network, regardless of theirdestination ID. This mode can be used to implement anetwork monitor with the transmitter on- or off-line. Notethat ACKs are only sent for packets received with adestination ID equal to the COM20020D's programmednode ID. This feature can be used to put the COM20020Din a 'listen-only' mode, where the transmitter is disabled andthe COM20020D is not passing tokens. Defaults low.

3,2,1 Clock Prescaler Bits3,2,1

CKP3,2,1 These bits are used to determine the data rate of theCOM20020D. The following table is for a 20 MHz crystal:(Clock Multiplier is bypassed)CKP3

00001

CKP200110

CKP101010

DIVISOR8163264128

SPEED2.5Mbs1.25Mbs625Kbs

312.5Kbs156.25Kbs

NOTE: The lowest data rate achievable by theCOM20020D is 156.25Kbs. Defaults to 000 or 2.5Mbs. ForClock Multiplier output clock speed greater than 20 MHz,CKP3, CKP2 and CKP1 must all be zero.

0 Slow ArbitrationSelect

SLOWARB This bit, when set, will divide the arbitration clock by 2.Memory cycle times will increase when slow arbitration isselected.NOTE: For clock multiplier output clock speeds greaterthan 40 MHz, SLOWARB must be set. Defaults to low.

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Table 12 - Setup 2 RegisterBIT BIT NAME SYMBOL DESCRIPTION7 Read Bus Timing

SelectRBUSTMG This bit is used to Disable/Enable the High Speed CPU

Read function for High Speed CPU bus support.RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable. Itdoes not influence write operation. High speed CPU Readoperation is only for non-multiplexed bus.

6 Reserved This bit is undefined.5,4 Clock Multiplier CKUP1, 0 Higher frequency clocks are generated from the 20 MHz

crystal through the selection of these two bits as shown.This clock multiplier is powered-down on default. Afterchanging the CKUP1 and CKUP0 bits, the ARCNET coreoperation is stopped and the internal PLL in the clockmultiplier is awakened and it starts to generate the 40 MHz.The lock out time of the internal PLL is 8mSec typically.After 1 mS it is necessary to write command data '18H' tocommand register for re-starting the ARCNET coreoperation. EF bit must be 1 if the data rate is over 5Mbps.CAUTION: Changing the CKUP1 and CKUP0 bits must beone time or less after releasing a hardware reset.

CKUP1 CKUP0 Clock Frequency (Data Rate)0 0 20 MHz (Up to 2.5Mbps) Default0 1 40 MHz (Up to 5Mbps)1 0 Reserved1 1 Reserved

Note: After changing the CKUP1 or CKUP0 bits, it isnecessary to write a command data '18H' to the commandregister. Because after changing the CKUP [1, 0] bits, theinternal operation is stopped temporarily. The writing of thecommand is to start the operation.These initializing steps are shown below.1) Hardware reset (Power ON)2) Change CKUP[1, 0] bit3) Wait 1mSec (wait until stable oscillation)4) Write command '18H' (start internal operation)5) Start initializing routine (Execute existing software)

3 EnhancedFunctions

EF This bit is used to enable the new enhanced functions in theCOM20020D. EF = 0: Disable (Default), EF = 1: Enable. IfEF = 0, the timing and function is the same as in theCOM20020, Revision B. See appendix A. EF bit must be1 if the data rate is over 5Mbps.EF bit should be 1 for new design customers.EF bit should be 0 for replacement customers.

2 No Synchronous NOSYNC This bit is used to enable the SYNC command duringinitialization. NOSYNC= 0, Enable (Default) The line mustbe idle for the RAM initialization sequence to be written.NOSYNC= 1, Disable:) The line does not have to be idle forthe RAM initialization sequence to be written. See appendixA.

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Table 12 - Setup 2 RegisterBIT BIT NAME SYMBOL DESCRIPTION1,0 Reconfiguration

Timer 1, 0RCNTM1,0 These bits are used to program the reconfiguration timer as a

function of maximum node count. These bits set the time outperiod of the reconfiguration timer as shown below. Thetime out periods shown are for 5 Mbps.RCNTM1 RCNTM0 Time Out

PeriodMax Node Count

0 0 420 mS Up to 255 nodes0 1 105 mS Up to 64 nodes1 0 52.5 mS Up to 32 nodes1 1 26.25 mS* Up to 16 nodes

Note*: The node ID value 255 must exist in the network for26.25 mS timeout to be valid.

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FIGURE 8 - SEQUENTIAL ACCESS OPERATION

Address Pointer Register

Low

2K x 8

RAM

11

Data Register

8

I/O Address 04H

I/O Address 03H

11-Bit Counter

MemoryAddress Bus

MemoryData Bus

D0-D7

High

I/O Address 02H

INTERNAL

38

INTERNAL RAM

The integration of the 2K x 8 RAM in theCOM20020D represents significant real estatesavings. The most obvious benefit is the 48 pinpackage in which the device is now placed (adirect result of the integration of RAM). Inaddition, the PC board is now free of thecumbersome external RAM, external latch, andmultiplexed address/data bus and controlfunctions which were necessary to interface to theRAM. The integration of RAM representssignificant cost savings because it isolates thesystem designer from the changing costs ofexternal RAM and it minimizes reliability problems,assembly time and costs, and layout complexity.

Sequential Access Memory

The internal RAM is accessed via a pointer-basedscheme. Rather than interfering with systemmemory, the internal RAM is indirectly accessedthrough the Address High and Low PointerRegisters. The data is channeled to and from themicrocontroller via the 8-bit data register. Forexample: a packet in the internal RAM buffer isread by the microcontroller by writing thecorresponding address into the Address PointerHigh and Low Registers (offsets 02H and 03H).Note that the High Register should be written first,followed by the Low Register, because writing tothe Low Register loads the address. At this pointthe device accesses that location and places thecorresponding data into the data register. Themicrocontroller then reads the data register (offset04H) to obtain the data at the specified location. Ifthe Auto Increment bit is set to logic "1", thedevice will automatically increment the addressand place the next byte of data into the dataregister, again to be read by the microcontroller.This process is continued until the entire packetis read out of RAM. Refer to Figure 8 for anillustration of the Sequential Access operation.When switching between reads and writes, thepointer must first be written with the startingaddress. At least one cycle time should separate

the pointer being loaded and the first read (seetiming parameters).

Access Speed

The COM20020D is able to accommodate veryfast access cycles to its registers and buffers.Arbitration to the buffer does not slow down thecycle because the pointer based access methodallows data to be prefetched from memory andstored in a temporary register. Likewise, data tobe written is stored in the temporary register andthen written to memory.

For systems which do not require quick accesstime, the arbitration clock may be slowed down bysetting bit 0 of the Setup1 Register equal to logic"1". Since the Slow Arbitration feature divides theinput clock by two, the duty cycle of the input clockmay be relaxed.

SOFTWARE INTERFACE

The microcontroller interfaces to the COM20020Dvia software by accessing the various registers.These actions are described in the InternalRegisters section. The software flow foraccessing the data buffer is based on theSequential Access scheme. The basic sequenceis as follows: Disable Interrupts Write to Pointer Register High (specifying

Auto-Increment mode) Write to Pointer Register Low (this loads the

address) Enable Interrupts Read or Write the Data Register (repeat as

many times as necessary to empty or fill thebuffer)

The pointer may now be read to determinehow many transfers were completed.

The software flow for controlling the Configuration,Node ID, Tentative ID, and Next ID registers isgenerally limited to the initialization sequence andthe maintenance of the network map.

39

Additionally, it is necessary to understand thedetails of how the other Internal Registers areused in the transmit and receive sequences and toknow how the internal RAM buffer is properly setup. The sequence of events that tie these actionstogether is discussed as follows.

Selecting RAM Page Size

During normal operation, the 2K x 8 of RAM isdivided into four pages of 512 bytes each. Thepage to be used is specified in the "EnableTransmit (Receive) from (to) Page fnn" command,where "nn" specifies page 0, 1, 2, or 3. Thisallows the user to have constant control over theallocation of RAM.

When the Offset bit "f" (bit 5 of the "EnableTransmit (Receive) from (to) Page fnn" commandword) is set to logic "1", an offset of 256 bytes isadded to the page specified. For example: totransmit from the second half of page 0, thecommand "Enable Transmit from Page fnn"(fnn=100 in this case) is issued by writing 00100011 to the Command Register. This allows afiner resolution of the buffer pages withoutaffecting software compatibility. This scheme isuseful for applications which frequently use packetsizes of 256 bytes or less, especially formicrocontroller systems with limited memorycapacity. The remaining portions of the bufferpages which are not allocated for current transmitor receive packets may be used as temporarystorage for previous network data, packets to besent later, or as extra memory for the system,which may be indirectly accessed.

If the device is configured to handle both long andshort packets (see "Define Configuration"command), then receive pages should always be512 bytes long because the user never knowswhat the length of the receive packet will be. Inthis case, the transmit pages may be made 256bytes long, leaving at least 512 bytes free at anygiven time. Even if the Command Chainingoperation is being used, 512 bytes is still

guaranteed to be free because CommandChaining only requires two pages for transmit andtwo for receive (in this case, two 256 byte pagesfor transmit and two 512 byte pages for receive,leaving 512 bytes free). Please note that it is theresponsibility of software to reserve 512 bytes foreach receive page if the device is configured tohandle long packets. The COM20020D does notcheck page boundaries during reception. If thedevice is configured to handle only short packets,then both transmit and receive pages may beallocated as 256 bytes long, freeing at least1KByte at any given time.

Even if the Command Chaining operation is beingused, 1KByte is still guaranteed to be freebecause Command Chaining only requires twopages for transmit and two for receive (in thiscase, a total of four 256 byte pages, leaving 1Kfree).

The general rule which may be applied todetermine where in RAM a page begins is asfollows:Address = (nn x 512) + (f x 256).

Transmit Sequence

During a transmit sequence, the microcontrollerselects a 256 or 512 byte segment of the RAMbuffer and writes into it. The appropriate buffersize is specified in the "Define Configuration"command. When long packets are enabled, theCOM20020D interprets the packet as either a longor short packet, depending on whether the bufferaddress 2 contains a zero or non-zero value. Theformat of the buffer is shown in Figure 9. Address0 contains the Source Identifier (SID); Address 1contains the Destination Identifier (DID); Address2 (COUNT) contains, for short packets, the value256-N, where N represents the number ofinformation bytes in the message, or for longpackets, the value 0, indicating that it is indeed along packet. In the latter case, Address 3(COUNT) would contain the value 512-N, where Nrepresents the number of information bytes in

40

FIGURE 9 - RAM BUFFER PACKET CONFIGURATION

SID

DID

COUNT = 256-N

NOT USED

DATA BYTE 1

DATA BYTE 2

DATA BYTE N-1

DATA BYTE N

NOT USED

SID

DID

0

COUNT = 512-N

NOT USED

DATA BYTE 1

DATA BYTE 2

DATA BYTE N-1

DATA BYTE N

SHORT PACKETFORMAT

LONG PACKETFORMAT

ADDRESS ADDRESS0

1

2

COUNT

255

511

N = DATA PACKET LENGTHSID = SOURCE IDDID = DESTINATION ID(DID = 0 FOR BROADCASTS)

0

1

2

COUNT

511

3

41

the message. The SID in Address 0 is used bythe receiving node to reply to the transmittingnode. The COM20020D puts the local ID in thislocation, therefore it is not necessary to write intothis location. Please note that a short packet maycontain between 1 and 253 data bytes, while along packet may contain between 257 and 508data bytes. A minimum value of 257 exists on along packet so that the COUNT is expressible ineight bits. This leaves three exception packetlengths which do not fit into either a short or longpacket; packet lengths of 254, 255, or 256 bytes.If packets of these lengths must be sent, the usermust add dummy bytes to the packet in order tomake the packet fit into a long packet.

Once the packet is written into the buffer, themicrocontroller awaits a logic "1" on the TA bit,indicating that a previous transmit command hasconcluded and another may be issued. Each timethe message is loaded and a transmit commandissued, it will take a variable amount of time beforethe message is transmitted, depending on thetraffic on the network and the location of the tokenat the time the transmit command was issued.The conclusion of the Transmit Command willgenerate an interrupt if the Interrupt Mask allowsit. If the device is configured for the CommandChaining operation, please see the CommandChaining section for further detail on the transmitsequence. Once the TA bit becomes a logic "1",the microcontroller may issue the "EnableTransmit from Page fnn" command, which resetsthe TA and TMA bits to logic "0". If the messageis not a BROADCAST, the COM20020Dautomatically sends a FREE BUFFER ENQUIRYto the destination node in order to send themessage. At this point, one of four possibilitiesmay occur.

The first possibility is if a free buffer is available atthe destination node, in which case it respondswith an ACKnowledgement. At this point, theCOM20020D fetches the data from the TransmitBuffer and performs the transmit sequence. If asuccessful transmit sequence is completed, theTMA bit and the TA bit are set to logic "1". If thepacket was not transmitted successfully, TMA willnot be set. A successful transmission occurswhen the receiving node responds to the packet

with an ACK. An unsuccessful transmissionoccurs when the receiving node does not respondto the packet.

The second possibility is if the destination noderesponds to the Free Buffer Enquiry with aNegative AcKnowledgement. A NAK occurswhen the RI bit of the destination node is a logic"1". In this case, the token is passed on from thetransmitting node to the next node. The next timethe transmitter receives the token, it will againtransmit a FREE BUFFER ENQUIRY. If a NAK isagain received, the token is again passed onto thenext node. The Excessive NAK bit of theDiagnostic Status Register is used to prevent anendless sending of FBE's and NAK's. If no limit ofFBE-NAK sequences existed, the transmittingnode would continue issuing a Free BufferEnquiry, even though it would continuouslyreceive a NAK as a response. The EXCNAK bitgenerates an interrupt (if enabled) in order to tellthe microcontroller to disable the transmitter viathe "Disable Transmitter" command. This causesthe transmission to be abandoned and the TA bitto be set to a logic "1" when the node nextreceives the token, while the TMA bit remains at alogic "0". Please refer to the Improved Diagnosticssection for further detail on the EXCNAK bit.

The third possibility which may occur after aFREE BUFFER ENQUIRY is issued is if thedestination node does not respond at all. In thiscase, the TA bit is set to a logic "1", while the TMAbit remains at a logic "0". The user shoulddetermine whether the node should try to reissuethe transmit command.

The fourth possibility is if a non-traditionalresponse is received (some pattern other thanACK or NAK, such as noise). In this case, thetoken is not passed onto the next node, whichcauses the Lost Token Timer of the next node totime out, thus generating a networkreconfiguration.

The "Disable Transmitter" command may be usedto cancel any pending transmit command whenthe COM20020D next receives the token.Normally, in an active network, this command willset the TA status bit to a logic "1" when the tokenis received. If the "Disable Transmitter" commanddoes not cause the TA bit to be set in the time it

42

takes the token to make a round trip through thenetwork, one of three situations exists. Either thenode is disconnected from the network, or thereare no other nodes on the network, or the externalreceive circuitry has failed. These situations canbe determined by either using the improveddiagnostic features of the COM20020D or usinganother software timeout which is greater than theworst case time for a round trip token pass, whichoccurs when all nodes transmit a maximum lengthmessage.

Receive Sequence

A receive sequence begins with the RI status bitbecoming a logic "1", which indicates that aprevious reception has concluded. Themicrocontroller will be interrupted if thecorresponding bit in the Interrupt Mask Register isset to logic "1". Otherwise, the microcontrollermust periodically check the Status Register. Oncethe microcontroller is alerted to the fact that theprevious reception has concluded, it may issuethe "Enable Receive to Page fnn" command,which resets the RI bit to logic "0" and selects anew page in the RAM buffer. Again, theappropriate buffer size is specified in the "DefineConfiguration" command. Typically, the pagewhich just received the data packet will be read bythe microcontroller at this point. Once the "Enable

Receive to Page fnn" command is issued, themicrocontroller attends to other duties. There isno way of knowing how long the new receptionwill take, since another node may transmit apacket at any time. When another node doestransmit a packet to this node, and if the "DefineConfiguration" command has enabled thereception of long packets, the COM20020Dinterprets the packet as either a long or shortpacket, depending on whether the content of thebuffer location 2 is zero or non-zero. The formatof the buffer is shown in Figure 10. Address 0contains the Source Identifier (SID), Address 1contains the Destination Identifier (DID), andAddress 2 contains, for short packets, the value256-N, where N represents the message length,or for long packets, the value 0, indicating that it isindeed a long packet. In the latter case, Address3 contains the value 512-N, where N representsthe message length. Note that on reception, theCOM20020D deposits packets into the RAMbuffer in the same format that the transmittingnode arranges them, which allows for a messageto be received and then retransmitted withoutrearranging any bytes in the RAM buffer otherthan the SID and DID. Once the packet isreceived and stored correctly in the selectedbuffer, the COM20020D sets the RI bit to logic "1"to signal the microcontroller that the reception iscomplete.

FIGURE 10 - COMMAND CHAINING STATUS REGISTER QUEUE

TRI RI TA POR TEST RECON

TMA TTA

TMA TTA

TRI

MSB LSB

43

COMMAND CHAINING

The Command Chaining operation allowsconsecutive transmissions and receptions to occurwithout host microcontroller intervention.

Through the use of a dual two-level FIFO,commands to be transmitted and received, as wellas the status bits, are pipelined.

In order for the COM20020D to be compatible withprevious SMSC ARCNET device drivers, thedevice defaults to the non-chaining mode. In orderto take advantage of the Command Chainingoperation, the Command Chaining Mode must beenabled via a logic "1" on bit 6 of the ConfigurationRegister.

In Command Chaining, the Status Registerappears as in Figure 10.

The following is