combinational circuit design - national chiao tung...

Introduction to VLSI and System-on-Chip Design

Combinational Circuit Design

Lan-Da Van (), Ph. D.Department of Computer ScienceNational Chiao Tung University

Taiwan, R.O.C.Fall, 2009

[email protected]

http://www.cs.nctu.edu.tw/~ldvan/

Lan-Da Van VLSI-05-2

Lecture 5


OutlinesIntroductionStatic CMOS Circuits

Static Complementary Logic GatesAsymmetric GateSkewed GateP/N ratios

Ratioed CircuitsPseudo-nMOS GatesDifferential Cascode Voltage Switch Logic (DCVSL)

Dynamic CMOS CircuitsDomino Logic

Transmission GateConclusion


Lecture 5


Universal/CompleteA set of functions f1, f2, ..fn is universal/complete iffevery Boolean function can be generated by a combination of the functions.{AND, OR, Inverter} is universal/complete. However, {AND, OR} is not universal/complete.AOI = and/or/invert; OAI = or/and/invert.NAND is a universal/complete gate; NOR is a universal/complete gate. How to prove??Transmission gates are not universal/complete gate.If your set of logic gates is not universal/complete, you cant design arbitrary logic.


Lecture 5


Logical Effort Factor

What makes a circuit fast?I=CdV/dt => Low capacitanceHigh currentSmall swing

Logical effort is proportional to C/IpMOS are the enemy!!

High capacitance for a given currentCan we take the pMOS capacitance off the input?Various circuit families try to do this

VICt pd )/(


Lecture 5








Lecture 5


Static Complementary GatesStatic: do not rely on the stored charge.Complementary: have complementary pullup (p-type) and pulldown (n-type) networks.Simple, effective, reliable; hence ubiquitous.

pullupnetwork

pulldownnetwork

VDD

VSS

outinputs


Lecture 5


Pullup/Pulldown Network Design

Pullup and pulldown networks are duals.To design one gate, first design one network, and then compute dual to get other network.Design Steps

Step 1: Formulate Boolean function in fully complement formStep 2: Implement the fully complement form using nMOS(i.e., pull-down network).Step 3: Complement the pull-down network to obtain dual network (i.e., pull-up network) using pMOS.


Lecture 5


NAND Gate


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NOR Gate


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Compound GateAn and-or-invert-21 (AOI-21) gate:out = [ab+c]

symbol circuit

and

or

invert

Network

Dual Network


Lecture 5


Complex CMOS Gate VDD

AB

C

D

DA

B C

OUT = D + A (B+C)


Lecture 5


Logical Effort of Compound Gate

ABCD

Y

ABC Y

A

BC

C

A B

A

B

C

D

A

C

B

D

2

21

4

44

2

2 2

2

4

4 4

4

gA = 6/3

gB = 6/3

gC = 5/3

p = 7/3

gA = 6/3

gB = 6/3

gC = 6/3

p = 12/3

gD = 6/3

YA

A Y

gA = 3/3

p = 3/3

2

1YY

unit inverter AOI21 AOI22

A

C

DE Y

B

Y

B C

A

D

E

A

B

C

D E

gA = 5/3

gB = 8/3

gC = 8/3

gD = 8/3

2

2 2

22

6

6

6 6

3

p = 16/3

gE = 8/3

Complex AOI

Y A B C= + Y A B C D= + ( )Y A B C D E= + +Y A=


Lecture 5


Example: Delay Calculation (1/3)

Calculate the minimum delay of the function F=AB+CD using the following circuits. Each input has a maximum of 20 ut of transistor width. The output must drive a load equivalent to 100 ut of transistor width. Estimate the transistor sizes to achieve this delay.

H = 100 / 20 = 5B = 1N = 2


Lecture 5


NAND Solution (2/3)

100.3

9/8051)9/16(9/16)3/4()3/4(

422

=+=

==

=====

=+=

PfND

Ff

GBHFGP

N


Lecture 5


Compound Solution (3/3)

4.112.3

105122)1()3/6(

513/12

=+=

==

=====

=+=

PfND

Ff

GBHFGP

N


Lecture 5


Example: Width Calculation (1/2)

Annotate your designs with transistor sizes that achieve this delay.

44,

, =

=f

gCC iioutiin 31

,, =

=

f

gCC iioutiin

p2

n2

p1

n1

p1

n1


Lecture 5


Example: Width Calculation (2/2)

Annotate your designs with transistor sizes that achieve this delay.


Lecture 5


Symmetric Gate

Our parasitic delay model was too simpleCalculate parasitic delay for Y falling

If input A is critical.If input B is critical.


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Asymmetric Gates

Asymmetric gates favor one input over anotherEx: suppose input A of a NAND gate is most critical

Use smaller transistor on A (less capacitance)Boost size of noncritical inputSo total resistance is same

gA = 10/9greset = 2gavg = (gA + greset)/2 = 14/9

Asymmetric gate approaches g = 1 on critical inputBut total logical effort goes up


Lecture 5


Skew Definition

Skewed gates favor one edge over another


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Skewed Gates

Skewed gates favor one edge over anotherEx: suppose rising output of inverter is most critical

Downsize noncritical nMOS transistor

Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.

gu = 2.5 / 3 = 5/6gd = 2.5 / 1.5 = 5/3


Lecture 5


Logical Effort for Skew Gate

Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.Skewed gates reduce size of noncritical transistors

HI-skew gates favor rising output (small nMOS)LO-skew gates favor falling output (small pMOS)

Logical effort is smaller for favored direction; but larger for the other direction


Lecture 5


Logical Effort of Skewed Gates

1/2

2A Y

1

1

22

B

AY

BA

1/21/2

4

4

1

1A Y

2

2

11

B

AY

BA

11

2

2

gu = 5/6gd = 5/3gavg = 5/4

gu = 4/3gd = 2/3gavg = 1

gu = 1gd = 2gavg = 3/2

gu = 2gd = 1gavg = 3/2

gu = 3/2gd = 3gavg = 9/4

gu = 2gd = 1gavg = 3/2

Y

Y

1

2A Y

2

2

22

B

AY

BA

11

4

4

gu = 1gd = 1gavg = 1

gu = 4/3gd = 4/3gavg = 4/3

gu = 5/3gd = 5/3gavg = 5/3

Y


Lecture 5


Best P/N Ratio

Prove that the P/N ratio that gives lowest average delay in a logic gate is the square root of the ratio that gives equal rise and fall delays.Sol: For inverter, we have selected P/N ratio (i.e, k) for unit rise and fall resistance.

Using logical effort => tpdf = (P+1)(1/(I+k))Using logical effort => tpdr = (P+1)(1/(P+P/k))tpd = (P+1)(1+k/P)/(2x(1+k)) = (P + 1 + k + k/P)/)/ (2x(1+k))Differentiate tpd w.r.t. PLeast delay is P = k1/2

Ref. CKT


Lecture 5


P/N Ratios

In general, best P/N ratio is sqrt of that giving equal delay.

Only improves average delay slightly for invertersBut significantly decreases area and power


Lecture 5


Pseudo-nMOS

In the old days, nMOS processes had no pMOSInstead, use pull-up transistor that is always ON

In CMOS, use a pMOS that is always ONRatio issueMake pMOS about effective strength of pulldown network

out

in

ds

0 0.3 0.6 0.9 1.2 1.5 1.80

0.3

0.6

0.9

1.2

1.5

1.8

P = 24

P = 4

P = 14

Vin

Vout

Strong Pull-down

Weak Pull-up


Lecture 5


Pseudo-nMOS Characteristics

Logic 1 output is always at VDD.Logic 0 output is above VSS.

VOL = 0.25 (VDD - VSS) is one plausible choice.

Consumes static power.Has much smaller pullup network than static gate.Asymmetrical response. Pullup time is longer than pulldown time.


Lecture 5


Pseudo-nMOS NAND gate

VDD

GND


Lecture 5


Logical Effort of Pseudo-nMOSGates

Design for unit current on outputto compare with unit inverter.pMOS fights nMOS


Lecture 5


Pseudo-nMOS Design

Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H

G = 1 * 8/9 = 8/9F = GBH = 8H/9P = 1 + (4+8k)/9 = (8k+13)/9N = 2D = NF1/N + P =

1

k

4 2 8 133 9

H k ++


Lecture 5


Pseudo-nMOS Power

Pseudo-nMOS draws power whenever Y = 0Called static power P = IVDDA few mA / gate * 1M gates would be a problem

Use pseudo-nMOS sparingly for wide NORsTurn off pMOS when not in use


Lecture 5


DCVS Logic OperationDCVSL = differential cascode voltage switch logic.Static logicconsumes no static power.Uses latch to compute output quickly.Exactly one of true/complement pulldown networks will complete a path to the power supply. (i.e., requires true/complement inputs, produces true/complement outputs.)Pulldown network will lower output voltage, turning on other p-type, which also turns off p-type for node which is going down.


Lecture 5


DCVS Structure


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Example: DCVSL


Lecture 5








Lecture 5


Dynamic Logic Operation

Uses precharge clock to compute output in two phases:Controlled by clock .Precharge: p-type pullup precharges the storage node; inverter ensures that output goes low.Evaluate: storage node may be pulled down, so output goes up.

Output inverter is needed for two reasons:make sure that outputs start low, go high so that domino output can be connected to another domino gate (monotonic input rising)protects storage node from outside influence.


Lecture 5


Comparison of Three Gates

Dynamic gates uses a clocked pMOS pullupTwo modes: precharge and evaluate

gDYNAMIC=1/3gPSEUDO=8/9gSTATIC=1


Lecture 5


Logical Effort of Dynamic Gates

1

1

AY

2

2

1

B

AY

A B 11

1

gd = 1/3pd = 2/3

gd = 2/3pd = 3/3

gd = 1/3pd = 3/3

Y

2

1

AY

3

3

1

B

AY

A B 22

1

gd = 2/3pd = 3/3

gd = 3/3pd = 4/3

gd = 2/3pd = 5/3

Y

32 2


Lecture 5


Dynamic Effect with Monotonicity

Dynamic gates require monotonically rising inputs (A) during evaluation

0 -> 00 -> 11 -> 1But not 1 -> 0

Gate outputs fall in sequence:

gate 1 gate 2 gate 3


Lecture 5


Monotonicity Woes

But dynamic gates produce monotonically falling outputs during evaluationIllegal for one dynamic gate to drive another!


Lecture 5


Domino Gates (1/2)


Lecture 5


Domino Gates (2/2)

Follow dynamic stage with inverting static gateDynamic / static pair is called domino gateProduces monotonic outputs

A

W

B C

X Y Z

domino AND

dynamicNAND

staticinverter


Lecture 5


Dual-Rail Domino

Domino only performs noninverting functions:AND, OR but not NAND, NOR, or XOR

Dual-rail domino solves this problemTakes true and complementary inputs Produces true and complementary outputs

sig_h sig_l Meaning

0 0 Precharged

0 1 0

1 0 1

1 1 invalid

Y_h

finputs

Y_l

f


Lecture 5


Example: AND/NAND

Given A_h, A_l, B_h, B_lCompute Y_h = A * B, Y_l = ~(A * B)Pulldown networks are conduction complements


Lecture 5


Example: XOR/XNOR

Sometimes possible to share transistors

Y_hY_lA_l

B_h

= A xor B

B_l

A_hA_lA_h= A xnor B


Lecture 5


Leakage

Dynamic node floats high during evaluationTransistors are leaky (IOFF 0)Dynamic value will leak away over timeFormerly miliseconds, now nanoseconds!

Use keeper to hold dynamic nodeMust be weak enough not to fight evaluation

Make Sable state but power still lose


Lecture 5


Charge Sharing

Dynamic gates suffer from charge sharing

x

Y

A

x

Y

Charge sharing noise

Yx Y DD

x Y

CV V VC C

= =+


Lecture 5


Domino Summary

Domino logic is attractive for high-speed circuits1.5 2x faster than static CMOSBut many challenges:

MonotonicityLeakageCharge sharingNoise

Widely used in high-performance microprocessors


Lecture 5


Comparison of Circuit Families


Lecture 5


OutlinesIntroduction: Combinational Logic FunctionsStatic CMOS Circuits


Ratioed CircuitsPseudo-nMOS GatesCascode Voltage Switch Logic




Lecture 5


Switch LogicCan implement Boolean formulas as networks of switches.Can build switches from MOS transistorstransmission gates.Transmission gates do not amplify but have smaller layouts.


Lecture 5


Boolean Functions and Switches

Pseudo-AND Pseudo-OR

b

ab

a

ab + ab

Switch network inputs may be connected to power supply or logic signals.If switch network output is not connected to power supply through switch path, output will float.


Lecture 5


Switch Multiplexer


Lecture 5


Pass Transistor Circuits

Use pass transistors like switches to do logicInputs drive diffusion terminals as well as gatesCMOS + Transmission Gates:

2-input multiplexerGates should be restoring


Lecture 5


Behavior of n-type Switchn-type switch has source-drain voltage drop when conducting:

conducts logic 0 perfectly;introduces threshold drop into logic 1.

Voltage drop causes next stage to be turned on weakly.

VDD VDD - Vt

VDD

VDD VDD - Vt

VDD


Lecture 5


Behavior of Complementary Switch

Complementary switch products full-supply voltages for both logic 0 and logic 1:

n-type transistor conducts logic 0;p-type transistor conducts logic 1.

Has two source/drain areas compared to one for inverter.


Lecture 5


Charge SharingInterior nodes in a switch network may not be driven.Charge can accumulate on small parasitic capacitances.Shared charge can produce erroneous output values.At undriven nodes, charge is divided according to capacitance ratio.


Lecture 5


Example: Charge SharingLong chains of switches have intermediate nodes which may be disconnected from power supplies.

CabCia Cbc


Lecture 5


Charge Over Time

Time i Cia a Cab b Cbc c C0 1 1 1 1 1 1 1 1

1 0 0 1 0 0 1 0 1

2 0 0 0 1/2 1 1/2 0 1

3 0 0 0 1/2 0 3/4 1 3/4

4 0 0 1 0 0 3/4 0 3/4

5 0 0 0 3/8 1 3/8 0 3/4

Make sure that for every input combination, there is a path from the power supply to the output.


Lecture 5


Conclusions

You should learn in depth about the following topics:

Static CMOS CircuitsDynamic CMOS CircuitsTransmission Gates

Combinational Circuit DesignOutlinesUniversal/CompleteLogical Effort FactorOutlinesStatic Complementary GatesPullup/Pulldown Network DesignNAND GateNOR GateCompound GateComplex CMOS GateLogical Effort of Compound GateExample: Delay Calculation (1/3)NAND Solution (2/3)Compound Solution (3/3)Example: Width Calculation (1/2)Example: Width Calculation (2/2)Symmetric GateAsymmetric GatesSkew DefinitionSkewed GatesLogical Effort for Skew GateLogical Effort of Skewed GatesBest P/N RatioP/N RatiosPseudo-nMOSPseudo-nMOS CharacteristicsPseudo-nMOS NAND gateLogical Effort of Pseudo-nMOS GatesPseudo-nMOS DesignPseudo-nMOS PowerDCVS Logic OperationDCVS StructureExample: DCVSLOutlinesDynamic Logic OperationComparison of Three GatesLogical Effort of Dynamic GatesDynamic Effect with MonotonicityMonotonicity WoesDomino Gates (1/2)Domino Gates (2/2)Dual-Rail DominoExample: AND/NANDExample: XOR/XNORLeakageCharge SharingDomino SummaryComparison of Circuit FamiliesOutlinesSwitch LogicBoolean Functions and SwitchesSwitch MultiplexerPass Transistor CircuitsBehavior of n-type SwitchBehavior of Complementary SwitchCharge SharingExample: Charge SharingCharge Over TimeConclusions

combinational circuit design - national chiao tung...

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