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Common-Source Stage 2 Lecture 39 1. Input/Output Impedances of Degenerated Common Source Stage 2. Biasing Technique 3. Self-biased Common Source Stage By 황위나

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Page 1: Common-Source Stage 2 - Yonsei Universitytera.yonsei.ac.kr/class/2015_2_1/lecture/Lesson_31_2_ppt.pdf · Common-Source Stage 2 •Lecture 39 1. ... Self-biased Common Source Stage

Common-Source Stage 2

• Lecture 39

1. Input/Output Impedances of Degenerated Common Source Stage

2. Biasing Technique

3. Self-biased Common Source Stage

• By 황위나

Page 2: Common-Source Stage 2 - Yonsei Universitytera.yonsei.ac.kr/class/2015_2_1/lecture/Lesson_31_2_ppt.pdf · Common-Source Stage 2 •Lecture 39 1. ... Self-biased Common Source Stage

Input/Output Impedances of

Degenerated CS Stage

Rout = RD // (1+gmr0)Rs+r0

Rin = infitiny

At low frequencies

(input current =0)

RD (1+gmr0)

Rs+r0

Vx

Page 3: Common-Source Stage 2 - Yonsei Universitytera.yonsei.ac.kr/class/2015_2_1/lecture/Lesson_31_2_ppt.pdf · Common-Source Stage 2 •Lecture 39 1. ... Self-biased Common Source Stage

Biasing Technique( λ = 0)

1. Gain when there is a input …

Gain = 𝑉𝑥

𝑉𝑖𝑛

𝑉𝑜𝑢𝑡

𝑉𝑥

=R1//R2

(R1//R2 ) +Rinput(-gmRD)

Choose R1//R2 >> Rinput

RD

R1//R2

Rinput

Page 4: Common-Source Stage 2 - Yonsei Universitytera.yonsei.ac.kr/class/2015_2_1/lecture/Lesson_31_2_ppt.pdf · Common-Source Stage 2 •Lecture 39 1. ... Self-biased Common Source Stage

2. To stay SATURATION

VDD – IDRD > Vin – VTh

VDD – Vin + VTh

ID> RD

3. Apply capacitor between two CS stage

To isolate DC current level from each other

4. ID is sensitive to VDD , Temperature , µCox(W/L)

Page 5: Common-Source Stage 2 - Yonsei Universitytera.yonsei.ac.kr/class/2015_2_1/lecture/Lesson_31_2_ppt.pdf · Common-Source Stage 2 •Lecture 39 1. ... Self-biased Common Source Stage

5. Reduce sensitivity with degenerated CS stage

VDD

𝑅2

𝑅1+𝑅2= VGS + IDRS

Self-biased CS stage

VTh increases ID increases

Drain voltage = Gate voltage = VDD – IDRD

Rs

( VDD - IDRD - VTh )2