Microprocessor (COM 9323)

Lecture 3: The Microprocessor and Its Architecture

Ahmed Elnakib, PhD

Assistant Professor, Mansoura University, Egypt

1Feb 24th, 2016

Text Book/References*

Textbook:The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry

B. Brey, Prentice Hall, 2009 (Chapter 02)

References:Wikipedia

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*The presentation is based on the text book and their official presentations

Contents

oIntel Terminology terms Multiple cores

Hyper-threading technology

Turbo-Boost technology

Out of order execution

oInternal Microprocessor Architecture

oHow its memory space is addressed?

Real mode of operation

Protected mode of operation

Flat mode of operation

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Core 2/Multiple Core/Hyper threaded Microprocessor

oThe hyper-threaded processor contains two execution units that eachcontain a complete set of the registers capable of running softwareindependently or concurrently. These two separate machine contextsshare a common bus interface unit

o During machine operation each processor is capable of running a thread(process) independently, increasing the execution speed of an applicationthat is written using multiple threads

oPrograms that do this are called multithreaded applications

oMultithreading is the ability of a central processing unit (CPU) or a singlecore in a multi-core processor to execute multiple processes or threadsconcurrently, appropriately supported by the operating system

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Example

I5 has two cores/4 threads:o Two physical cores, each core can run two threads because of intel's hyper-

threading, making 4 threads, beyond that it switches at high speeds betweenprocesses

o In essence your CPU can run 4 processes simultaneously, and switch at high speedbetween processes

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Intel Turbo Boost Technology (dynamic overclocking)

oIntel Turbo Boost is a technology implemented by Intel in certain versionsof its processors that enables the processor to run above its baseoperating frequency via dynamic control of the processor's clock rate

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Intel Turbo Boost Technology (Example 1)

o For Core i7-920XM, normal operating frequency is 2.0 GHz.

o Turbo is indicated as: 2/2/8/9 in which the first number is the multiple of 133⅓ MHz supported when four cores are active, the second number is the multiple for three cores, the third number is for two cores, and the fourth number is for one active core.

o Subject to limits on temperature, current and power consumption, the processor can increase its clock speed (from a base frequency of 2.0 GHz) in steps of 133⅓ MHz to

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# of cores active # of Turbo Steps Max frequency Calculation

4 or 3 2 2.26 GHz2000 + (2 × 133) = 2000 +

267 = 2267

2 8 3.06 GHz2000 + (8 × 133) = 2000 +

1067 = 3067

1 9 3.20 GHz2000 + (9 × 133) = 2000 +

1200 = 3200

Intel Turbo Boost Technology (Example 2)

o For Core i7-2920XM, normal operating frequency is 2.5 GHz.

o Turbo is indicated as: 7/7/9/10 in which the first number is the multiple of 100 MHz supported when four cores are active, the second number is the multiple for three cores, the third number is for two cores, and the fourth number is for one active core.

o Subject to limits on temperature, current and power consumption, the processor can increase its clock speed (from a base frequency of 2.5 GHz) in steps of 100 MHz to:

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# of cores active # of Turbo Steps Max frequency Calculation

4 or 3 7 3.20 GHz2500 + (7 × 100) = 2500 +

700 = 3200

2 9 3.40 GHz2500 + (9 × 100) = 2500 +

900 = 3400

1 10 3.50 GHz2500 + (10 × 100) = 2500

+ 1000 = 3500

Out of order execution (dynamic execution)

o A processor executes instructions in an order governed by the availability

of input data, rather than by their original order in a program

oIn doing so, the processor can avoid being idle while waiting for the

preceding instruction to complete to retrieve data for the next instruction

in a program, processing instead the next instructions which are able to

run immediately and independently

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Report 02: Due to Feb. 25th , 8.30 AM

o Individually

o Use the internet to make a report on I3, I5, and I7 technology

o Report will be delivered by hand before the lecture

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Contents

oIntel Terminology terms Multiple cores

Hyper-threading technology

Turbo-Boost technology

Out of order execution

oInternal Microprocessor Architecture

oHow its memory space is addressed?

Real mode of operation

Protected mode of operation

Flat mode of operation

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oThe architecture of Intel microprocessors is presented, as are the ways that the family members address the memory system

oAddressing modes for this powerful family of microprocessors are described for the real, protected, and flat modes of operation

Why studying the architecture?

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oBefore a program is written or instruction investigated, internal configuration of the microprocessor must be known.

oIn a multiple core microprocessor each core contains the same programming model

oEach core runs a separate task or thread or two multiple threads simultaneously

Internal Microprocessor Architecture

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Physical Memory Systems of Intel Family

8-bit data bus16-bit data bus

20-bit address bus

25-bit address bus

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Physical Memory Systems of Intel Family (cont’d)32-bit data bus

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Physical Memory Systems of Intel Family (cont’d)

64-bit data bus

o8086 through Core2 considered program visible. registers are used during programming and are specified by the

instructions

oOther registers considered to be program invisible. not addressable directly during applications programming

The Programming Model

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o80286 and above contain program-invisible registers to control and operate protected memory and other features of the microprocessor

o80386 through Core2 microprocessors contain full 32-bit internal architectures.

o8086 through the 80286 are fully upward-compatible to the 80386 through Core2

The Programming Model (cont’d)

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The Intel Programming Model

The programming model of

the 8086 through core 2

microprocessor including the 64-

bit extensions

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The Intel Programming Model (cont’d)

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The Intel Programming Model (cont’d)

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Multipurpose Registers-I

oRAX - a 64-bit register (RAX), a 32-bit register (accumulator) (EAX), a 16-bit register (AX), or as either of two 8-bit registers (AH and AL).

oThe accumulator is used for instructions such as multiplication, division, and some of the adjustment instructions.

oIntel plans to expand the address bus to 52 bits to address 4P (peta) bytes of memory

Multipurpose Registers

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oRBX, addressable as RBX, EBX, BX, BH, BL. BX register (base index) sometimes holds offset address of a location in the memory

system in all versions of the microprocessor

oRCX, as RCX, ECX, CX, CH, or CL. a (count) general-purpose register that also holds the count for various instructions

oRDX, as RDX, EDX, DX, DH, or DL. a (data) general-purpose register

holds a part of the result from a multiplication or part of dividend before a division

Multipurpose Registers (cont’d)

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oRBP, as RBP, EBP, or BP. points to a memory (base pointer) location for memory data transfers

oRDI addressable as RDI, EDI, or DI. often addresses (destination index) string destination data for the string instructions

oRSI used as RSI, ESI, or SI. the (source index) register addresses source string data for the string instructions

like RDI, RSI also functions as a general-purpose register

Multipurpose Registers (cont’d)

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Multipurpose Registers-II

oR8 - R15 found in the Pentium 4 and Core2 if 64-bit extensions are enabled. data are addressed as 64-, 32-, 16-, or 8-bit sizes and are of general purpose

oMost applications will not use these registers until 64-bit processors are common. the 8-bit portion is the rightmost 8-bit only bits 8 to 15 are not directly addressable

as a byte

Multipurpose Registers (R8-R15)

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oInclude RIP, RSP, and RFLAGS segment registers include CS, DS, ES, SS, FS, and GS

oRIP addresses the next instruction in a section of memory. defined as (instruction pointer) a code segment

oRSP addresses an area of memory called the stack. the (stack pointer) stores data through this pointer

Special-Purpose Registers

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oRFLAGS indicate the condition of the microprocessor and control its operation.

oFlags are upward-compatible from the 8086/8088 through Core2 .

Flags

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oThe rightmost five and the overflow flag are changed by most arithmetic and logic operations. although data transfers do not affect them

Flags (cont’d)

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oFlags never change for any data transfer or program control operation

oSome of the flags are also used to control features found in the microprocessor

Flags (cont’d)

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oC (carry) holds the carry after addition or borrow after subtraction. also indicates error conditions

oP (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity; logic 1 for even parity. if a number contains three binary one bits, it has odd parity

if a number contains no one bits, it has even parity

Flags (cont’d)

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oCA (auxiliary carry) holds the carry (half-carry) after addition or the borrow after subtraction between bit positions 3 and 4 of the result.

oZ (zero) shows that the result of an arithmetic or logic operation is zero.

oS (sign) flag holds the arithmetic sign of the result after an arithmetic or logic instruction executes.

Flags (cont’d)

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oT (trap) The trap flag enables trapping through an on-chip debugging feature

oI (interrupt) controls operation of the INTR (interrupt request) input pin.

oD (direction) selects increment or decrement mode for the DI and/or SI registers.

Flags (cont’d)

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oO (overflow) occurs when signed numbers are added or subtracted. an overflow indicates the result has exceeded the capacity of the machine

oIOPL used in protected mode operation to select the privilege level for I/O devices.

oNT (nested task) flag indicates the current task is nested within another task in protected mode operation.

Flags (cont’d)

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oRF (resume) used with debugging to control resumption of execution after the next instruction.

oVM (virtual mode) flag bit selects virtual mode operation in a protected mode system.

oAC, (alignment check) flag bit activates if a word or doubleword isaddressed on a non-word or non-doubleword boundary.

Flags (cont’d)

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oVIF is a copy of the interrupt flag bit available to the Pentium 4–(virtual interrupt)

oVIP (virtual) provides information about a virtual mode interrupt for (interrupt pending) Pentium. used in multitasking environments to provide virtual interrupt flags.

Flags (cont’d)

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oID (identification) flag indicates that the Pentium microprocessors support the CPUID instruction. CPUID instruction provides the system with information about the Pentium

microprocessor

Flags (cont’d)

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oGenerate memory addresses when combined with other registers in the microprocessor.

oFour or six segment registers in various versions of the microprocessor.

oA segment register functions differently in real mode than in protected mode.

Segment Registers

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oCS (code) segment holds code (programs and procedures) used by the microprocessor.

oDS (data) contains most data used by a program. Data are accessed by an offset address or contents of other registers that hold the

offset address

oES (extra) an additional data segment used by some instructions to hold destination data

Segment Registers (cont’d)

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oSS (stack) defines the area of memory used for the stack. stack entry point is determined by the stack segment and stack pointer registers

the BP register also addresses data within the stack segment

Segment Registers (cont’d)

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oFS and GS segments are supplemental segment registers available in 80386–Core2 microprocessors. allow two additional memory segments for access by programs

oWindows uses these segments for internal operations, but no definition of their usage is available.

Segment Registers (cont’d)

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Questions

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