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COMP 541, Lab 1 Anselmo Lastra (original 2002, revised 1/2009) This lab consists of 2 parts:

- Part 1 is the introductory tutorial.

- Part 2 is your assignment. It’s meant to reinforce the tutorial.

CAUTION: Careful of static electricity.

Please ground yourself before touching board!

Part 1. Tutorial You are going to create a 3 input combinational circuit. You will implement the following function: D= AB +C The procedure will be to

• Create a new project • Add a Verilog file • Simulate the circuit • Assign the A, B, C, and D inputs and outputs to chip pins. • Download your design to the board • Test the result

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Creating a Project Start by double clicking on the Project Navigator icon (on the desktop or under Xilinx in the Start Menu). This is what you will see. (Note: depending on the previous state of ISE, you may see a project open. If so, go to the File menu and select Close Project)

To create new project, select File -> New Project, which will bring up following window.

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Choose a project name. This will also become a subdirectory of the location you choose next. Perhaps name it Tutorial_1. Project Location: click on … to browse and change the folder to some convenient place. Make sure there are spaces in the name and the path! This has caused a problem in the past. I suggest making a folder in D: with your name because the C drive is small on most of the lab machines. Choose HDL. (Hardware Description Languages).

Click Next.

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Project Device Options should be as follows:

Family: Spartan3E Device: xc3s1200-4fg320 Simulator: ISE Simulator

How do you know this stuff? It’s printed on the FPGA chip. Click Next.

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We’ll add a file later, so just click Next.

Click Next. You’ll see a summary of what you’ve selected.

Click Finish.

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Creating a new Verilog File After you are done with this, back in Project Navigator you should have,

Now, either

(a) highlight xc3s1200e-4fg320 in the Sources window and double click on Create New Source in the Processes window, or

(b) right-click xc3s1200e-4fg320 and select New Source. You’ll find that both of these modes of interaction are available for most actions.

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You will see the following window.

On the left panel, select Verilog Module and in the file name box, type lab1_part1 (no spaces!). Click next. You could add the input and output ports in this next window, but it’s easier to just type the information into the text file. Click next. Click finish.

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Click on the lab1_part1.v tab of the main window.

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Entering the Verilog. The editor will open and show you a template for a Verilog file like this.

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:51:58 01/17/2009 // Design Name: // Module Name: lab1_part1 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module lab1_part1( ); endmodule

Type your source code in, beginning with inputs and outputs in the declaration. For example,

module lab1_part1(input A, B, C, output D ); assign D = A & B | ~C; endmodule

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Simple Simulation In order to simulate, we need to specify a set of test vectors. These are inputs to the circuit under test. We can specify these in multiple ways. Today we’ll try the visual test waveform editor. In a future lab, we will also write simulation code in Verilog. Go back to the Sources tab in the Sources window. You can select Tutorial_1 and double click Create New Source or right click Tutorial_1 and select New Source… In the dialog box, select Test Bench Waveform and name it lab1_tbw.

Click next. Make sure it’s associated with the Verilog source file (should be no problem since it’s the only design in the project at the moment). Click Next and Finish. You may get a warning (below). If so, ignore it.

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The clock timing dialog box will pop up.

Select Combinatorial on the upper right panel and click Finish. Now you’ll see a waveform window.

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We can click on the blue boxes to toggle the binary values. Enter a set of values to test every possible combination. In the example below, I’ve used A as the low order of an input sequence from 0 to 7.

Save the test bench waveform.

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You need to change the Sources in order to see the simulation commands. Select the Sources tab in the Sources window and on the pull-down (below) select Behavioral Simulation. You’ll see the tbw file and the UUT (unit under test), the Verilog file. Select the TBW.

On the processes tab (lower) you’ll see the simulation options. Open Xilinx ISE Simulator with the plus symbol, and you’ll see Simulate Behavioral Model. Double click the Simulate Behavioral Model item (or right click and select run).

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You’ll see a window like this.

Note that you may not see the full simulation. For example, in the window above, the lower 200 ns is not visible. You can just slide the blue pointer to the left to see it, or right clock and select zoom full view. Note that the binary values listed in the second column correspond to the time shown by the blue pointer. There are some zooming tools that you may choose by right-clicking on the black window, or by clicking on the icons in the toolbar. *** Is this what you expect for D= AB +C ? If not, go back and debug (or read the next couple of pages for more instructions on looking at the internal state).

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Digging Deeper How about if there’s a problem and we want to see the values of some internal nodes in the simulation? For example, suppose we typed assign D = A & B + ~C; In other words, we used a + (addition in Verilog) symbol instead of a vertical bar (OR). We’d see the following waveforms.

We can’t figure out what’s going on, so we decide we want to examine the two parts of the Boolean expression separately.

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First, rewrite the Verilog to assign the intermediate signals to named wires as follows.

module lab1_part1(input A, B, C, output D ); wire P, Q; assign P = A & B; assign Q = ~C; assign D = P + Q; // Did this wrong for debugging endmodule

Close the simulation window to stop the simulation. Go back and rerun the simulation. The diagram will look the same. On the sources window, click on lab1_part1. You’ll see the signals associated with that module, including the internal signals P and Q. Click and drag P and Q to the waveform window.

Now that you’ve seen how to run a basic simulation, let’s move on to the steps necessary to try your design on the actual hardware.

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Running on the FPGA So far we’ve been working only on the logical design. Next we’d like to test on actual hardware. To do this we need to add more information about the chip’s pins to which the peripherals (in our case just one LED and three switches) that we plan to use are connected. To determine the names of the pins, we need to go to the documentation of the board, which is located at https://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdf (you may want to download a local copy to make it easy to reference next time)

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The switches and LEDs are arrayed along the bottom of the board.

We’ll use SW0, SW1, SW2, and LD0, which are the rightmost ones of each set. Have a look at page 5 to see the Figure 8, a schematic diagram duplicated below.

As you can see, SW0 is connected to pin G18, which will be L when SW0 is OFF, and H when it is on. Similarly, LD0 will be lit when pin J14 is H. The pin assignments are also printed on the board.

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Assigning Package Pins OK, so we should assign pins as follows.

Signal In/Out Device Pin A Input SW0 G18 B Input SW1 H18 C Input SW2 K18 D Output LD0 J14

NOTE: Please be careful when assigning pins. Double check your work. It’s possible to damage a device (such as the FPGA or one of the memories on the board) by assigning an FPGA output to a device output. Now, go back to the Project Navigator. Change the mode on the Sources window from Behavioral Simulation to Implementation. Right click to add a source and choose Implementation Constraints File. The constraints in this case will be the I/O pins. Give the file a name.

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Now, select the lab1_part1.v (Verilog file) and expand the User Constraints process in the Processes window (see below). Choose Floorplan Area / IO / Logic – Post Synthesis and run it (right click and select run or double click).

You’ll get this warning window. Click OK (ignore it).

A new window will pop up, the Xilinx PACE tool.

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The sub-window of interest is the one on the lower left. You can drag the border to make it wider. Click on LOC for input A and enter the pin number, G18 (ignore the pull down menu – enter the pin designation). The result is shown below.

Now enter the other pin assignments to get the result shown below.

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Save the pin assignments entered into the PACE tool (you can close that window if you like). The PACE tool just manipulates a text file, so another way to enter pin assignments is to edit the text file directly using the Edit Constraints (text) command.

#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "A" LOC = "G18” ; NET "B" LOC = "H18"; NET "C" LOC = "K18"; NET "D" LOC = "J14"; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE

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Creating the Programming File In this step we’ll create a file that’s downloaded to the FPGA. Go back to Project Navigator and select the Verilog file in the Sources window. Then right-click Generate Programming File in the Processes tab. Select Properties… Choose the Startup Options tab and choose JTAG Clock for the FPGA Start-Up Clock property. Click OK.

In the Processes window double-click Generate Programming File (or right-click and select Run). You should see green checkmarks (below).

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If you see any yellow questions marks, there’s a problem that’s detailed in the Console window. You may need to figure it out and fix the problem. This step generates a file with a .bit extension that contains the programming codes for the FPGA chip. In this case it’ll be lab1_part1.bit. In the next step we’ll download that file to the FPGA.

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Downloading to the Board Connect the NEXYS2 board to the USB port and power it on. The ON/OFF switch is on the upper left of the board. You’ll use the Adept tool from Digilent to download the configuration file. Start it from the Start menu by going to Digilent\Adept\ExPort. The following window will pop up.

Click Initialize Chain. You’ll now see two devices, the FPGA and the ROM (read only memory). We’ll be using the FPGA, of course.

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Click on the Browse button by the FPGA, and navigate to the file that you just generated.

Select it and click Program Chain. You should get a message as shown below.

Your design should now be on the board.

Testing Flip the switches and see how the output changes. Is the output what you expect it to be? *** Show your implementation to the TA. ***

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PART 2, Design a Hex Decoder. You will design a Hex-to-Seven-Segment decoder. There is a good explanation of a similar decoder in your book, Exercise 2.10 on page 75. The only difference between the decoder in your book and the one you are going to design is that you are not stopping at 9 as an output value, but rather at hexadecimal F. You will be able to use this decoder to debug circuits you design later. I’ll ask you to write the truth table and think about this project as homework before lab. We suggest that you test this using simulation. Use switches 0 through 3 for your hex input, and any one of the 4 seven-segment displays. To use the display, you’ll need to drive the anode low. For example, to use the rightmost display (the documentation shows AN0 as left, but that’s not what I found), make F17 LOW and the rest (H17, C18, F15) H. Similarly, the cathodes must be held at ground to light the segment. So, for example, to display a one, drive CB and CC low, and the rest of the cathodes high.

Show the working circuit to the TA, Mr. Haohan Li.. Send the truth table and Verilog to the TA by email (lihaohan@cs.unc.edu). Lab reports are due by Tuesday 2:00 PM. Things you (hopefully) learned:

- How to create a Verilog file. - Basic simulation. - How to assign package pins. - How to download the design to the board.