Compact Modeling of Thin Film Transistors for Flexible Hybrid IoT Design

Leilai Shao†, Ting Lei†, Tsung-Ching Huang†, Sicheng Li, Ta-ya Chu, Man Wong,Raymond Beausoleil, Zhenan Bao, and Kwang-Ting Cheng

Abstract—Flexible Electronics (FE) is emerging for low-cost,light-weight wearable electronics, artificial skins and IoT nodes,benefiting from its low-cost fabrication and mechanical flexibility.Combining FE with thinned silicon chips, known as flexiblehybrid electronics (FHE), can take advantages of both low-cost printed electronics and high performance silicon chips,which brings together flexible form factors and IoT innovations.Thin film transistors (TFTs), as a critical component for FHEapplications, have achieved tremendous improvements in chargecarrier mobility, device stability and scalability; however, an ac-curate compact model for TFTs which can capture fundamentalbehaviors of TFTs and be broadly applicable to multiple flexibletechnologies is still missing for circuit and system design. Such amodel is crucial for designing flexible hybrid IoT (Flex-IoT) inorder to enable design explorations and technology evaluations.In this paper, we present a SPICE-compatible unified compactmodel covering DC, AC and technology scaling of TFTs forFlex-IoT designs. We validated the presented model for threedifferent types of TFT technologies and performed circuits-levelinvestigations based on fabricated Pseudo-CMOS circuits. Wedemonstrate that the presented TFT model can provide accurateand trustworthy predictions for circuit evaluation and Flex-IoTsystem design.

Index Terms—Flexible hybrid electronics, Flex-IoT, thin-filmtransistors, compact model, Pseudo-CMOS, design automation.

I. INTRODUCTION

Flexible electronics is emerging as an alternative to con-ventional silicon electronics for applications such as wearablesensors, artificial skin, medical patches, bendable displays,foldable solar cells and disposable RFID tags [1][2]. Un-like conventional silicon electronics that needs sophisticatedbillion-dollar foundry for manufacturing, flexible electroniccircuits can be fabricated on thin and conformable substratessuch as plastic films, with low-cost high-throughput man-ufacturing methods such as ink-jet printing and roll-to-rollimprinting. The time-to-market as well as manufacturing costcan therefore be significantly reduced. Its flexible form factoralso enables innovative designs for consumer electronics andbiomedical applications [3][4].

However, circuit using pure flexible electronics suffersfrom slower operating speed and less reliability comparingto complementary-metal-oxide-semiconductor (CMOS) tech-nology. For sensing applications, such as touch, temperature,sweat and bio-medical sensors [2], speed requirement is notcritical and TFT technologies can operate at ∼Mhz range

†These authors contribute equally in this work. L. Shao, is with theDepartment of Electrical and Computer Engineering, University of CaliforniaSanta Barbara, CA, 93106, USA. E-mail: lshao@ece.ucsb.edu. L. Ting andZ. Bao are with Department of Chemical Engineering, Stanford University,Stanford, California 94305, USA. T-C. Huang, S. Li and R. Beausoleil arewith Hewlett Packard Enterprise, Palo Alto, California 94305, USA. T-Y.Chu is with Advanced Electronics and Photonics Research Centre, NationalResearch Council Canada, Ottawa, Canada. K-T. Cheng and M. Wong arewith Hong Kong University of Science and Technology, Hong Kong, China.The developed compact model is available at: https://github.com/llshao/CNT-TFT-Verilog-A

Manuscript received June 15, 2018; revised October 26, 2018.

Fig. 1: A conceptual flexible hybrid IoT node.

to support such applications. Printing or solution compatibleprocesses make the integration between TFTs and sensorsmuch easier and TFT itself also can be used for sensing[5]. Through heterogeneous integration of flexible devicesand thinned silicon chips, we can bring low-cost sensing andhigh performance computing to various connected ”things” forwearables and Flex-IoT sensing nodes. A conceptual Flex-IoT sensing node is illustrated in Fig. 1, where TFTs, sensorsand thinned silicon chips are integrated on the same flexiblesubstrate.

There exist several challenges before Flex-IoT can bebroadly employed for next-generation wearable and IoT prod-ucts. Due to material properties, TFTs are usually mono-type,either only p- or only n-type, devices [6]. Making air-stablecomplementary TFT circuits is quite challenging or oftenrequires heterogeneous process integration of two differentTFT technologies. Existing CMOS design methodologies forsilicon electronics, therefore, cannot be directly applied fordesigning flexible electronics. Other factors such as high sup-ply voltages and large process variations also make designinglarge-scale TFT circuits a significant challenge. To ease designchallenges and perform technology evaluations, a trustworthyTFT compact model is needed to facilitate simulations anddesign explorations.

Several TFT compact models targeting specific technologies[7] have been developed in the past, which may not begeneralized for other technologies. Some studies focus only onmodeling the DC behavior [8], which doesn’t support transientsimulations. In this paper, we present a unified compact modelof TFTs covering DC, AC and technology scaling factorfor supporting Flex-IoT design, and validate the model forthree TFT technologies: carbon nanotube (CNT) TFTs, indiumgallium zinc oxide (IGZO) TFTs and organic TFTs. Based onthis model, we further perform circuit level validation basedon fabricated Pseudo-CMOS inverters, sequence generatorsand ring-oscillators. The proposed model is implemented inVerilog-A which is compatible with SPICE simulation of

CMOS circuitry, thus enables designers to explore TFT basedflexible hybrid circuits and evaluate their potentials. The restof this paper is organized as follows: Section II providesobservations and model derivations for TFTs; Section IIIdemonstrates model validations against transistors and circuitmeasurements; Section IV investigates the technology scalingeffect; Section V draws the conclusion.

II. UNIFIED TFT MODEL

-2 -1 0 1

Vg(V)10-10

10-8

10-6

10-4VD=-0.5V

-2 -1 0 1

Vg(V)0

10

20

30VD=-0.5V

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)10-9

10-8

10-7

10-6

10-5

10-4

I S (A

)

Measured I-V Curve VD=-0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)0

1

2

3

Gm

(S)

10-5

TransconductanceVD=-0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)0

10

20

30

(cm

2/V

s) Mobility=25.7cm2/VsVD=-0.5

(a)

Linear Region

Contact Effect

|𝑽𝑮𝑺 −𝑽𝒕𝒉| = 𝟏

Mobility Enhancement

CNT-TFT Measured I-V

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)10-9

10-8

10-7

10-6

10-5

10-4

I S (A)

Measured I-V Curve VD=-0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)0

1

2

3

Gm (S

)

10-5

TransconductanceVD=-0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)0

10

20

30

(cm

2 /Vs) Mobility=25.7cm2/Vs

VD=-0.5

-5 0 5 10 15

Vg(V)10-14

10-12

10-10

10-8

10-6VD=0.1V

-5 0 5 10 15Vg(V)0

5

10

15VD=0.1V

(b)

Mobility Enhancement

IGZO-TFT Measured I-V

Linear Region-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)10-9

10-8

10-7

10-6

10-5

10-4

I S (A)

Measured I-V Curve VD=-0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)0

1

2

3

Gm

(S)

10-5

TransconductanceVD=-0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)0

10

20

30

(cm

2 /Vs) Mobility=25.7cm2/Vs

VD=-0.5

Fig. 2: Measured I-V curves and mobility dependency on gatevoltages: (a) CNT-TFT with L = 25µm and W = 125µm; (b)IGZO-TFT L = 20µm and W = 30µm.

A. Observations and Motivations

To investigate the effective mobility of fabricated TFTs, lowsource drain voltages (VDS = −0.5V and VDS = 0.1V )are chosen for CNT-TFT and IGZO-TFT accordingly. Themeasured I-V curves are shown in the top part of Fig. 2 andthe bottom part shows the effective mobility µeff . From Fig.2, we observed that the effective mobility µeff is enhancedas the |VGS | increases for both CNT-TFT and IGZO-TFT,when |VGS | is relative small. Similar mobility dependencyphenomenon has been observed in OTFT and a-Si TFT [7],and the commonly accepted theories are based on charge driftin the presence of tail-distributed traps (TDTs) and variablerange hopping (VRH) [7]. This common phenomenon amongdifferent TFT technologies encourages us to build a unifiedmodel to capture fundamental behaviors of different TFTsbased on TDTs and VRH assumptions.

B. Assumptions and Analysis

1) Mobility Enhancement: Both theories indicate the fieldenhancement of the mobility :

µ =

µ0(VG − Vth)γ , N-type TFTµ0(Vth − VG)γ , P-type TFT

(1)

, where Vth is the threshold voltage, γ is the field enhancementfactor for mobility and µ0 is defined as the effective mobilitywhen |VG−Vth| = 1, as illustrated in Fig. 2(a). This mobilityenhancement assumption explains the increase of the effectivemobility at a low |VGS |.

Fig. 3: TFT intrinsic model with contact resistances.

2) Contact Effect: The degeneration of mobility at high|VGS | can be explained partially by the contact resistancesRS and RD at source/drain terminals, as shown in Fig. 3.These resistances result in effective gate-source/drain-sourcevoltage drops: VGS = VGS − RS IDS , VDS = VDS − (RS +RD)IDS = VDS − RC IDS , where RC = RS + RD and thecurrent with contact effect is denoted as IDS . The derivationsare not presented here for simplicity and the contact effect canbe illustrated as follows:

IDS ≈WCoxµ

L1 + kRC(VGS − Vth)(VGS − Vth)−

1

2VDSVDS

(2)

IDSIDS

≈ µ

µ=

1

1 + kRC(VGS − Vth); k =

W

LCoxµ (3)

From Eq. (3), we can conclude that contact resistances lead tomobility reduction with a factor of 1/(1 + kRC(VGS − Vth))and it becomes more significant as |VGS | increases, whichexplains the degeneration of the effective mobility with a high|VGS | as shown in Fig. 2(a). For devices shown in Fig. 2, CNT-TFT has relative larger k comparing to IGZO-TFT kCNT ≈25kIGZO, thus leading to more obvious mobility degeneration.

3) Surface Roughness Effect: As gate voltage increases,electrons tend to flow closer the channel surface. Due tothe low-cost fabrication process of TFTs, interface traps andsurface roughness exist commonly leading to degeneration ofthe effective mobility [9]:

µ

µ=

1

1 + θ(VGS − Vth); (4)

Here, θ ∝ 1/tox is a parameter related to the thickness of thegate oxide layer. This phenomenon combining with contacteffect will lead to an overall mobility drop with a factor of ≈1/(1 + (θ + kRC)(VGS − Vth)). Although, surface roughnessand contact effect have identical formula with a term proposalto VGS − Vth, their physical explanations are different.

C. Model Derivations

We first establish the intrinsic current model based on themobility enhancement assumption, then extend the model tocapture parasitics and second order effects.

1) Intrinsic Current Model: We integrate the mobility en-hancement assumption Eq. (7) with the n type charge driftmodel of Eqs. (5)-(6) to derive the intrinsic current model [7]:

IDS(x) = QCH(x)v; v = ueff∂V (x)

∂x(5)

QCH(x) =WCox(VG − Vth − V (x)) (6)ueff = µ0(VG − Vth − V (x))γ (7)

Since the current is constant in the channel [9], integratingalong the channel

∫ x=Lx=0

IDS(x)dx yields:

IDS =k

(γ + 2)(VGS − Vth)γ+2 − (VGD − Vth)γ+2 (8)

where k is defined as WCoxµ0

L . Similar to metal-oxide-field-effect-transistor (MOSFET), we divide Eq. (8) into two re-gions: 1) linear region, and 2) saturation region. Applying theTaylor expansion and keep the first and second order terms,we can then simplify the formula as:

IDS ≈

k′VGT − 1+γ

2VDSVDS , VDS ≤ VGT

k′

(γ+2)V 2GT , VDS > VGT

(9)

k′ = kV γGT ; VGT = VGS − Vth (10)

Notice that Eq. (9) becomes a conventional MOSFET modelwhen γ = 0. This is because the main difference between theTFT intrinsic model, Eq. (8) and the MOSFET model is themobility enhancement dependency on the gate voltage. Thisinherent connection between Eq. (8) and the MOSFET modelleads to a major advantage: we can readily include second-order effects, such as channel length modulation, into Eq. (8)taking advantage of mature MOSFET theories.

2) Extending the Intrinsic Model: To further enrich thecapability of the TFT intrinsic model, we incorporate thechannel length modulation 1 + λVSD and surface roughnesseffect into Eq. (8) and the limiting function flim(VG, V ) isadded to provide smooth transitions between the sub-threholdregion and the above-threshold region [9] :

IDS =k′β

γ + 2(f(VG, VS)

γ+2 − f(VG, VD)γ+2)(1 + λVDS) (11)

flim(VG, V ) = SS ln[1 + exp(VG − Vth − V

SS)];β =

1

1 + θVGT(12)

where λ is the channel length modulation factor and SS isrelated to the sub-threshold slope.

3) Extrinsic Contact Resistance : Two series resistancesRS and RD are added to account for the contact effect asshown in Fig. 3. To accurately extract the contact resistance,we apply transmission line method (TLM) to ∼500 fabricatedCNT based devices, as shown in Fig. 4. The total resistanceRtotal of the two terminal test structure is composed of contactresistance Rc = Rcs +Rcd and channel resistance Rch. Here,Rch is the sheet resistance of the channel and Rc = Rcd+Rcsis the unit width contact resistance.

Rtotal =RcW

+RchL

W(13)

Eq. (13) indicates that the Rtotal is a linear function of L if Wis kept as a constant. Fig. 4 contains two critical parameters:1) unit width contact resistance (Rc/W = 4.78KΩ) can beextracted from the intersection when L = 0; 2) the minimumwidth (Wmin ≈ 2µm) required for source/drain terminalcan be extracted from the intersection when Rtoal = 0.The extracted contact resistance will be used in our modeland Wmin for source/drain terminal will guide the devicefabrications.

𝑅"# 𝑅"$𝑅"%

0 20 40 60 80 100Channel Length m

0

50

100

150

200

250

300

350

Res

tota

l K

Restotal K v.s. Channel Lenght

Restoal = 2.46*L + 4.78

Fig. 4: Contact resistance TLM extrapolation based on ∼ 500fabricated devices with L = 10, 20, 50, 100 µm and W = 40 µm.

4) Gate Capacitance: Two lumped capacitors CGS andCGD are added to characterize the transient behavior of theTFT circuits. Due to the large device sizes (hundreds of µmscale), two lumped capacitors are sufficient accurate to capturethe transient responses of TFT circuits. Gate source/drainparasitic capacitors CGSO and CGDO are also included toimprove the accuracy.

CGS = CGCS + CGSO; CGD = CGCD + CGDO; (14)CGSO = CGDO = CoxWLov; (15)

CGCS =∂QCH∂VGS

=2CoxWL

3[1− (

VGT − VDSe2VGT − VDSe

)2] (16)

CGCD =∂QCH∂VGD

=2CoxWL

3[1− (

VGT2VGT − VDSe

)2] (17)

VDSe =1

2[VDS + VGT −

√V 2δ + (VDS − VGT )2] (18)

where Lov is the gate source/drain overlap and Vδ is a smallnumber (∼ 10mV ) to improve convergence. CGCS and CGCDare adapted from the Meyer capacitance model and typical gatevoltage dependent behaviors are shown in Fig. 7(a). The finalequivalent circuit model is shown in Fig. 3 and all equationscan be implemented in Verilog-A for SPICE simulations.

III. MODEL VALIDATIONS

In this section, we compare the SPICE simulation resultswith measured drain-source current versus gate voltages (I-V) curves from CNT-TFT, IGZO-TFT and OTFT. And circuitlevel validations are performed with fabricated Pseudo-CMOSinverters and ring-oscillators [1].

A. Device Validation

We first examined the unified TFT compact model withthree measured I-V curves from CNT, IGZO and OrganicTFTs. It can be seen that the model is able to accurately predictthe dc behaviors of different TFTs, which well demonstratethe broad applicability of the unified compact model. Theexcellent match between model predictions and measurementdata further confirm the validity of the above-mentioned modelderivations and assumptions. We extracted model parametersfor three types of TFTs listed in Table I. For CNT-TFTs,52 devices’ statistical information are also included and aGaussian distribution is assumed for process variations, wherethe mean value µ and standard deviation σ are shown.

Field effect mobility extracted based on an idealized MOS-FET current model has been widely used for TFT performance

Fig. 5: Validations of the unified TFT model with measured I-V curves: (a) CNT-TFT with W = 125µm and L = 25µm [10]; (b) OTFTwith W = 5000µm and L = 10µm [11]; (c) IGZO TFT with W = 30µm and L = 20µm [12].

TABLE I: Extracted parameters for CNT, IGZO and Organic TFTs

Notation (Unit) CNT-TFT [µ, σ] IGZO-TFT [µ] OTFT [µ]L (um) [25, -] 20 10W (um) [125, -] 30 5000Lov (um) [10, -] 10 20Cox (nF/cm2) [200, -] 70 15Vth (V ) [0.5, 0.102] 1.9 -4.2SS (V/dec) [0.28, 0.0388] 0.8 0.6µ0 (cm2/V s) [25.69, 0.19] 1.6 0.02RC (Ω) [1531, 291] 2500 80000λ (V −1) [0.064, 0.0185] 0.002 0.028γ (-) [0.20, 0.116] 0.3 0.5θ (V −1) [0.01, 0.002] 0.005 0.002

benchmarking. With the field-dependent properties, the ex-tracted mobility could vary significantly at different effectivegate voltage bias. Therefore, to fair evaluate the performanceof a TFT, combination of the low field effect mobility (µ0) andfield-dependent factor (γ) should be used to fairly evaluatethe mobility performance. Thus, the unified compact modelenables accurate simulation and also serves as a benchmarkfor technology evaluations.

B. Circuits Validation

Beside single devices, the model must be able to predictthe circuit level behaviors with high accuracy. We thereforecompare the SPICE simulation results with the measuredvoltage transfer curves (VTC), rising/falling times and ring-oscillator’s waveform.

1) Introduction to Pseudo-CMOS: Pseudo-CMOS is a de-sign style proposed to address challenges of TFT circuit design

based on mono-type devices [1], which has been proven arobust design style for flexible digital, analog, and powercircuits. Compared to conventional mono-type digital designstyles, such as the diode-load or resistive-load designs, Pseudo-CMOS offers better noise margin and provides post-fabricationtunability at the cost of an additional power rail VSS . Thereare two topologies of Pseudo-CMOS: depletion (Pseudo-D)type and enhancement (Pseudo-E) type. Both Pseudo-D andPseudo-E inverter’s schematics are shown in Fig. 6(a) and (b),which consists of three power rails, VDD, VSS and GND, andfour transistors M1−4.

2) VTC Validation: In Fig. 6(c), we compare the SPICE-simulated voltage transfer curves (VTCs) with actual measure-ment data, where solid lines are SPICE simulations and dotsare measurements. Simulated VTCs match closely with thecircuit measurements over a wide range of supply voltagesVDD, from 0.8V to 1.6V. Despite minor discrepancies inlow supply voltages, the proposed model accurately predictsthe DC behaviors of a Pseudo-D inverter. In Fig. 6(d), 26pseudo-D inverter’s VTCs are plotted together and the SPICEsimulations (bold lines) can accurately predict the averagebehaviors of the VTCs using the mean values in Table I.

3) Dynamic Validation: We validated our AC model us-ing the Pseudo-CMOS inverter’s rising/falling times, ring-oscillator’s measured waveforms and sequence generator’sdynamic behaviors. As shown in Fig. 7(b), with the developedDC model and capacitance model, the transient simulationresult well captures the oscillation frequency and the amplitudecompared with the measurement data. To analyze the wafer

Fig. 6: (a) Schematic of a Pseudo-D inverter; (b) Schematic of a Pseudo-E inverter; (c) Dot lines: Measured VTCs for a CNT-TFT basedPseudo-D inverter with VDD=1.6V, 1.2V, 1V, 0.8V; solid lines: model predictions; (d) Dot lines: 26 measured VTCs of CNT-TFT basedPseudo-D inverter with VDD=1.6V, 1.2V, 1V, 0.8V; solid lines: model predictions with extracted parameters in Table I.; (e) 50 Monte Carlosimulations of Pseudo-E inverters’ rising time; (f) 10 measured Pseudo-E inverters’ rising time;(g) 50 Monte Carlo simulations of Pseudo-Einverters’ falling time; (h) 10 measured Pseudo-E inverters’ falling time;

level variations, we first conducted a cased study on thePseudo-E inverter’s dynamic behaviors after taking variationsinto considerations. Monte Carlo simulations were performedwith standard variation summarized in Table I of CNT-TFTs.As shown in Fig. 6(e)-(h), our model can indeed capturethe dynamic behaviors and variations of Pseudo-E inverters,as evident by good match to results of fabricated CNT-TFTbased devices. Also, we designed and tested 34 five-stage ringoscillators in a 4-inch wafer with their statistics summarizedin Fig. 7(c). 500 Monte Carlo simulations are performed withthe developed model and statistical simulation results showless than 10% errors comparing to physical measurements asindicated in Fig. 7(c)-(d). These errors are mainly caused bydevice and interconnect parasitics, which will be discussed inthe next section and could be a very important future work.Furthermore, we designed, fabricated and tested a linear feed-back shift register (LFSR) based sequence generator, whichcan be applied in signature generation, cryptography and test-patter generation, as shown in Fig. 7(e)-(f). The sequencegenerator contains more than 100 CNT-TFTs and our model isable to accurately predict the outcome of such a medium scalecircuit, as indicated in Fig. 7(g), which further demonstratesour model’s capability to predict relative complex circuitry’sbehaviors.

For large scale circuits design, model’s stability and scala-bility are crucial. We examined these aspects of our modelwith Hspice and Spectre simulators using ring oscillatorsas a test-bench. Simulation results from two simulators areconsistent with each other. Transient waveform, frequency andrunning time of ring oscillators from 5 stages to 101 stagesare summarized in Fig. 7(h)-(i). All ring oscillators show fastconvergence and the running time shows a linear relationshipwith the circuit complexity, which indicates the good stabilityand scalability of the developed compact model.

At the device level, validations have been conducted forthree different TFT technologies. At the circuit level, we com-pared the model predictions with fabricated Pseudo-CMOScircuits. In summary, the good match between model andmeasurements of both DC and transient simulations indicatethat the developed unified TFT model can accurately predictboth device and circuit level behaviors.

IV. TECHNOLOGY SCALING

In this section, we further investigate the channel lengthscaling effect.

First, we compared the model predictions of a Pseudo-D inverter with measurements of 6 fabricated circuits withchannel length of 3µm. As shown in Fig. 8(a), the comparisonbetween the DC simulation and the circuit measurementsfor Pseudo-D inverters shows a good correlation for channellength down to 3µm. For AC behaviors, a 5-stage Pseudo-E based ring-oscillator is used as a vehicle for investigatingthe scaling effect. Both model predictions and measurementsof ring-oscillator’s frequency are shown in Fig. 8(b). Bothsimulations and measurements show that frequency does notincrease quadratically as channel length decreases. This isbecause the non-negligible device parasitics, such as contactresistance and parasitic gate capacitance. Another observationis that as channel length decreases, the deviation of modelpredictions from the measurements grows. This phenomenonis due to non-trivial interconnect parasitics. For instance, aprinted wire’s sheet resistance could be as large as ∼ 1Ω/.Also, typical TFT process only has 2-3 metal layers, whichinevitably will increase the overlap between layers causingsignificant parasitic capacitance. Thus, for high performanceTFT circuit design, accurate interconnect model and layoutparasitic extraction are necessary to better capture the circuitbehaviors. This would be an important subject of future studyto further improve the accuracy of the simulation results.

-2 -1.5 -1 -0.5 0VDS (V)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7No

rmal

ized

Cap

acita

nce

Meyer's Capacitance

CGS

CGD

VGS from 0 to -2 (V)

(a) (b)

Fig. 7: (a) Meyer capacitance model for p-type devices; (b) SPICE simulated five-stage ring-oscillator’s waveform vs. measured waveform; (c)34 measured 5-stage Pseudo-D ring oscillators’ stage delay; (d) 50 Monte Carlo simulations of ring oscillators’ stage delay; (e)-(f) Schematicand die photo of a 3-bit maximum-length linear feedback shift register (LFSR) composed of three D-filp flops (DFFs) and one XOR gate;(g) Measurements and simulation results of a fabricated sequence generator (’1110010’) with CLK=100 Hz, VDD=4 V and VSS=-4 V; (h)Waveforms of ring oscillators from 5 stages to 101 stages; (i) Simulated frequency and running time vs. ring oscillator’s stage with a totalof 500 us simulation time and a 200 ns time step.

Fig. 8: (a) Dot lines: 6 CNT-TFT based Pseudo-D inverter’s VTCswith channel length L = 3µm; solid line: model predictions forPseudo-D inverter; (b) Model prediction of CNT-TFT based 5-stagering-oscillator’s frequency vs. measured frequency.

V. CONCLUSION AND FUTURE WORK

In this paper, we present a unified TFT model for flexiblehybrid IoT circuit and system design. The proposed modelhas been validated using three different TFT technologiesand several Pseudo-CMOS circuits, covering both DC andAC behaviors. Also, we investigate technology scaling effectwith channel scaled from 25µm to 3 µm. The analysis andmeasurement indicate that device parasitics should be carefullyoptimized to approach the ideal quadratic improvement withchannel length scaling. We further identify that interconnectparasitics should be included to further improve the simulationaccuracy.

REFERENCES

[1] T.-C. Huang, K. Fukuda, T. Someya, and K.-T. Cheng, “Pseudo-cmos:A design style for low-cost and robust flexible electronics,” IEEETransactions on Electron Devices, vol. 58, no. 1, pp. 141–150, 2011.

[2] S. Wang, J. Xu, W. Wang, G.-J. N. Wang, R. Rastak, F. Molina-Lopez,J. W. Chung, S. Niu, V. R. Feig, J. Lopez et al., “Skin electronicsfrom scalable fabrication of an intrinsically stretchable transistor array,”Nature, vol. 555, no. 7694, p. 83, 2018.

[3] C. Wang, D. Hwang, Z. Yu, K. Takei, J. Park, T. Chen, B. Ma, andA. Javey, “User-interactive electronic skin for instantaneous pressurevisualization,” Nature materials, vol. 12, no. 10, pp. 899–904, 2013.

[4] T. Lei, M. Guan, J. Liu, H.-C. Lin, R. Pfattner, L. Shaw, A. F. McGuire,T.-C. Huang, L. Shao, K.-T. Cheng et al., “Biocompatible and totallydisintegrable semiconducting polymer for ultrathin and ultralightweighttransient electronics,” Proceedings of the National Academy of Sciences,vol. 114, no. 20, pp. 5107–5112, 2017.

[5] C. Zhu, A. Chortos, Y. Wang, R. Pfattner, T. Lei, A. C. Hinckley,I. Pochorovski, X. Yan, J. W.-F. To, J. Y. Oh et al., “Stretchabletemperature-sensing circuits with strain suppression based on carbonnanotube transistors,” Nature Electronics, vol. 1, no. 3, p. 183, 2018.

[6] T.-C. Huang, L. Shao, T. Lei, R. Beausoleil, Z. Bao, and K.-T. Cheng,“Robust design and design automation for flexible hybrid electronics,”in Circuits and Systems (ISCAS), 2017 IEEE International Symposiumon. IEEE, 2017, pp. 1–4.

[7] O. Marinov, M. J. Deen, U. Zschieschang, and H. Klauk, “Organic thin-film transistors: Part i—compact dc modeling,” IEEE Transactions onElectron Devices, vol. 56, no. 12, pp. 2952–2961, 2009.

[8] J. Zhao, P. Yu, S. Qiu, Q. Zhao, L. Feng, S. Ogier, W. Tang, J. Fan,W. Liu, Y. Liu et al., “Universal compact model for thin-film transistorsand circuit simulation for low-cost flexible large area electronics,” IEEETransactions on Electron Devices, 2017.

[9] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOSTransistor. Oxford Univ. Press, 2011.

[10] L. Shao, T.-C. Huang, T. Lei, Z. Bao, R. Beausoleil, and K.-T. Cheng,“Compact modeling of carbon nanotube thin film transistors for flexiblecircuit design,” in Design, Automation & Test in Europe Conference &Exhibition (DATE), 2018. IEEE, 2018, pp. 491–496.

[11] T.-Y. Chu, Z. Zhang, A. Dadvand, C. Py, S. Lang, and Y. Tao, “Directwriting of inkjet-printed short channel organic thin film transistors,”Organic Electronics, vol. 51, pp. 485–489, 2017.

[12] L. Lu, J. Li, H. S. Kwok, and M. Wong, “High-performance and reliableelevated-metal metal-oxide thin-film transistor for high-resolution dis-plays,” in Electron Devices Meeting (IEDM), 2016 IEEE International.IEEE, 2016, pp. 32–2.