Comparison and evaluation of the PLL techniques

for the design of the grid-connected inverter systems

A.Nicastri, A. Nagliero Dept of Electrotechnical and Electronic Eng.

Polytechnic of Bari

Via E.Orabona 4

70125 – Bari - Italy

antonionicastri@aol.com, nagliero@deemail.poliba.it

Abstract- The knowledge of the phase, amplitude and

frequency of the utility voltage is a fundamental aspect

for the design of the grid-connected inverter systems. In

this paper are presented the basic features of the PLL

technique. A particular attention is dedicated to the

Synchronous Reference Frame-PLL scheme. About the

generation of the orthogonal voltages system an

evaluation of the most employed techniques is shown:

Transport Delay, Inverse Park Transformation, Hilbert

Transformation, Second Order Generalized Integrators

(SOGI). Moreover some problems in filtering are treated.

The internal filtering – due to the PD structure – and the

external filtering – due to the harmonics presence in the

grid voltage. In both the cases the most employed

solutions are shown. For the internal filtering: Low Pass

Filter, Resonant Filter, Moving Average Filter, Repetitive

Controller. For the external filtering two alternative

schemes are presented: the Dual SOGI-PLL and the

Enanched-PLL (EPLL).

I. INTRODUCTION

Phase, amplitude and frequency of the utility voltage are

critical information for the operation of the grid-connected

systems. The grid voltage monitoring is used to ensure that

the performance of a grid-connected system comply with the

standard requirements for operation under comon utility

distortions In such applications, an accurate and fast detection

of the phase angle of the utility voltage is essential to assure

the correct generation of the reference signals. Thus, phase-

locked loop topologies must handle distorted utility voltages

if they are intented to applications that required the tracking

of the utility voltage vector [1]. The Phase-Locked Loop

(PLL) structure is a feedback control system that

automatically adjusts the phase of a locally generated signal

to match the phase of an input signal [2].

Fig. 1. Conceptual scheme of the PLL

Fig. 2. Block diagram of the PLL

Basically it consists of three blocks: a Phase Detector (PD), a

Loop Filter (LP) and a Voltage Control Oscillator (VCO)

(Fig.1). The VCO generates the output oscillation while the

PD block values the phase difference between the input and

output signals namely the phase error between the two

signals. The Loop Filter, typically a PI controller, is

employed to minimize the phase error and to provide an

opportune driving signal to the VCO [3].

A first classification of the different PLL-based techniques

can be made considering the PD structure. The simplest PD

implementation consists in a signal multiplier. Under the

assumption of a small-signal analysis, the phase difference

can be approximate by its sinus value according to the

following trigonometric formula

ˆ ˆ ˆ ˆsin( ) sin cos cos sinε θ θ θ θ θ θ θ θ= − = − = − (1)

in which θ and θ̂ are respectively the phase of reference and

the output signal [4].

II. SYNCHRONOUS REFERENCE FRAME PLL

At present, one of the most employed PLL topology is the

Synchronous Reference Frame PLL (SRF-PLL) (Fig.3).

Fig. 3. Block diagram of the single-phase SRF-PLL

If vα is the single-phase voltage input, vβ is an internally

generated signal that is a 90 degrees shifted version of vα [5].

The Park transformation block changes the reference frame,

bringing the voltages system from an α β− stationary

978-1-4244-6392-3/10/$26.00 ©2010 IEEE 3865

reference frame to a d-q rotating synchronous reference

frame.

ˆ ˆcos sin

ˆ ˆsin cos

d

q

v v

v v

α

β

θ θ

θ θ

� �−� � � �= � �� � � �� � � �� � � �

(2)

The feedback loop controls the angular position of this d-q

reference frame. In particular the utility voltage vector is

totally lined up to the d-axis. In this way it coincides with all

its d-component; consequently the q-component is made

equal to zero. The d-component describes the voltage vector

amplitude course [6].

Fig. 4. Reference transform αβ -dq

III. QUADRATURE SIGNAL GENERATION

About the quadrature signal generation, there are different

implementation techniques; the most simple way is using a

Transport Delay of T/4 that introduces a phase shift of 90

degrees. In this case, all the harmonics of the input signal are

characterized by the same time delay.

Other approaches are based on Inverse Park Transformation,

Inverse Hilbert Transformation or through the use of a

Second Order Generalized Integrator (SOGI)

A. Inverse Park Transformation

The Inverse Park Transformation is given by

cos sin

sin cos

d

q

vv

vv

α

β

δ δ

δ δ

� �� � � �= � �� � � �� �� � � �

(3)

The resulting scheme is shown in Fig.5. In this case two

interdependent nonlinear loops are formed. In fact the outputs

of the Direct Park Transformation block are used as inputs of

the dq/αβ block and vice versa. A pair of first-order low-pass

filters, one for each d-q voltage signal, is employed between

the two blocks as energy storage elements to avoid algebric

loops [7].

Fig. 5. Block diagram of Inverse Park Transformation based PLL

B. Hilbert Transformation

The Hilbert Transform of a generic signal x(t) is defined as

following

( )( )

P xH x d

t

ττ

π τ

∞

−∞

=−� (4)

in which P is the Cauchy principal value.

The ideal Hilbert transformer violates the systems causality

property therefore it is not practically realizable [6].

However, it is possible to approximate the transformation

through the use of a Finite Impulse Response (FIR) filter,

with coefficients defined as

1 cos[( 0.5 ) ] for 0.5

( 0.5 )[ ]

0 for 0.5

n Nn N

n Nh n

n N

π

π

− −�≠

−= =�

(5)

where N is the filter order, n is the coefficient index

( 0 n N< < ) and [ ]h n are the coefficents of the filter.

The last method considered uses a structure based on the

Second Order Generalized Integrator (SOGI)

C. Second Order Generalized Integrator

The transfer function of adaptive filter based on the Second

Order Generalized Integrator is defined as

2 2( )

sGI s

s

ω

ω=

+ (6)

where ω represents the resonance frequency of the SOGI [8].

The close-loop scheme in Fig. 6 is essentially composed by a

pair of integrators. The first one needs to the generation of

the signal 'v , which has the same phase of the input signal

v , while the second one is employed in the generation of the

quadrature signal 'qv that is a 90 degrees shifted version of

v . The closed-loop transfer functions are

'

2 2( ) ( )d

v k sH s s

v s k s

ω

ω ω= =

+ + (7)

' 2

2 2( ) ( )q

qv kH s s

v s k s

ω

ω ω= =

+ + (8)

where the parameter k adjusts the system filtering capability.

All the presented methods, except the last one, have same

shortcomings: frequency dependency, high complexity,

nonlinearity, problems in filtering. The SOGI-based

technique, on the contrary, provides a couple of orthogonal

and already filtered signals only through the use of the simple

scheme in Fig.6.

Fig. 6. Adaptive filter based on the SOGI

IV. FILTERING OPTIONS FOR PLL

The main problem in the phase detection is the rejection of

the harmonics. It is possible distinguishing between an

internal and an external filtering. The internal filtering is

exclusively due to the PD structure while the external

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filtering is not linked to any intrinsic features of the system

but it regards the grid voltage conditions in terms of

waveforms purity.

The operation implemented in the PD block is the following

n d

2

2

2 h a rm o n ic t e r m

ˆ( ) ( ) c o s ( ) s in ( )

ˆ ˆs in ( ) s in ( 2 )2

in o u tv t v t A k t t

A kt

ω θ ω θ

θ θ ω θ θ

= + + =

� �� �= − + + +� �� �

� � �� � ��

(9)

in which A is the amplitude factor and k is the PD gain [9].

Under the assumption of a small-signal analysis, it is possible

rewriting the term between brackets as

nd nd2 harmonic term 2 harmonic term

ˆ ˆ ˆ( ) sin(2 ) sin(2 )t tθ θ ω θ θ ε ω θ θ− + + + = + + +������� �������

(10)

The PD output is given by two terms: the first one is actually

the phase error namely the phase difference between the input

and output signals; the other one is a 2nd

harmonic term

superimposed to the useful signal that it needs filtering.

There are various approaches to improve the PD scheme. All

the techniques are based on the addition of a further filter

above the PI controller.

A. Low Pass Filter

The first technique uses a Low Pass Filter (LPF) (Fig.7). The

transfer function of the LPF with the unitary gain is

1( )

(1/ 2 ) 1c

H sf sπ

=+

(11)

where cf is the cut-off frequency. In this way the tracking

precision is improved but the dynamic response is slowed and

the filtering performance results frequency sensitive because

the LPF introduces phase shifting in signals [10].

Fig. 7. LPF technique for harmonics rejection

B. Resonant Filter

Alternatively the LPF can be replaced with a Second Order

Resonant Filter (RF) as shown in Fig. 8

The RF transfer function is

2 2

2( )

fk sH s

s ω=

+ (12)

where fk determines the bandwidth and ω is the resonant

frequency. This filter is more stable that the first one. It

guarantees a superior capability in the harmonics rejection

but it doesn’t introduce any phase shifting at the resonant

frequency. At the others frequencies the shifting introduced is

90± ° [11].

Fig. 8. RF technique for harmonics rejection

C. Moving Average Filter

Another method to improving the PD rejection capability is

based on the Moving Average Filter (MAF) as shown in

Fig.9 [12]. The MAF operator of a generic signal x(t) is

defined as shown in (13)

1( ) ( )

t

t Tx t x d

T ωω

τ τ−

= � (13)

Fig. 9. MAF technique for harmonics rejection

where Tω is the window width and 1/f Tω ω= the equivalent

frequency of the MAF. When the input signal contains

sinusoidal components with a multiple frequency of fω , the

MAF output is a constant value. Choosing an opportune

value of the window width, the behaviour of this filter

approximates a Low Pass Filter. The transfer function of the

MAF is

[ ]1 cos( ) sin( )( )( )

( )MAF

j k T k TX jkH jk

X jk k T

ω ω

ω

ω ωωω

ω ω

− −= = (14)

D. Repetitive Controller

The last option considered is the employment of a Repetitive

Controller (RC) (Fig.10). This kind of filter improves the

rejection capability of the PI controller amplifying the second

harmonic [13]. The Repetitive Controller is essentially a

bandpass filter in which the odd harmonics are filtered while

the even harmonics no. Indirectly the proportional gain of the

PI controller is increased and so the rejection capability too.

Fig. 10. Repetitive Controller technique for harmonics rejection

The model of the Repetitive Controller is based on a DFT

algorithm (Fig. 11). The discrete transfer function of the

controller is given by

( ) ( )1

0

2 2cos

h

N i

DFT ai h NF z h i N z

N N

π− −

= ∈

� � �= + ⋅� �� �

� �� �� � (15)

that represents practically the equation of a N order FIR

filter with unity gain on all selected harmonics h.

Fig. 11. Repetitive Controller

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V. THREE PHASE PLL

The three phase SRF-PLL scheme is shown in Fig.12. The

three-phase topology is not too different from the analogous

single-phase. The system doesn’t change neither in its

constitutive elements nor in the technique to obtain the

synchronization between the inputs and outputs.

The Park transformation block brings the voltages system

from the α β− stationary reference frame to the d-q rotating

synchronous reference frame. The q component is made

equal to zero and it is controlled by the feedback loop, while

the d component depicts the voltage vector amplitude. The

utility voltage can be represented as

, ,

c o s

2c o s

3

2c o s

3

a b c mv V

θ

θ π

θ π

� � �� �� ��

= −� �� �� �� �

� �� +� �� �� �

� �� �

(16)

A further transformation block (abc/ αβ ) is put above the

Park Transformation Block to obtain a diphase voltage

system from the three phase inputs. This is the unic

considerable difference of this scheme in comparison with

the single-phase SRF-PLL. The transformation block

implements the following vectorial equation

1 1

12 2 2

03 3 3

2 2

a

b

c

vv

vv

v

α

β

� � � �− −� �� � � �� �=� � � �� �� � � �− � �� �� �

(17)

The performances of all these schemes are evaluated

considering two basic aspects. First of all the tracking

precision: the phase error between the output and input

signals must converge to zero. Moreover the system must

exhibit a fast dynamic response that corresponds to

considering a short transitory. Generally a system

characterized by a rapid dynamic response, presents a greater

tracking error and vice versa. For this reason, nowadays, the

internal parameters of the schemes are derived as trade-off

between those two aspects making use of the settling time

[14]. The SRF-PLL behaviour is not very satisfactory in

presence of harmonics or notches in the grid voltage. [15] In

these cases the filtering capability of the system makes worse

considerably. The outputs are yet synchronized with the input

voltage system but the waveforms are not filtered: inputs and

outputs have the same THD. An external filtering is

necessary in order to obtain synchronized but also cleaned

output signals. All the employed techniques are based on the

extraction of the positive sequence.

A pair of SOGIs are employed in the Quadrature-Signals

Generator (QSG) to obtain two couples of orthogonal and

cleaned signals (Fig.13). These four signals enters in the

Positive-Sequence Calculator. (PSC). This technique exhibits

a fast, precise, and frequency-adaptive response under faulty

grid conditions. Practically the grid disturbances are filtered

before entering in the PLL scheme. The global performances

results improved because the PLL is connected to a filtered

version of qv+ [16].

The Enhanched PLL (EPLL) uses a more advanced scheme

in phase detection. This scheme is obtained by the

combination of an Adaptative Notch Filter (ANF) with a

conventional PLL (Fig.14). This kind of PD exhibits superior

performances about the rejection capability. The main feature

of the EPLL is its possibility of estimating the input

fundamental component. This last signal is employed to

derivate the error value.

Fig. 12. Three phase SRF-PLL scheme

Fig. 13. Dual SOGI-PLL

Moreover this mechanism provides additional informations

such as the amplitude and the phase angle of the input signal.

[17]. It does not need any subsystem for quadrature signal

generation because the EPLL provides also a 90° shifted

version of the input signal.

The Quadrature PLL (QPLL) is an interesting variant of the

EPLL. It is based on the estimating in-phase and in-

quadrature phase amplitudes of the fundamental component

of the input signal [18].

The output signal is defined as a linear combination between

these signals with coefficients sk and qk . About the EPLL

and QPLL three-phase configurations the topology is equal in

both the cases (Fig.15). The three-phase scheme employs six

single-phase EPLL. The first group (above the detection

block) is used to extract, phase by phase, the fundamental

components of the input voltages system. The second group

(below the detection block) is used for the evaluation of the

angle-phase. In the Positive Sequence Detection block is

implemented the following vectorial equation

2

2

2

( ) 1 ( )1

( ) 1 ( )3

( ) 1 ( )

f

a a

f

b b

f

c c

v t v t

v t v t

v t v t

β β

β β

β β

+

+

+

� � � � � � �� �

=� � � �� �� � � �� �� � � �� �

(18)

in which ( )( ) ( ) ( )a b cv t v t v t+ + + is the instantaneous positive-

sequence system in input to the second group of EPLLs,

( )( ) ( ) ( )f f f

a b cv t v t v t are the fundamental components of the

input voltages system and β is a 120° phase shift in the time

domain.

Fig. 14. Sigle phase EPLL scheme 3868

Fig. 15. Three-phase EPLL scheme

VI. EXPERIMENTAL RESULTS

The various PLL schemes have been implemented on DSP

TMS320F2812. This DSP uses a 16 bits fixed-point

representation of signals and parameters thus an internal

conversion is necessary. The position of the fixed point sets

univocally the number of bits employed for the integer part

and the number of bits useful to the conversion of the

fractional part. In the case of negative number, the most

significant bit (MSB) is used as sign bit. For the signals, the

point is fixed considering the greater and the smaller assumed

value and making sure that this two extremes result correctly

codified without underflow or overflow. In the case of a

parameter is sufficient codifying the exact value without

underflow or overflow. The fixed-point range for signed

number is given by the following equation 12 2 1I Iα−− ≤ ≤ − (16)

in which I is the number of bits ordained for the integer

part.

The hardware setup (Fig.16) is composed by:

• measurement boards for grid voltages (VR, VS, VT)

and the DC voltageVdc;

• the eZdsp TMS320F2812 board equipped with the

TMS320F2812 DSP;

• interface board;

• grid simulator PACIFIC 345-AMX for the

generation of the input voltages system with or

without harmonics presence.

The Code Composer Studio has been employed for the

waveforms visualization.

In the following, an evaluation of the external filtering

capability of the various techniques is made.

The Matlab simulations have been made considering a

symmetric harmonic contribution of 5th

and 7th

(THD=12%)

(Fig.17-18-19-20).

For the real test the harmonic contribution has been

implemented as a transient disturbance on the waveforms. In

the following figures are shown the experimental result

(Fig.21-22-23-24).

Real and simulated results are perfectly adherent. All the

proposed schemes, except the SRF-PLL, filter the harmonics

in input. In the following table (Tab.I) is shown quantitatively

the filtering that the various methods allow in term of THD.

TABLE I

THD OF THE INPUT AND OUTPUT SIGNALS

Device Input THD [%] Output THD [%]

SRF-PLL 12,09 12,09

EPLL 12,09 0,28

QPLL 12,09 3,60

DSOGI-PLL 12,09 4,04

Fig. 16: Experimental setup.

Fig. 17. SRF-PLL filtering capability

Fig. 18. EPLL filtering capability

Fig. 19. QPLL filtering capability

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Fig. 20. DSOGI-PLL filtering capability

Fig. 21. SRF-PLL filtering capability

Fig. 22. EPLL filtering capability

Fig. 23. QPLL filtering capability

Fig. 24. DSOGI-PLL filtering capability

VII. CONCLUSIONS

In this paper the grounds of the PLL technique has been

showed with particular reference to the SRF-PLL scheme. A

focus on the principal matters and an evaluation of the actual

solutions have been presented.

The filtering capability is a crucial aspect in these

applications. It is possible optimize the resultant

performances essentially in two ways:

- improving the basic SRF-PLL scheme with the addition of -

futher controllers and/or filters.

- making use of more complex schemes in phase detection in

order to obtain cleaned signals above the PLL scheme.

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