comparison of multiplier circuits - ijrter · carry save adder multiplier, 4x4 carry look ahead...

International Journal of Recent Trends in Engineering & Research (IJRTER) Conference on Electronics, Information and Communication Systems (CELICS’17)

Special Issue; March - 2017 [ISSN: 2455-1457] DOI : 10.23883/IJRTER.CONF.20170331.051.KFZSV

@IJRTER-2017, All Rights Reserved 272

COMPARISON OF MULTIPLIER CIRCUITS

J. Ayee Vinotha1, V. Vishvagarni2, J. Revathi3, R. Vikashini priyaa4, S. Sathish5

Department of Electronics and Communication Engineering

Coimbatore Institute of Engineering and Technology

ABSTRACT:

Today Multipliers play an very important role in

various applications .Because speed, area and

power consumption are dependence on Multiplier

circuits. So we need to concentrate on choosing the

Multiplier circuits. For example “Serial-Parallel”

multipliers compromise the speed, it lead better

performance for area and power consumption.

Multiplication is one of the most basic arithmetic

operations. It is used in digital applications, central

processing units, and digital signal processors. The

main aim of this project is to reduce the power

consumption.In VLSI these are all the important

parameters for implementation. Low power and

high speed in VLSI is the biggest challenge for the

designer.In this project we compares the power,

speed, area and delay of the multiplier circuits such

as 4x4 Multiplier,4x4 Wallace Multiplier, 4x4

Carry Save Adder Multiplier, 4x4 Carry Look

Ahead Adder Multiplier circuits.All the above

circuits are implemented using Verilog module in

xilinx software.Based on the result of this project

we conclude the best multiplier among these.

INTRODUCTION:

MULTIPLIER:

The objective of good multiplier is to provide a

physically compact, high speed and low power

consumption unit. To reduce significant power

consumption of multiplier, it must be design in

good direction to reduce the number of operation.

There are no. of techniques that to perform binary

multiplication.

A).4X4 NORMAL BINARY MULTIPLICATION

The figure A shows the normal 4 bit binary

multiplication. A basic multiplier consists of three

parts (i) partial product generation (ii) partial

product addition and (iii) final addition. A

multiplier essentially consists of two operands, a

multiplicand “A” and a multiplier “B” and

produces a product “P”. In the first stage, the

multiplicand and the multiplier are multiplied bit

by bit to generate the partial product terms. The

second stage is the most important, as it is the most

complicated and determines the overall speed of

the multiplier. This stage includes addition of these

partial product terms to generate the product “P”.

This paper will be more focused on the

optimization of this stage, which consists of the

addition of all the partial products. If speed is not

an issue, the partial products can be added serially,

reducing the design complexity. However, in high-

speed design, the Wallace tree construction method

is usually used to add the partial products in a tree-

like fashion in order to produce two rows of partial

products that can be added in the last stage.

Although fast, since its critical path delay is

proportional to the logarithm of the number of bits

in the multiplier.

B).4X4 MULTIPLIER CIRCUIT DIAGRAM

HALF ADDER

Half adder is a combinational arithmetic circuit that

adds two numbers and produces a sum bit (S) and

carry bit (C) as the output. If A and B are the input

bits, then sum bit (S) is the X-OR of A and B and

the carry bit (C) will be the AND of A and B. From

this it is clear that a half adder circuit can be easily




constructed using one X-OR gate and one AND

gate.

C).HALF ADDER CIRCUIT

C).TRUTH TABLE OF HALF ADDER

FULL ADDER:

A full adder adds binary numbers and accounts for

values carried in as well as out. A one-bit full adder

adds three one-bit numbers, often written as A,B,

and Cin; A and B are the operands, and Cin is a bit

carried in from the next less significant stage.

D). FULL ADDER TRUTH TABLE

D). FULL ADDER CIRCUIT DIAGRAM

By using the full adder and half adder circuit we

can design a multiplier in a good manner, this must

be implemented in vlsi domain.

WALLACE MULTIPLIER:

A Wallace multiplier is an efficient methodology

that can be easily hardware implementable. It

mainly consists of the three steps:

1. partial product generation,

2. partial product grouping and

3. reduction, and addition.

Consider the multiplication of two 4-bit numbers

A and B. The Eshows structure of 4-bit Wallace

multiplier. a0, a1, a2, a3 represents the bits of

multiplicands A and bo, bl, b2, b3 represents the

bits of the multiplier B. For the 4-bit multiplication

Wallace multiplier requires four stages the first

stage is consisting of half adders and the following

stage requires full adders. The output is of 8-bit

which is shown in the Fig. 1 as P. Wallace

multiplier requires 4 half adders and 8 full adders

for the 4-bit multiplication while binary array

multiplier requires 20 full adders. Hence, it shows

significant amount of the hardware saving in terms

of the adder requirement. As number of bits is

increasing then the saving of adders is also more if

implemented using Wallace multiplier technique.




E).4X4 WALLACE

MULTIPLICATIONPROCESS

Fig E shows the multiplication of two 4-bit

numbers. The numbers are denoted by A and B

where a0,a1 ,a2 a3 represents the bits of

multiplicand A with as its least significant bit and

as its most significant bit andb0 ,b1 ,b2 ,b3

represents the bits of multiplier B with b0 as its

least significant bit and b3 as its most significant

bit. The product of the two 4-bit numbers is

denoted by P which is of 8-bit with p0 as the least

significant bit and p7 as the most significant bit.

Fig F shows the basic multiplication of two

numbers and thus producing the result, P. Now the

use of half adders and full adders is explained in

next Fig. 8.

F).WALLACE MULTIPLICATION IN

TERMS OF PARTIAL PRODUCTS

Shows the multiplication of two numbers A and B

as explained in Fig. F and producing its result as P.

Fig. G explains the method of addition of different

intermediate terms. The different intermediate

terms formed after the multiplication of two 4-bit

numbers are shows the multiplication of two

numbers A and B as explained in Fig. F and

producing its result as P. Fig. G explains the

method of addition of different intermediate terms.

The different intermediate terms formed after the

multiplication of two 4-bit numbers are

a0b0,a1b0,a2b0,a3b0,a0b1,a1b1,a2b1,a3b1,a0b2,a1

b2,a2b2,a3b2,a0b3,a1b3,a2b3,a3b3.Two

intermediate terms in one column are added using a

half adder and more than two terms in one column

are added using full adder as explained in fig G.

The sum obtained after each addition.

F).8 bit Wallace tree multiplier partial product

generation process.

OUTPUT OF WALLACE TREE

MULTIPLIER

3.CARRY SAVE ADDER:

Carry Save Adder is a type of digital adder used in

many computer application. It differs from other

adder I .e its output contains sequence of sum bits

and sequence of carry bits.




H).BLOCK DIAGRAM OF CARRY SAVE

ADDER

OUTPUT OF CARRY SAVE ADDER

MULTIPLIER

Carry Save Adder is mainly used in the addition of

three or more n-bit numbers. CSA is identical to the

Full Adder. Instead of using any other adder here

we can use CSA for the addition of the partial

product terms of each group. Other adders when

compared with CSA are slow and CSA working is

more easy to understand.It consumes three n-bit

input integers to be added and produces two

outputs,n-bit partial sum and n-bit carry.Unlike the

normal adders such as ripple carry adder ,a CSA

consists of multiple one bit full adders without any

carry chaining.A carry save adder may be

implemented in several different ways.A CSA

instead of trying to solve the addition problem,it

solves a different problem of adding three numbers

together into a problem of adding two numbers

together.

CARRY LOOK AHEADER:

In ripple carry adders, the carry propagation time

is the major speed limiting factor as seen in the

previous lesson.

Most other arithmetic operations, e.g.

multiplication and division are implemented using

several add/subtract steps. Thus, improving the

speed of addition will improve the speed of all

other arithmetic operations.

Accordingly, reducing the carry propagation delay

of adders is of great importance. Different logic

design approaches have been employed to

overcome the carry propagation problem.

One widely used approach employs the principle of

carry look-ahead solves this problem by

calculating the carry signals in advance, based on

the input signals.

This type of adder circuit is called as carry look-

ahead adder (CLA adder). It is based on the fact

that a carry signal will be generated in two cases:

(1) when both bits Ai and B

i are 1, or

(2) when one of the two bits is 1 and the carry-in

(carry of the previous stage) is 1.

To understand the carry propagation problem, let’s

consider the case of adding two n-bit numbers A

and B.

The Boolean expression of the carry outputs of

various stages can be written as follows:

C1 = G

0 + P

0C

0

C2 = G

1 + P

1C

1 = G

1 + P

1 (G

0 + P

0C

0)

= G1 + P

1G

0 + P

1P

0C

0

C3 = G

2 + P

2C

2 = G

2 + P

2G

1 + P

2P

1G

0 + P

2P

1P

0C

0

C4 = G

3 + P

3C

3

= G3 + P

3G

2 + P

3P

2G

1 + P

3P

2P

1G

0 + P

3P

2P

1P

0C

0

I).CARRY LOOK AHEAD BLOCK

DIAGRAM




OUTPUT OF CARRY LOOK AHEAD

MULTIPLIER

The 4-bit carry look-ahead (CLA) adder consists of

3 levels of logic:

First level: Generates all the P & G signals. Four

sets of P & G logic (each consists of an XOR gate

and an AND gate). Output signals of this level (P’s

& G’s) will be valid after 1τ.

Second level: The Carry Look-Ahead (CLA) logic

block which consists of four 2-level

implementation logic circuits. It generates the carry

signals (C1, C

2, C

3, and C

4) as defined by the above

expressions. Output signals of this level (C1, C

2, C

3,

and C4) will be valid after 3τ.

Third level: Four XOR gates which generate the

sum signals (Si) (S

i = P

i ⊕ C

i). Output signals of

this level (S0, S

1, S

2, and S

3) will be valid after 4τ.

J).4X4 CARRY LOOK AHEAD MULTIPLIER

DIAGRAM

CONCLUSION:

Thus we have successfully made a 4x4 multiplier

using Xilinx platform. As mentioned above, the

main purpose of using a carry look ahead adder

was to reduce the time to calculate the carry bits.

We have used a mapping technique to calculate the

partial products of the multiplication and then

giving these partial products to the carry look ahead

adders we have obtained the final product. In future

we will implement carry save adder for making a

multiplier.

In this paper an area efficient and high speed

Wallace multiplier using reduced carry save adder.

In this proposed design the area delay product is

less than the existing design. Based on result of

these four multipliers, we can measure the power,

area, speed, delay on we can conclude the best one

multiplier among these multipliers.

REFERENCE:

[1] Maroju SaiKumar, Dr. P. Samundiswary,

“Design and Performance Analysis of Various

Adders using Verilog”, IJCSMC, Vol. 2, Issue. 9,

September 2013, pg.128 – 138

[2] C. Jaya Kumar, R.Saravanan,“VLSI Design for

Low Power Multiplier using Full Adder”, European

Journal of Scientific Research, ISSN 1450-216X

,Vol.72, No.1 (2012), pp. 5-16.

[3] Sreehari veeramanchaneni, Kirthi Krishna M,

Lingamneni Avinash, Sreekanth Reddy Puppala,

and M.B. Srinivas,” Novel Architectures for High

Speed and Low power 3-2, 4-2 and 5-2

compressors”20th international conference on

VLSI Design , jan 2007 , pp. 324-329.

[1] C.Vinoth1, V. S. Kanchana Bhaaskaran2, B.

Brindha, S. Sakthikumaran, V.Kavinilavu,

B.Bhaskar, M. Kanagasabapathy and B. Sharath,”

A Novel low power and high speed Wallace tree

multiplier for risc processor”,C

comparison of multiplier circuits - ijrter · carry save adder multiplier, 4x4 carry look ahead...

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