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1
Compatibility of Models Among Simulators Facilitated by Verilog-A Technique
Modelithics, inc.
Larry Dunleavy
Jiang Liu
Eric O’Dell
MOS-AK Workshop , Berkeley California, December 7, 2016
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Outline
• Introduction to Modelithics and multi-
simulator compatibility problem
• Model development flows using custom
API’s vs. Verilog-a & limitations
• Application to customized non-linear
models
• A GaN HEMT model example
• Closing comments
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ALL MODELS ARE WRONG BUT SOME ARE USEFUL
Box, G. E. P. (1979). Robustness in the strategy of scientific model
building. In R. L. Launer, and G. N. Wilkinson, (eds.) Robustness in
Statistics. New York: Academic Press
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• Modelithics addresses the industry need for high-
accuracy RF/Microwave simulation models that:
– Are standardized across various vendors
– Offer enhanced scalability features
– Provide significant savings versus in-house modeling
• Modelithics primary business offerings/expertise:
Sell and support premium active and passive model
libraries (over 12,000 COTS devices represented!)
Perform custom measurement and modeling
services for RF, microwave and mm-wave devices
Brief Intro to Modelithics “Excellence in Modeling since 2001”
Highly scalable and accurate models supporting
multiple vendors on multiple platforms
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Introduction
• There are lots of RF and microwave CAE software
platforms in the market that cater to specific interests
of designers
– Keysight ADS & Genesys, NI AWR DE, Ansys Designer/HFSS,
Cadence Spectre, Pspice , Sonnet
– Budget, familiarity, type of designs, PDK
availability, etc.
• It is a tough task for model developers to develop
different model versions for all supported simulators
with consistent performance
– Adapting the same model to each different EDA tool
API’s is time and labor-intensive !
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Introduction (cont.)
• A “write-once, run-everywhere” modeling
approach would be ideal scenario for
developers as they can focus more on the
model performance less on API differences
• The Verilog-a modeling language has potential
in this regard as more and more CAE vendors
adopt a “Verilog-A path” in their products
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Typical Development Procedure using Built-in APIs
Model
Parameter
Registration
Nodal Y Matrix
Filling
Math Model
Implementation
Model
Compilation /
Debugging
PDK packaging /
Documentation
Inform the simulator what parameters will be
passed into the model (simulator specific)
Assemble the MNA (modified nodal analysis)
matrix by stamping all the elements used in the
model netlist to the matrix (simulator specific)
Add the mathematic expression of the model to
the code (can be generalized to share across
simulators)
Compile the model code and test the model
object to make sure it matches with expectation
(simulator specific)
Prepare the PDK delivery (simulator specific)
This process has to be repeated for every simulator
supported: time and labor intensive
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Modelithics’ Practice
• Currently Modelithics highly scalable “Microwave Global™”
passive RLC models (RLCs) based on the built-in APIs
approach for multiple CAE platforms, including:
– Keysight’s ADS and Genesys
– NI AWR Design Environment (aka Microwave Office)
– Cadence’s Virtuoso
– Ansys’ HFSS
– Sonnet
• We are able to divide the model codes into general and
simulator-specific modules so we can focus on model
performance instead of implementations
(But we have come a long way to get to this point! )
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Verilog-a: Brief Introduction
• Verilog-a is a subset of Verilog-AMS (analog and
mixer-signal) standard
– High-level hardware description language for analog
behavior; specifically it is designed to describe
models for SPICE-class simulators;
– It enables designers to characterize electrical
systems, through the potential and flow (voltage and
current) description;
– Components are constructed using collections of
nodes (voltages) and branches (currents)
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Simulator Independence of Verilog-a
• Verilog-a models are theoretically independent
from specific simulators:
– Model developers only need to concentrate on
constructing the constitutive relationships between
the input and output using the verilog-a syntax,
while verilog-a compilers process the interaction
between the models and simulators
– Similar to the “Write-once, run everywhere” cross-
platform Java language
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Typical Development Procedure using Verilog-a Approach
Model
Parameter
Registration
Nodal Y Matrix
Filling
Math Model
Implementation
Model Compilation
/ Debugging
Simulator 1
PDK packaging /
Documentation
Simulator 1
Inform the simulator what parameters will be
passed into the model (verilog-a specific)
Assemble the MNA (modified nodal analysis)
matrix by stamping all the elements used in the
model netlist to the matrix (verilog-a specific)
Add the mathematic expression of the model to
the code (verilog-a specific)
Compile the model code and test the model
object to make sure it matches with expectation
(simulator specific)
Prepare the PDK delivery (simulator specific)
Model Compilation
/ Debugging
Simulator n
…
PDK packaging /
Documentation
Simulator n
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Limitations in Verilog-a Models
Translator-dependent:
– It is up to the vendors’ translator to get the verilog-
a code correctly translated into built-in APIs style
for simulation (errors can happen here)
– The simulated results may be different slightly due
to: How the model is linearized; initialized; numeric
truncation, etc.
– It is up to the translator to determine if all or part
of the standard is supported
– Some system calls may not be supported equally
between translators
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Limitations in Verilog-a Models (cont.)
Simulation speed:
– Due to the generalization of the Verilog-a
language, the translated code may not be as
succinct as using the built-in APIs directly
– This can lead to some loss in the simulation
speed
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MDLX’s Verilog-a Diode Model Library
• NLD (Non-linear Diodes) Library
– Over 70 models
– Available in multiple simulators
• Keysight ADS
• Keysight Genesys
• NI/AWR Design Environment (AWRDE)
• ANSYS HFSS, Cadence (in development)
– Uses same Verilog-a cores for each simulator
• 10 in house developed diode model cores
– Parasitics not included in cores
• Added as part of model porting to each simulator
Tolerance_Cap=1
Sim_mode=0
Tand=0.022
T_mtl=0.043 mm
Er_sub=4.24
H_sub=1.4986 mm
Part=Toshiba 1SV229
VAR_TSH_TE1A_001_1MDLX
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MODvtte1a001ID=MDLX_Diode1MSUB=0Sim_mode=0Tolerance_Cap=1
Toshiba 1SV229 Varactor
Diode Model Symbols from
(left to right) AWR, Genesys
and ADS
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Modelithics Qorvo-GaN Non-linear Model Library
– ~60 models: both die-level and package devices
– Fully sponsored – free to Qorvo customers
– Available in multiple simulators • Keysight ADS
• NI/AWR Design Environment (AWRDE)
– Uses same Verilog-a cores for each simulator
– Modelithics version of a modified Angelov model • Parasitics separated from nonlinear core
• Enable intrinsic voltage/current sensing
• Enhanced scalability and thermal modeling features.
M
Gate
Source
Drain1
2
3
SUBCKTID=S2NET="HMT_QOR_TGF2819_FL_001"VDQ=32self_heat=1Temperature=25 DegC
TGF2819-FL
120W GaN
Device Model
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Case Study: VA-based GaN Transistor Model in Three CAEs
• A GaN model is illustrated here as a successful
verilog-a model practice
• It consists of a modified Angelov nonlinear core
implemented in verilog-a, surrounded by parasitic
and package elements
• DCIV/SP/power sweep/loadpull contours will be
demonstrated in following slides
– As will be demonstrated, good agreements have been
achieved through the usage of Verilog-a core model for
both linear and nonlinear performances.
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A simple DCIV Simulation Setup in three Simulators
M
Gate
Source
Drain1
2
3
SUBCKTID=S1NET="HMT_QOR_TGF2978_SM_001"VDSQ=32self_heat_factor=1Temperature=25 DegC
SwpStep
IVCURVEID=IV2VSWEEP_start=0 VVSWEEP_stop=40 VVSWEEP_step=1 VVSTEP_start=-4 VVSTEP_stop=1 VVSTEP_step=0.25 V
Cadence
ADS
AWR
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IV Simulation Results
0 20 40 60 80
Voltage (V)
DCIV
0
500
1000
1500
2000
2500
3000
3500
IVCurve() (mA)DCIV_encode
ADS Cadence AWR
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S-parameter Results: Cadence vs. ADS
5GHz, 32Vds, -2.77Vgs, Ids 100mA,
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S-parameter Results: AWR vs. ADS 0 1.0
1.0
-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
S11Swp Max
11000MHz
Swp Min
500MHz
S(1,1)SP_sim
S(1,1)TGF2978_SP_32VVd_m2p76VVg_25C
500 5500 1050011000
Frequency (MHz)
S12_mag
-50
-45
-40
-35
-30
-25
-20DB(|S(1,2)|)SP_sim
DB(|S(1,2)|)TGF2978_SP_32VVd_m2p76VVg_25C
500 5500 1050011000
Frequency (MHz)
S21_mag
-10
0
10
20
30500 MHz25.87 dB
DB(|S(2,1)|)SP_sim
DB(|S(2,1)|)TGF2978_SP_32VVd_m2p76VVg_25C
0 1.0
1.0
-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
S22Swp Max
11000MHz
Swp Min
500MHz
S(2,2)SP_sim
S(2,2)TGF2978_SP_32VVd_m2p76VVg_25C
500 5500 1050011000
Frequency (MHz)
Error_SP
0
2e-007
4e-007
6e-007
8e-007 |Eqn(error_S11)|Output Equations
|Eqn(error_S12)|Output Equations
|Eqn(error_S21)|Output Equations
|Eqn(error_S22)|Output Equations
Error Plot
5GHz, 32Vds, -2.77Vgs, Ids 100mA,
21
Power Sweep: AWR vs. ADS
5.5 15.5 25.5 31.5
HB_Pout_Freq1
20
25
30
35
40
45
50
DB(|Pcomp(PORT_2,1)|)[1,X] (dBm)HB_sim_Freq1.AP_HB
PlotCol(1,3)TGF2978_PS_5GHz_32VVd_m2p77VVg
5.5 15.5 25.5 31.5
HB_Iout_Freq1
0
500
1000
1500 p1
|Icomp(I_METER.AMP3,0)|[T,X] (mA)HB_sim_Freq1.AP_HB
PlotCol(1,5)TGF2978_PS_5GHz_32VVd_m2p77VVg
p1: Freq = 5000 MHz
5.56.57.58.59.510.511.512.513.514.515.516.517.518.519.520.521.522.523.524.525.526.527.528.529.530.531.5
HB_PAE_Freq1
0
10
20
30
40
50
60p2
PAE(PORT_1,PORT_2)[1,X]HB_sim_Freq1.AP_HB
PlotCol(1,4)TGF2978_PS_5GHz_32VVd_m2p77VVg
p2: Freq = 5000 MHz
5.5 15.5 25.5 31.5
Error_HB_Freq1
0
0.001
0.002
0.003
0.004
0.005
0.006|Eqn(error_Gain)|Output Equations
|Eqn(error_Pout)|Output Equations
|Eqn(error_PAE)|Output Equations
|Eqn(error_Iout)|Output Equations
Error Plot
5GHz, 32Vds, -2.77Vgs, Ids 100mA,
22
Power Sweep: Cadence vs. ADS
0.000
10.000
20.000
30.000
40.000
50.000
60.000
0.000 5.000 10.000 15.000 20.000 25.000 30.000 35.000
ADS Gain
ADS Pout
ADS PAE
Cadence Gain
Cadence Pout
Cadence PAE
Gain
Pout
PAE
5GHz, 32Vds, -2.77Vgs, Ids 100mA,
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Power Contours: 9GHz, 32Vds, -2.76Vgs, IdsQ of 100mA
ADS Cadence AWR
0 1.0
1.0
-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
LP_Pdel_Freq1
Swp Max
43.7989dBm
Swp Min
39dBm
G_LPCM(PLoad,1,5,10,0)[T]
LP_Data_Freq1
G_LPCMMAX(PLoad,10,0)[T]
LP_Data_Freq1
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PAE Contours: 9GHz, 32Vds, -2.76Vgs, IdsQ of 100mA
ADS Cadence AWR
0 1.0
1.0
-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
LP_PAE_Freq1Swp Max
50.8924%
Swp Min
30%
G_LPCM(PAE,5,5,10,0)[T]LP_Data_Freq1
G_LPCMMAX(PAE,10,0)[T]LP_Data_Freq1
25
Conclusion
• The myriads of available CAE solutions in the market present a challenge for model providers to port and maintain model updates
• Traditionally Model providers have to code separarely for each set of built-in APIs
• Verilog-a modeling approach offers a “write-once, run everywhere” possibility that steers developers’ focus on model quality instead of implementation
• Not so fast! There remain differences among the vendors’ translators so that the code they develop can work properly and consistently across simulators and some custom treatment for each simulator is still required.