Ben Guo, Fan Xu, Zheyu Zhang, Zhuxian Xu, Fred Wang, Leon M. Tolbert, Benjamin J. Blalock Center for Ultra-wide-area Resilient Electric Energy Transmission Networks (CURENT),

Department of Electrical Engineering and Computer Science, The University of Tennessee

Knoxville, TN 37996-2250, USA bguo@utk.edu

Abstract— An overlap time for two commutating switches is necessary to prevent current interruption in a three-phase buck rectifier, but it may cause input current distortion. In this paper, a modified pulse-based compensation method is proposed to compensate for the overlap time. In addition to the traditional method which places the overlap time based on the voltage polarity, this new method first minimizes the overlap time to reduce its effect and then compensates the pulse width according to the sampled voltage and current. It is verified by experiments that the proposed method has better performance than the traditional method, especially when the line-to-line voltage crosses zero. Another distortion comes from the irregular pulse distribution when two sectors change in a 12-sector space vector PWM. This paper proposes two compensation methods for that scenario as well, compensating the duty cycle and increasing switching frequency near the boundaries of two sectors. It is shown through experiments that both methods can reduce the input current distortion in the buck rectifier.

Index Terms—Three-phase buck rectifier, current source, overlap time, space vector, sector change.

I. INTRODUCTION The three-phase buck-type rectifier can be used as an active

front end in high-efficiency power supplies for communication and data centers [1][2]. Its topology is shown in Fig. 1, where a diode is in series with the MOSFET to form the switch in order to block the voltage in both directions.

Fig. 1. Three-phase buck rectifier with freewheeling diode.

Overlap time is added in the gate signals of the buck rectifier to prevent DC current interruption [1-3]. The overlap time will cause error in the current control and increase the low-order harmonics in the input current [4]. The distortion caused by the overlap time is shown to be proportional to its duration and the carrier frequency [5]. A compensation method for the overlap time is proposed in [6], which adds overlap time to the gate

signal of the switch that bears reverse voltage. It assumes that the transition time is much smaller than the pulse width and can be omitted. But this assumption is not precise when the sinusoidal voltage on the device is crossing zero or the current on the DC inductor is small at light load.

Another distortion comes from the modulation scheme. The 12-sector space vector modulation has been shown to have lower switching loss compared to traditional 6-sector modulation schemes [7-11]. Two sub-sectors are divided according to the input current and voltage relationship in each 60˚ sector in Fig. 2. The vector arrangement will be changed to achieve lowest switching voltage in two sub-sectors. But this will produce irregular pulse distribution and cause input current distortion at the moment of sector change [6][10-12]. When the arrangement of the vectors alternates near the boundary of two sub-sectors, the interval between two pulses will become short on one switch and long on its complementary switch.

(a)

(b) Fig. 2. Sector division in space vector PWM: (a) Input current and voltage;

(b) Space vector plane.

In this paper, the current distortion caused by the overlap time is analyzed first. A modified pulse-based method is proposed for the overlap time compensation. The commutation in the buck rectifier is modeled, and a minimized overlap time is proposed. Based on the model, the compensation pulse width

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Compensation of Input Current Distortion in Three-Phase Buck Rectifiers

can be generated under different switching voltage and current. The proposed method is verified through experiments in a 7.5 kW all-SiC buck rectifier.

Then the irregular pulse distribution is analyzed as well. Two methods are proposed to reduce the irregular pulse distribution—compensating for the duty cycle and increasing the switching frequency near the sector change. Both methods are analyzed and verified through simulation or experiments in this paper.

II. OVERLAP DISTORTION AND ITS COMPENSATION As shown in Fig. 1, the commutation occurs between the

upper three switches (S1, S3, and S5) or the lower three switches (S4, S6, and S2) in the buck rectifier. The basic commutation unit can be drawn in Fig. 3, containing two switches Sx and Sy. The voltage sources Vx and Vy indicate two phase voltages, and Idc is the DC current on the inductor Ldc. In Fig. 4, a double pulse test circuit is built based on Fig. 3 to study the commutation under different operating conditions. The active switches are 1200 V SiC MOSFETs, CMF20120D, from Cree [13], and the series diodes are 1200 V SiC Schottky barrier diodes (SBDs), SDP60S120D, from SemiSouth [14].

(a) (b) Fig. 3. Commutation unit in buck rectifier: (a) Circuit schematic; (b) Gate

signals.

Fig. 4. Device double pulse test board.

A. Distortion Caused by Overlap Time The commutation between S1 and S3 in Sector 2 and 3 (Fig.

2) are taken as an example. The typical gate signals are shown in Fig. 5 for S1 and S3. The overlap time ∆ is added on the reference gate signals of S1 and S3 to prevent the interruption of DC inductor current, as shown in Fig. 5.

When 0, the transition happens when S1 switches at and rather than the ideal moment and , resulting in a

gain in the input current and a loss in . When 0, the transitions occur at and when S3 switches, rather than the ideal moment and , resulting in a loss in and a gain in . This gain and loss will cause distortion of the fundamental

component of the input current in Fig. 6, where the effect of the overlap time toggles when or cross zero.

Fig. 5. Overlap time distortion.

Fig. 6. Input current distortion.

B. Modified Pulse-based Compensation Method The traditional pulse-based compensation method adds the

overlap time to the gate signal of the switch which bears reverse voltage. It depends on the polarity of the line-to-line voltage. As shown in Fig. 7, the gate pulse width of S3 is added by 2 ∆ to compensate the overlap time in Sector 2 when 0. The input current will have no distortion since the transition happens at the ideal moment and . Similarly, the overlap time is added on the S1 gate signal in Sector 3 when 0. The traditional compensation method assumes that the commutation time is much smaller than the pulse width and can be omitted.

Fig. 7. Traditional compensation.

Fig. 8. Slow transition distortion.

However, the commutation time will become much longer and cannot be ignored when the line-to-line voltage is crossing zero or the DC current is small under light load, as shown in Fig. 8. Under these conditions, the traditional method is not enough to compensate for the overlap time effect. The turn-on waveforms of Sx are measured in the double pulse test (Figs. 3 and 4) and shown in Fig. 9(a) when = 340 V and = 20 A. In Fig. 9(b), = 10 V and = 20 A. The rise time of is more than 200 ns in Fig. 9(b), ten times of that shown in Fig. 9(a). The turn-off waveforms of Sx are shown in Fig. 10 when

= 680 V. The fall time of is 40 ns when = 12 A in Fig. 10(a) while 280 ns when = 1.5 A in Fig. 10(b).

(a)

(b) Fig. 9. Measured turn-on waveforms: (a) = 340 V, = 20 A; (b)

= 10 V, = 20 A.

(a)

(b) Fig. 10. Measured turn-off waveforms: (a) = 680 V, = 12 A; (b) = 680 V, = 1.5 A.

A modified pulse-based compensation method is proposed to compensate the overlap time. As shown in Fig. 11, two more

modules are added to the traditional method. First, the minimum overlap time ∆ is selected for the gate signal to speed up the transition and reduce the compensation effort. The commutation process is modeled to generate the compensation pulse width according to line-to-line voltage , DC current

, and the overlap time ∆. Finally the ideal reference pulse width is added by 2 ∆ and to get the actual reference pulse width , which is sent to the modulator.

Fig. 11. Modified pulse-based compensation method.

C. Commutation Analysis in Buck Rectifier To model the commutation in the buck rectifier, the

theoretical turn on waveform of Sx is shown in Fig. 12 when 0 [15]. When the parasitic inductance is not considered, the channel current of the MOSFET is proportional with the gate voltage from to , as the solid line shown in Fig. 12. The gate charge time is proportional to the gate resistor

and the input capacitor (including gate-source capacitor and gate-drain capacitor ).

Fig. 12. Theoretical turn on waveform of Sx.

Fig. 13. Sx turn on circuit with parasitic inductance.

When is considered, the current rise time will be increased when the switching voltage is low, as the dash line shown in Fig. 12. In this case, the voltage is distributed on the parasitic inductance in Fig. 13. The current rise time can be written as ⁄ .

The current rise time of Sx is determined by the larger of the two and is given by 2 , ⁄ , where

. When is small, is predominantly ⁄ . The charge loss of Sx or the charge gain of Sy can be approximated by 2⁄ .

Conservatively, Sy should be kept on until current is fully commutated to Sx when 0. The overlap time ∆ should be larger than , which is long when is close to zero.

Actually it is possible to accelerate the turn-on process of Sx with careful selection of ∆ . If ∆ is set to the gate charge time

Time (100ns/div)

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2 , the gate of S1 has reached the turn-on voltage at the end of overlap time although its current has not reached . When Sy is turned off, the DC inductor will force the current to be commutated to Sx.

Fig. 14. Sx turn on circuit with reduced overlap time.

The commutation with reduced overlap time can be described with the equivalent circuit in Fig. 14. When Sy is turned off, the related current and voltage in the commutation can be expressed by (1) where is the transconductance of the MOSFET, _ the gate-source voltage of Sy, and the gate drive voltage.

___ __ ⁄

(1)

In this transition, the voltage on Sx has already dropped to a low value, so can be ignored in (1). The voltage spike on Sy can be given by (2) and is proportional to the gate turn off speed of Sy and the parasitic inductance .

_ (2)

The experimental waveforms of the turn on process under different overlap times are shown in Figs. 15 to 17 when = 10 V and = 20 A. The overlap time, current rise time, and voltage spike on Sy are listed in Table I. When overlap time is 550 ns in Fig. 17, there is no voltage spike on Sy.

TABLE I. SWITCHING CHARACTERISTICS WITH DIFFERENT OVERLAP TIME Overlap Time Current Rise Time Voltage Spike on Sy

10 ns 70 ns 70 V 150 ns 180 ns 25 V 550 ns 270 ns -

Fig. 15. Turn on with 10 ns overlap time.

Fig. 16. Turn on with 150 ns overlap time.

Fig. 17. Turn on with 550 ns overlap time.

In Figs. 15 and 16, it is obvious that the slope of will increase when Sy is turned off. The commutation is accelerated while the voltage spike is affordable.

With reduced overlap time, the commutation can be accelerated and the charge loss can be largely reduced. The compensation time for the turn-on process of Sx can be expressed by (3) when 0. _ ,, 2 , ∆

, ∆ 1 ∆2 , ∆ (3)

The theoretical turn off waveform of Sx is shown in Fig. 18 when 0 [15]. Before Sx is turned off, Sy has been turned on although there is no current flowing in it. In this commutation, the overlap time should be long enough for the gate of S3 to be charged.

If the junction capacitor on Sy is not considered, Sx current will not drop until is charged to , as the solid line shown in Fig. 18. The channel current of the MOSFET in Sx is proportional with its gate voltage from to . The current fall time can be approximated by 2 .

But in the actual circuit, the junction capacitor on Sy will always delay the voltage increase on Sx, as the dash line shown in Fig. 18. The equivalent circuit can be drawn in Fig. 19, where

and are mainly the output capacitance of the devices. includes the drain-source capacitance and gate-drain

capacitance of the MOSFET. is the junction capacitance of the series diode. When Sx is turned off, will be charged and will be discharged by the DC current. The

0 1 2 3 4 5 6 7 8 9 100

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charge or discharge time can be approximated by ⁄ , where .

The current fall time of Sx is determined by the larger of the two and is given by 2 , ⁄ . When is large and is small, is predominantly ⁄ . The charge gain of Sx or the charge loss of Sy can be approximated by 2⁄ .

Fig. 18. Theoretical turns off

waveform of Sx. Fig. 19. Sx turn off circuit with

parasitic capacitance.

The compensation time for turn-off process of Sx can be expressed by (4) when 0 . Its pulse width should be reduced when 0. The junction capacitance is a function of the voltage on the device [13][14]. A look-up table is built in a digital signal processor to estimate under different voltage conditions.

__ , , 2 (4)

D. Application of Proposed Compensation Method Based on the analysis above, the minimum overlap time ∆ is

the gate charge time 2 for both the turn-on and turn-off process. The compensation time for Sx is __ , __ , when 0 . Meanwhile, the pulse width of Sy should be reduced by __ , __ , when 0.

Take S1 in Fig. 1 as an example. S1 has switching behavior in 180� of a line period. The compensation pulse width in 6 sectors is listed in Table II for S1 and its complementary switch. The modulation scheme is Modified Fullwave Symmetrical Modulation (MFSM) [7].

TABLE II. COMPENSATION PULSE WIDTH Sector Compensation Pulse Width Voltage

10 S1 __ , __ , 0 S5 __ , __ ,

11 S1 __ , __ , 0 S5 __ , __ ,

12 S1 __ , __ , 0 S5 __ , __ ,

1 S1 __ , __ , 0 S3 __ , __ ,

2 S1 __ , __ , 0 S3 __ , __ ,

3 S1 __ , __ , 0 S3 __ , __ ,

E. Experimental Verification A 7.5 kW all-SiC three-phase buck rectifier was built (Fig.

20) [16], whose parameters are shown in Table III. 4-paralleled SiC MOSFETs and 2-paralled SiC Schottky diodes are connected in series for each switch in order to reduce the conduction loss.

Fig. 20. 7.5kW all-SiC buck rectifier.

TABLE III. THREE-PHASE CURRENT SOURCE RECTIFIER PARAMETERS Power Rating 7.5 kW

Input Voltage Rating Three-phase line-to-line 480 Vac,rms Input Inductor 110 µH each phase Input Capacitor 6 µF each phase

Output Voltage Rating 400 Vdc Output Inductor 1.9 mH Output Capacitor 150 µF

Switching Frequency 28 kHz Efficiency 98.5 %

Power Factor > 99 %

The parameters are listed in Table IV for the compensation formula (3) and (4). The time constant and turn-off delay

are measured in the converter and the parasitic inductance is estimated based on the PCB trace length. The parasitic capacitance is estimated based on the junction capacitance value provided in the device datasheets [13][14]. It is shown in Fig. 21 that decreases as the switching voltage increases.

TABLE IV. COMPENSATION PARAMETERS IN THE CONVERTER Time Constant 10 ns for turn on process

20 ns for turn off process Parasitic inductance 100 nH Turn-off delay 40 ns

Fig. 21. Cp under different switching voltage.

Experiments were carried out to verify the proposed compensation method. As shown in Fig. 22, the input current

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AC input capacitors

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Cold plateAC inductor connector

0 100 200 300 400 500 600 700 80010

-1

100

101

102

Switching Voltage (V)

Cp

(nH

)

will have much distortion when the overcompensated. With the proposed compensadistortion is largely reduced.

Fig. 22. Experiment results without (upper) and withcompensation (480Vac, 2.5A Idc).

In Figs. 23 to 26, the buck rectifier is operainput line-to-line voltage and 20A output curretraditional compensation method is applied witime. The overlap time is chosen to be longer ttime when the voltage is small. The input currwhen the line-to-line voltage crosses zero.

Based on the previous analysis, the overlareduced to accelerate the commutation. As sthe overlap time is only 100 ns, and the distorthan that in Fig. 23. Their harmonic comparFig. 27. The total harmonic distortion (THD1.9% to 1.4% with the reduced overlap time.

In Fig. 25, though the overlap time is scompensated based on the commutation modepaper. The distortion is reduced compared wharmonic comparison is shown in Fig. 28. Thfrom 1.9% to 1.7% with the pulse compensati

Small overlap time and the compensatiocommutation model are both used in Fig. almost no obvious distortion in the current harmonic comparison is shown in Fig. 29. Thfrom 1.9% to 1.3% with the proposed method

The compensation pulse width for S1 chathe experiment, as shown in Fig. 30. The turn-time Ton is largest when the voltage crosses zcompensation time Toff is small in this experiturn-off speed of S1 is high in this case.

Fig. 23. Experiment results with traditional(208 Vac, 20A Idc, 500 ns overlap tim

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Fig. 24. Experiment results with (208 Vac, 20A Idc, 100 ns

Fig. 25. Experiment results with(208 Vac, 20A Idc, 500 ns

Fig. 26. Experiment results wit (208 Vac, 20A Idc, 100 ns

Fig. 27. Harmonic reduction with(208 Vac, 20A

Fig. 28. Harmonic reduction with(208 Vac, 20A

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Fig. 29. Harmonic reduction with proposed method (208 Vac, 20A Idc).

Fig. 30. Compensation pule width for S1 (208 Vac, 20A Idc, 500 ns overlap time).

Fig. 31. Experiment results with traditional method (480 Vac, 5A Idc, 500 ns overlap time).

Fig. 32. Experiment results with proposed method (480 Vac, 5A Idc, 100 ns overlap time).

Fig. 33. Harmonic reduction with proposed method (480 Vac, 5A Idc).

Fig. 34. Compensation pule width for S1 (480 Vac, 5A Idc, 100 ns overlap time).

In Figs. 31 and 32, the buck rectifier is operating under 480V input line-to-line voltage and 5A output current. The proposed method can reduce the distortion in the current waveform. Their harmonic comparison is shown in Fig. 33. The THD decreases from 2.5% to 2.0% with the proposed method.

In this case, the turn-off speed is low under large voltage and small current. The turn-off compensation time Toff changes with the voltage in Fig. 34.

Because of the fast switching speed of SiC devices, the compensation pulse width is usually less than 300 ns. The distortion will be more severe when some lower speed devices are used or the input capacitor is small or the converter is operating at higher switching frequency. In these applications, the proposed method will bring more improvement to the current waveform.

III. IRREGULAR PULSE DISTRIBUTION AND ITS COMPENSATION

A. Distortion Caused by Irregular Pulse Distribution The irregular pulse distribution of the modulation usually

happens in the 12-sector modulation schemes. Different from 6-sector modulation, two sub-sectors are divided in each 60˚ sector according to the input current and voltage relationship, as shown in Fig. 2.

Fig. 35. Irregular pulse distribution in MFSM.

Fig. 36. Irregular pulse distribution in asymmetric modulation.

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Traditional, overlap=500nsProposed, overlap=100ns

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0 2 4 6 8 10 12 14 16 180

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Fig. 37. Pulse-based damping method.

The arrangement of the vectors will alternate in two sub-sectors to achieve the lowest switching voltage within a switching cycle. The vector arrangement change in two consecutive sectors is shown in Figs. 35 and 36 for Modified Fullwave Symmetrical Modulation (MFSM) [7] and 12-sector asymmetric modulation respectively [11].

B. Compensation Methods for Irregular Pulse The shaded area in Figs. 35 and 36 indicates the input current

of the buck rectifier. S1 and S5 have irregular pulse distribution at the boundary of Sector 10 and 11, as shown in both figures. An average function is applied to the pulse current with the average period of switching cycle . The average currents and deviate from the reference currents and near the boundary, which can be described by the extra charge ∆ . In Fig. 36, the peak value of can reach two times that of , while in Fig. 35 the peak value of is only 1.5 times that of . The extra charge ∆ in Fig. 36 is four times that of Fig. 35, so the distortion of 12-sector asymmetric PWM is much worse than the symmetric MFSM.

Two methods are proposed here to reduce the extra charge ∆ . The first is to increase the switching frequency near the boundary of the two sectors. In this way ∆ can be reduced because the deviation time is shortened. This method will bring more switching loss, which is acceptable since it only occurs near 6 sector boundaries on the space vector plane.

The second effective method is a pulse-based compensation method. As shown in Fig. 37, S1 has pulse width and S5 has pulse width ( and are duty cycles of S1 and S5 respectively and is the switching period). If the pulse width of S1 is reduced by , the deviation of from can be reduced. The current pulse is distributed more regularly at the sector change. The extra charge ∆ is split into two parts, ∆ and ∆ , each of which is smaller than ∆ . ∆ and ∆ can be given by (5). The optimal point for the pulse-based compensation is achieved when ∆ ∆ , . ∆ 1 ∆ 1 (5)

The simulation results given in Figs. 38 and 39 demonstrate that the pulse-based damping method can reduce the irregular pulse distribution and the input current distortion.

(a) (b) Fig. 38. Simulation of distortion during sector change:(a) Current on AC inductors; (b) Enlarged picture of the current distortion and gate signal.

(a) (b) Fig. 39. Simulation of distortion after compensation:(a) Current on AC inductors; (b) Enlarged picture of the current distortion and gate signal.

The pulse-based compensation method can only be applied to the asymmetric PWM. It will not increase the switching frequency and is easy to apply. Increasing the switching frequency near sector boundary can be widely applied to both symmetric and asymmetric PWMs.

C. Experimental Verification The three-phase buck rectifier in Fig. 20 is operating under

208 V input line-to-line voltage and 5A output current. Without compensation at the sector change, the irregular pulse causes current distortion in Fig. 40. The green curve in the figure is the gate signal of S1 and the black curve is the gate signal of S3. The arrangement of the two active vectors changes as shown in Fig. 40.

Fig. 40. Experiment results without irregular pulse compensation.

Fig. 41. Experiment results with pulse-based compensation.

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1 sTδδ1 sTδ

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6I 1I 0I 1I 6I 0Iai *

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10

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Fig. 42. Experiment results with increased switching frequency.

The pulse-based compensation is applied in Fig. 41, where the pulse width of S3 is reduced and the pulse width of S1 is increased to compensate the irregular pulse. The distortion is reduced compared with Fig. 40. The switching frequency is increased from 28 kHz to 40 kHz near the boundary of the two sectors in Fig. 42, where the distortion is also reduced.

However, there is still some distortion in the current waveform. It is because of the sliding intersection between two active vectors, as described in [6].

VI. CONCLUSIONS In this paper, a modified pulse-based compensation method

is proposed to compensate overlap time. In addition to the traditional method that places the overlap time based on the voltage polarity, the new method first minimizes the overlap time to reduce its effect and then compensates the pulse width according to the sampled voltage and current. The experiments have demonstrated its advantages over traditional methods especially when the switching voltage is near zero. Two methods are proposed to reduce the irregular pulse distribution during sector change within 12-sector modulation schemes. Besides increasing switching frequency, the pulse-based damping method can also reduce the deviation of the average current near the boundary of two consecutive sectors.

ACKNOWLEDGEMENT This work made use of Engineering Research Center Shared

Facilities supported by the Engineering Research Center Program of the National Science Foundation and DOE under NSF Award Number EEC-1041877 and the CURENT Industry Partnership Program.

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