computational synthesis of arbitrary floating impedances

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Int. J. Circ. ¹heor. Appl., 26, 463—475 (1998)

COMPUTATIONAL SYNTHESIS OF ARBITRARY FLOATINGIMPEDANCES

R. CABEZA* AND A. CARLOSENA

Dpto. de Ingenierıa Electrica y Electronica, Universidad Publica de Navarra, 31006-Pamplona, Spain

ABSTRACT

An algorithm for the synthesis of immittances is briefly described. Given a driving point immittance function andspecifying the number of nodes, the algorithm will generate all the networks fulfilling the specified function with thepredetermined number of nodes. This algorithm has been implemented with MathematicaTM in a desktop workstationwith excellent results. In order to demonstrate the usefulness of this algorithm, several examples are presented, withtheoretical and simulation analysis. ( 1998 John Wiley & Sons, Ltd.

KEY WORDS: impedance simulation; RC-active circuits; current conveyors; computational methods

INTRODUCTION

Technical literature in Circuit Theory is rich in papers proposing novel circuits to realize a given networkfunction of any kind such as a voltage or current transfer function, transimpedance, etc.1~5 Sometimes thesecircuits are simply proposed, giving no information about the procedure followed to obtain them, in case itexisted. In other cases, new circuits originate by applying given network transformations of properties toknown ones. In this process not only the topology of the circuit may change, but also the number and kind ofpassive and active devices. Finally, more systematic methodologies have been proposed to obtain newcircuits, in which case we can properly talk about methods of synthesis. Such methods can be roughly dividedinto two major classes: first, methods that are able to give at least one solution circuit for a number ofdifferent synthesis problems, and second, methods that generate all possible solution circuits for a particularproblem properly bounded. To give two representative example of each case, a method is proposed inReferences 6 and 7 that gives one circuit that possesses an input impedance of any order, while in Reference8 all single and variable frequency, second-order oscillators are generated.

Advantages and limitations of both kinds of methods are clear. In the first case, the method solves manysynthesis problems but the solution given is not necessarily optimum. In the second, the success is heavilybased on a correct delimitation of synthesis conditions so that the number of intermediate cases to analyse isnot so high, which makes the method time-consuming and unpractical. To avoid this limitation a computa-tional solution has been sometimes tried9 using a knowledge-based approach but the main problem is now todefine the synthesis rules for a number of different synthesis problems.

An alternative computational solution that obtains, at the same time, all solutions for several differentsynthesis problems is feasible today. This is possible thanks to some popular and readily available softwaretools, such as symbolic analysers, and simple workstations or high-performance PCs.

In this paper we present an algorithm that is potentially able (depending on time and memory limitations)to generate all circuits, represented in terms of nullors and passive elements, that possess a given floating

*Correspondence to: R. Cabeza, Dpto. de Ingenierıa Electrica y Electronica, Universidad Publica de Navarra, 31006-Pamplona, Spain.Email: [email protected]

CCC 0098—9886/98/050463—13$17.50 Received 24 February 1997( 1998 John Wiley & Sons, Ltd. Revised 2 February 1998

immittance in one of their ports. The algorithm states the minimum complexity for the circuit in terms ofnodes and active devices and then initiates an exhaustive analysis of all possible combinations. Then,impedance functions are calculated and further simplifications are accomplished in order to reduce thecircuit to the minimum complexity. The functions that match the proposed target, and the correspondingcircuit, are retained as possible solutions. To avoid computational explosion, a number of rules, based onnetwork properties, are incorporated to eliminate redundant or inconsistent cases and also mechanisms areintroduced to avoid duplication of calculation that have been previously accomplished.

The algorithm has been tested with some classical problems in which the solution is known, giving thecorrect results. It has been also applied to other more complex problems giving in this case new solutions toadd to the ones known so far. Computing times (several minutes) are reasonable for even complicatedsynthesis problems.

It should be apparent that it is not our intention to claim for better circuits than the ones reported so far byother authors. The algorithm we propose has to be applied to obtain all of the simplest circuits, expressed interms of nullors and passive impedances that possess a given input immittance. From this point, and oncea particular active device has been selected to implement the nullors, it should be possible to decide whichimplementation is best with regard to a given parameter such as bandwidth, noise, etc.

DESCRIPTION OF THE ALGORITHM

The starting point of all synthesis problems is a known network function. In our case, a function f will expressthe driving point immittance function that is sought. That is to say, suppose that we are interested inadmittances, networks will be sought that possess two nodes whose input admittance is given by

½IN"f (½

i) (1)

where ½irepresents an arbitrary one-port impedance. In most cases of interest, it will be however either

a resistor or capacitor.Let N be the number of variables of f. For example, in the case of a classic GIC, we have

½IN"

½1½

3½

5½

2½

4

(2)

then in this case N"5.If we want the synthesis algorithm to be as general as possible, then the active elements to be used have to

possess a generic character. For this reason, we opted to use nullors; see Figure 1. In this general sense, thestarting network will be completely connected, speaking in topological terms. That is to say, in the initialnetwork one and only one admittance exists between any two nodes.

A synthesis algorithm as the one described here, must be exhaustive and complete; in other words, it mustgenerate all the possible solutions to the problem. In our case, all the networks that fulfill equation (1) should

Figure 1. General scheme for the synthesis problem

464 R. CABEZA AND A. CARLOSENA

( 1998 John Wiley & Sons, Ltd. Int. J. Circ. ¹heor. Appl., 26, 463—475 (1998)

be obtained. To this end, a progessive method of synthesizing is proposed, that begins with networks witha reduced number of nodes, and later on progressively increases it. The need to put a superior bound to thisnumber of nodes is clear but, before solving this problem, we should differentiate between external nodes,labelled as 1 and 2 in Figure 1, and internal nodes which are anything else.

It is easy to understand that the case with the maximum number of nodes corresponds to the smallestdegree of incidence on each one of them. Thus, for an external node the minimum number of elements thatshould be incident on it is two, in case that it could not be simplified to a simpler structure. For an internalnode, however, this minimum number is three. Suppose that is being synthesized with M nullors, thefollowing relationships should be fulfilled

2N#4M"2]n%9#3]n

*/(3a)

n"n%9#n

*/(3b)

where n%9

represents the number of external nodes (obviously two), n*/

the internal ones, while n.!9

is thesuperior bound which is being sought. We recall that N is the number of variables of f. From (3a) and (3b) it isdeduced that

n.!9

"2#floor A2N#4(M!1)

3 B (4)

where the function floor(x) calculates the greatest integer less than or equal to x. Applying (4) to the previousexample of the GIC, Table I is obtained, varying accordingly the number of nullors required.

Once the number of nodes of the completely connected network is defined, the algorithm follows by thedefinition of the position of the M nullators and M norators. The most general base will be that in which alland each one of the possible positions for the active elements are studied. It is easy to demonstrate that thetotal number of possible locations of M nullors in a network of n nodes is given by

nT,A

nM2 B (5)

where

nM,A A

n

2BM B (6)

Again, for the case of the GIC, nT"5460, assuming a network with 6 nodes and 2 nullors. From this point

the study of all and each one of these possible structures could be undertaken. However this approximationwould be impractical, due to the calculation time required. To make the algorithm feasible, the number ofstructures to be studied should be reduced. To this end, the following criteria have been considered:

(i) Assuming the nullators/norators assimilated to two graphs, respectively, in such a way that each edgecorresponds to the position of these elements in the original network, it should be verified that eachone of these graphs is a forest. In other words, none of the two graphs can contain cycles.

Table I

M 2 3 4

n.!9

6 8 9

COMPUTATIONAL SYNTHESIS OF ARBITRARY FLOATING 465


(ii) Once the cycles are excluded, all those positions of the nullators/norators that were a relocation ofsome other will be withdrawn.

(iii) Those possibilities that contain either a nullator or a norator between the external nodes will be alsoexcluded, whether it were directly or by some reordering.

(iv) The last simplification is to withdraw those structures that have a nullator and a norator between thesame nodes, either directly or by a reordering.

Merging all these rules, a high degree of simplification is obtained. In complex situations, reduction factorsup to 14 000 can be reached.

Now, for each one of the possible positions of the active elements, the input admittances were calculated,½

'

IN, with the external nodes as the input port, making use of the method of the undefined admittance matrix.

Let us suppose that the function ½

'

INcalculated in this way depends on P admittances of the network. The last

step of the synthesis process should be to calculate all the possible subsets of N elements of thoseP admittances. For each one of these subsets, its complementary set is calculated, and then, each one of theP—N admittances present in that complementary is made to tend to 0. By doing so, a series of functions, ½

'

IN,

are obtained with N variables that will be compared to the original function (1). At this point of the process,the synthesis procedure could be considered concluded. Nevertheless, if we proceed in this way, a largenumber of useless solutions would be obtained, because they would be repetitions of previous ones. To avoidthis duplicity, and before doing any calculations, each new network that fulfils (1) is checked, to see if it is or isnot isomorphic, in the topological sense, with previous solutions. In order to do this, a weighted graphassociated with the obtained network is built in such a form that a weight of 1 is associated to the edge withan admittance, a weight of 2 for those associates with a nullator, and finally a weight of three for the norators.With this checking procedure, the synthesis process ends.

Further details of the implementation of the algorithm are out of the scope of this paper, but readersinterested in it are encouraged to contact the authors.

EXAMPLE

In order to illustrate the performance of the described algorithm, a real case of synthesis is detailed in the nextparagraphs. One of the most simple and well-known problems in the synthesis of immittance is the NegativeImpedance Convertor (NIC). For this system, equation (1) becomes

½IN"!

½1½

3½

2

(7)

The number of active elements and the nodes of the global net need to be calculated, according to (4), in orderto determine completely the synthesis problem. In our case, we will assume two active elements which givesfive nodes. With this starting point, the algorithm generates all possible positions for two nullators and twonorators in the five nodes net, and later on they will be coupled to obtain two nullors. The number ofpositions of a single nullator (norator) in a five node net is ten. Since in this synthesis problem there are twoactive elements, there are thus 45 possible pairs of nullators (norators). Finally, if we make couples among theset of nullators and norators, we obtain 990 positions for two nullors in a five nodes net. However, thealgorithm drastically reduces this number. First reduction is produced among the 45 pairs of two nullators(norators). Rows and columns in Table II represent the ten possible positions for each nullator (norator) byits node numbers. Each entry in this table has a number with a different significance: 1 means that there is atleast one cycle; 2 means that a nullator or a norator is connected between external nodes, and then it can berejected; 3 means that this position is a relocation of a previous one and finally 0 indicates that the positionfulfills all requirements to pass into the next stage. Counting in Table II, 19 entries are obtained which arevalid to build nullors with them. In Table III these 19 cases are shown (rows and columns) with their 171corresponding values: 1 means that a nullator is in parallel with a norator; 2 means that a reordering of that



Table II

M1,2NM1,2N 2 M1,3NM1,3N 2 1 M1,4NM1,4N 2 0 1 M1,5NM1,5N 2 0 0 1 M2,3NM2,3N 2 2 0 0 1 M2,4NM2,4N 2 0 2 0 0 1 M2,4NM2,5N 2 0 0 2 0 0 1 M3,4NM3,4N 2 3 3 0 3 3 0 1 M3,5NM3,5N 2 3 0 3 3 0 3 0 1 M4,5NM4,5N 2 0 3 3 0 3 3 3 3 1

Table III

MM1,3N, M1,4NNMM1,3N, M1,4NN 1 MM1,3N, M1,5NNMM1,3N, M1,5NN 1 1 MM1,3N, M2,4NNMM1,3N, M2,4NN 1 1 1 MM1,3N, M2,5NNMM1,3N, M2,5NN 1 1 1 1 MM1,3N, M4,5NNMM1,3N, M4,5NN 1 1 1 1 1 MM1,4N, M1,5NNMM1,4N, M1,5NN 1 1 0 0 2 1 MM1,4N, M2,3NNMM1,4N, M2,3NN 1 0 0 0 0 1 1 MM1,4N, M2,5NNMM1,4N, M2,5NN 1 0 0 1 0 1 1 1 MM1,4N, M3,5NNMM1,4N, M3,5NN 1 2 0 0 0 1 1 1 1 MM1,5N, M2,3NNMM1,5N, M2,3NN 0 1 0 0 0 1 1 0 0 1 MM1,5N, M2,4NNMM1,5N, M2,4NN 0 1 1 0 0 1 0 0 0 1 1 MM1,5N, M3,4NNMM1,5N, M3,4NN 2 1 0 0 0 1 0 0 0 1 1 1 MM2,3N, M2,4NNMM2,3N, M2,4NN 2 0 1 0 0 0 1 0 0 1 1 2 1 MM2,3N, M2,5NNMM2,3N, M2,5NN 0 2 0 1 0 0 1 1 2 1 0 0 1 1 MM2,3N, M4,5NNMM2,3N, M4,5NN 0 0 0 0 1 2 1 0 0 1 0 0 1 1 1 MM2,4N, M2,5NNMM2,4N, M2,5NN 0 0 1 1 2 2 0 1 0 0 1 0 1 1 2 1 MM2,4N, M3,5NNMM2,4N, M3,5NN 0 2 1 0 0 0 0 0 1 0 1 0 1 2 0 1 1 MM2,5N, M3,4NNMM2,4N, M3,4NN 2 0 0 1 0 0 0 1 0 0 0 1 2 1 0 1 0 1 MM3,4N, M3, 5NNMM3,4N, M3,5NN 2 2 0 0 2 2 0 0 1 0 0 1 2 2 2 2 2 2 1

position leads to the previous condition; and finally 0 means again that the associated nullors fulfill allrequirements. In Table II, 81 valid cases can be counted. So the proposed algorithm has reduced the totalnumber of configuration to be calculated by a factor of 12.

For each one of these 81 valid positions, the input admittance is calculated. In the next paragraphs, thesimplification process for expressions is outlined. We consider two representative cases. The first one isassociated with the following position for the two nullors: MMM1, 3N, M2, 4NN, MM1, 4N, M1, 5NNN. In this case the



input admittance is shown by the following equation

½ªIN"

½23½25#½

25½34#½

12½35#½

23½35#½

25½35

½35

(8)

where ½ij

is obviously the admittance connecting nodes i and j.Applying the method outlined above, we must simplify these expressions to obtain a function with three

variables. Since (8) is a function of five variables, and (7) has three we must calculate all subsets with twoelements of these admittances, and then they are made to tend to 0. In this manner we obtain ten expressions.However, six of them must be discarded because they suffer from indeterminations or dependencies with twovariables or less. So, the surviving four expressions are shown in Table IV.

By inspecting these four expressions, it is easy to conclude that the current position of nullors is notappropriate for the synthesis of expression (7).

The next case under study is the first one that gives successful results: MMM1, 3N, M4, 5NN, MM1, 4N, M3, 5NNN.Now the input admittance is

½ªIN"

½12

½15#½

15½23#½

15½24!½

23½24

#½12½25#½

15½25!½

12½34!½

23½24!½

24½34!½

25½34

½15#½

25!½

34(9)

In this expression there are six different admittances, so, there are 20 simplified related ones, but ten of themare again pathological; the remaining ones are shown in Table V. The element at row three and column onefulfils the initial requirements.

Table IV

½xIN"

½12

½35#½

23½35

½35

½xIN"

½12

½35#½

25½35

½35

½xIN"

½23

½25#½

23½35#½

25½35

½35

½xIN"

½25

½34#½

25½35

½35

Table V

½{IN"

½12

½15#½

12½25#½

15½25

½15#½

25

½xIN"

½12

½25!½

12½34!½

25½34

½25!½

34

½xIN"

½15

½23#½

15½24!½

23½24

½15

½xIN"

½15

½23#½

15½25

½15#½

25

½xIN"

½15

½24#½

15½25

½15#½

25

½xIN"

½15

½25!½

25½34

½15#½

25!½

34

½xIN"!

½23

½24

½25

½xIN"

½23

½24#½

23½34#½

24½34

½34

½xIN"

½23

½34#½

25½34

½25!½

34

½xIN"

½24

½34#½

25½34

½25!½

34



Table VI

MM1,3N, M4,5NN MM1,5N, M3,4NN ½xIN"!

½23½25

½24


½24½25

½23


½13½14

½15


½13½15

½14


½14½15

½13

Among all the rest of the positions for two nullors, another five solutions, shown in Table VI, can be found.It is easy to demonstrate that the six solutions found are isomorphic in the topological sense. So this allows tostate that there is a unique solution for expression (7) using two nullors in a five node net.

All of the above calculations take less than 2 min on a personal computer.

PRACTICAL CASES

In this section we develop the study of various examples. It is necessary to point out that in spite of the factthat the above example only considers simple resistors and capacitors as possible admittances, the describedalgorithm is completely general. They could be, for instance, an inductor or a resistor and capacitors in series.These restrictions are used in order to compare the results of the algorithm with results from classicalRC-active synthesis.

Example I. Our first application for the algorithm presented above is a second-order general impedance.Let us assume that the following functional form for a floating impedance is to be designed:

Z1~2

"Z1#

Z1Z

3Z

2

#

Z1Z

3Z

5Z

2Z

4

(10)

Its application to simulate an arbitrary second-order impedance is clear, or for instance a series connection ofcapacitor, inductor and resistor. This has a direct application to the synthesis of biquadratic filters. A similarfunctional dependence has been studied by Hilberman7 but working with admittances and in a more genericframework, see Example III in this section. Also, Higashimura10 has used such impedance within a similarcontext.

For this kind of impedance, the result provided by the algorithm is the set of four circuits shown in Figure2. Four more have to be added resulting from the interchange of all nullators by norators, i.e. an adjointtransformations,11 which results in equivalent impedances. Relocation of nullators (norators) is also possiblein Figure 2(a) (adjoint of Figure 2(a)). We would like to remember that all these nullor topologies, and thepractical circuits originated from them are completely novel and much simpler than the solutions given inReferences 7 and 10.

Regarding the practical implementation, and considering existing active devices, the following conclusionsarise:

1. Opamps can be used to implement the impedance shown in Figure 2(a) in case it is grounded (terminal1 grounded, and nullators and norators interchanged). In contrast, it cannot be implemented withCCII!.



Figure 2. New four structures to implement equation (10)

Figure 3. CCII! implementations for Figures 2(b) and (c)

2. Circuits shown in Figures 2(b) and 2(c) can be implemented with two CCII!, Figures 3(a) and (b),respectively. Note that in Hilberman’s refereed work, to obtain a functionality equivalent to (10), threeVUGA (i.e. CCII!) are necessary. In order to swap in (10) impedance by admittance it is enough toinsert one admittance between nodes 1 and 2 in Figures 2, and remove admittance 1 or 4; see Figure 7.On the other hand, Higashimura uses at least three CCII#.

3. Circuit shown in Figure 2(d) is only feasible by making use of two active devices implementinga nullor.12 It goes without saying that any of the others are also possible with nullors.

Note the huge number of possible practical impedances that result from the four (eight in fact) possibletopologies combined with the choice of the active devices and also the selection of Z

1through Z

5. In this

way, the general impedance given by expression (10) can be used to implement a variety of frequency forms,depending on the particular choices for each Z

i. Restricting ourselves to the cases where each one out of three



terms in (10) is of different order, the possibilities are limited to the following:

R1#

R1

C3R

2s#

R1

C3C

5R

2R

4s2

(11a)

R1#C

2R

1R

3s#C

2C

4R

1R

3R

5s2 (11b)

1

C1s#

1

C1C

3R

2s2#

1

C1C

3C

5R

2R

4s3

(11c)

1

C1s#

C2R

3C

1

#

C2C

4R

3R

5s

C1

(11d)

It is easy to interpret each expression in terms of the series of impedances they represent. The last onesimulates an RLC series circuit, being much simplier and general than the one recently published inReference 13.

To give a practical example of the performance of these impedances, we will use the simple voltage dividershown in Figure 4. Combining Z

6(either capacitor or resistor) and the four possible forms in expressions (11),

several different transfer functions are obtained, mainly second and third order filters. Suppose for instanceZ

6"R

6and Z

1~2as in expression (11a). The resulting (high-pass) filter can be now be implemented by

making use of any of the four topologies. In case we were forced to use (negative) current conveyors, then onlyFigures 2(b) and 2(c) would be suitable.

Several configurations have been simulated making use of a complete model of a CCII-bipolar implemen-tation.12 The two high-pass filters mentioned above will be shown here as representative examples.Magnitude frequency response is shown in Figure 5, where resistor and capacitor values are in all cases 1 k)and 10 nF, respectively, giving a cut-off frequency around 10 kHz. Both circuits deviate from the idealresponse at low frequencies, this effect being more severe with the circuit shown in Figure 2(b). An analyticalprediction of such a behaviour is not easy to interpret due to the complexity of the circuits and also the needfor a complex model for the CCII. However, many parameters have been modified along the simulationprocess in order to investigate their effects in the circuit performance. The conclusions are mainly two:

(a) Implementation of the circuit shown in Figure 2(b) with CCII- is particularly sensitive to the currenttransfer function between Z and X terminals.

(b) On the other hand, implementation of the circuit shown in Figure 2(c) with CCII- is sensitive to thevoltage transfer function between X and ½.

Deviations as low as 0)001 from the ideal value, unity in both cases, reflect in the dramatic changes in thecurves of Figure 5. Note that conventional CCII implementations are composed by open-loop voltage andcurrent buffers with voltage and current tracking errors of this order and even larger.

These two facts are also true, and even more important, in other filters made up of the same two circuits.Therefore, the conclusions can be generalized to the circuits at hand and possibly extended to other CCII

Figure 4. Simple voltage divider using floating impedance implementation



Figure 5. Magnitude response for a low-pass filter: (—) ideal response; (— — ) implementation with figure 3(a); ( ) ) ) ) ) implementation withFigure 3(b)

Figure 6. Two nullor structures with input admittance given by (9)

circuits proposed in the literature but never practically demonstrated. Current conveyors are extremelypowerful devices, particularly in open-loop configurations, but cautions have to be taken when embedded inmultiple feedback loops.

Example II. The second application for the algorithm is based on the next input admittance:

½IN"½

1#

½1½3

½2

(12)

In this case, the output obtained from the program is represented in Figure 6. The first topology, given inReference 14, can be implemented with two opamps or two CCII!, while the novel (b) and (c) cases can onlybe implemented with CCII!.

Example III. The third example of the use of the algorithm gives more fruitful results and represents thegeneralization of the above one. In this case the function to seek is

½IN"½

1#

½1½3

½2

#

½1½3½5

½2½4

(13)



Figure 7. Dual structures from Figure 2, implementing expression (10)

At least two nullors are needed to obtain this functionality. The synthesis algorithm finds four possiblestructures, shown in Figure 7. The case (a) is feasible with opamps, while the cases (b) and (c) need CCII-s.However, case (d) can only be carried out with a complete implementation for the nullor. Obviously,expression (13) is the dual one for expression (10), so Figures 2 and 7 are directly related.

Expression (13) has an additional interest. This kind of functionality represents one of the simplest cases inthe general synthesis procedure proposed by Hilberman.6 This procedure pursues the generation ofadmittances whose expression is of the polynomial type, i.e.

½IN"a

0#a

1s#a

2s2#2#a

nsn (14)

with the coefficients aibeing negative, positive or zero. In order to synthesize this kind of admittances,

assuming positive coefficients, the following expression can be used:

½IN"½

1#

½1½3

½2

#

½1½3½5

½2½4

#2 (15)

where the even admittances are resistances, and the odd ones are capacitors with normalized value. Thus,expression (13) represents the case of order two of (14). Now the first difference is apparent. While Hilbermanuses three CCII! to implement (13), the new method demonstrates that two are needed at the most. Thisadvantage can be generalized by observing that an expression as (14) can be obtained nesting the followingbasic functions:

½IN"a

1½1#a

2

½1½3

½2

(16a)

½IN"b

1½1#b

2

½1½3

½2

#b3

½1½3½5

½2½4

(16b)



Table VII

1 2 3 4 5 6

a0

# # ! ! 0 0a1

# ! # ! # !

New 2 2 3 2 3 2Classical 2 4 4 5 3 4

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

b0

# # # # ! ! ! ! # # ! ! 0 0 0 0 0 0b1

# # ! ! # # ! ! 0 0 0 0 # # ! ! 0 0b2

# ! # ! # ! # ! # ! # ! # ! # ! # !

New 2 3 3 3 3 5* 3 3 3 3 3 5* 3 5* 3 3 2 5*Classical 3 5 5 5 6 6 6 7 4 5 5 6 4 5 5 6 3 5

with

ai, b

i"#1, 0,!1 and a

2, b

3O0 (17)

These 24 possible functionalities have been synthesized through the proposed algorithm obtaining satisfac-tory results. Table VII gathers the minimum number of necessary CCII! in order to obtain each case of(13). The structures labelled with an asterisk in this table have a number of active elements that have not beentested with the algorithm. So these numbers are just an estimation.

As an example of the improvement proposed, one case described in Reference 6 is taken, where thefollowing function is synthesized:

½IN"!2s6#3s5#5s4!4s3!2s2#s#10 (18)

In order to obtain this input admittance through the basic function of (13), and Table VII, we would nest theblock number eight of such a table, in the form

½IN"½

1#

½1½3

½2

!

½1½3

½2½4C½5

#

½5½7

½6

!

½5½7

½6½8A½9

#

½9½11

½10

!

½9½11½13

½10½12BD (19)

Therefore, we would use seven resistors, six capacitors and nine CCII!. In contrast, Hilberman’s methoduses 11 resistors, six capacitors and 11 CCII!. Furthermore, he had to impose several design conditionsbetween resistances, restrictions that are not needed in the synthesis method proposed in this paper.

CONCLUSIONS

In this paper we have demonstrated the feasibility of a computational algorithm, implemented in Mathemat-icaTM, to obtain all possible nullor networks that realize a given impedance function. The program is onlylimited by computer memory. Novel topologies for the simulation of a particular kind of impedance resultingfrom this approach, have been shown. Implementations with opamps, nullors and CCII! have beensuggested and some examples, in the latter case, tested by simulation. While the feasibility of the circuits wasdemonstrated, some limitations were identified which must to be taken into account when designing multiplefeedback circuits with CCIIs as the base active device.

A similar methodology can be extended for the solution of other different problems such as transferfunction synthesis.



ACKNOWLEDGEMENTS

The Gobierno de Navarra (OF 441/92, OF 497/93) and Ministerio de Educacion Ciencia (TIC94/0544) areacknowledged for financial support. Also we would like to thank the anonymous reviewers, who with theircomments have contributed to clarify some confusing concepts introduced in the original version of thispaper.

REFERENCES

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computational synthesis of arbitrary floating impedances

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