computer organization and networks - tu graz
TRANSCRIPT
![Page 1: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/1.jpg)
Computer Organization and Networks(INB.06000UF, INB.07001UF)
Winter 2019/2020
Stefan Mangard, www.iaik.tugraz.at
Chapter 4: Basics on Processors
![Page 2: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/2.jpg)
The Limitation of State Machines
• The State machines that we have discussed so far have been designed for a specific application (e.g. controlling traffic lights)
• Changing the application requires building a new state machine, new hardware, …
• We want to have a general purpose machine that • Can be used for all kinds of different applications• Can be reconfigured quickly
We want general purpose hardware that is “configured” for a particular application by software
www.iaik.tugraz.at
2
![Page 3: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/3.jpg)
How do Build This?
• There are several approaches towards building a state machine (a processor) that is controlled by software to perform a given task
• The most widely used approach is the Von Neumann Model – it is the basis of x86 and ARM CPUs
• It was proposed in 1945 by John Von Neumann (born in Budapest)
www.iaik.tugraz.at
3
![Page 4: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/4.jpg)
Von Neumann Model
www.iaik.tugraz.at
4
![Page 5: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/5.jpg)
Von Neumann Model
• Components of a computer built based on Von Neumann
• Processing Unit
• Control Unit
• Memory
• Input
• Output
• Bus
www.iaik.tugraz.at
5
![Page 6: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/6.jpg)
Von Neumann Model
www.iaik.tugraz.at
6
Processing Unit
Control Unit
Bus
Output(Monitor, Printer, Network, Disc, …)
Input(Keyboard, Disc,
Network, …)
CPUMemory
![Page 7: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/7.jpg)
Von Neumann Model
www.iaik.tugraz.at
7
Processing Unit
Control Unit
Bus
Output(Monitor, Printer, Network, Disc, …)
Input(Keyboard, Disc,
Network, …)
CPUMemory
Data Registers
Program Counter
Instruction Register
ALU
![Page 8: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/8.jpg)
Arithmetic Logic Unit (ALU)
www.iaik.tugraz.at
8
• The ALU is a combinational circuit performing calculation operations
• Basic Properties• Takes two inputs (A, B)
• Performs an operation based on one or both inputs
• Returns an output
ALU
![Page 9: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/9.jpg)
Data Registers (Register File)
www.iaik.tugraz.at
9
Data Registers
x0
x1
x2
x3
x4
x31
…
![Page 10: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/10.jpg)
Data Registers (Register File)
www.iaik.tugraz.at
10
Data Registers
x0
x1
x2
x3
x4
x31
…
Operand A
Operand B
Sel_A
Sel_B
![Page 11: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/11.jpg)
Data Registers (Register File)
• Basic Properties• Data registers with two
output MUX
• Input is stored in any one of the registers (selection via write_selsignal)
• Typical register sizes: 8, 16, 32, 64 bit
www.iaik.tugraz.at
11
Data Registers
x0
x1
x2
x3
x4
x31
…
Operand A
Operand B
Sel_A
Sel_B
Input
write_sel
![Page 12: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/12.jpg)
Processing Unit
• The processing unit constitutes the data path of the CPU
• Based on control signals that are provided as inputs operations are performed in the ALU and data registers are updated
• Where do we get the control signals from?
www.iaik.tugraz.at
12
Processing Unit
Data Registers
ALU
![Page 13: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/13.jpg)
Instruction Register
• The instruction register stores the instruction that shall be executed by the data path
• The instruction decoder maps the instruction register to control signals
• Where do the instructions come from?
www.iaik.tugraz.at
13
Control Unit
Program Counter
Instruction Register
Instruction Register
InstructionDecoder
ControlSignals
![Page 14: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/14.jpg)
Von Neumann Model
www.iaik.tugraz.at
14
Processing Unit
Control Unit
Bus
Output(Monitor, Printer, Network, Disc, …)
Input(Keyboard, Disc,
Network, …)
CPUMemory
Data Registers
Program Counter
Instruction Register
ALU
![Page 15: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/15.jpg)
Memory address
write(0: don’t write,1: write)
data input
data output
15
00: 8320000204: 0321400208: 832000020C: 0321400210: B381200014: 2324300218: 730010001C: 0000000020: 0000000024: 0000000028: 2A0000002C: 0D000000
….
www.iaik.tugraz.at
![Page 16: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/16.jpg)
Main memory is a “RAM”
Random Access Memory
(“Memory where arbitrary read and write accesses can be performed”)
16
www.iaik.tugraz.at
![Page 17: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/17.jpg)
Reading from memory
010101 … 1010101
Reading from memory
17
www.iaik.tugraz.at
![Page 18: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/18.jpg)
Writing to Memory
Reading from memory
Writing to memory
010101 … 1010101
18
www.iaik.tugraz.at
![Page 19: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/19.jpg)
A Word in Memory in Case of a 32-bit System
Reading
Writing
010101 … 010101Word in memory(“Speicherwort”)
19
1 Word consists of 32 bit = 4 byte
www.iaik.tugraz.at
![Page 20: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/20.jpg)
Each Byte in Memory Has an Address
010101 … 1010101
010101 … 1010101110100 … 0011101010111 … 1000001010101 … 1010101110100 … 0011101010111 … 1000001010101 … 1010101110100 … 0011101010111 … 1000001
010101 … 1010101110100 … 0011101010111 … 1000001110100 … 0011101010111 … 1000001010111 … 1000001
00:04:08:0C:10:14:18:1C:20:24:28:2C:30:34:38:3C:
Address:
20
Address
(increment by 1 is an increment of the position
by 1 byte)
1 Word = 4 byte = 32 bit
www.iaik.tugraz.at
![Page 21: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/21.jpg)
The Indices of the Bits Within a Word in Memory
010111 … 1000001
Address:
Bit 31 Bit 0
21
00:04:08:0C:10:14:18:1C:20:24:28:2C:30:34:38:3C:
010101 … 1010101
010101 … 1010101110100 … 0011101010111 … 1000001010101 … 1010101110100 … 0011101010111 … 1000001010101 … 1010101110100 … 0011101
010101 … 1010101110100 … 0011101010111 … 1000001110100 … 0011101010111 … 1000001010111 … 1000001
www.iaik.tugraz.at
![Page 22: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/22.jpg)
Memory0x00
0x01
0x02
0x03
0xFF..FF
0001001 … 110100
address(32 wires,where to read from or where to store to)
write(1 wire0: don’t write,1: write)
data input (32 wires)
data output
(32 wires)
clk (when to store)
0001001 … 110100
0001001 … 110100
0001001 … 110100
0001001 … 110100
22
www.iaik.tugraz.at
![Page 23: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/23.jpg)
Our CPUprogram counter
instruction register
registerfile
(R0…RF)
address(32 wires,
where to read from or where to store to)
data output
(32 wires)
datainput
(32 wires)
write(1 wire0: read,1: write)
controllogic
23
www.iaik.tugraz.at
![Page 24: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/24.jpg)
CPU + Memory + Bus
clk25
www.iaik.tugraz.at
![Page 25: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/25.jpg)
CPU is Active, Memory is Passive
address
write
cpu_din
cpu_dout
clk 26
www.iaik.tugraz.at
![Page 26: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/26.jpg)
CPU’s Job: Fetch, Decode, and Execute
address
write
cpu_din
cpu_dout
clk
PC = 0x00;while(1) {
IR = memory[PC];PC= PC + 4;if (IR == 0)
break;else
execute instruction;}
27
www.iaik.tugraz.at
![Page 27: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/27.jpg)
Example: Content in Main Memory
address
write
cpu_din
cpu_dout
clk
PC = 0x00;while(1) {
IR = memory[PC];PC=PC + 4;if (IR == 0)
break;else
execute instruction;}
28
00: 8320000204: 0321400208: 832000020C: 0321400210: B381200014: 2324300218: 73001000
….
www.iaik.tugraz.at
![Page 28: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/28.jpg)
(1) Initialize PC with 0x00
address
write
cpu_din
cpu_dout
clk
00: 123401: 234502: ????03: ????
.
.10: 810011: 820112: 000013: ????
PC: 00
IR: ????
PC = 0x00;while(1) {
IR = memory[PC];PC=PC+4;if (IR == 0)
break;else
execute instruction;}
X0: 0000
X1: ????
X2: ????
X3: ????
29
00: 8320000204: 0321400208: 832000020C: 0321400210: B381200014: 2324300218: 73001000
….
www.iaik.tugraz.at
![Page 29: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/29.jpg)
(2) Fetch First Instructionaddress
=00
write = 0
cpu_din = 83200002
cpu_dout
clk
00: 123401: 234502: ????03: ????
.
.10: 810011: 820112: 000013: ????
PC: 00
IR: 83200002
PC = 0x00;while(1) {
IR = memory[PC];PC=PC+4;if (IR == 0)
break;else
execute instruction;}
X0: 0000
X1: ????
X2: ????
X3: ????
30
00: 8320000204: 0321400208: 832000020C: 0321400210: B381200014: 2324300218: 73001000
….
www.iaik.tugraz.at
![Page 30: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/30.jpg)
(3) Increment Value in PC
cpu_dout
clk
00: 123401: 234502: ????03: ????
.
.10: 810011: 820112: 000013: ????
PC: 04
IR: 83200002
PC = 0x10;while(1) {
IR = memory[PC];PC++;if (IR == 0)
break;else
execute instruction;}
X0: 0000
X1: ????
X2: ????
X3: ????
address
write
cpu_din
31
00: 8320000204: 0321400208: 832000020C: 0321400210: B381200014: 2324300218: 73001000
….
www.iaik.tugraz.at
![Page 31: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/31.jpg)
(4) Decode and Execute Machine Instruction 0x83200002
cpu_dout
clk
00: 123401: 234502: ????03: ????
.
.10: 810011: 820112: 000013: ????
PC: 04
IR: 83200002
PC = 0x10;while(1) {
IR = memory[PC];PC++;if (IR == 0)
break;else
execute instruction;}
X0: 0000
X1: ????
X2: ????
X3: ????
address
write
cpu_din
32
00: 8320000204: 0321400208: 832000020C: 0321400210: B381200014: 2324300218: 73001000
….
www.iaik.tugraz.at
![Page 32: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/32.jpg)
Machine Instructions
• What does it mean to execute machine instruction 0x83200002 ?
• Who defines this?
• How many different instructions are there?
• How many instructions do we need?
www.iaik.tugraz.at
33
![Page 33: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/33.jpg)
Instruction Set Architectures
www.iaik.tugraz.at
40
![Page 34: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/34.jpg)
Instruction Set Architecture (ISA)
• An instruction is the basic unit of processing on a computer
• The instruction set is the set of all instructions on a given computer architecture
• Options to represent instructions• Machine language:
• A sequence of zeros and ones, e.g. 83200002 this is the sequence of zeros and ones the processor takes into its instruction register for decoding and execution
• Length varies can be many bytes long (up to 15 bytes on x86 CPUs)
• Assembly language:• This is a human readable representation of an instruction, e.g. ADD x3, x1, x2
• The ISA is the interface between hardware and software
www.iaik.tugraz.at
41
ISA
Software
Hardware
![Page 35: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/35.jpg)
Instruction Set Architectures
• There are many instruction set architectures from different vendors• Examples: Intel x86, AMD64, ARM, MIPS, PowerPC, SPARC, AVR, RISC-V, …
• Instruction sets vary significantly in terms of number of instructions• Complex Instruction Set Computer (CISC)
• Hundreds of instructions that include instructions performing complex operations like entire encryptions• Examples: x86 and x64 families
• Reduced Instruction Set Computer (RISC)• Instruction set including just basic operations (Motivation: less complexity in hardware and compilation,
speed)• Examples: ARM, RISC-V
• One Instruction Set Computer (OISC)• Computers with a single instruction (academic), e.g. SUBLEQ
see https://en.wikipedia.org/wiki/One_instruction_set_computer
www.iaik.tugraz.at
42
![Page 36: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/36.jpg)
Competition between Instruction Sets
• Given a fixed program (e.g. written in C), which instruction leads
• to the smallest code size (the smallest number of instructions need to express the program)?
• to best performance on a processor implementing the ISA?
• lowest power consumption on a processor implementing the ISA?
• …
www.iaik.tugraz.at
43
![Page 37: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/37.jpg)
Open vs. Closed Instruction Sets
• Most instruction sets are covered by patentsBuilding a computer that is compatible with that instruction set requires
patent licensing
• RISC-V (the instruction set of this course) • is open
• developed at UC Berkeley
• An instruction family from low-end 32bit devices to large 64bit CPUs
• Significant momentum in industry and academia
• More information and full specs available at https://riscv.org/
www.iaik.tugraz.at
44
![Page 38: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/38.jpg)
www.iaik.tugraz.at
45
Processing Unit
Control Unit
Bus
Output(Monitor, Printer, Network, Disc, …)
Input(Keyboard, Disc,
Network, …)
Memory
Data Registers
Program Counter
Instruction Register
ALU
![Page 39: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/39.jpg)
First RISC-V Basics
www.iaik.tugraz.at
46
![Page 40: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/40.jpg)
Basics
www.iaik.tugraz.at
47
The base instruction set has fixed-length 32-bit instructions
What information do include in the 32
bit?
• The operation to be executed
• Parameters (e.g. source registers, target register, constants)
![Page 41: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/41.jpg)
www.iaik.tugraz.at
48
• Opcode, funct3, funct7: definition of the functionality
• Imm: immediate values (constants)
• rs1, rs2: source registers
• rd: destination register
![Page 42: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/42.jpg)
Example
www.iaik.tugraz.at
49
![Page 43: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/43.jpg)
Example
www.iaik.tugraz.at
50
![Page 44: Computer Organization and Networks - TU Graz](https://reader030.vdocuments.net/reader030/viewer/2022013001/61cace99682d8e6436278823/html5/thumbnails/44.jpg)
Example
www.iaik.tugraz.at
51