computer organization & architecture - unify study · 2020. 9. 28. · computer architecture...
TRANSCRIPT
COMPUTERORGANIZ ATION &
ARCHITECTURE
FOR UGC NET, GATE & PHD ENTRANCE
COMPUTER ORGANIZATION AND ARCHITECTURE
• Machine instructions and addressing modes.
ALU, data‐path and control unit. Instruction
pipelining. Memory hierarchy: cache, main
memory and secondary storage; I/O interface
(interrupt and DMA mode).
Register Transfer and Microoperations: Register Transfer Language,
Bus and Memory Transfers, Arithmetic, Logic and Shift Microoperations.
Basic Computer Organization and Design: Stored Program
Organization and Instruction Codes, Computer Registers, Computer
Instructions, Timing and Control, Instruction Cycle, Memory-Reference
Instructions, Input-Output, Interrupt.
Programming the Basic Computer: Machine Language, Assembly
Language, Assembler, Program Loops, Subroutines, Input-Output
Programming.
Microprogrammed Control: Control Memory, Address Sequencing,
Design of Control Unit.
Central Processing Unit: General Register Organization, Stack Organization,
Instruction Formats, Addressing Modes, RISC Computer, CISC Computer.
Pipeline and Vector Processing: Parallel Processing, Pipelining, Arithmetic Pipeline,
Instruction Pipeline, Vector Processing Array Processors.
Input-Output Organization: Peripheral Devices, Input-Output Interface,
Asynchronous Data Transfer, Modes of Transfer, Priority Interrupt, DMA, Serial
Communication.
Memory Hierarchy: Main Memory, Auxillary Memory, Associative Memory, Cache
Memory, Virtual Memory, Memory Management Hardware.
Multiprocessors: Characteristics of Multiprocessors, Interconnection Structures,
Interprocessor Arbitration, Interprocessor Communication and Synchronization, Cache
Coherence, Multicore Processors.
Previous
Year
Total No of
Questions
Topics
Dec 2019 9 Question 8085 Programming -1 Q
Matching from COA basic
Addressing mode numerical -1Q
Numerical from memory unit – 1Q
System call – 1 Q
Microinstruction format numerical – 1Q
I/O interface – 1Q
Pipeline – 1Q
RISC Characteristics – 1Q
UGC NET Previous Years Analysis
June 2019 7 Question Numerical from memory unit – 2Q
Types of memory – 1 Q
Micro program control unit – 1Q
Encoder decoder numerical – 1Q
Addressing mode – 1Q
Machine Instruction Numerical – 1Q
Dec 2018 4 Question 2 level cache – 1Q
Numerical from memory unit – 1Q
Addressing modes – 1 Q
Interrupt – 1 Q
UGC NET Previous Years Analysis
2020 6 Question Numerical from memory unit – 1Q
Interrupt and DMA – 1Q
Multiplexer Numerical – 1Q
Memory mapping with cache numerical – 1Q
Instruction format numerical – 1Q
Pipeline Numerical– 1Q
GATE Previous Years Analysis
Computer architecture deals with the logical and physical design of a computer
system. The Instruction Set Architecture (ISA) defines the set of machine-code
instructions that the computer's central processing unit can execute. The
microarchitecture describes the design features and circuitry of the central
processing unit itself. The system architecture (with which we are chiefly concerned
in this section) determines the main hardware components that make up the
physical computer system (including, of course, the central processing unit) and the
way in which they are interconnected. The main components required for a
computer system are listed below.
•Central processing unit (CPU)
•Random access memory (RAM)
•Read-only memory (ROM)
•Input / output (I/O) ports
•The system bus
•A power supply unit (PSU)
The core system components are mounted on a backplane, more
commonly referred to as a mainboard (or motherboard). The mainboard is a
relatively large printed circuit board that provides the electronic channels
(buses) that carry data and control signals between the various
components, as well as the necessary interfaces (in the form of slots or
sockets) to allow the CPU, Memory cards and other components to be
plugged into the system. In most cases, the ROM chip is built in to the
mainboard, and the CPU and RAM must be compatible with the
mainboard in terms of their physical format and electronic configuration.
Internal I/O ports are provided on the mainboard for devices such as
internal disk drives and optical drives.
External I/O ports are also provided on the mainboard to enable the
system to be connected to external peripheral devices such as the
keyboard, mouse, video display unit, and audio speakers. Both the video
adaptor and audio card may be provided "on-board" (i.e. built in to the
mainboard), or as separate plug-in circuit boards that are mounted in
an appropriate slot on the mainboard. The mainboard also provides
much of the control circuitry required by the various system
components, allowing the CPU to concentrate on its main role, which
is to execute programs.
The interface between a computer’s hardware and its software
is its architecture. The architecture is described by what the
computer’s instructions do, and how they are specified.
Understanding how it all works requires knowledge of the
structure of a computer and its assembly language.
The computer is in a sense a communication system. Data is
constantly being moved between the CPU, memory and the
various devices. The CPU uses I/O addresses to direct data to
particular devices. The devices in turn use interrupts to notify
the CPU and operating system of their needs.
The von Neumann Architecture
The genesis of modern computers, however, came with the practice of
storing a program in memory. according to mathematician john von
neumann, for a machine to be a computer it must have the following:
1.addressable memory that holds both instructions and data.
2.an arithmetic logic unit.
3.a program counter.
The important computer architecture components from von neumann’s
stored program control computer are:
ALU
The arithmetic logic unit is the part of the cpu that executes
individual instructions involving data (operands).
Register
a memory location in the cpu which holds a fixed amount of data.
registers of most current systems hold 64 bits or 8 bytes of data.
CPU
The central processing unit is the engine of the computer that
executes programs.
PC
The Program counter, also called the instruction pointer, is a register
which holds the memory address of the next instruction to be
executed.
IR
The Instruction register is the register that holds the current
instruction being executed.
Accumulator
A register designated to hold the result of an operation performed
by the ALU.
Register File
A collection of several registers.
The CPU Control Unit
Fetch Phase
Fetch the next instruction and store it in the instruction register
Execute Phase
The ALU or I/O unit executes the instruction
•ALU does calculations
•I/O unit loads or stores data between main memory and
registers
The Arithmetic Logic Unit (ALU)
The CPU contains
• a number of registers, some of which fall on the address side, others
on the data side;
• an arithmetic logic unit;
• the control section or control unit;
• connections to the memory (a large unit of storage) by two buses,
the uni-directional address bus and the bi-directional data bus;
• internal buses or data pathways which allow the output of one
register to connect to the input of another.
THE CPU, INSTRUCTION FETCH & EXECUTE
CPU Registers
All Registers are edge-triggered D-types — we will use falling-edge-
triggered devices. the registers comprise nothing more than a row of Dtype
latches which share a common clock input providing temporary storage on
the CPU.
Because these registers outputonto buses they have tri-state buffers are connected to a single input OE, for “Output Enable”
Units in the CPU
CU The Control Unit is responsible for the timing and execution of the
various register transfers required to fulfill an instruction held in the IR. It
has a number of control lines coming out of it, which transmit CSL and
CSP levels and pulses to the various registers and logic units.
We shall develop its hardware as a one-hot sequencer later.
ALU The Arithmetic Logic Unit is responsible for bit operations on
data held in the AC and MBR and for storing the results. It contains
arithmetic adders, logical AND-ers and OR-ers, and so on. A special
requirement in our architecture is a “null operation” or “no-op” which
simply allows the output of the AC to appear at the output of the ALU.
SR Closely associated with the ALU is the Status Register or Condition Control
Word or Status Word. It is not quite the same as the other registers in that
it really just a collection of 1bit flags that indicate the outcome of operations
that the ALU has just carried out. There are the flags (you met in P2) Carry C,
Overflow V flags, negative flag N, and zero flag Z. These are monitored by the
CU.
Buses, registers, and their widths
The buses carry words of information which are many bits wide, and on
diagrams a bus is indicated either by a wide line, or by a single line with a
dash through it often accompanied by the bus width in bits.
Data: Microcontrollers have data bus widths of 4 bits, 8-bits, 16-bits and
32-bits, while the most advanced PCs use 64 bits. In these lectures we
will assume that the “memory width” is 16 bits or 2 Bytes. This means
that each location can store 2 Bytes. We will also assume that the data
bus is 16 bits wide, and the MBR and AC registers on the data side of
the CPU are therefore also 16 bits wide. The ALU is also 16 bits wide.
(a) The data side is 2 Bytes or 16 bits wide. The ALU has been omitted here, but
is also 16 bits wide. (b) You should not think that the MBR register (for
example) has grown multiple electrical inputs. The actual wiring involves tri-
state buffers,
Address: The address bus does not have to be the same width as the data bus.
The width on CPUs over time has increased in step with contemporary memory
technology,
with the the Intel 8086 (from 1979) having n = 20 address lines to
current processors
having n = 36 - 40.