computer_interface _ lec 3 _ interrupt

Interrupt

Dr. Amr Elsayed

InterruptInterruptInterruptInterrupt

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InterruptInterruptInterruptInterrupt

� An interruptinterruptinterruptinterrupt allows a program or an external device tointerrupt the execution of a program.

� The generation of an interrupt can occur by� Hardware (hardware interrupt)� Software (softwareinterrupt).

� When an interrupt occurs an interrupt service routine

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� When an interrupt occurs an interrupt service routine(ISR) is called.

� A hardware interrupt the ISR then communicates withthe device and processes any data, Then returns to theoriginal program.

� A software interrupt includes reading a key from thekeyboardkeyboardkeyboardkeyboard, outputtingoutputtingoutputtingoutputting texttexttexttext to the screen and reading thecurrent datedatedatedate andandandand timetimetimetime.

Software interruptsSoftware interruptsSoftware interruptsSoftware interrupts

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BIOS and the operating systemBIOS and the operating systemBIOS and the operating systemBIOS and the operating system

�The BIOS has two main partsThe BIOS has two main partsThe BIOS has two main partsThe BIOS has two main parts� The first is the part permanently stored in a ROM (the

ROMROMROMROM BIOSBIOSBIOSBIOS). It starts the computer (or bootstap) andcontains programs which communicate with residentdevices.

� The secondsecondsecondsecond stagestagestagestage isisisis loadedloadedloadedloaded whenwhenwhenwhen thethethethe operatingoperatingoperatingoperating

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� The secondsecondsecondsecond stagestagestagestage isisisis loadedloadedloadedloaded whenwhenwhenwhen thethethethe operatingoperatingoperatingoperatingsystemsystemsystemsystem isisisis startedstartedstartedstarted. This part is non-permanent andallows the user to access the hardware in an easy-to-use manner. It accepts commands from the keyboardand displays them to the monitor.

BIOS and the operating systemBIOS and the operating systemBIOS and the operating systemBIOS and the operating system

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Interrupt vectorsInterrupt vectorsInterrupt vectorsInterrupt vectors

� InterruptInterruptInterruptInterrupt vectorsvectorsvectorsvectors areareareare addressesaddressesaddressesaddresses which inform theinterrupt handler as to where to find the ISR.

� All interrupts are assigned a number from 0 to 255.� The interrupt vectors associated with each interrupt

number are stored in the lowerlowerlowerlower 1024102410241024 bytesbytesbytesbytes of PCmemory.

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memory.� The first two bytes store the offset first two bytes store the offset first two bytes store the offset first two bytes store the offset and the next two next two next two next two

store the segment addressstore the segment addressstore the segment addressstore the segment address.� For example,

� Interrupt 0 is stored from 0000000000000000::::0000000000000000 to 0000000000000000::::0003000300030003� Interrupt 1 from 0000000000000000::::0004000400040004 to 0000000000000000::::0007000700070007, and so

on.

Processor interruptsProcessor interruptsProcessor interruptsProcessor interrupts

�The processor-generated interrupts normallyoccur either when a program causes a certaintype of error or if it is being used in a debugmode.

� In the debug mode the program can be made tobreak from its execution when a break-point

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break from its execution when a break-pointoccurs.

�This allows the user to test the status of thecomputer.

� It can also be forced to step through a programone operation at a time (single-step mode).

Hardware Interrupts Hardware Interrupts Hardware Interrupts Hardware Interrupts

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Hardware InterruptsHardware InterruptsHardware InterruptsHardware Interrupts

�To service external equipment� Polling� Interrupt-driven software

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Hardware Interrupts Hardware Interrupts Hardware Interrupts Hardware Interrupts

Interrupt Handling

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Interrupt VectorsInterrupt VectorsInterrupt VectorsInterrupt Vectors

� Each device that requires to be ‘interrupt-driven’ isassigned an IRQ (interrupt request) line.

� Each IRQ is active high.� The first eight (IRQ0–IRQ7) map into interrupts 8 to 15

(08h–0Fh)� The next eight (IRQ8–IRQ15) into interrupts 112 to 119

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� The next eight (IRQ8–IRQ15) into interrupts 112 to 119(70h–77h).


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� Interrupt handlingInterrupt handlingInterrupt handlingInterrupt handling

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Typical uses of InterruptsTypical uses of InterruptsTypical uses of InterruptsTypical uses of Interrupts

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Programmable interrupt controller (PIC)Programmable interrupt controller (PIC)Programmable interrupt controller (PIC)Programmable interrupt controller (PIC)

� 8259 8259 8259 8259 is Programmable Interrupt Controller (PIC)is Programmable Interrupt Controller (PIC)is Programmable Interrupt Controller (PIC)is Programmable Interrupt Controller (PIC)� It is a tool for It is a tool for It is a tool for It is a tool for managing the interrupt requestsmanaging the interrupt requestsmanaging the interrupt requestsmanaging the interrupt requests....� 8259 8259 8259 8259 is a very flexible peripheral controller chip:is a very flexible peripheral controller chip:is a very flexible peripheral controller chip:is a very flexible peripheral controller chip:

� PIC can deal with up to 64 interrupt inputs� interrupts can be masked

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interrupts can be masked� various priority schemes can also programmed.

� originally (originally (originally (originally (in PC XTin PC XTin PC XTin PC XT) it is available as a ) it is available as a ) it is available as a ) it is available as a separate ICseparate ICseparate ICseparate IC� Later the functionality of Later the functionality of Later the functionality of Later the functionality of ((((two PICs)two PICs)two PICs)two PICs) is in the is in the is in the is in the

motherboards chipsetmotherboards chipsetmotherboards chipsetmotherboards chipset....� In some of the modern processors, the functionality of In some of the modern processors, the functionality of In some of the modern processors, the functionality of In some of the modern processors, the functionality of

the the the the PIC PIC PIC PIC is built in.is built in.is built in.is built in.


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� 8888----bit bibit bibit bibit bi----directional data bus, one address line is needed,directional data bus, one address line is needed,directional data bus, one address line is needed,directional data bus, one address line is needed,PIC has two control registers to be programmed, you can think of them as two output ports or two memory location.

� The direction of data flow is controlled by RD and WR.The direction of data flow is controlled by RD and WR.The direction of data flow is controlled by RD and WR.The direction of data flow is controlled by RD and WR.� CS is as usual connected to the output of the address CS is as usual connected to the output of the address CS is as usual connected to the output of the address CS is as usual connected to the output of the address

decoder.decoder.decoder.decoder.� Interrupt requests are output on INT which is connected Interrupt requests are output on INT which is connected Interrupt requests are output on INT which is connected Interrupt requests are output on INT which is connected

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� Interrupt requests are output on INT which is connected Interrupt requests are output on INT which is connected Interrupt requests are output on INT which is connected Interrupt requests are output on INT which is connected to the INTR of the processor. Int. acknowledgment is to the INTR of the processor. Int. acknowledgment is to the INTR of the processor. Int. acknowledgment is to the INTR of the processor. Int. acknowledgment is received by INTA.received by INTA.received by INTA.received by INTA.

� IRIRIRIR0000----IRIRIRIR7 7 7 7 allow allow allow allow 8 8 8 8 separate interrupt requests to be separate interrupt requests to be separate interrupt requests to be separate interrupt requests to be inputted to the PIC. inputted to the PIC. inputted to the PIC. inputted to the PIC.

� sp/en=sp/en=sp/en=sp/en=1 1 1 1 for master , sp/en=for master , sp/en=for master , sp/en=for master , sp/en=0 0 0 0 for slave. for slave. for slave. for slave. � CASCASCASCAS0000----3 3 3 3 inputs/outputs are used when more than one inputs/outputs are used when more than one inputs/outputs are used when more than one inputs/outputs are used when more than one

PIC to cascaded.PIC to cascaded.PIC to cascaded.PIC to cascaded.


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Example of two cascaded PICsExample of two cascaded PICsExample of two cascaded PICsExample of two cascaded PICs

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Example of Example of Example of Example of

two cascaded two cascaded two cascaded two cascaded

PICsPICsPICsPICs

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� PIC is to be initialized and programmed to control its PIC is to be initialized and programmed to control its PIC is to be initialized and programmed to control its PIC is to be initialized and programmed to control its operation.operation.operation.operation.

� The operation in simple words:The operation in simple words:The operation in simple words:The operation in simple words:when an interrupt occurs , the PIC determines the highestpriority, activates the processor via its INTR input, andsends the type number onto the data bus when the

OPERATIONOPERATIONOPERATIONOPERATION

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sends the type number onto the data bus when theprocessor acknowledges the interrupt.

� Priority:Priority:Priority:Priority:What is used in PC is fully nested mode. That is the lowestnumbered IRQ input has highest priority. Lower priorityinterrupts will not be forwarded to the processor until thehigher priority interrupts have been serviced.


a) Simultaneous interrupt requests arrive on IR4 and IR6. IR4 has highest

priority and its IS bit is set as the IR4 service routine is put in service. (b)

The IR4 service routine issues a rotate-on-nonspecific-EOI command,

resetting IS4 and assigning it lowest priority. IR6 is now placed in service.

(c) The IR6 service routine issues a rotate-on-nonspecific-EOI command,

resetting IS6 and assigning it lowest priority.

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� Interrupt port addressesInterrupt port addressesInterrupt port addressesInterrupt port addresses

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� Interrupt mask register bit definitionsInterrupt mask register bit definitionsInterrupt mask register bit definitionsInterrupt mask register bit definitions

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� Interrupt control register bit Interrupt control register bit Interrupt control register bit Interrupt control register bit

definitionsdefinitionsdefinitionsdefinitions

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� ExampleExampleExampleExample::::

� thethethethe lineslineslineslines IRQIRQIRQIRQ0000,,,, IRQIRQIRQIRQ1111 andandandand IRQIRQIRQIRQ6666 areareareare allowedallowedallowedallowed totototo interruptinterruptinterruptinterrupt thethethethe

processor,processor,processor,processor, whereas,whereas,whereas,whereas, IRQIRQIRQIRQ2222,,,, IRQIRQIRQIRQ3333,,,, IRQIRQIRQIRQ4444 andandandand IRQIRQIRQIRQ7777 areareareare disableddisableddisableddisabled....

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computer_interface _ lec 3 _ interrupt

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