Computing Faster Without CPUs

GOAL: Evaluate FPGA*-based Hypercomputer Potential for NASA Scientific Computations

* Field-Programmable Gate Array (e.g. Polycom)

TEAM: Drs. Olaf Storaasli & Robert Singleterry, PIs

PARTNERS: Star Bridge Systems#

NSA, USAF, MSFC

# NASA Space Act Agreement

Dave Rutishauser, Jarek Sobieski, Joe Rehder & Garry Qualls William Fithian (Harvard), Siddhartha Krishnamurthy (VT) Shaun Foley (MIT), Neha Dandawate (GS), Kristin Barr (JPMorgan) Patrick Butler (VT), Vincent Vance (VT), Robert Lewis (Morehouse)

William Fithian* (Harvard, Merit Scholar, Oracle Award)

*NASA-NHGS mentorship ‘00-’02

FPGA: New Computing ParadigmTraditional CPU

Gateware: VIVA Icons & Transports

26 MFLOPS/250 MHz SGI

Reconfigurable FPGA

Sequential: 1 operation/cycle

Fixed gates & data types

Wasteful: 99% gates idle/cycle yet all draw power

Software: Textdo i = 1, billion

c= a+b

end do

Parallel: Inherent

Dynamic gates & data types

Efficient: Optimizes gates to task

392+ MFLOPS/64 MHz FPGA

3.92+ GFLOPS/10 FPGA board

VIVA: Gateware Development ToolWhat: Simple tool to configure FPGAs (VHDL cumbersome)

Growth in VIVA Capability

Extensive Data Types

Trig, Logs, Transcendentals

File Input/Output

Vector-Matrix Support

Access to Multiple FPGAs

Extensive Documentation

Stable Development

Few “bugs”

NO Floating Point

NO Scientific Functions

NO File Input/Output

NO Vector-Matrix Support

Access to One FPGA

Primitive Documentation

Weekly Changes

Frequent “bugs”

VIVA 1 (Feb ’01) VIVA2 (July ’02)

How: Transforms high-level graphical code to logic circuitry

Why: Achieve near-ASIC speed (w/o chip design)

Langley Hypercomputers

10 FPGAs each

Langley Algorithms Developed*

* In AIAA & Military & Aerospace Programmable Logic Device (MAPLD) papers

.

• Factorial => Probability: Combinations/Permutations AIRSC

• Cordic => Transcendentals: sin, log, exp, cosh…

Integration & Differentiation (numeric)

Matrix Equation Solver: [A]{x} = {b} via Gauss & Jacobi

• Dynamic Analysis: [M]{ü} + [C]{u} + [K]{u} + NLT = {P(t)}

• Analog Computing: digital implementation

• Nonlinear Analysis: “Analog” simulation avoids NLT solution development time

Matrix Algebra: Vectors, Matrices, Dot Product

Numeric Integration

f(x)=x2 f(x)*xx

f(x)*xxi+1=xi+x

Control

Output (Area under curve)

f(x)

xx

VIVA Sparse Matrix Equation SolverJacobi Iterative (3x3 Demo)

Control 3 Row Loads 3 // Dot Products[A]{x}={b}x1 = 1/A11*(b1 - A12*x2 - A13*x3)

Progress - Roadmap

Hardware

VIVA

Apps

Partners USAF

HAL30

HAL15

HAL15 LaRC West

HAL15

NSA NSAx2 OSC PF

SBSSBS SBS NASA-SBS SAA NASA-SBS SAA

Cordic

N! f(x)d

x

[A]{x

}={b

}

VIVA1.5VIVA1 VIVA2

Dynam

ic A

nal.

dy/dx

Aug ‘02Aug ‘01 Dec ‘01 May ‘02 Year 2

Analog C

omputin

g

106 e

q.s

Large-

scal

e

Stru

c. A

nal.

Wea

ther

Code

DARPA Prop. with NSA

Robert @ SBS

NL Stru

ctura

l

A

nalys

is

MAPLD Conf.

Pathfinder NASA Engineering

JPL

HC-62M 120x power

Year 2: Exploit Latest FPGAs

Plans: - Millions of Matrix Equations for Structures, Electromagnetics & Acoustics - Rapid Static & Dynamic Structural Analyses - Cray Vector Computations in Weather Code (VT PhD) - Robert on Administrator’s Fellowship at Star Bridge Systems - Joint proposals with NSA & DARPA - Simulate advanced computing concepts using VIVA - Collaborate with SBS to expand VIVA libraries - Influence VIVA development to meet NASA application needs - Expand FPGA applications for NASA programs

Rapid Growth in FPGA Capability

FPGA (Feb ’01) FPGA (Aug ’02)

Xilinx FPGAGatesMultiplies in H/WClock Speed MHzMemoryMemory SpeedReconfigure TimeGFLOPS

Total GFLOPs

XC406262K010020Kb466 Gb/s100ms0.4

4 (10 FPGAs)

XC2V60006 million (97x)144 (18x18)300 (3x)3.5 Mb (175x)5 Tb/s (11x)40ms (2.5x)47 (120x)

470 (10 FPGAs)

SummaryWhat We’ve Learned

We like FPGA promise – accomplished much

Hardware: Tested 2 futuristic FPGA systems

FPGAs: Inherently //, flexible, efficient, & fast

VIVA: Powerful & growing (tailored to NASA needs)

Applications: Diverse “pathfinder” algorithms developed

FPGA technology: Advancing dramatically

Speed: Year 1: 4 GFLOPS => Year 2: 470 GFLOPSFuture: Year 2 promises “cutting edge” innovations

comprehensive NASA engineering applications