conclusion and future improvement
TRANSCRIPT
DESIGN AND IMPLEMENTATION OF
A SOFTWARE DEFINED RADIO RECEIVER
FOR AM BAND
By
ISLAM MOHAMMED WARRAG
INDEX NO. 064010
Supervisor
Dr. Mohamed Ali Abbas
A REPORT SUBMITTED TO
University of Khartoum
In partial fulfillment of the Requirement for the degree of B.Sc. (HONS)
Electrical and Electronic Engineering
(COMMUNICATION ENGINEERING)
Faculty of Engineering
Department of Electrical and Electronics Engineering
July 2011
ii
Dedication:
To my father, Mohammed, for passing on a passion for learning and intellectual
stimulation.
To my mother, Amal, for nurturing me through my youth and supporting my every
venture.
And to my brothers and the rest of my family for their moral support and interest in
this project.
To my friends, for their love, encouragement, and enthusiasm, during the day-to-
day development of this Project.
iii
Acknowledgement
Dr. Mohammed Ali has been the ideal thesis supervisor. His sage advice, insightful
criticisms, and patient encouragement aided the writing of this thesis in
innumerable ways.
I would like to convey my gratitude to the following individuals for providing me
with inspiration to embark on my project. My deepest thanks to my teachers Abdul
Kareem Abdurrahman and Yasser Salih whose steadfast support of this project was
greatly needed and deeply appreciated, my colleagues Mohammed Abdurrahman
and Omer Salah whom without this work would never be as it is now, Lastly thank
you my project mates Amani and Lubna for your hard and supportive work.
iv
Abstract
With the exponential growth in the ways and means by which people need to
communicate - data communications, voice communications, video communications, broadcast
messaging, command, control communications, etc. – modifying radio devices easily and cost-
effectively has become business critical. Software defined radio (SDR) technology brings the
flexibility, cost efficiency and power to drive communications forward, with wide-reaching
benefits realized by service providers and product developers through to end users.
A radio is any kind of device that wirelessly transmits or receives signals in the radio
frequency (RF) part of the electromagnetic spectrum to facilitate the transfer of information.
Traditional hardware based radio devices limit cross-functionality and can only be
modified through physical intervention. This results in higher production costs and minimal
flexibility in supporting multiple waveform standards. By contrast, software defined radio
technology provides an efficient and comparatively inexpensive solution to this problem,
allowing multimode, multi-band and/or multi-functional wireless devices that can be enhanced
using software upgrades.
At the beginning of this work, different parts were not available and that's why some
alternative designs were suggested and tested but the expected results were not achieved. Thus
most of these designs were eliminated.
This thesis deals with design and implementation of a low-cost SDR receiver which
samples AM Intermediate Frequency (IF) and demodulates it in real-time using coherent
demodulation. The system uses an AM/FM trainer kit to obtain an AM IF, a high speed analog to
digital convertor to digitize the IF signal , a FPGA to perform digital signal processing and
digital to analog convertor to transform samples of the signal to analog form in order to be heard
by the speaker.
v
المستخلص:
ز انسائم ذشم اذصاالخ – سراخا اناط نهراصمانسائم انر انسثم انائم ف يغ ان
-انخ االذصاالخ ، انقادج انسطشج انشسائم ،تث انفذ ، اذصاالخ انصذح االذصاالخ انثااخ
اع االسرثاس. اسرخذاو أى ا يفؼانح ي زث انركهفح تسنح اسرخذاو األخضج انالسهكح أصثر
إن األياو ، االذصاالخ نذفغ انطاقح ي زث انركهفح انكفاءج انشح انثشيداخ ف اداسج االخضج دهة
انسرخذي انائ. صال إنيطس انرداخ انخذياخ انذ ي قثم يقذي ذسقق فائذ اسؼح
ذكانف االراج يا رح ػ اسذفاع ف. انرذخم اناد خالل يفقط ك ذؼذه انرقهذ انشاد
اإلراػح انثشايحذكنخا ػه انقض ي رنك، ذؼشف انرؼذدج. اشكال انخاخ ف دػى ذقهم نهشح
ذشقح ذطش ك أ ساى ف انز، انرؼذد، انساذ نز انشكهح سثا فؼاال غش يكهف فش زال
انثشيداخ.
انرصاخ فأ تؼض يسرخذيح ، اخضاءؼذو ذفش سثح ن ػذ تذاح انؼم ف زا انششع ،
انرصايى. يؼظى ز ذى اسرثؼاد تانران انرقؼح. ذسقق انرائح نك نى اخرثاسا اقرشزد ذى انثذهح قذ
انرشدد سرخذو ذؼذم اذساع ح يخفض انركهف خاص اسرقثال ذصى ذفز ذرال ز االطشزح
(AM trainer kit) / FM انذسب يدػح سرخذو انظاو انسط تاسرخذاو ذؼذم االذساع انرضاي. زا
إف ، نهسصل ػه انرشدد انسط نالشاسج انؼذنح ذؼذم اذساع، يسل اشاساخ ي ذاثهح ان سقح
يسل اشاساخ ي سقح ان ذاثهح زر ك انشقح يؼاندح اإلشاساخ ألداء (FPGAت خ أ )
اسرخذاو انساػح ف ساع انصخ.
vi
Table of Contents
Dedication …………………………………………………………………………………………………………………………..…………… ii
Acknowledgement ……………………………………………………………………………………………………………………………iii
Abstract…………………………………………………………………………………………………………………………….………………iv
Table of Content …………………………………………………………………………………………………………………..………… vi
List of Figures …………………………………………………………………………………………………………………….………… viii
1 CHAPTER ONE INTRODUCTION ................................................................................................... 1
1.1 General background and motivation ............................................................................................ 1
2.1 Problem statement ........................................................................................................................ 3
1.3 Methodology ................................................................................................................................ 3
1.4 Applications of Software Defined Radio ..................................................................................... 3
1.5 Thesis Layout ............................................................................................................................... 4
2 CHAPTER TWO BACKGROUND AND LITERATURE REVIEW ................................................. 6
2.1 Basic Concepts ............................................................................................................................. 6
2.1.1 AM Modulation .................................................................................................................... 6
2.1.2 AM Demodulation ................................................................................................................ 6
2.1.3 Antenna ................................................................................................................................ 7
2.1.4 RF range and signals ............................................................................................................ 7
2.1.5 Intermediate Frequency ........................................................................................................ 8
2.1.6 Frequency mixer ................................................................................................................... 9
2.1.7 Analog to digital conversion ................................................................................................ 9
2.1.8 Digital to Analog Conversion ............................................................................................. 15
2.1.9 Filtering .............................................................................................................................. 15
2.1.9.2 Finite impulse response filters ........................................................................................................ 16
2.2 A Traditional Hardware Radio Architecture .............................................................................. 16
2.3 Practical software defined radio architecture ............................................................................. 17
2.3.1 RF Front-end Architectures ................................................................................................ 18
2.3.2 Field Programmable Gate Array (FPGA) ........................................................................... 20
2.4 Previous work ............................................................................................................................. 20
2.4.1 SDR design of a master degree student .............................................................................. 20
3 CHAPTER THREE DESIGN AND METHODOLOGY ................................................................... 23
3.1 Design overview ......................................................................................................................... 24
3.2 Hardware .................................................................................................................................... 24
vii
3.3 Software ..................................................................................................................................... 25
4 CHAPTER FOUR TOOLS AND IMPLEMENTATION .................................................................. 27
4.1 AM\FM Trainer Kit .................................................................................................................... 27
4.1.1 Section 1 (AM mixer, AM oscillator, and antenna) ........................................................... 29
4.1.2 Section 2 (First AM IF amplifier) ...................................................................................... 29
4.1.3 Section 3 (Second AM IF amplifier) .................................................................................. 31
4.1.4 Section 4 (AM detector and AGC stage) ............................................................................ 32
4.2 Coaxial cable .............................................................................................................................. 33
4.3 Spartan-3AN starter kit .............................................................................................................. 33
4.3.1 Analog capture circuit ........................................................................................................ 33
4.3.2 Field Programmable Gate Array (FPGA) ........................................................................... 34
4.3.3 Digital-to-Analog Converter .............................................................................................. 37
4.3.4 Serial Peripheral Interface .................................................................................................. 38
5 CHAPTER FIVERESULTS AND DISCUSSION ............................................................................ 39
5.1 Hardware Results: ...................................................................................................................... 39
5.2 Simulation Results ...................................................................................................................... 39
6 CHAPTER SIX CONCLUSION AND FUTURE IMPROVEMENT ............................................... 47
6.1 Challenges and Limitations ........................................................................................................ 48
6.1.1 Band pass filter: .................................................................................................................. 48
6.1.2 Mixer: ................................................................................................................................. 49
6.1.3 ADC: .................................................................................................................................. 49
6.1.4 Software Problem: .............................................................................................................. 50
6.2 Digital Signal Processing Alternatives ....................................................................................... 50
6.3 Future Improvement ................................................................................................................... 51
Appendix A ……………………………………………………………………………………………………………………………………….A1
Appendix B ………………………………………………………………………………………….…B1
viii
List of Figures
Figure 1.1.1: A Software-Define Radio (SDR) ............................................................................... 2
Figure 2.1.1: Spectrum of a band-limited continuous time analog signal .................................... 11
Figure 2.1.2: Spectrum of the signal sampled at fs = 2fmax ......................................................... 11
Figure 2.1.3: Spectrum of the signal sampled at fs > 2fmax ......................................................... 11
Figure 2.1.4: Spectrum of the signal sampled at fs < 2fmax ......................................................... 12
Figure 2.1.5: (a) Spectrum of a band-limited analog signal with undesired component ............. 12
Figure 2.1.6: (a) Spectrum of a band-pass signal centered at IF ................................................... 13
Figure 2.2.1: Traditional hardware radio architecture. .................................................................. 17
Figure 2.3.1: Example for Practical Software Defined Radio System .......................................... 18
Figure 2.3.2: Heterodyne (or super-heterodyne) architecture ....................................................... 19
Figure 2.4.1: Software Defined Radio Receiver for AM Band ..................................................... 21
Figure 2.4.1: Design Flow ............................................................................................................. 23
Figure 3.1.1: SDR receiver block diagram .................................................................................... 24
Figure 3.2.1: Hardware block diagram .......................................................................................... 24
Figure 3.3.1: Software block diagram ........................................................................................... 25
Figure 4.1.1: Assembled AM/FM Trainer kit ............................................................................... 28
Figure 4.1.2: AM radio section ..................................................................................................... 28
Figure 4.1.3: Assembly instructions of section 1 .......................................................................... 30
Figure 4.1.4: Assembly instructions of section 2 .......................................................................... 31
Figure 4.1.5: Assembly instructions of section 3 .......................................................................... 32
Figure 4.1.6: Assembly instructions of section 4 .......................................................................... 33
Figure 4.3.1: Coherent AM demodulation model ......................................................................... 35
Figure 4.3.2: Multi-stage filtering ................................................................................................. 36
Figure 4.3.3: N-stage Filter with down-sample by a factor of 2 at each stage .............................. 36
Figure 5.2.1: The Simulink model ................................................................................................ 40
Figure 5.2.2: Frequency spectrum of a cosine signal .................................................................... 41
Figure 5.2.3: Frequency spectrum of AM modulated signal ......................................................... 43
Figure 5.2.4: Frequency spectrum of the demodulated signal44Figure 5.2.5: Spectrum of the
signal after the multistage low pass filter………………….. ................................................. 45
Introduction Chapter one
1
CHAPTER ONE
INTRODUCTION
1.1 General background and motivation
Since the mid-1990s, the radio industry has actively focused on implementing more and
more radio functions in the digital domain. This has been furthered by availability of high speed,
high performance data converters and faster digital processors.
Such a system is more robust, compact, power-efficient and highly reconfigurable. An
ideal Software Radio system consists of a transmitting/receiving antenna, high speed data
converter and a powerful digital processor. However, the state of current technology is such that
this can only be partially achieved. Due to speed and performance limitations of existing data
converters and digital processors, it is customary to use an RF front-end between the antenna and
the data converter. Such a system is then termed as a Software-Defined Radio (SDR).
Software defined radio uses programmable digital devices to perform the signal processing
necessary to transmit and receive baseband information at radio frequency. Devices such as
digital signal processors (DSPs) and field programmable gate arrays (FPGAs) use software to
provide them with the required signal processing functionality. This technology offers greater
flexibility and potentially longer product life, since the radio can be upgraded very cost
effectively with software; for example if SDR receiver using ASK demodulation and the now
sender upgrade to FSK technology, the receiver is simply upgraded to FSK by downloading FSK
program on receiver.
A major challenge for software defined radio is to equal the efficiencies of purely
hardware solutions while providing the flexibility and intelligence that software can offer.
Since the SDR is introduced as a new technology for communication and data transfer, there are
several researches began to develop rapidly. For example the SDR is used by the US military to
keep pace with new modulation and demodulation techniques. But now the NATO is developing
a department for the software radio researches, because of effectiveness.
Introduction Chapter one
2
Figure 1.1.1 illustrates a practical SDR architecture. In the receive path, the antenna
signal is amplified by the Low Noise Amplifier (LNA). It is then mixed and band-pass filtered
(BPF) to generate the IF signal. This IF signal is then digitized by a high speed ADC.
The DSP down-converts the IF signal to baseband and subsequently demodulates it in
digital domain. The demodulated signal is played on a speaker.
Figure 1.1.1: A Software-Define Radio (SDR)
Radios built using SDR concept have the following advantages:
1. Increased system performance, flexibility and cost efficiency as the digitization is done
at an early stage.
2. A standard architecture can be used for a wide range of communication products. Hence,
interoperability is possible.
3. Increased adaptability. The radio can be reprogrammed to improve performance or add
more functionality.
4. Software modifications can be done at a fraction of the time of hardware modifications.
This can drastically reduce time to market and life-cycle costs.
Introduction Chapter one
3
1.2 Problem statement
Prior to the infusion of digital signal processing technology, most of the functions in a
radio system were implemented using analog circuitry. This had several limitations. First of all,
such a system was not reconfigurable. Any modification was possible only through physical
intervention. Secondly, complex communication algorithms were difficult to implement in the
analog domain due to the size of the components, associated costs and power consumption. Also,
performance of analog radio was dependent on external parameters like noise, temperature, etc.
With increase in speed of data converters and signal processors, it became possible to
implement analog functions in the digital domain.
The ultimate goal was to directly digitize the RF signal at the output of the receiving
antenna and implement all receiver functions in either digital hardware or software. This gave
birth to the software-defined radio (SDR) concept.
1.3 Methodology
The design and implementation of the system is developed using programming languages
(Very high speed integrated circuit Hardware Description Language -VHDL-), the digital signal
processor used here is Field Programmable Gate Array (FPGA) along with AM/FM trainer kit to
perform the hardware -RF- part.
1.4 Applications of Software Defined Radio
Tracking receivers can be highly automated because software radio allows DSPs to
perform the signal identification and analysis functions as well as the adaptable tuning functions.
Signal intelligence applications and radar benefit from the tight coupling of the A/D,
DDC, DUC, and DSP functions to process wideband signals.
Cellular phone applications are one of the strongest high-volume applications because of
the high density of tightly-packed frequency division multiplexed voice channels [1].
Introduction Chapter one
4
Direction finding and beam-forming are ideal applications for digital receivers because of
their excellent channel-to-channel phase and gain matching and consistent delay characteristics.
Software defined radios have significant use in military and wireless industry because
both of them have a variety of changing radio protocols in real time. One of the first software
defined radios was a US military project called SPEAK easy. The goal of the project was to
develop a radio for US military that could operate from 2 MHz to 2 GHz. It was one of the first
projects to use Field Programmable Gate Arrays (FPGA) for digital signal processing of radio
data.
Another project, called Joint Tactical Radio Systems (JTRS), is a US and allied program
to make radios which provide flexible and interoperable communications.
Although most current SDR development was started in the military with initiatives, the
advantages of the approach extend far beyond military use, and the technology is now center
stage for consideration in many commercial embedded applications as well. SDR offers
flexibility and field-upgradeability to RF systems that simply cannot be matched by traditional
analog-based RF design techniques.
A potential application of SDR is in the automotive industry. Many OEM manufacturers,
including Siemens VDO Automotive, are researching the option of eliminating bulky RF tuners
in car radio and digitizing entire AM/FM bands. Multiple AM/FM channels can be demodulated
simultaneously in digital domain [2].
1.5 Thesis Layout
Chapter 2: This chapter is a literature review of a basic concept used in this project, background
about hardware radio and practical software radio; also it shows a previous work done in this
project.
Chapter 3: This chapter explains general system design of SDR receivers and block diagrams of
design flow.
Chapter 4: This chapter describes the tools used to implement the design and to perform
different functions of the SDR receiver; also it shows with some details these tools which include
AM/FM trainer kit and Spartan-3AN kit and the specific role of each part of them.
Chapter 5: It is a results and discussion chapter which shows the results in each stage of the
design and discusses these results and compares it with the theoretical expected results and also
Introduction Chapter one
5
contains general background mathematic behind each result. The problems and limitation of the
design are discussed here.
Chapter 6: This chapter concludes the project and also shows some problems faced during this
project and failure trials of the design. It also includes future recommendation to improve this
project.
Appendix A: explain the FDA tools and its specific way of design.
Appendix B: contains selected chapters from the manual Spartan-3AN kit related to the design
we use to perform the objectives of this project.
Literature review Chapter two
6
2 CHAPTER TWO
BACKGROUND AND LITERATURE REVIEW
This chapter discusses common basic concepts of software defined radio receiver
implementation. It also talks about the hardware architecture of the radio and it its disadvantages
so that the reader could be able to evaluate the causes behind moving toward software in
different parts of our lives. Then we show the ideal SDR implementation. Finally it concludes
with practical SDR receiver and the previous work in this project.
2.1 Basic Concepts
2.1.1 AM Modulation
Amplitude modulation (AM) is a technique used in electronic communication, most
commonly for transmitting information via a radio carrier wave. AM works by varying the
strength of the transmitted signal in relation to the information being sent.
In radio communication, a continuous wave radio-frequency signal (a sinusoidal carrier
wave) has its amplitude modulated by an audio waveform before being transmitted.
In the frequency domain, amplitude modulation produces a signal with power
concentrated at the carrier frequency and in two adjacent sidebands. Each sideband is equal in
bandwidth to that of the modulating signal and is a mirror image of the other [3].
2.1.2 AM Demodulation
Demodulation is the act of extracting the original information-bearing signal from a
modulated carrier wave. A demodulator is an electronic circuit (or computer program in a
software defined radio) that is used to recover the information content from the modulated
carrier wave.
Literature review Chapter two
7
An AM signal encodes the information onto the carrier wave by varying its amplitude in
direct sympathy with the analogue signal to be sent. There are two methods used to demodulate
AM signals.
The envelope detector: is a very simple method of demodulation. It consists of a rectifier, and a
low-pass filter. The rectifier may be in the form of a single diode, or may be more complex.
Many natural substances exhibit this rectification behavior, which is why it was the earliest
modulation and demodulation technique used in radio. The filter is usually a RC low-pass type,
but the filter function can sometimes be achieved by relying on the limited frequency response of
the circuitry following the rectifier.
The product detector: multiplies the incoming signal by the signal of a local oscillator with the
same frequency and phase as the carrier of the incoming signal. After filtering the original audio
signal will result [3].
2.1.3 Antenna
Smart antenna systems can adaptively point the main antenna beam in the direction of a
desirable transceiver and point one or more antenna nulls towards interfering signals.
Alternatively, smart antennas can be made to resonate at different frequencies, depending upon
the need to emulate different radios or use a different part of the spectrum with fewer interferers.
2.1.4 RF range and signals
Radio frequency (RF) is a rate of oscillation in the range of about 3 kHz to 300 GHz,
which corresponds to the frequency of radio waves, and the alternating currents which carry
radio signals. RF usually refers to electrical rather than mechanical oscillations, although
mechanical RF systems do exist.
RF signal is coming from an antenna. So it contains electromagnetic waves. But when the
signal is processed using electronic circuits, the range of frequency may not be sufficient. So that
RF has to be converted to some other frequency acceptable by the circuit [4].
Literature review Chapter two
8
2.1.5 Intermediate Frequency
An intermediate frequency is a frequency to which a carrier frequency is shifted as an
intermediate step in transmission or reception. The intermediate frequency is created by mixing
the carrier signal with a local oscillator signal in a process called heterodyning, resulting in a
signal at the difference or beat frequency. Intermediate frequencies are used in super-heterodyne
radio receivers, in which an incoming signal is shifted to an IF for amplification before final
detection is done. There may be several such stages of intermediate frequency in a super-
heterodyne, which is called double (or triple) conversion.
Intermediate frequencies are used for three general reasons. At very high (gigahertz)
frequencies, signal processing circuitry performs poorly. Active devices such as transistors
cannot deliver much amplification (gain) without becoming unstable. Ordinary circuits using
capacitors and inductors must be replaced with cumbersome high frequency techniques such as
waveguides. So a high frequency signal is converted to a lower IF for processing.
A second reason to use an IF, in receivers that can be tuned to different stations, is to
convert the various different frequencies of the stations to a common frequency for processing. It
is difficult to build amplifiers, filters, and detectors that can be tuned to different frequencies, but
easy to build tunable oscillators. Super-heterodyne receivers tune in different stations simply by
adjusting the frequency of the local oscillator on the input stage, and all processing after that is
done at the same frequency, the IF. Without using an IF, all the complicated filters and detectors
in a radio or television would have to be tuned in unison each time the station was changed, as
was necessary in the early tuned radio frequency receivers.
But the main reason for using an intermediate frequency is to improve frequency
selectivity. In communication circuits, a very common task is to separate out or extract signals or
components of a signal that are close together in frequency. This is called filtering. Some
examples are, picking up a radio station among several that are close in frequency, or extracting
the chrominance subcarrier from a TV signal. With all known filtering techniques the filter's
bandwidth increases proportionately with the frequency. So a narrower bandwidth and more
selectivity can be achieved by converting the signal to a lower IF and performing the filtering at
that frequency.
Literature review Chapter two
9
Perhaps the most commonly used intermediate frequencies are around 455 KHz for AM
receivers and 10.7 MHz for FM receivers. Intermediate frequency (IF) are generated by mixing
the RF and LO frequency together to create a lower frequency called IF. Most of the ADC/DAC
operates in low sampling rates, so input RF must be mixed down to IF to be processed.
Intermediate frequency tends to be lower frequency range compared to the transmitted RF
frequency. However, the choices for the IF are most depending on the available components
such as mixer, filters, amplifiers and others that can operate at lower frequency. There are other
factors involved in deciding the IF frequency, because lower IF is susceptible to noise and higher
IF can cause clock jitters [4].
2.1.6 Frequency mixer
Frequency mixer is a nonlinear electrical circuit that creates new frequencies from two
signals applied to it. In its most common application, two signals at frequencies f1 and f2 are
applied to a mixer, and it produces new signals at the sum f1 + f2 and difference f1 - f2 of the
original frequencies. Other frequency components may also be produced in a practical frequency
mixer.
Mixers are widely used to shift signals from one frequency range to another, a process
known as heterodyning, for convenience in transmission or further signal processing. For
example, a key component of a super-heterodyne receiver is a mixer used to move received
signals to a common intermediate frequency. Frequency mixers are also used to modulate a
carrier frequency in radio transmitters [4].
2.1.7 Analog to digital conversion
An analog-to-digital converter is a device which converts a continuous quantity to a
discrete time digital representation. An ADC may also provide an isolated measurement.
Typically, an ADC is an electronic device that converts an input analog voltage or current
to a digital number proportional to the magnitude of the voltage or current [4].
Since digital conversion is such an integral function of the software radio, it is
worthwhile to first review the associated fundamental digital signal processing concepts.
Literature review Chapter two
11
2.1.7.1 Sampling techniques
The sampling process is very important in radio receivers using digitization at the RF or
IF. The content of the sampled signal is mainly dependent upon the sampling rate and the
minimum and maximum frequency components of the analog input signal. When a continuous
time signal is uniformly sampled, the spectrum of the original signal F (f) is repeated at integral
multiples of the sampling frequency, fs. In other words, F (f) becomes periodic [2].
The four commonly used uniform sampling techniques are – Nyquist sampling, over-
sampling, quadrature sampling and band-pass sampling.
a. Nyquist sampling
The Nyquist sampling theorem says that exact reconstruction of a continuous time analog
signal from its samples is possible if the signal is band-limited and the sampling frequency is
greater than twice the signal bandwidth. The sampling frequency at twice the signal bandwidth is
called as Nyquist frequency or Critical frequency. If fmax is the maximum frequency component
of an analog signal then spectrum of the signal sampled at the Nyquist frequency is shown in
Fig. 2.1.1.
If the signal is sampled at less than the Nyquist frequency (called under-sampling), the
spectral replicas overlap causing aliasing. The sampled signal gets corrupted and cannot be
exactly recovered. Figure 2.1.4 depicts aliasing due to under-sampling. In order to avoid aliasing,
an anti-aliasing filter is used before the ADC. The cut-off frequency of the anti-aliasing filter is
one half of the sampling frequency. Nyquist sampling demands an extremely sharp cut-off anti-
aliasing filter. Unfortunately, practical realizable filters cannot provide this type of ‗brick-wall‘
response.
Even in Nyquist sampling, if an undesired (i.e. out-of-band) signal is present along with the
analog signal, it folds over and causes spectral overlap thus corrupting the signal of interest. This
is shown in Figure 2.1.5. The anti-aliasing filter serves the purpose of attenuating the undesired
signal too [2].
b. Oversampling
In oversampling, the signal is sampled at much more than twice the Nyquist rate. As depicted
in Fig. 2.1.3, the main advantage of this technique is that the spectral replicas of the sampled
Literature review Chapter two
11
signal are spaced further apart from each. This relaxes the steep cut-off frequency requirements
of the anti-aliasing filter.
c. Quadrature sampling
The homodyne architecture for phase and frequency modulated systems use quadrature
down-conversion to generate the 'I' and 'Q' quadrature components. These are complex valued
signals and contain twice the information as the real valued signal. Hence, they can be sampled
at one half the sampling rate of the real valued signal. This type of sampling is called as
quadrature sampling. The only disadvantage is that ADC needs to have two input channels for
digitizing the two components.
Figure 2.1.1: Spectrum of a band-limited continuous time analog signal
Figure 2.1.2: Spectrum of the signal sampled at fs = 2fmax
Figure 2.1.3: Spectrum of the signal sampled at fs > 2fmax
Literature review Chapter two
12
Figure 2.1.4: Spectrum of the signal sampled at fs < 2fmax
Figure 2.1.5: (a) Spectrum of a band-limited analog signal with undesired component
Figure 2.1.5: (b) Spectrum of the signal sampled at fs = 2fmax
d. Band-pass Sampling
RF signals are typically band-pass signals. The information bandwidth of an RF signal is
much less than it is RF or IF frequency. Band-pass sampling is the technique of under-sampling
a modulated signal to achieve frequency translation by intentional aliasing. Here, the sampling
frequency is based on the information bandwidth of the RF signal and not on the carrier or IF.
Radio receivers that digitize at Radio Frequency or Intermediate Frequency usually use band-
pass sampling. The concept is graphically depicted in Fig. 2.1.6. Since aliasing takes place, it is
necessary to make sure that no portion of the information bandwidth of the signal folds on top if
itself, creating interference.
For band-pass sampling to work effectively, a very steep roll-off band-pass filter is
required to attenuate undesired signals outside the band of interest. Another severe limitation is
Literature review Chapter two
13
that the ADC should be able to effectively operate on the highest frequency component in the RF
signal [2].
Like most other SDR projects, this project also uses band-pass sampling to sample the
AM IF signal.
Figure 2.1.6: (a) Spectrum of a band-pass signal centered at IF
Figure 2.1.6: (b) Spectrum of the signal band-pass sampled at fs < fIF
2.1.7.2 Effective Number of Bits
Although an ADC may convert the analog sample into an n-bit digital word, the process
of making that conversion is prone to error and not all of the bits will be meaningful.
The effective number of bits (ENOB) specifies the dynamic performance of an ADC at a specific
frequency, amplitude, and sampling rate relative to an ideal ADC‘s quantization noise [5].
2.1.7.3 Quantization
Sampled analog signals are quantized in time; to allow manipulation of sampled signals
by computers and DSPs they must also be quantized in amplitude. The time-related quantization
step size is simply the reciprocal of the sampling frequency Fs. The amplitude-related
quantization step size q of an analog to digital converter is calculated by:
Literature review Chapter two
14
Where Vfs is the full-scale voltage range of the ADC and N is the number of binary bits.
For example, a typical 14-bit ADC suitable for SDR has a peak to peak full-scale voltage range
of 2.2V. The AD6644 will quantize the 2.2-V range into 16,383 equally spaced values resulting
in a q of 0.134 mV. Assuming that the ADC rounds to the nearest quantization value, the worst-
case error is q/2.
Let‘s now consider an analog input sine-wave with full-scale peak to peak amplitude of
A; the quantization step size is now:
For this case the quantization error, e, is assumed to be a uniformly distributed random variable
in the interval of ± q/2 with zero mean. The variance, or quantization noise power, is given by:
∫
( )
∫
The signal to noise ratio can be calculated by dividing the average signal power in the
sine-wave, A2/8, by the quantization noise power and expressing this in decibels, as follows:
(
) (
)
Practical limitations in the production of high-performance converters make this
theoretical figure harder to obtain as the number of bits is increased [5].
2.1.7.4 Coding
There are many binary coding schemes in existence. The two coding methods most often
used for ADCs are Straight Binary and Two's Complement.
The Straight Binary coding scheme is probably the most commonly known one. It is also one of
the most common output coding schemes used with ADCs that have a single-ended input. (It is
also the most common data coding scheme used at DAC inputs.)
The other most common coding scheme used with ADCs that have differential inputs is
the Two's Complement, sometimes written as 2's Complement. This coding method simply takes
the Offset Binary scheme and inverts the MSB, such that the MSB is now a sign bit.
Literature review Chapter two
15
2.1.7.5 Static and Dynamic Errors
Distortion produced by a digital converter can be attributed to its static nonlinearity and dynamic
nonlinearity features. The converter‘s dc transfer function is used to characterize static
nonlinearity and express this as a number of bits of integral nonlinearity (INL) and differential
nonlinearity (DNL) error.
Dynamic nonlinearity is the more important SDR-related parameter, and this is
commonly expressed through specifications such as signal to noise and distortion (SINAD) and
SFDR and Spurious Free Dynamic Range (SFDR) [5].
2.1.8 Digital to Analog Conversion
In electronics, a digital-to-analog converter (DAC) is a device that converts a digital code
to an analog signal (current, voltage, or electric charge).
A DAC converts an abstract finite-precision number into a concrete physical quantity. In
particular, DACs are often used to convert finite-precision time series data to a continually
varying physical signal.
A typical DAC converts the abstract numbers into a concrete sequence of impulses that
are then processed by a reconstruction filter using some form of interpolation to fill in data
between the impulses. Other DAC methods produce a pulse-density modulated signal that can
then be filtered in a similar way to produce a smoothly varying signal [4].
2.1.9 Filtering
2.1.9.1 Band-pass filters
A band-pass filter is a device that passes frequencies within a certain range and rejects
(attenuates) frequencies outside that range. An example of an analogue electronic band-pass
filter is an RLC circuit.
An ideal band-pass filter would have a completely flat pass-band and would completely
attenuate all frequencies outside the pass-band. Additionally, the transition out of the pass-band
would be instantaneous in frequency. In practice, there is no ideal band-pass filter. The filter
does not attenuate all frequencies outside the desired frequency range completely; in particular,
there is a region just outside the intended pass-band where frequencies are attenuated, but not
rejected.
Literature review Chapter two
16
2.1.9.2 Finite impulse response filters
A finite impulse response (FIR) filter is a type of a signal processing filter whose impulse
response (or response to any finite length input) is of finite duration, because it settles to zero in
finite time. This is in contrast to infinite impulse response (IIR) filters, which have internal
feedback and may continue to respond indefinitely. The impulse response of an Nth-order
discrete-time FIR filter lasts for N+1 samples, and then dies to zero. FIR filters can be discrete-
time or continuous-time, and digital or analog [6].
2.2 A Traditional Hardware Radio Architecture
To appreciate where software radio is heading it is first useful to review traditional
hardware radio architecture. Figure 2.2.1 illustrates a dual conversion super-heterodyne
transceiver. This design has been around since the 1930s and it is almost certain that a majority
of homes would possess a super-heterodyne receiver of some sort (broadcast radio, television,
and so on).
From the receiver point of view the RF from the antenna is converted down to an
intermediate frequency by mixing or multiplying the incoming signal with the first local
oscillator, LO1. The IF is filtered and then mixed down to baseband by the second oscillator,
LO2, and mixer. The baseband modulated signal is demodulated to produce the analog receive
information, and the reciprocal functions are performed for the transmitter.
The number of conversion stages is dependent upon the RF operating frequency, and
theoretically it is possible to add stages and push the operating frequency higher. The analog
super-heterodyne radio has experienced a marvelously successful history; it was used in 1G
mobile phone terminals and is sure to endure in low-cost broadcast radio receivers for many
years to come. This architecture was suited to 1G mobile phone systems, such as advanced
mobile phone system (AMPS), which used frequency modulation (FM) and frequency division
multiplexing (FD) to allow multiple users to access a fixed piece of spectrum.
The AMPS system allocates a dedicated 30-kHz spectrum slice to each user irrespective
of the amount of information required to be exchanged [5].
Literature review Chapter two
17
Figure 2.2.1: Traditional hardware radio architecture.
2.3 Practical software defined radio architecture
For many communication systems used today (like cell phone system) it is not practical
yet to implement the ideal SDR architecture. That‘s because it is simply difficult to sample high
frequency band signals directly due to the technological limitations.
But if we cannot implement the ideal SDR, simply decide where the radio stop being hardware
defined and start to software defined. So the practical Architecture will be hybrid. Many
parameters affect this decision like received (or sent) signal frequency and the available
sampling rate.
With an ideal SDR architecture all the radio‘s functions from the antenna to the
information interface are performed and programmed by a single high-level software language
using generic computing and signal processing hardware.
The basic SDR with a wideband RF front end, as shown in Figure 2.6, goes a significant
way toward meeting the ideal goal.
The architecture in Figure 2.3.1 is divided into hardware defined subsystem and a
software defined subsystem. The hardware subsystem details some lower-level physical
components (PA, LNA, ADC, and so on), whereas the software subsystem is purely functional
and contains no indication of physical devices or lower-level partitions.
The main role for the hardware subsystem is to shift the entire frequency spectrum to
intermediate frequency to be ready for sampling and digitization.
Literature review Chapter two
18
Figure 2.3.1: Example for Practical Software Defined Radio System
The software defined digital subsystem consists of digital frequency conversion and
baseband processing. For receive the wideband multicarrier signal from the analog to digital
converter is distributed to each of the frequency down converters for processing [5].
The hardware subsystem is basically the RF front end and it has different architectures.
2.3.1 RF Front-end Architectures
The primary criteria in selecting any RF front-end architecture are complexity, cost,
power distribution and number of external components. There are three RF front end
architectures in popular use today: heterodyne (or super-heterodyne), homodyne (or direct
conversion or zero-IF) and low-IF (or digital-IF) architecture [2].
2.3.1.1 Heterodyne Architecture
In heterodyne architecture, the RF signal is translated to lower IF frequencies in multiple
stages by mixing it with a local oscillator signal. Figure 2.3.2 depicts such a design. The RF
signal is passed through the BPF and amplified by the LNA. Before the signal is mixed with first
local oscillator (fLO1) to generate first IF (fIF1), it is passed through the image reject filter (IRF).
The IRF rejects the image frequency located at the sum of the LO and IF frequencies (fLO + fIF1).
Literature review Chapter two
19
If the image is not rejected then it will fall directly on the IF after mixing and corrupt the signal
information. The channel select filter rejects adjacent channels and improves channel selectivity.
The first IF signal is mixed with second local oscillator (fLO2) to obtain the second IF signal
(fIF2). Most AM/FM radios use heterodyne architecture with two stages of down-conversion. The
second IF frequency for AM and FM band is 455 kHz and 10.1 MHz respectively.
Figure 2.3.2: Heterodyne (or super-heterodyne) architecture
2.3.1.2 Homodyne Architecture
In homodyne architecture, the RF signal is directly translated to baseband by mixing it
with LO signal whose frequency is same as the carrier frequency. For double-sided AM signal,
this technique works well because it overlaps positive and negative parts of the input spectrum.
2.3.1.3 Low-IF Architecture
The low-IF architecture is hybrid of heterodyne and homodyne architectures.
Here, the RF signal is converted into a low-IF signal and then digitized. Down-conversion from
low-IF to baseband takes place in the digital domain.
Mixing and filtering can be done efficiently in the digital domain. However, the ADC
requirements are more stringent. The ADC should have sufficient input analog bandwidth. The
dynamic range of the ADC must be wide enough to accommodate variations in the signal level
due to path loss and multipath fading. Also, the SFDR should be sufficiently high to keep the
baseband signal from getting corrupted. The BPF filter before the ADC should have sharp cut-
Literature review Chapter two
21
off frequencies to attenuate out-of-band signals. Any signal with frequency more than half the
sampling frequency will fold over in the digital domain.
The software subsystem is basically the FPGA which is programmed by a VHDL code.
2.3.2 Field Programmable Gate Array (FPGA)
An FPGA is an integrated circuit containing a large array of identical logic cells. The
interconnections between cells are programmable; changes can be made in the field over the
lifetime of the device. Cells can be grouped into logic blocks to form higher-level functions.
Functionality is usually described with a hardware language such as VHDL or Verilog; a
synthesis tool is then used to automatically determine the routing required through the device
and produces a register transfer logic (RTL) description. The combination of the algorithm being
implemented, the VHDL code and the efficiency of the synthesis tool will determine the
resources used and the maximum clock frequency for the FPGA. This is a major difference when
compared with a DSP or RCP, where the maximum clock frequency is fixed and independent of
the code running on the device.
VHDL (Very high speed integrated circuit Hardware Description Language) is a hardware
description language used in electronic design automation to describe digital and mixed-signal
systems such as field-programmable gate arrays and integrated circuits.
2.4 Previous work
2.4.1 SDR design of a master degree student
The basic block diagram of the low-cost SDR receiver designed for this project is shown
in Fig. 2.4.1. The AM/FM trainer kit is used to convert the AM signal to amplified AM IF signal.
It is then under-sampled using the high speed ADC of Measurement Computing's PCI-based
DAS4020/12 data acquisition board. Quadrature demodulation is used to demodulate the signal
in and play it in real-time on PC speakers. DSP algorithms are written in MATLAB which is a
simulation and mathematical software from The Math-works Inc.
Literature review Chapter two
21
Figure 2.4.1: Software Defined Radio Receiver for AM Band
2.4.1.1 AM/FM Trainer Kit
This trainer kit is a low cost receiver kit; the antenna signal is fed to the mixer which
down-converts the RF signal to an IF of 455 kHz. The weak IF signal from the mixer is
amplified by the first IF amplifier which is tuned to 455 kHz. The second IF amplifier is also
tuned to 455 kHz and has a fixed gain of about 50. The IF signal is taped out at the output of the
second IF amplifier.
2.4.1.2 DAS4020/12 PCI-based DAQ Card
The AM IF signal from the AM/FM trainer kit is converted into digital domain by
Measurement Computing (MMC)'s DAS4020/12 PCI-based DAQ card.
The PCI-DAS4020/12 is a high speed, analog data acquisition board for PCI bus
computers.
The main advantage of using this card is its seamless operation with standard engineering
software like MATLAB and Lab-VIEW.
2.4.1.3 MATLAB with Data Acquisition Toolbox (DAQ)
Math-Works' MATLAB is a high-level technical computing language and interactive
environment for algorithm development, data visualization, data analysis, and numeric
computation. It has command line, scripting, modular, and graphical programming modes.
In that project MATLAB's DAQ Toolbox was used to control and communicate with the
DAQ card and PC soundcard. The DAQ Toolbox provides a complete set of tools for analog
input, analog output and digital I/O from a variety of PC-compatible data acquisition hardware
including those from Measurement Computing. The toolbox allows configuring external
Literature review Chapter two
22
hardware devices, reading data into MATLAB for immediate analysis, and sending out data.
Together, MATLAB and DAQ Toolbox offer a single, integrated environment to support the
entire data acquisition and analysis process.
MATLAB's Graphical User Interface Development Environment (GUIDE) was used to build the
Graphical User Interface (GUI).
2.4.1.4 PC with Speakers
A PC is required to run MATLAB to acquire data, perform signal processing and output
the processed data to the speakers through the soundcard.
Design and Methodology Chapter three
23
CHAPTER THREE
3 DESIGN AND METHODOLOGY
The ideal receiver scheme would be to attach an analog-to-digital converter to an
antenna. A digital signal processor would read the converter, and then its software would
transform the stream of data from the converter to any other form the application requires.
The ideal scheme is not completely realizable due to the actual limits of the technology.
The main problem is the difficulty of conversion between the digital and the analog domains at a
high enough rate and a high enough accuracy at the same time.
This chapter gives a system level overview of the SDR receiver. Systems designs should
start from the top down and the bottom up simultaneously, making their way to a conclusion via
iteration.
Figure3.1: Design Flow
Design and Methodology Chapter three
24
3.1 Design overview
Figure 3.1.1: SDR receiver block diagram
In figure 3.1.1 the analog signal captured by the antenna is a high frequency signal in the
RF range. The RF hardware block down-converts this signal to IF range in order to be ready for
A/D conversion. The digitized signal is then passed to the DSP software block to extract the
digital base-band samples, these samples are processed by the D/A converter and the analog
output audio signal can be heard clearly by the speaker.
3.2 Hardware
Since ideal SDR cannot be implemented; we must decide where the radio stops being
hardware defined and where it starts being software defined. Most receivers use a variable-
frequency oscillator, mixer, and filter to tune the desired signal to a common intermediate
frequency or baseband, where it is then sampled by the analog-to-digital converter.
Figure 3.2.1: Hardware block diagram
The multiple RF signals received by the antenna are filtered by a channel select filter so
as to pass only the desired AM range, then a low noise amplifier -which maintains acceptable
signal to noise ratio- is used to amplify these weak signals before passing them to the image
reject filter. The image signal is located on the opposite side of the LO frequency and folds on
top of the IF band as the signal is down-converted in a mixer. This creates a serious interference
Design and Methodology Chapter three
25
issue that needs to be addressed using an image reject filter. All these operations are done in the
filtering and LNA block shown in figure 3.2.1.
The RF tuner converts the analog RF signals to analog IF frequencies which will then be
amplified for further processing.
3.3 Software
Software defined radio technology provides an efficient solution to the limitation of the
traditional hardware; allowing multi-mode, multi-band and/or multi-functional wireless devices
that can be enhanced using software upgrades.
The main function of the blocks in figure 3.3.1 is to demodulate the digital IF samples so
as to recover the digital baseband samples. These samples are multiplied with digital sinusoidal
samples of a local oscillator whose frequency is that of the digital IF signal. The effect of this
multiplication is to shift the spectrum of the AM signal down to DC level so that a low pass filter
having a fixed cutoff frequency can be used to pass the baseband message of the radio channel of
interest.
Figure 3.3.1: Software block diagram
Design and Methodology Chapter three
26
In digital sample representation, we have:
[ ( )] ( ) ( )
( ) [ ( )] ( ) ( ) [ ( )][ ( ( ) ) ( )
( ) [ ( )]
[ ( )] ( ( ) ) ( )
The low pass filter after the mixer is design to remove all but the baseband signals.
Consequently, the output of the demodulator will be
( ) [ ( )]
This has an AC component proportional to the baseband message signal m (n). Thus the AM
signal has been successfully demodulated.
Tools and Implementation Chapter four
27
4 CHAPTER FOUR
TOOLS AND IMPLEMENTATION
The ideal scheme is not completely realizable due to the actual limits of the technology.
Since ideal SDR cannot be implemented; we must decide where the radio stops being hardware
defined and where it starts being software defined. Design decisions, including the choice of
sampling frequency, sampling bandwidth, and over or under/pass-band sampling, are key factors.
The concept of where and how a design is started is an important one [5].
The two major components that make the system are: AM/FM Trainer kit, Spartan-3AN.
4.1 AM/FM Trainer Kit
This trainer kit, manufactured by Elenco Electronics, Inc., is a low cost receiver kit used
for demonstrating principles of communication. It is a super-heterodyne receiver of the standard
AM and FM frequencies.
The kit is delivered as a plane board and the various components with the appropriate
values are soldered into the board in order to constitute the different sections needed in the RF
front end architecture. Good soldering practices are used to prevent bad connections. Figure
4.1.1 shows the assembled AM/FM Trainer kit [7].
The parts identified here are the parts needed only for the AM radio. Figure 4.1.2 shows
the block diagram of the AM section of the receiver. The antenna signal is fed to the mixer
which down-converts the RF signal to an IF of 455 kHz.
This is accomplished by heterodyning the RF signal with the Local Oscillator (LO)
signal. The weak IF signal from the mixer is amplified by the first IF amplifier which is tuned to
455 kHz. The first IF amplifier has a variable gain which depends upon the voltage of the AGC
(Automatic Gain Control) stage [2].
Tools and Implementation Chapter four
28
Figure 4.1.1: Assembled AM/FM Trainer kit
The AGC stage feeds back a DC voltage to the first AM IF amplifier in order to maintain
a near constant level of audio at the detector. The second IF amplifier is also tuned to 455 kHz
and has a fixed gain of about 50. It selectively amplifies the IF signal and feeds it to the AM
detector. The AM detector converts the IF signal to a low level audio signal. The Audio
Amplifier stage increases the power of the demodulated audio signal received from the AM
Detector to a power level capable of driving the speaker.
For this project, the IF signal is taped out at the output of the second IF amplifier and
then fed -using the coaxial cable- to the ADC in Spartan-3AN kit where the coherent AM
demodulation takes place [2].
Figure 4.1.2: AM radio section
Tools and Implementation Chapter four
29
4.1.1 Section 1 (AM mixer, AM oscillator, and antenna)
In a super-heterodyne type receiver, the radio wave at the antenna is amplified and then
mixed with the local oscillator to produce the intermediate frequency (IF). Transistor Q7 not
only amplifies the RF signal, but also simultaneously oscillates at a frequency 455 kHz above the
desired radio station frequency. Positive feedback from the collector to the emitter of Q7 is
provided by coil L5 and capacitor C31. During the heterodyning process the following four
frequencies are present at the collector of Q7:
1. The local oscillator frequency, OF.
2. The RF carrier or radio station frequency.
3. The sum of these two frequencies, OF + RF.
4. The difference of these two frequencies, OF – RF.
The ―difference frequency‖ is used as the intermediate frequency in AM radios. The
collector of Q7 also contains an IF transformer (T6) tuned only to the difference frequency. This
transformer rejects all frequencies except those near 455 kHz. T6 also couples the 455 kHz
signal to the base of Q8 to be processed by the IF amplifiers. The antenna and the oscillator coils
are the only two resonant circuits that change when the radio is tuned for different stations. Since
a radio station may exist 455 kHz above the oscillator frequency, it is important that the antenna
rejects this station and selects only the station 455 kHz below the oscillator frequency. The
frequency of the undesired station 455 kHz above the oscillator is called the image frequency. If
the selectivity of the antenna (Q factor) is high, the image will be reduced sufficiently. The
oscillator circuit must also change when the radio is tuned in order to remain 455 kHz above the
tuning of the desired radio station. The degree of accuracy in keeping the oscillator frequency
exactly 455 kHz above the tuning of the antenna is called tracking accuracy [7].
4.1.2 Section 2 (First AM IF amplifier)
The operation of the first IF amplifier is the same as the second IF amplifier with one
important difference: The gain of the first IF amplifier decreases after the AGC(Automatic Gain
Control) threshold is passed to keep the audio output constant at the detector and prevent
overload of the second IF amplifier. This is accomplished by making the voltage on the base of
transistor Q8 lower as the signal strength increases. Since the voltage from base to emitter is
fairly constant, the drop in voltage at the base produces a similar drop in voltage at the emitter of
Q8. This drop lowers the voltage across R37 and thus, reduces the DC current through R37.
Tools and Implementation Chapter four
31
Since all of the DC current from the emitter of Q8must go through R37, the DC current in Q8 is
therefore lowered.
When the DC current in a transistor is lowered, its effective emitter resistance increases.
The AC gain of transistor Q8 is equal to the AC collector load of Q8 divided by its effective
emitter resistance. Raising the value of the effective emitter resistance, thus, lowers the AC gain
of Q8 [7].
Figure 4.1.3: Assembly instructions of section 1
Tools and Implementation Chapter four
31
Figure 4.1.4: Assembly instructions of section 2
4.1.3 Section 3 (Second AM IF amplifier)
The purpose of the second IF amplifier to increase the amplitude of the intermediate
frequency (IF) and at the same time provide selectivity. Selectivity is the ability to ―pick out‖
one radio station while rejecting all others. The second IF transformer (T8) acts as a band-pass
filter with a 3dB bandwidth of approximately 6 kHz.
Both IF amplifiers are tuned to a frequency of 455 kHz and only need to be aligned once
when the radio is assembled.
These amplifiers provide the majority of the gain and selectivity needed to separate the
radio stations. The gain at 455kHz in the second IF amplifier is fixed by the AC impedance of
the primary side of transformer T8, and the DC current in Q9. The current in Q9 is set by
resistors R39, R40 and R41. Both C36 and C37 bypass the 455 kHz signal to ground, making Q9
a common emitter amplifier. The signal is coupled from the first IF amplifier to the second IF
amplifier through transformer T7. The IF transformers not only supply coupling and selectivity,
they also provide an impedance match between the collector of one stage and the base of the next
stage. This match allows maximum power to transfer from one stage to the next [7].
Tools and Implementation Chapter four
32
Figure 4.1.5: Assembly instructions of section 3
4.1.4 Section 4 (AM detector and AGC stage)
The purpose of the detector is to change the amplitude modulated IF signal back to an
audio signal. This is accomplished by a process called detection or demodulation. First, the
amplitude modulated IF signal is applied to a diode in such a way as to leave only the negative
portion of that signal. The diode acts like an electronic check valve that only lets current pass in
the same direction as the arrow (in the diode symbol) points.
When the diode is in conduction (On Condition), it will force the capacitors C33 and C38
to charge to approximately the same voltage as the negative peak of the IF signal.
After conduction stops in the diode (Off Condition), the capacitors will discharge through
resistors R36 and R42. The discharge time constant must be small enough to follow the audio
signal or high frequency audio distortion will occur.
The purpose of the automatic gain control (AGC) circuit is to maintain a constant level at
the detector, regardless of the strength of the incoming signal. Without AGC, the volume control
would have to be adjusted for each station and even moderately strong stations would clip in the
final IF amplifier causing audio distortion. AGC is accomplished by adjusting the DC bias of the
first IF amplifier to lower its gain as the signal strength increases [7].
Tools and Implementation Chapter four
33
Figure 4.1.6: Assembly instructions of section 4
4.2 Coaxial cable
Coaxial cable differs from other shielded cable used for carrying lower frequency signals,
such as audio signals, in that the dimensions of the cable are controlled to give a precise,
constant conductor spacing, which is needed for it to function efficiently as a radio frequency
transmission line. [4]
4.3 Spartan-3AN starter kit
Three sections of Spartan-3AN kit are used in this project, analog capture circuit, field
programmable gate array (FPGA) and digital to analog converter (DAC) (see Appendix B).
4.3.1 Analog capture circuit
The Spartan-3AN FPGA Starter Kit board includes a two-channel analog capture circuit,
consisting of a programmable scaling pre-amplifier and an analog-to-digital converter (ADC).
The output of the preamplifier connects to the ADC. Both the pre-amplifier and the ADC
are serially programmed or controlled by the FPGA.
To avoid aliasing, the ADC (analog-to-digital converter) needs to sample signal at
sampling rate at least twice the highest frequency of the received signal (455KHz), thus a
sampling rate of 1.5 MHz will be sufficient for the ADC to allow for some margin.
Tools and Implementation Chapter four
34
4.3.2 Field Programmable Gate Array (FPGA)
An FPGA is a semiconductor device containing programmable logic components and
programmable interconnects. The functionality of basic logic gates (AND, OR, XOR, NOT) or
more complex combinational functions such as decoders and simple math functions can be
duplicated by programming logic components of the FPGA. Most FPGAs today include memory
blocks too. Different logic components are connected together by a hierarchy of programmable
interconnects. Hardware descriptive languages like VHDL or VERILOG are used to program
FPGAs [2].
System Generator is a DSP design tool from Xilinx that enables the use of the Math-
Works model-based Simulink design environment for FPGA design.
Previous experience with Xilinx FPGAs or RTL design methodologies is not required
when using System Generator. Designs are captured in the DSP friendly Simulink modeling
environment using a Xilinx specific block set. All of the downstream FPGA implementation
steps including synthesis and place and route are automatically performed to generate an FPGA
programming file [8].
The model shown in figure 4.3.1 was designed mainly for coherent AM demodulation
which consists of registers, multiplier and multistage FIR filters. Using the system generator
block, the VHDL code was generated.
The gateway-in takes the input via the serial peripheral interface (SPI) from the ADC.
Registers are used as storage area so that all data must be represented in a register before
it can be processed; because the FPGA is not capable of handling high rate of changes in the data
inserted. In figure 4.3.1, the incoming modulated signal –from the ADC- and the generated
carrier signal are both placed in registers before multiplication can take place.
The effect of this multiplication is to shift the spectrum of the AM signal down to DC
level so that a low pass filter having a fixed cutoff frequency can be used to pass the baseband
message of the radio channel of interest [9].
For AM receivers, the Low Pass Filter (LPF) plays a critical role in isolating adjacent
channel interferences, and thus minimizing the noise at the output. The bandwidth of an AM
channel is 9 kHz, thus a LPF having pass-band from 0-4.5 kHz is desired.
Tools and Implementation Chapter four
35
Figure 4.3.1: Coherent AM demodulation model
In designing the FIR filter, we seek to minimize the filter order (or number of filter taps)
while satisfying requirements. FIR filter theory states that the filter order is approximately
proportional to the input sampling frequency and inversely proportional to the width of the
transition band. That is the higher the input sampling frequency, the higher the filter order, and
the narrower the transition band, the higher the filter order [9].
(4.1)
Given that pass-band ripple and stop-band attenuation are kept fixed.
Knowing that Fs = 1500 kHz (sampling rate of the ADC), Fpass
= 3 kHz and Fstop
= 4.5
kHz, thus using equation (4.1), the number of filter taps required would be [1500/ (4.5-3) =
1000]. This number of taps is astronomically large due to very high input sampling rate and the
narrow transition band. Therefore, a single FIR filter satisfying our requirements would be
impossible to be realized in hardware. However, close observation reveals that since the output
of the filter is a baseband message of bandwidth around 4 kHz, the output sample rate needs not
be maintained at 1500 kHz, but could be reduced to around twice the bandwidth of the baseband
message (about 8 kHz) just to satisfy the Nyquist theorem. This fact allows us to employ a
Tools and Implementation Chapter four
36
common strategy of multistage filtering to reduce the number of filter taps. The single stage
Filter of very high order is replaced by a chain of N stages of smaller order [7].
Figure 4.3.2: Multi-stage filtering
Consider the fundamental case in figure 4.3.3 where at each stage, the sampling rate is
reduced by a half (a factor of 2), let fin
be the input sampling rate (to the first stage), and fout
be
the desired output sampling rate (of the last stage), then (
) hence the number of stages
is given by:
(
) ( )
Figure 4.3.3: N-stage Filter with down-sample by a factor of 2 at each stage
Let fc
be the cutoff frequency of all the filters in the chain, noting that fc
is our designed cut off
frequency for the original single stage high order filter. The stop-band frequency of the filter in
Tools and Implementation Chapter four
37
each stage is set at half the new sampling rate for the next stage. Table shows details of the
cutoff and stop-band frequency for each filter in the chain.
Using equation (4.1), we can estimate the total number of filter taps (denoted M) required in this
case as follow [9]:
( )
Calculation of the number of taps:
Equation 4.3 was used to calculate the number of taps of the FIR filters presented in figure 4.4:
Fout was chosen to be 15 KHz to satisfy Nyquist theorem.
(
)
fc = 4 KHz.
M = 4.043 + 4.087 + 4.178 + 4.373 + 4.823 + 6.073 + 12.605
The Math-Works FDA tool which is a standard MATLAB function can be used to create
coefficients for the Xilinx FIR Compiler.
The gateway out then sends the output via the serial peripheral interface (SPI) to the
DAC.
4.3.3 Digital-to-Analog Converter
The Spartan-3AN FPGA Starter Kit board includes an SPI-compatible, four-channel,
serial Digital-to-Analog Converter (DAC). The DAC has 12-bit unsigned resolution.
Tools and Implementation Chapter four
38
4.3.4 Serial Peripheral Interface
The interconnection between two SPI devices always happens between a master device
and a slave device. Compared to some peripheral devices like sensors which can only run in
slave mode the master is the active part in this system and has to provide the clock signal that a
serial data transmission is based on. The slave is not capable of generating the clock signal and
thus cannot get active on its own. The slave just sends and receives data if the master generates
the necessary clock signal. The master however generates the clock signal only while sending
data. That means that the master has to send data to the slave to read data from the slave. The
slave just sends and receives data if the master generates the necessary clock signal.
Devices communicate using a master/slave relationship, in which the master initiates the
data frame. When the master generates a clock and selects a slave device, data may be
transferred in either or both directions simultaneously. In fact, as far as SPI is concerned, data are
always transferred in both directions. It is up to the master and slave devices to know whether a
received byte is meaningful or not.
Input/output Signals (Pins) of the Serial Peripheral Interface SPI:
SPI specifies four signals: clock (SCLK); master data output, slave data input (MOSI);
master data input, slave data output (MISO); and slave select (/SS). SCLK is generated by the
master and input to all slaves. MOSI carries data from master to slave. MISO carries data from
slave back to master. A slave device is selected when the master asserts its /SS signal.
MOSI: Master Output Slave Input.
MISO: Master Input Slave Output.
SCLK: Clock signal from master to slave.
SS: Slave select from master to slave.
If multiple slave devices exist, the master generates a separate slave select signal for each slave.
Results and Discussion Chapter five
39
5 CHAPTER FIVE
RESULTS AND DISCUSSION
5.1 Hardware Results:
The assembled AM trainer kit is working properly; the desired AM channels were tuned
easily giving voice with a little noise. This is because the signal reception is not very good in the
laboratory where this test was run. Also the receiver is a low-cost radio and hence has a
relatively poor performance for weak signals.
The detector section along with the speaker were needed only for testing purposes in
order to make sure that different radio stations can be selected accurately.
5.2 Simulation Results
Knowing that the model that has been designed is used to demodulate the AM signal
inserted to the FPGA.
This model cannot be tested unless the code generated is loaded to the FPGA and the real
AM radio signal is inputted; so to test it we must generate AM modulated signal using
MATLAB Simulink blocks and use it along with this model. This is done by having a cosine
wave multiplied by carrier signal with frequency 455 KHz. Figure 5.1 shows the simulation
model used for testing.
In the model shown in figure 5.2.1 we notice that we have used frequency spectrum in
several stages in order to show the results in each stage and compare it the theoretical results
expected.
Frequency methods focus on how signals of different frequencies are represented in a
signal. In many electrical circuits and systems, the different parts of the signal spectrum are
treated differently. Different treatment of different parts of the electromagnetic spectrum means
that we can separate out signals.
Results and Discussion Chapter five
41
Figure 5.2.1: The Simulink model
Results and Discussion Chapter five
41
Since the audio signal is a summation of sinusoidal signals and for approximation and
testing purposes we use a cosine signal as input in the simulation.
In the first stage we plot the spectrum of the input (cosine) signal in the frequency
domain and the result is shown in figure 5.2.2.
Figure 5.2.2: Frequency spectrum of a cosine signal
In the second stage the modulating signal was then multiplied by another cosine signal
with a frequency to produce AM modulated signal as was seen in the previous chapters.
To determine this AM modulated signal in the frequency domain we firstly need to know
more about Fourier transform of signals generally and then to know it in our specific case here.
The mathematical expression of the cosine signal in the time domain is as follows:
( )
( )
Results and Discussion Chapter five
42
By using Euler rule the cosine function can be approximated as two exponential functions
as we have seen in equation (5.1).
Generally the Fourier transform of a signal is performed as shown in equation (5.2):
( ) ∫ ( )
( )
The AM modulated signal can be written in a simple manner as described in equation (5.3)
( ) ( ) ( ) ( )
Where ( ) is the modulating signal.
Using equations (5.1), (5.2) and (5.3) and combined them together we can write an expression
for the modulated signal as follows:
( ) ∫ ( ) ( )
∫ ( )
( ) ( )
( ) ( ) ( )
Equation (5.4) shows that if we have any arbitrary signal multiplied by a cosine signal in
the time domain and we need to find its Fourier transform; i.e. its representation in the frequency
domain then we firstly find the spectrum of the signal -before multiply it be the cosine function-
and simply shift this spectrum around the frequency of the cosine signal. This characteristic is
known as shifting theory and it's one of the most important characteristic of Fourier transform
and usually used to simplify the calculations.
In the case we discussed here ( ) ( ) then the spectrum is simply the
spectrum shown in figure 5.2, shifted around the carrier frequency which is 455 KHz. This is
shown clearly in figure 5.3 which shows the AM modulated signal.
In figure 5.2.3 we notice that we have two components in the positive and negative
frequencies; in fact there is only positive frequency and the negative is just for mathematical
purposes.
Results and Discussion Chapter five
43
Figure 5.2.3: Frequency spectrum of AM modulated signal
As mentioned previously this is all done to test the model that we use in this project, and
as we have seen earlier the demodulation method used is coherent demodulation in which the
modulated signal is multiplied by another cosine signal with the same frequency as the carrier
used in modulation process.
To find the spectrum of the demodulated signal shifting theory is used here. The analysis
of this process in frequency domain is that since we have two component of the signal in positive
and negative frequencies then we can divide the analysis into two parts; firstly the positive
component: since the positive component is ( ) then the multiplication with ( )
will result in another two components one placed around double the carrier frequency and the
other one around the zero frequency. In the negative component we do the same procedure and
the result is as same as the positive component except that the first component is at the negative
double frequency. This is shown in figure 5.2.4.
Results and Discussion Chapter five
44
Figure 5.2.4: Frequency spectrum of the demodulated signal
In order to get our baseband signal back then the signal results from the demodulation
step must be passed through low pass filter in order to filter out the components of the signal in
higher harmonics; this is done by using multi stage filter because one stage filter has high order
and cannot be implemented practically. The output of this last stage is our modulating (cosine)
signal. This can be realized from figure 5.2.5 which confirms this theoretical abstraction.
Since the simulation process done properly and the signal we entered can be recovered
after the modulation and demodulation process then we have made sure that the model is doing
exactly what it is supposed to do.
Results and Discussion Chapter five
45
Figure 5.2.5: Spectrum of the signal after the multistage low pass filter
After this successfully simulation test these blocks must be converted into a VHDL code
using ISE system generator in order to be able to load it to the FPGA. This code was generated
also correctly but we faced a problem in our design, this problem is illustrated below in more
details but before that let's take a complete vision of the signal path from the moment it have
been captured by the antenna until we can hear a voice by the speaker.
Firstly the signal is captured by the antenna along with many other signals in the RF
range, then to have specific range a band select filter is used to reject all signals outside the AM
range, this signal has a very low power so in order to amplify it without having much noise a low
noise amplifier is used to perform this function. After that it is mixed with a local oscillator to
down-convert it to Intermediate Frequency. All these steps are done using AM/FM trainer kit
and at this point its functions are completed and the signal is taken away from it for further
processing.
Results and Discussion Chapter five
46
The jobs of the software begin immediately after the RF hardware completes its
functions; here the digital signal processing is done using PFGA. But we have a little problem
here which is the signal taken from the AM/FM trainer kit is an analog signal and the FPGA
deals only with the digital signals; fortunately this problem can be solved simply by using analog
to digital converter. Then the digitized signal is entered to FPGA to perform the demodulation
process, and prior to use a speaker to hear the audio signal a digital to analog process must take
place because the speaker deals with analog signals only.
Luckily ADC, FPGA and DAC are packaged together in one kit- Spatran-3AN kit. Data
received by ADC is in parallel form and the FPGA receive data in digital form so we must
provide interface between them so that data can flow easily. This interface can be done using
Serial Peripheral Interface (SPI) protocol. This protocol allows the date to be transferred from
ADC to FPGA serially and to be received by the DAC in parallel manner.
The ADC and DAC have SPI built in them so we don't need to program them but the
FPGA don't. The biggest problem faced us was how to provide SPI interface in the FPGA; our
solution was to write a VHDL code and compile it with ISE compiler and then tried to link it
with the code generated from the model by the ISE system generator. This is done correctly and
the pins assignment of the FPGA with ADC and DAC was done as shown in the manual of the
kit and after all that a synthesize process (by the ISE synthesizer) was done without any errors.
This solution seems perfect from the first look but the problem is that the ISE is not capable of
compiling a code generated from a MATLAB Simulink along with SPI code written in VHDL.
In order to solve this problem there is two solutions: either by trying to write the whole
code in VHDL without the using of MATLAB Simulink, or by using a block in Simulink which
perform the SPI protocol function; i.e. either by using pure VHDL code, or using pure MATLAB
Simulink, but not a mix of them. In the former case the code is downloaded to the FPGA as
VHDL code, and in the latter case as bit stream manner.
Conclusion and Future Improvement Chapter
six
47
6 CHAPTER SIX
CONCLUSION AND FUTURE IMPROVEMENT
With the increasing computing power of modern microprocessors it becomes feasible to
process radio signals completely in software reducing the complexity of the hardware.
While traditional hardware is still in common use and will be for quite some time to
come Software Define Radio (SDR) systems look very promising for the future. The flexibility
of software based systems with regards to various use cases and adaptability to a variable
environment will make them mainstream for many different applications.
They will be capable of replacing traditional hardware systems like FM radio or TV
broadcast as well as cell based phone systems. Actually, it is quite possible that these different
categories of radio systems will merge over time.
Software Defined Radio receiver has several advantages comparing with the Hardware
Defined Radio receiver:
a. The ability to receive and transmit various modulation methods using a common set of
hardware.
b. The ability to alter functionality by downloading and running new software at will.
c. The possibility of adaptively choosing an operating frequency and a mode best suited for
prevailing conditions.
d. The opportunity to recognize and avoid interference with other communications
channels.
e. Elimination of analog hardware and its cost, resulting in simplification of radio
architectures and improved performance.
f. The chance for new experimentation.
The general idea of SDR is to use hybrid system; i.e. RF hardware subsection and
software subsection; this goal can be achieved using different designs. The chosen of one design
Conclusion and Future Improvement Chapter
six
48
among all alternatives depends on several factors: the strength of the signal received and its
modulation scheme, the required SNR, the availability of the components used and the cost of
them, and so on.
In this project different designs and trials were made in order to achieve the objectives of
the project but unfortunately there were some problems and limitations along with most of the
designs as we can see in the following section.
6.1 Challenges and Limitations
A software-defined radio receiver can be implemented in different designs having the
same basic concepts; it is just a matter of using different alternatives performing the same
functions.
6.1.1 Band pass filter:
Using the operational amplifier to implement the band pass filter was our first
trial; this BPF is used basically to select the AM band from the frequencies captured by the
antenna. Band pass filters designed using op-amps are very practical but for other
applications; in this case frequency limitations can introduce a real problem. According to
the op-amp characteristics and the gain-bandwidth product (which is only 1MHz for LS-
741); the maximum received frequency will not exceed 1MHz (less than the upper limit of
the AM band 1.5MHz) in the case of unity gain. This is not acceptable because the received
signal is already weak and it needs amplification in the range of (20-30 dB), otherwise the
information carried by the signal will be lost. Other types of op-amps were suggested
because of their higher gain-bandwidth product; but they were not sufficient for passing the
desired frequencies.
Another alternative is the passive filter (an electric filter composed of passive
elements, such as resistors, inductors, or capacitors, without any active elements, such as
vacuum tubes or transistors). In order to design a band-pass filter; a combination of both the
high-pass filter and the low-pass filter was used. The main challenge of this design is to
calculate the perfect values for the resistors, capacitors and inductors given the exact cut-off
frequencies of the AM band. These passive filters are not commonly used because they are
not practical; high frequencies are not easily implemented (filtered) using such simple
Conclusion and Future Improvement Chapter
six
49
circuits. So cascaded stages of these simple circuits must be used; but the values needed for
the components are not available and the number of elements is large.
A design consisting of five transistors was also suggested; but it was a little
complicated and with more requirements (equal Beta) which are difficult to find because of
manufacturing tolerance.
6.1.2 Mixer:
In the design of radio receivers; the RF band should be down converted to IF band
according to the hardware limitations so a frequency mixer is used with the help of a
local oscillator.
A diode-ring modulator was one of the alternatives, but because of the highly nonlinear
nature of the diodes, the impedances at the three ports (transformers) are poorly
controlled, making matching difficult. Furthermore, there is considerable coupling
between the three ports; this, and the high power needed at the LO port, make it very
likely that there will be some component of the (highly distorted) LO signal coupled back
toward the antenna. Finally, it will be apparent that a passive mixer such as this cannot
provide conversion gain; in the idealized scenario, there will be a conversion loss. A
practical mixer will have higher losses due to the resistances of the diodes and the losses
in the transformers.
An IC for the ring modulator is available; so the diodes matching problem is eliminated,
but on the other hand the external circuit that is connected to the chip to construct the
frequency mixer is too complicated and the values used are not available.
The whole mixing idea is not needed here in SDR; since we are not restricted to a particular
value for the IF. This is one of the advantages of using software in digital signal processing. A
digital IF filter was suggested to select a particular channel.
6.1.3 ADC:
An ADC chip was the first option suggested to convert the analog received signal into digital
form which is suitable for the PC in order to be able to demodulate it by the software
program. This chip couldn't be used because the coding process is done by 8 bits per sample
and this will lead to inaccurate results in the information recovery (DAC).This problem could
be solved using an IC chip with 12 bits per sample , unfortunately this chip is not available.
Conclusion and Future Improvement Chapter
six
51
The most commonly used method to implement the ADC is by using microcontroller chip,
which has coding accuracy of 10 bits per sample, although this method has perfect results in
low frequencies; it can't be implemented because we need a high sampling frequency that
makes the whole system frequency much higher than that generated by the internal oscillator,
so in order to perform this method we should use an external oscillator which is not
available.
A/D conversion can also be achieved by the PC soundcard, but this couldn't be done here
since its frequency limit is 44.1 kHz while the RF signal has a very high frequency range.
This fact also eliminates the idea of using the IF digital filter, which creates the need of the
mixer.
6.1.4 Software Problem:
The code for the demodulation can be written easily using MATLAB (m file) and
workspace, but the problem was how to insert the demodulated signal with its relative high
frequency to the PC to run the code and extract the baseband modulating signal. According to the
limitation of the frequencies that can be handled by the sound card and the serial port they are
not one of the choices here. This signal can be inserted using USB2 but even if we insert it
successfully we will face another problem which is that the MATLAB cannot handle the high
oscillation of the signal.
All the problems mentioned so far have been eliminated by the use of the AM/FM trainer kit
along with Spartan-3AN kit.
Using embedded microprocessors in an FPGA and combining them with other advanced
features of the fabric allows for a powerful solution on a single, reprogrammable chip.
6.2 Digital Signal Processing Alternatives
The alternatives available for digital signal processing are - Application Specific
Integrated Circuits (ASIC) and Digital Signal Processors (DSP).
ASICs are integrated circuits customized to accomplish specific tasks at high
performance levels. They are unrivaled in speed, power efficiency and computational density.
Because of their high design and production cost, they are usually used in high volume designs.
Conclusion and Future Improvement Chapter
six
51
The major disadvantage is that they are not reconfigurable. They can be used for implementing
limited to standard static functions. Because of these limitations, their use in SDRs is limited.
A DSP is a specialized microprocessor designed specifically for digital signal processing,
generally in real-time computing. It has an optimized signal processing instruction set and can be
programmed using high level programming languages like C and C++. On a performance matrix,
DSPs fall in between ASICs and FPGAs. They have moderate costs but very short times to
market. They are the backbone of most SDR systems today. Many leading semiconductor
companies are currently developing SDR specific DSPs [2].
DSP tends to minimize cost and maximize flexibility in receivers. Thus, another goal of
SDR research is to eliminate as much analog hardware as possible. It may be possible someday
to digitally sample signals directly from the antenna while still maintaining high dynamic range.
6.3 Future Improvement
Instead of using MATLAB Simulink blocks; a VHDL can be used to write the
demodulation code so that the linking between it and the SPI code can be done properly
then compiling it using ISE compiler and loaded the overall code into the FPGA. Another
option to solve the problem of the mismatching between the code generated and the SPI
code; is to compose the SPI protocol using MATLAB Simulink blocks, then generate the
code in a bit stream manner and loaded it directly to the FPGA without the need to pass
through the VHDL stage.
The project could be extended to include other modulation schemes as well like FM, SW,
CB, etc. Quadrature demodulation can be used for FM if two analog input channels are
available. Noise canceling algorithms can also be implemented to further improve signal
to noise ratio.
Instead of converting RF to IF, the whole AM band could be band-pass sampled. This
will allow demodulation of multiple AM channels at the same time. However this will
require an amplifier with a sharp band-pass response to reject all out-of-band signals.
This amplifier will be placed between the antenna and the DAQ card.
A-1
Appendix A
Filter Design and Analysis using FDA Tool of MATLAB
The Filter Design and Analysis Tool (FDA Tool) is a powerful user interface for
designing and analyzing filters quickly. FDA Tool enables you to design digital FIR
or IIR filters by setting filter specifications, by importing filters from your MATLAB
Work space. FDA Tool also provides tools for analyzing filters, such as magnitude
and phase response.
Use FDATOOL in MATLAB:
If you type
>>fdatool
in command window, FDA tool will be opened. There you can select FIR or IIR filter,
order of filter and cutoff frequency of a filter (HPF, LPF or BPF).
Getting Started
Type fdatool at the MATLAB command prompt:
>>fdatool
A Tip of the Day dialog displays with suggestions for using FDA Tool. Then,
the GUI displays with a default filter.
The GUI has three main regions:
1. The Current Filter Information region.
2. The Filter Display region.
3. The Design panel.
A-2
The upper half of the GUI displays information on filter specifications and
responses for the current filter. The Current Filter Information region, in the
upper left, displays filter properties, namely the filter structure, order, number
of sections used and whether the filter is stable or not. It also provides access to the
Filter manager for working with multiple filters.
The Filter Display region, in the upper right, displays various filter responses, such as,
magnitude response, group delay and filter coefficients.
The lower half of the GUI is the interactive portion of FDA Tool. The Design Panel,
in the lower half is where you define your filter specifications. It controls what is
displayed in the other two upper regions. Other panels can be displayed in the lower
half by using the sidebar buttons.
Designing a Filter
We will design a low pass filter that passes all frequencies less than or equal to 20%
of the Nyquist frequency (half the sampling frequency) and attenuates frequencies
greater than or equal to 50% of the Nyquist frequency.
We will use an FIR Equiripple filter with these specifications:
1. Pass-band attenuation 1 dB
2. Stop-band attenuation 80 dB
3. A pass-band frequency 0.2 [Normalized (0 to 1)]
4. A stop-band frequency 0.5 [Normalized (0 to 1)]
To implement this design, we will use the following specifications:
1. Select Low-pass from the dropdown menu under Response Type and
Equiripple under FIR Design Method. In general, when you change the
Response Type or Design Method, the filter parameters and Filter Display
region update automatically.
2. Select Specify order in the Filter Order area and enter the specified filter
order.
3. The FIR Equiripple filter has a Density Factor option which controls the
density of the frequency grid. Increasing the value creates a filter which more
closely approximates an ideal equiripple filter, but more time is required as the
computation increases. Leave this value at 20.
A-3
4. Select Normalized (0 to 1) in the Units pull down menu in the Frequency
Specifications area.
5. After setting the design specifications, click the Design Filter button at the
bottom of the GUI to design the filter. The magnitude response of the filter is
displayed in the Filter Analysis area after the coefficients are computed.
Viewing other Analyses
Once you have designed the filter, you can view the following filter analyses in the
display window by clicking any of the buttons on the toolbar:
In order from left to right, the buttons are
1. Magnitude response
2. Phase response
3. Magnitude and Phase responses
4. Group delay response
5. Phase delay response
6. Impulse response
7. Step response
8. Pole-zero plots
9. Filter Coefficients
10. Filter Information
Changing Axes Units
You can change the x- or y-axis units by right-clicking the mouse on an axis
label and selecting the desired units. The current units have a checkmark.
Optimizing the Design
To minimize the cost of implementation of the filter, we will try to reduce the number
of coefficients by using Minimum Order option in the design panel.
Change the selection in Filter Order to Minimum Order in the Design Region and
leave the other parameters as they are.
Click the Design Filter button to design the new filter.
4A-
Exporting the Filter
Once you are satisfied with your design, you can export your filter to the following
destinations:
1. MATLAB workspace
2. MAT-file
3. Text-file
Select Export from the File menu. If exporting to the MATLAB workspace the steps
are:
1. Open the FDA tool.
2. Click on File -> Export
3. Select Workspace, and export as Coefficients.
4. This will generate a new variable called Num in MATLAB workspace.
5. Go to the n-tap filter - > properties
6. Put the new variable name Num
7. Test the filter.
B-1
APPENDIX B Selected chapters from the manual of Spartan-3AN kit related to our project.
General Description of FPGA
Spartan-3A/3AN FPGA Features and Embedded Processing Functions
The Spartan-3A/3AN Starter Kit board highlights the unique features of the Spartan-3A and
Spartan-3AN FPGA families and provides a convenient development board for embedded
processing applications. The board highlights these features:
1. Spartan-3AN specific features
Nonvolatile configuration from internal SPI Flash
2. Spartan-3A/3AN specific features
Parallel NOR Flash configuration
SPI serial Flash configuration using either the STMicroelectronics or Atmel Data-Flash
architectures
Multi-Boot FPGA configuration from both Parallel NOR and SPI serial Flash PROM.
Spartan-3A and Spartan-3AN FPGAs
The Spartan-3AN FPGA platform offers nonvolatile pin-compatible versions of the
Spartan-3A FPGA platform. The Spartan-3AN FPGAs support the same external programming
sources as Spartan-3A FPGAs, but add an additional internal SPI Flash programming mode. The
internal SPI Flash can also be used for user data. The Spartan-3A/3AN Starter Kit Board
supports both external and Spartan-3AN internal configuration options.
Spartan-3AN FPGAs require VCCAUX to be 3.3V while Spartan-3A FPGAs allow
VCCAUX to be either 2.5V or 3.3V. The Spartan-3A/3AN Starter Kit Board uses a default
VCCAUX of 3.3V. Spartan-3A and Spartan-3AN FPGAs have different documentation and
availability. Verify the latest version of the appropriate documentation on xilinx.com.
B-2
Chapter Nine
Analog Capture Circuit
The Spartan®-3A/3AN FPGA Starter Kit board includes a two-channel analog capture circuit,
consisting of a programmable scaling pre-amplifier and an analog-to-digital converter (ADC), as
shown in Figure 9-1.
The analog capture circuit consists of a Linear Technology LTC6912-1 programmable
preamplifier that scales the incoming analog signal on the J22 header. The output of the
preamplifier connects to a Linear Technology LTC1407A-1 ADC. Both the pre-amplifier and the
ADC are serially programmed or controlled by the FPGA.
B-3
Digital Outputs from Analog Inputs
The analog capture circuit converts the analog voltage on VINA or VINB and converts it to a 14-
bit digital representation, D [13:0], as expressed by Equation 9-1.
The GAIN is the current setting loaded into the programmable pre-amplifier. The reference
voltage for the amplifier and the ADC is 1.65V, generated via a voltage divider shown in Figure
9-2. Consequently, 1.65V is subtracted from the input voltage on VINA or VINB.
B-4
The maximum range of the ADC is ±1.25V, centered on the reference voltage, 1.65V. Hence,
1.25V appears in the denominator to scale the analog input accordingly.
Finally, the ADC presents a 14-bit, two‘s complement digital output. A 14-bit, two‘s
complement number represents values between -213
and 213
-1. Therefore, the quantity is scaled
by 8192, or 213
.
See ―Programmable Pre-Amplifier‖ to control the GAIN settings on the programmable pre-
amplifier.
The reference design files provide more information on converting the voltage applied on VINA
or VINB to a digital representation.
Programmable Pre-Amplifier
The LTC6912-1 provides two independent, inverting amplifiers with programmable gain. The
purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it maximizes
the conversion range of the DAC, namely 1.65 ± 1.25V.
Interface
Table 9-1 lists the interface signals between the FPGA and the amplifier. The SPI_MOSI and
SPI_SCK signals are shared with other devices on the SPI bus. The AMP_CS signal is the
active-Low slave select input to the amplifier.
Programmable Gain
Each analog channel has an associated programmable gain amplifier (see Figure 9-2). Analog
signals presented on the VINA or VINB inputs on the J7 header are amplified relative to 1.65V.
The 1.65V reference is generated using a voltage divider of the 3.3V voltage supply.
B-5
SPI Control Interface
Figure 9-3 highlights the SPI-based communications interface with the amplifier. The gain for
each amplifier is sent as an eight-bit command word, consisting of two four-bit fields. The most-
significant bit, B3, is sent first.
The AMP_DOUT output from the amplifier echoes the previous gain settings. These values can
be ignored for most applications. The SPI bus transaction starts when the FPGA asserts
AMP_CS Low (see Figure 9-4). The amplifier captures serial data on SPI_MOSI on the rising
edge of the SPI_SCK clock signal. The amplifier presents serial data on AMP_DOUT on the
falling edge of SPI_SCK.
UCF Location Constraints
Figure 9-5 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
Analog-to-Digital Converter (ADC)
The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously when the
AD_CONV signal is applied.
Interface
Table 9-3 lists the interface signals between the FPGA and the ADC. The SPI_SCK signal is
shared with other devices on the SPI bus. The active-High AD_CONV signal is the active- Low
slave select input to the DAC. The DAC_CLR signal is the active-Low, asynchronous reset input
to the DAC.
B-6
SPI Control Interface
Figure 9-6 provides an example SPI bus transaction to the ADC. When the AD_CONV signal
goes High, the ADC simultaneously samples both analog channels. The results of this conversion
are not presented until the next time AD_CONV is asserted, a latency of one sample. The
maximum sample rate is approximately 1.5MHz. The ADC presents the digital representation of
the sampled analog values as a 14-bit, two‘s complement binary value.
UCF Location Constraints
Figure 9-8 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
B-7
Chapter Ten
Digital-to-Analog Converter (DAC)
The Spartan®-3A/3AN FPGA Starter Kit board includes an SPI-compatible, four-
channel, serial Digital-to-Analog Converter (DAC). The DAC device is a Linear Technology
LTC2624 quad DAC with 12-bit unsigned resolution. The four outputs from the DAC appear on
the J21 header, which uses the Diligent six-pin Peripheral Module format. The DAC and the
header are located immediately below the Ethernet RJ-45 connector, as shown in Figure 10-1.
SPI Communication
As shown in Figure 10-2, the FPGA uses a Serial Peripheral Interface (SPI) to
communicate digital values to each of the four DAC channels. The SPI bus is a full-duplex,
synchronous, character-oriented channel employing a simple four-wire interface. A bus master—
the FPGA in this example—drives the bus clock signal (SPI_SCK) and transmits serial data
(SPI_MOSI) to the selected bus slave—the DAC in this example. At the same time, the bus slave
provides serial data (SPI_MISO) back to the bus master.
B-8
Interface Signals
Table 10-1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI,
DAC_OUT, and SPI_SCK signals are shared with other devices on the SPI bus. The DAC_CS
signal is the active-Low slave select input to the DAC. The DAC_CLR signal is the active-Low,
asynchronous reset input to the DAC.
B-9
The serial data output from the DAC is primarily used to cascade multiple DACs. This
signal can be ignored in most applications although it does demonstrate full-duplex
communication over the SPI bus.
SPI Communication Details
After driving the DAC_CS slave select signal Low, the FPGA transmits data on the
SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising edge
of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge. The
LTC2624 DAC transmits its data on the DAC_OUT signal on the falling edge of SPI_SCK. The
FPGA captures this data on the next rising SPI_SCK edge. The FPGA must read the first
DAC_OUT value on the first rising SPI_SCK edge after DAC_CS goes Low. Otherwise, bit 31
is missed. After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by
returning the DAC_CS slave select signal High. The High-going edge starts the actual digital-to-
analog conversion process within the DAC.
Communication Protocol
Figure 10-4 shows the communications protocol required to interface with the
LTC2624DAC. The DAC supports both 24-bit and 32-bit protocol. The 32-bit protocol is shown.
Inside the DAC, the SPI interface is formed by a 32-bit shift register. Each 32-bit command
word consists of a command and an address, followed by a data value. As a new command enters
the DAC, the previous 32-bit command word is echoed back to the master. The response from
the DAC can be ignored although it is a useful to confirm correct communication.
B-9
The FPGA first sends eight dummy or don‘t care bits, followed by a four-bit
command. The most commonly used command with the board is COMMAND [3:0] =
0011 binary, which immediately updates the selected DAC output with the specified
data value. Following the command, the FPGA selects one or all the DAC output
channels via a four-bit address field. Following the address field, the FPGA sends a
12-bit unsigned data value that the DAC converts to an analog value on the selected
output(s). Finally, four additional dummy or don‘t care bits pad the 32-bit command
word.
Specifying the DAC Output Voltage
As shown in Figure 10-2, each DAC output level is the analog equivalent of a
12-bitunsigned digital value, D [11:0], written by the FPGA to the DAC via the SPI
interface. The voltage on a specific output is generally described in Equation 10-1.
The reference voltage, VREFERENCE, is different between the four DAC outputs.
Channels A and B use a 3.3V reference voltage. Channels C and D have a separate
reference voltage, nominally also 3.3V, supplied by the LP3906 regulator designated
as IC18. The reference voltage for Channels C and D can be modified, as described in
―I2C Voltage Adjustment Interface,‖
The reference voltages themselves have a 5% tolerance, so there are slight
corresponding variances in the output voltage.
UCF Location Constraints
Figure 10-5 provides the UCF constraints for the DAC interface, including the
I/O pin assignment and the I/O standard used.
B-9
