NET201- Principles of Information & Technology Systems Second Semester 1435/1436 H Assignment 1 Model Answer

Princess Nora Bint Abdulrahman University Faculty of Computer and Information Sciences Department of Networks and Telecommunications

Question 1: complete the following table: (4 Points)

Connector name Used for Image

VGA (Video Graphics Array) [blue]

To connect the monitor with the video connector on the system unit

DVI (Digital Video Interface) [white] (DVI-D, DVI-A ,or DVI-I , mini-DVI)

       

NET201- Principles of Information & Technology Systems Second Semester 1435/1436 H Assignment 1 Model Answer

Princess Nora Bint Abdulrahman University Faculty of Computer and Information Sciences Department of Networks and Telecommunications

 

Question 2: Solve the following: (3 points)

a) Suppose that a CPU has an Address bus with 30 wires, what is the maximum amount of RAM this CPU can handle?

The maximum amount of RAM =

The memory address space = 230

230 = 1073741824 which is 1 GB

b) If a CPU has an address bus with 44 wires, what is the maximum amount of RAM this CPU can handle?

The maximum amount of RAM =

The memory address space = 244

RCA (Radio Corporation of America) [White, red and yellow]

To carry audio and video signals

HDMI (High Definition Multimedia Interface)

The newest video connector primarily designed for home

theater

       

NET201- Principles of Information & Technology Systems Second Semester 1435/1436 H Assignment 1 Model Answer

Princess Nora Bint Abdulrahman University Faculty of Computer and Information Sciences Department of Networks and Telecommunications

244 = 17592186044416 Bytes which is 16 TB

Or

The memory address space = 𝟐𝟒.𝟐𝟒𝟎

The maximum amount of RAM = 16 TB

c) How many Address bus wires needed to handle a 4 GB RAM ?

4 GB = 4294967296 Bytes

2 ? = 4294967296 Bytes

Log2 (4294967296) = 32 wire

Or 𝟐𝟐.𝟐𝟑𝟎 = 𝟐𝟑𝟐 à 32 wire

Question 3: Suppose that: There are 4 instructions: I1, I2, I3 and I4. (3 Points)

I2 takes 2 clock cycles for execution

I3 takes 3 clock cycles for decoding.

a. Draw the figure for 4-stage pipeline.

b. How many cycles needed for the 4 instructions to be completed? 9  Cycles  

c. Determine the latency for each instruction. (Hint: the instruction latency is the time to complete a single instruction from start to finish)

Clock cycle

1 2 3 4 5 6 7 8 9

I1 F1 D1 E1 W1 I2 F2 D2 E2 W2 I3 F3 D3 E3 W3 I4 F4 D4 E4 W4

       

NET201- Principles of Information & Technology Systems Second Semester 1435/1436 H Assignment 1 Model Answer

Princess Nora Bint Abdulrahman University Faculty of Computer and Information Sciences Department of Networks and Telecommunications

I1  fetched  at  time  t1  and  completed  its  execution  at  t4  à  4  clock  cycles  

I2  fetched  at  time  t2  and  completed  its  execution  at  t6  à  5  clock  cycles  

I3  fetched  at  time  t3  and  completed  its  execution  at  t8  à  6  clock  cycles  

I4  fetched  at  time  t4  and  completed  its  execution  at  t9  à  6  clock  cycles  

Notice:  The  instruction  4  latency  is  4  cycles,  but  it  took  6  cycles  due  to  pipeline  stall