Considerations and Benefits of Plasma Etch Based Wafer Dicing

Richard Barnett, Dr Oliver Ansell, Dr Dave Thomas SPTS Technologies Limited

Ringland Way, Newport. NP18 2TA. UK. richard.barnett@spts.com, +44(0)1633 414000

Abstract

Wafer dicing has been traditionally carried out using mechanical methods, including diamond saw and laser techniques. However, these techniques are imperfect, in that there is a need to manage the damage caused by them through compromises in pattern density and throughput. However, for power devices, chip cards and LEDs, the trends are towards thinner wafers and smaller die sizes, and these compromises further undermine the conventional dicing methods and render them less cost effective.

For other devices, including bio-compatible MEMS, conventional dicing is unable to provide the level of cleanliness required.

This paper will describe how the use of silicon plasma etching can produce a step change in dicing capability, even for the thin wafer scenario described above, that will provide increased die densities, increased throughputs and improved device reliability.

Limitations of Current Dicing Methods Dicing saws and lasers have been the default choice for

wafer singulation methods for decades. Their accepted use has been so engrained in the semiconductor industry’s consciousness that even the negative aspects of their adoption have been managed through various compromises.

There are the known risks of chipping or cracking from the saw approach, and sputtering/ablation damage from the laser. This damage cannot be wholly prevented, and so, there is an exclusion zone, which isolates the active die from these events. Further space is used to provide a sufficiently wide dicing lane for the cutting medium (e.g. saw blade or laser spot) to travel across the wafer. The lanes themselves can be in the region of 80μm to >100μm wide.

Another method of accommodating the inherent risk of damage from these cutting techniques is to slow the saw blade or laser process. When narrower lanes are used, reduced speed of dicing can mitigate against chipping or sputtering. But, this will inevitably reduce the throughput.

Some laser approaches, and the majority of saw dicing use water jets to guide or cool the cutting media. This is not compatible with the incoming range of biomedical MEMS devices being developed today.

An extension of laser dicing is the Stealth Dicing (SD) approach which creates a series of voids within the bulk of the wafer and completes singulation by “tearing” along the perforations.

Typically, wafers are thinned prior to dicing, down to approximately 200μm. However, there is a trend within the power device and chip card application spaces to go thinner. Certainly for power devices, with the need for lower voltage operation, some are suggesting that wafers will be thinned to <50μm.

For conventional dicing methods this can be problematic, as the level of control needed to manage the damage will reduce the throughputs even further.

Plasma –based Dicing Dicing lanes are simply trenches to be cut, or etched,

through the wafer. There are many other parallels that can be drawn between the dimensions that are typically used for dicing lanes and those in the creation of MEMS devices. So, can the techniques used for etching MEMS trenches be used for dicing wafers?

Figure 1: Examples of MEMS trench etches

For deep silicon etching, the Bosch process [1] has been

synonymous with MEMS for almost twenty years and in that time process hardware has been developed to be able to take advantage of the switched process to create deep anisotropic features without any sidewall damage.

For dicing, the key requirements are that the lane is “cut” without causing any damage to the active regions of the device and should not generate any crack propagation or stress raising sites. It is well documented that the Bosch process, with the cyclical isotropic silicon etch steps in each “loop” only creates a sidewall scallop and this is not normally considered as a physical influence on the integrity of structures etched in this way.

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Figure 2: Sidewall scallops typical of the Bosch process

Plasma dicing has further significant advantages compared

to the mechanical methods. In terms of throughput, the plasma approach has the upper hand since all dicing lanes will be etched in parallel, unlike the mechanical methods that are limited to serial rastering of the cutting medium up and down each of the lanes, either individually or in some cases in groups of 3-5 if multiple spot lasers are used. More detailed throughput comparisons are made later on.

Die layout can also be affected, positively, by a switch to a plasma based approach. Since X-Y rastering would no longer be a limitation, the need to place die in rigid rows is eliminated. There are mechanical methods, where a 60º rotation can be handled, but this still requires uniform placement of die. Plasma dicing gives the designer opportunities to place die in different layouts to maximize the number of die, or perhaps to have dissimilar die on a single wafer. This flexibility even stretches to non-standard die shapes, such as hexagons or circles.

Die density can be increased dramatically when the dicing lane width is reduced. Si DRIE can easily etch trenches of 10μm width (and lower) to depths of >100μm. The chart below shows how the number of die per wafer increases as the dicing lane width decreases. Based on the example of 1.5mm2 die, on a 200mm wafer, the number of die increases by almost 27% when reducing the lane width from 200μm down to 10μm. When considering even smaller die, e.g. 1mm2, the gain is >40%.

Figure 3: Chart showing die density vs. dicing lane width

Another advantage for plasma dicing is in yield. Low end-

of-line (EoL) yield for dicing would not be tolerated and plasma dicing would not be expected to impact the high yields necessary at this stage. It should be noted, that for all the protection put in place to alleviate the impact of laser ablation, there can still be yield loss due to sputtered material, as much as 1.5% of the completed die being singulated.

At this point, it can be said that from the silicon etching consideration, plasma etch is a viable alternative to saw or laser for wafer dicing.

Substrates The major difference between conventional plasma

etching and dicing is the substrate. For dicing before grinding (DBG) [2], the substrate is standard. But, for conventional dicing (or dicing post grinding, DPG), the wafers are thinned and mounted on a tape tightly suspended from a metallic or plastic frame. These approaches are described in the images below.

Figure 4a: Dicing Before Grinding (DBG)

Figure 4b: Dicing Post Grinding (DPG)

Figure 5: 200mm wafer supported on a dicing frame

The frame is one element that needs accounting for since

the substrate size is no longer the diameter of the wafer, but the diameter of the frame. Typically the outer diameter of the

Scallop

Silicon

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frame is approx 1.5 times the diameter of the wafer. E.g. 200mm wafer uses ~300mm diameter frame.

Wafer Size (mm) Frame OD

(mm) 100 150 150 180-200 200 250-300 300 400

Table 1: Wafer size vs. frame size These frames are used by the subsequent pick-and-place

equipment and so a plasma dicing system should be capable of accommodating them without modifications, so that no retooling is required. Although, the etch module should be capable of handling the frame diameters, it should be also noted that smaller wafer diameters can be positioned onto larger frames for processing.

The substrate causes two further issues for the plasma dicing case; i) mechanical handling of the pre and post diced wafer and ii) management of the tape and frame within the process chamber.

Handling of the tape and framed substrate is perhaps the simplest activity that needs to be dealt with. By ignoring the make-up of the substrate and effectively substituting a fixed structure, normal handling practices can be used. The key here is the need to handle via the frame rather than the wafer.

The alternative would likely fail as any contact points beneath the wafer region would be rendered almost useless after singulation, as there would be no rigidity to manage the weight of the overall substrate. The same argument is made for the substrate lifts inside the process module, and so contact areas around the frame diameter are used instead.

Now, assuming the framed substrate can be handled into the process module, it should be considered whether the framed substrate is compatible with the plasma environment within the Si etch process module. In order to determine this, a series of trials were run, by processing framed wafers with a typical Bosch Si etch recipe.

The most critical items being investigated at this stage were; i) does the tape survive the plasma chemistry, heat, etc? ii) can clamping of the substrate be maintained until singulation? iii) Can the singulated die be removed from the tape?

In all cases, the results were positive. The chart shows the backside He cooling flow remaining controlled until the singulation point, and the image shows, not only, that the tape survived, but the Si die could also be lifted clearly from the tape. This showed that the adhesive had not cured or cross-linked in any way during processing.

Figure 6: He backside cooling flow during plasma dicing run

Figure 7: Si lifting off tape, post-plasma dice

Plasma Etching System With the boundaries set by the substrate diameter and with

Si as the predominant material, SPTS selected its 300mm Omega fxP etch system and the 300mm Rapier process module for plasma dicing. [3] Being 300mm compatible, this system is able to accept the frames for wafers up to 200mm.

Figure 8: SPTS Rapier process module

Aside from the compatibility of the 300mm Rapier with

the frame dimensions, there are other factors which led to the selection of this module type for plasma dicing.

In the case of DBG, where the singulation actually happens during a subsequent grinding step, etch depth

Singulation

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uniformity is crucial to prevent failed singulation or dramatic over-grinding. For DPG, where the etch can stop directly on the tape, low etch depth non-uniformity is important in reducing the need for longer over-etch times, potentially risking damage to the tape and loss of die.

The Rapier module has a patented dual-source arrangement, with two independent RF sources, each with its own gas feed. The primary source & gas feed is centrally located and the secondary source & gas feed is around the edge of the loaded substrate. This arrangement gives a very uniform plasma density within the chamber, contributing to the control and delivery of a low etch non-uniformity. [4]

Figure 9: Rapier module plasma density The combination of these two plasma sources in this

arrangement also provides a highly efficient dissociation of the process gases, particularly in generating the fluorine atoms necessary for higher etch rates. In other applications, the Rapier module is able to achieve >35μm/min etch rates.

Figure 10: Chart showing Rapier cavity etch rate trend Coupled to the process capability, the Rapier can also be

fitted with the ClaritasTM enhanced OES endpoint detection system. [5] Claritas is able to detect endpoints for processes where pattern densities are <0.1% and also when process pressures are >100mT. Standard CCD array OES equipment cannot detect signal changes in these cases. The Claritas endpoint system was used in the earlier trials and detected strong endpoint signals, as can be seen in the images below.

Figure 11: Claritas endpoint signals for plasma dicing (main etch & over etch)

With the need to run high etch rates for maximized throughput and to minimize overetch to protect the tape, the combination of Rapier and Claritas is particularly suited for plasma dicing.

Materials In all of the tests described above, the frames and tapes

used were all standard, off-the-shelf parts. Both plastic and metal frames have been used and neither exhibited any problems during the process or handling. The other common element to the trials is the restriction of the materials that can be exposed within the dicing lanes.

This is an integration challenge that has to be met by the design owners. It is clear that the plasma chemistries necessary to etch metals would be incompatible with the frame and tape materials. Therefore, metal layers should be cleared from the dicing lanes during the device process flow. Test structures, however, can remain in place as these will not bridge the lanes, but exist isolated within them.

It is assumed that this requires a minor modification of the earlier metal etch steps in the process flow, exposing the dicing lanes and clearing the metal at the same time as it is patterned for the active die.

Although plasma dicing is predicated on the basis that metals should be cleared from the lanes themselves, the use of backside metals and solder bumps are not necessarily detrimental to the overall plasma dicing approach.

Backside metallization, a key element for power devices, can assist the plasma dicing process by providing a more efficient electrostatic clamp. This allows a more aggressive Si

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etch process to be used as there will be improved cooling contact between the wafer and platen surface. In this scenario, etch rates can be pushed even higher without risk to the substrate. An example of this configuration is discussed later.

We have also found that having exposed solder bumps on the die is not detrimental to the overall process. Through careful management of the process window, wafers with this arrangement can be successfully diced using the Bosch process.

Figure 12: Plasma dicing in the presence of solder bumps

The final integration step that is required to take full

advantage of plasma dicing is the patterning of the wafers, providing a suitable mask for the dicing etch process.

Lithography on a thinned wafer is not a simple task, however there are techniques available that can be used to provide a dicing etch mask. In any case, either a photoresist or dielectric hard mask can be used.

Dicing etch trials have been successfully completed with both types of mask. An oxide hard mask open etch, can also be carried out, prior to the silicon etch on framed substrates. Oxide etches, relying on higher bias powers require some compromise to prevent damage to the frame and tape. However, there are hardware solutions that can allow oxide etch rate to be regained without affecting the overall plasma dicing result.

Plasma Dicing Results The following are some examples of plasma dicing

regimes that have been investigated.

Die Size Dicing Lane Etch Rate Throughput 1.5mm2 15μmx250μm >8μm/min 2.0wph 1.5mm2 15μmx100μm >10μm/min 4.6wph 1.0mm2 17μmx120μm >20μm/min 7.0wph 16mm2 80μmx280μm >20μm/min 3.6wph

Table 2: Plasma dicing Etch Rates & Throughputs For the range of etch rates and throughputs, shown above,

the plasma dicing approach is at least 2-3 times more

productive than the existing, conventional dicing PoR employed. And in each case the throughput gain from plasma dicing is further enhanced with the additional die per wafer gained from reducing the dicing lane width. E.g. For the 1.0mm2 die, 17μmx120μm dicing lane, the PoR has an 80μm dicing lane. The reduction in lane width provides 7-10% more die per wafer in the plasma dicing case.

Figure 13: 15μm x 100μm dicing lane

Figure 14: Die with 15μm x 250μm dicing lane

Figure 15: 17μm x 120μm dicing lane with backside metallization

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Figure 16: 80μm x 280μm dicing lane, showing solder bumps on die Conclusions

As device trends move to thinner silicon, smaller die or applications grow to include invasive biomedical MEMS devices the conventional approaches to wafer dicing begin to be more and more compromised in terms of capability and cost effectiveness. By applying semiconductor processes to this final fabrication step, there are many advantages to be gained in die density, pattern layout, throughput, yields, costs and application space.

SPTS has developed a plasma dicing system able to take advantage of the Si etch capabilities of the Bosch process that can act as a drop in replacement for the conventional dicing methods but operate within the controls and security of the semiconductor cleanroom, bringing the backend into the frontend.

Acknowledgments Many thanks to Dr Oliver Ansell, Tony Barrass, Brian

Kiernan, Matt Smith, Mark Ford and the SPTS Etch & Platform Engineering groups.

References 1. Laermer, F, Schlip A, “Method of anisotropically etching

silicon”. US Patent 5501893. 2. Klug, G, “ Advanced solutions for ultra-thin wafers and

packaging” Microelectronics and Packaging Conference, 2009. EMPC 2009, Rimini, Italy. June 2009, pp.1-4.

3. Barnett, R, et al, “A New Plasma Source for Next Generation MEMS Deep Si Etching”, 60th Electronic Components and Technology Conference, Las Vegas, NV, June 2010, pp.1056-1059.

4. Barnett, R, et al, “Yield and productivity improvements through use of advanced dual plasma source for TSV reveal & wafer dicing applications”, 13th Electronics Packaging Technology Conference, Singapore, December 2011, pp.585-589.

5. Ansell, O, et al “ClaritasTM – A Unique And Robust Endpoint Technology For Silicon Drie Processes With Open Area Down To 0.05%”, To Be Published at 27th IEEE Conference on Micro Electro Mechanical Systems (MEMS 2014), San Francisco CA, January 2014.

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