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Considerations for High Speed PCB Track Design in 10Gb/s Serial Data Transmission

White PaperSteve Bowers and Dr Herbert Lage Applications Engineering Avago Technologies Fiber Optic Products Division

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AbstractA fundamental evaluation of a variety ofapproaches for designing a high-speed (10 Gb/s)serial differential electrical channel is examined.The application of the electrical interface has beensimulated using HSpice software. It demonstratedhow the signal quality could be affected by the useof microstrip versus stripline traces and theirassociated advantages and disadvantages isdiscussed. Example XFI channels were assembledfrom the simulation results to demonstrateviability of the application.

IntroductionThis white paper describes the mainconsiderations in the design of a PCB for thetransmission of 10 Gb/s serial data. It has beenwritten to aid the PCB designer to devise thelayout for a host board for use with the Agilent 10Gb/s HFCT-711XPD XFP LC differential serialtransceiver and the electrical channel to theSerDes IC (XFI channel). Its focus is on thefrequency-dependent attributes of the variouscomponents within the electrical channel.Additionally, the parametric issues of a pluggableconnector are examined.

The XFI Electrical ChannelA block diagram of a typical electrical channel isshown in Figure 1. This is a simplified electricalchannel within an XFP application. The electricalcharacteristics of the data are assumed to be XFIcompliant, see the XFP MSA (www.xfpmsa.org)for further details on an XFI interface. Thenumbers in Table 1 relate to the position withinthe channel:

Table 1. XFI data channel details

Number Location

1 - 2 Channel from the IC pads to the IC I/O pins

2 - 3 10Gb/s data channel including vias

3 - 4 Channel through the pluggable connector

4 - 5 10Gb/s data channel including vias

5 - 6 Channel from the IC I/O pins to the IC pads

Figure 1. Block diagram of an electrical XFI channel

Within the XFP MSA is an option to utilize eyeopener ICs. This enables a reduction in theamount of jitter on the signal in both directions ofthe XFI channel. However, the interest here is inthe degradation of signal quality due to thechannel, ie. practical tests are necessary for anabsolute evaluation of the channel. Wheremeasured data is not yet available, the parametricvalues for components and parasitics within theXFI channel have been estimated.

There are many factors affecting the signalintegrity of high-speed data links: -

1. Track dimensions2. Dielectric material properties of the PCB3. The physical design of the pluggable

connector (effects of implementation)4. Discontinuities between the track and

component pads (reflections)5. Type and length of track used, microstrip /

strip line6. Physical configuration of vias7. Data pattern-dependency of the signal

quality – jitter8. Temperature dependency

Here, we will examine each one in turn andanalyze the associated effects on the transmitteddigital data stream.

Track Length/Width and PCB MaterialsTrack dimensions together with PCB materialproperties become more prohibitive withincreasing frequency.

The dielectric constant, er, of the PCB materialdictates the effective capacitance around thetransmission lines and is frequency dependent.Additionally, the velocity of an electromagneticwave that travels through a dielectric is reducedproportionally to the square root of the dielectricconstant er, ie. for a given EM wave, as erincreases, the velocity decreases. Furthermore, asthe frequency of the EM wave increases, theeffective er of many dielectrics used for themanufacture of PCBs decreases. The group

XFP

Internal ICI/Os

1 2 3 4 5

10 Gb/s datalines (tracks)

XFPpluggableconnector


Serdes ICI/Os

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Abstract

A fundamental evaluation of a variety of approaches for designing a high-speed (10 Gb/s) serial differential elec-trical channel is examined. The application of the electri-cal interface has been simulated using HSpice software. It demonstrated how the signal quality could be affected by the use of microstrip versus stripline traces and their as-sociated advantages and disadvantages is discussed. Ex-ample XFI channels were assembled from the simulation results to demonstrate viability of the application.

Introduction

This white paper describes the main considerations in the design of a PCB for the transmission of 10 Gb/s serial data. It has been written to aid the PCB designer to de-vise the layout for a host board for use with the Avago 10 Gb/s HFCT-711XPD XFP LC differential serial transceiver and the electrical channel to the SerDes IC (XFI channel). Its focus is on the frequency-dependent attributes of the various components within the electrical channel. Addi-tionally, the parametric issues of a pluggable connector are examined.

The XFI Electrical Channel

A block diagram of a typical electrical channel is shown in Figure 1. This is a simplified electrical channel within an XFP application. The electrical characteristics of the data are assumed to be XFI compliant, see the XFP MSA (www.xfpmsa.org) for further details on an XFI interface. The numbers in Table 1 relate to the position within the channel:

XFP

Internal ICI/Os

1 2 3 4 5


XFPpluggableconnector


Serdes ICI/Os

6

Figure 1. Block diagram of an electrical XFI channel

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Within the XFP MSA is an option to utilize eye opener ICs. This enables a reduction in the amount of jitter on the signal in both directions of the XFI channel. However, the interest here is in the degradation of signal quality due to the channel, ie. practical tests are necessary for an absolute evaluation of the channel. Where measured data is not yet available, the parametric values for components and para-sitics within the XFI channel have been estimated.

There are many factors affecting the signal integrity of high-speed data links: -

1. Track dimensions

2. Dielectric material properties of the PCB

3. The physical design of the pluggable connector (effects of implementation)

4. Discontinuities between the track and component pads (reflections)

5. Type and length of track used, microstrip / strip line

6. Physical configuration of vias

7. Data pattern-dependency of the signal quality – jitter

8. Temperature dependency

Here, we will examine each one in turn and analyze the as-sociated effects on the transmitted digital data stream.

Track Length/Width and PCB Materials

Track dimensions together with PCB material properties become more prohibitive with increasing frequency. The dielectric constant, er, of the PCB material dictates the effective capacitance around the transmission lines and is frequency dependent. Additionally, the velocity of an electromagnetic wave that travels through a dielectric is reduced proportionally to the square root of the dielectric constant er, ie. for a given EM wave, as er increases, the ve-locity decreases. Furthermore, as the frequency of the EM wave increases, the effective er of many dielectrics used for the manufacture of PCBs decreases. The group velocity of an electrical signal therefore depends on its frequency, an effect known as dispersion. However, this effect is usually small and will be ignored for the purposes of this study. The dielectric material of a PCB is generally composed of glass fiber and resin. The er is affected by the ratio of glass to resin used to make the laminate. The most com-mon dielectric material used in high-speed data transmis-sion is FR4. This material has a low er with a typical resin/glass ratio of around 55%. At 5 GHz, er is about 4.2 [Ritchey 1999].

The losses of transmission lines are determined by the skin effect of the conductor and the absorption of electric en-ergy by the dielectric. The skin effect confines the current flow to the surface of the conducting material, typically copper. Increasing the surface area, ie. by increasing the width of the transmission line, can mitigate the skin effect. The loss of electric energy in the dielectric is described by its loss tangent tan(d). In most digital applications up to about 1 GHz the dielectric loss is a small fraction of the loss due to the skin effect. However, since dielectric losses increase faster with frequency than skin-effect losses, they can become the dominating loss mechanism for very high data rate systems.

When transmitting at frequencies of around 5 GHz or high-er, the combination of trace dimension and PCB material is paramount in finding the right trade-off between low channel-loss, ie. low attenuation to maintain signal levels well above digital decision thresholds, and minimizing jit-ter or standing wave effects through the right amount of attenuation of unwanted reflections. For a shorter trace length at 5 GHz, the use of a lossy combination in order to introduce a small amount of additional attenuation may actually help to improve the overall XFI channel return loss.

Pluggable Connectors

When using a pluggable connector, it is essential that the physical properties of the connector do not limit its use in the intended data channel. The electrical parasitics of the connector, eg. inductance, have to be included during the evaluation. The parasitic values are usually available from the manufacturer of the connector and enable the use of electrical simulation for Signal Integrity evaluation of the data channel.

PCB Layout Design and Microstrip versus Stripline Geometry

A Time Domain Reflectometer can be used to evaluate discontinuities in the data track. It is critical to avoid re-flections when transmitting data to ensure that only a clean signal with well defined edges and voltage levels is received. In the case of a short track length in an XFI chan-nel transmitting at around 5 GHz, it maybe an advantage to use a PCB material that has a higher loss tangent tan (d) to help absorb reflections and hence improve signal quality1. Furthermore, the type of track used, stripline or microstrip, has both advantages and disadvantages for high-speed data transmission. See Table 2.

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velocity of an electrical signal therefore dependson its frequency, an effect known as dispersion.However, this effect is usually small and will beignored for the purposes of this study.

The dielectric material of a PCB is generallycomposed of glass fiber and resin. The er isaffected by the ratio of glass to resin used to makethe laminate. The most common dielectricmaterial used in high-speed data transmission isFR4. This material has a low er with a typicalresin/glass ratio of around 55%. At 5 GHz er isabout 4.2 [Ritchey 1999].

The losses of transmission lines are determined bythe skin effect of the conductor and the absorptionof electric energy by the dielectric. The skin effectconfines the current flow to the surface of theconducting material, typically copper. Increasingthe surface area, ie. by increasing the width of thetransmission line, can mitigate the skin effect. Theloss of electric energy in the dielectric is describedby its loss tangent tan(d). In most digitalapplications up to about 1 Ghz the dielectric lossis a small fraction of the loss due to the skin effect.However, since dielectric losses increase fasterwith frequency than skin-effect losses, they canbecome the dominating loss mechanism for veryhigh data rate systems.

When transmitting at frequencies of around 5 Ghzor higher, the combination of trace dimension andPCB material is paramount in finding the righttrade-off between low channel-loss, ie. lowattenuation to maintain signal levels well abovedigital decision thresholds, and minimizing jitteror standing wave effects through the right amountof attenuation of unwanted reflections. For ashorter trace length at 5 GHz, the use of a lossycombination in order to introduce a small amountof additional attenuation may actually help toimprove the overall XFI channel return loss.

Table 2. Microstrip versus Stripline

Note:1. Reference: XFP Multisource Agreement Rev 1.0

Advantages Disadvantages

Stripline Buried track avoids surface EMI emission and improves EMIimmunity.

Vias have to be used:1) Can lead to reduced signal quality by causing reflections.2) Can limit the track length due to narrow track width and increased dielectric losses.

Microstrip Longer track lengths permitted; does not require vias so fewerimpedance discontinuities that can impact Signal Integrity - morepredictable.

Can lead to an EMI emission and immunity penalty for thechannel both for the transmitting device and surroundingcomponents - open-air emissions.

Pluggable ConnectorsWhen using a pluggable connector, it is essentialthat the physical properties of the connector donot limit its use in the intended data channel. Theelectrical parasitics of the connector, eg.inductance, have to be included during theevaluation. The parasitic values are usuallyavailable from the manufacturer of the connectorand enable the use of electrical simulation forSignal Integrity evaluation of the data channel.

PCB Layout Design and Microstrip versus StriplineGeometryA Time Domain Reflectometer can be used toevaluate discontinuities in the data track. It iscritical to avoid reflections when transmittingdata to ensure that only a clean signal with welldefined edges and voltage levels is received. In thecase of a short track length in an XFI channeltransmitting at around 5 GHz, it maybe anadvantage to use a PCB material that has a higherloss tangent tan (d) to help absorb reflections andhence improve signal quality1. Furthermore, thetype of track used, stripline or microstrip, hasboth advantages and disadvantages for high-speeddata transmission. See Table 2.

The Use of Vias in High-Speed Data TransmissionThe introduction of vias in to a high-speedelectrical design can lead to multiple electricalreflections caused by impedance discontinuities inthe data line. Additionally, the manufacturingprocess can be troublesome at frequencies >1 GHzto achieve the required signal quality. Otherconsiderations are: simplifying electrical designsand optimizing signal integrity.

Data Pattern-Dependency of the Signal Quality – JitterThe frequency content of the test pattern and the‘typical’ live traffic will determine how the signal is

The Use of Vias in High-Speed Data Transmission

The introduction of vias in to a high-speed electrical de-sign can lead to multiple electrical reflections caused by impedance discontinuities in the data line. Additionally, the manufacturing process can be troublesome at fre-quencies >1 GHz to achieve the required signal quality. Other considerations are: simplifying electrical designs and optimizing signal integrity.

Data Pattern-Dependency of the Signal Quality – Jitter

The frequency content of the test pattern and the ‘typi-cal’ live traffic will determine how the signal is affected by the format of the data. The Synchronous Optical Network, SONET, data format typically has more content at lower frequencies than an Ethernet pattern, normalized to re-move the bit rate difference. This is due to long strings of Ones and Zeroes that are allowed in the SONET format. Thus the range of frequencies that the PCB has to handle is relatively different for each of the network protocols. This can have a significant affect on the signal quality due to resonance effects and the overall frequency dependence of the data channel. It can therefore be important to check that a data channel not only works at the highest frequen-cies, but also does not cut off any low frequency content that could be present in SONET protocols for example.

Note: The simulations within this document have utilized the PRBS 27-1 data stream.

N.B. It is probable that a pattern with a lower frequency content, e.g. PRBS 223-1 would display worse results, however using this pattern would result in a much longer simulation time due to the required resolution of the waveforms, thus longer patterns were not used in the simulations.

Temperature dependency

It is clear that materials used in the manufacture of PCBs can have differing coefficients of thermal expansion. How-ever, the temperature range of a typical data application does not usually exceed the –40 to +85 °C limits. Over this temperature range the relative dimensional change of the PCB materials is less than 1%, and in the case of differential tracks, both tracks should be affected by the same amount. Such a small change in length of the traces should be insignificant in terms of the Signal Integrity of the XFI data channel. Similarly, for track width, the propor-tional change is of the same amount as the length change with temperature. Again, this is very minor with regards to the practical limits that apply to track width control in a typical manufacturing environment.

Vias may experience stress caused by the expanding dielectric, due to differences in the thermal expansion coefficients of copper and FR4. This can threaten the mechanical integrity of the PCB and could lead to cracks in the vias for very thick PCBs, which may in turn manifest itself as intermittent failure [Ritchey 1999]. The most criti-cal process step in that respect is soldering operations, which raise the temperature of the PCB to around +185°C. However, unless cracks occur during the manufacturing operations of the PCB temperature changes are not ex-pected to affect the high-frequency properties of the XFI data channel. Hence temperature dependence will not be further discussed.

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XFI Channel Simulation

The XFI channel has been simulated to show how the various properties, discussed above, can influence the sig-nal shape and quality. In this section, the XFI channel is separated into component models. The simulation tools used were Agilent Advance Design System v.2002 and Synopsis (formerly Avanti) HSpice v.2002.2.1. The sche-matic in Figure 2 demonstrates how the receiver section of a XFP module was modeled to enable the simulation of an XFI compliant channel. The significance of the vari-ous elements of this XFP receiver model will be discussed in some detail before we look at simulation results for a whole XFI data channel. Additional detail of the output buffer model of the XFP receiver is shown in Figure 3. As can be seen from the schematic a Current-Mode Logic (CML) buffer model has been devised in order to meet the I/O buffer specifications of the XFP MSA. The following table explains the various elements of the output buffer model shown in Figure 3:

Figure 2. XFI channel model components

Module - lines(L mod ; 50 Ω )

DC - blocks

XFP - TycoCONNECTOR

XFICompliant

PackageModel

Output BufferModel

XFP50 Ω Resistor

1. Differential digital signal generator

2. 6th order Bessel filter to generate realistic analog edges and eye shapes1

3. Fine-tuning network to slow the final settling of the buffer, if required. The RC time constant used here is 4 ps.

4. Fast open-collector transistors with 50 ohm internal pull-up resistors – intrinsic switching speed approxi-mately 10-15 ps. The current source in the “tail” deter-mines the signal amplitude.

5. Capacitance of the die bond-pads and other parasitic capacitances. The capacitance used in this model is 0.1 pF.

Note:1. Reference: “The Art of Electronics” (Second Edition) by Paul Horowitz

and Winfield Hill, Cambridge University Press, Chapter 5 “Active Filters and Oscillators”.

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XFP Model Components

From the die pads the signal needs to pass through the IC package before it is launched onto the transmission lines inside the XFP module. Figure 4 shows the Scattering (S) parameters S11 and S12 of the preliminary quantizer IC package model that was used to account for package- induced parasitics between the Silicon die and the quan-tizer SMT pin1. At this point it shall suffice to say that the package model is compliant with performance require-ments of an XFI data channel. The preliminary model used here is based on an RLC-”ladder” approach that is explained in more detail later in this white paper when we will look at the influence of the receiver IC package on the Signal Integrity of a XFI channel link.

A surface mounted dc-block allows the decoupling of the XFP module supply voltage from the voltages used by the Serializer/Deserializer (SerDes) IC on the host board. Figure 5 shows a schematic of the equivalent circuit for the parasitics of the 47 nF dc blocking capacitors that was used in the simulations.Note:1. SMT: Surface Mount Technology

A Spice model of the pluggable connector, supplied by Tyco Electronics, was also inserted into the XFI channel model. The pins corresponding to the RD+/- signals were terminated with two 50 W resistors as depicted in Figure 2.

All other connector pins were grounded. A simulation was run where the XFP receiver model was stimulated with a 10 Gb/s PRBS (27-1) bit pattern. The differential waveforms were probed between pins RD+ and RD- of the XFP mod-ule connector (host side), the resultant eye-plot is dis-played in Figure 6.

Due to the complexity of the XFP connector model, sim-ulation times tend to be long. A compact version of the model was therefore constructed in order to save process-ing time. The compact model is an equivalent single-line model that ignores the coupling between the pins and consequently cannot be used for connector-induced crosstalk analysis, however, it accurately describes the im-pedance discontinuity caused by the connector. The simu-lated Time-Domain Reflectometry (TDR) responses of the two connector models are shown in Figure 7. The agree-ment between the 2 models is satisfactory. This is also confirmed by XFI channel simulations where the resultant eye-plot together with the XFI compliant eye mask1 is shown in Figure 8. It can be seen that the eye-plot with the compact model is very comparable with the plot us-ing the full connector model. All subsequent simulations used the compact connector model unless otherwise stat-ed. Furthermore, the eye diagram in Figure 8 will serve as a reference for quantitative evaluations of eye closure as a function of XFI link design parameters.

Figure 3. Schematic of the quantizer CML output buffer created for XFI simulation

CML_Out -

CML_Out +

+

+

+

VccCML Buffer

3

4 5

21

6th orderBessel Filter

dc biasing

RC Eye -shape fine

adjustment

Pad Parasiticcapacitance

RC timeconstant

is 4ps

6

6

Figure 4. S11 and S21 plot of the quantizer IC package model. The model is based on an RLC “ladder” approach, which is explained in a laterchapter of this white paper.

Figure 5. Schematic of the parasitics for the dc blocking capacitors

CC21C=47 nF

CC23C=47 nF

CC26C=108 fF

CC27C=108 fF

CC25C=108 fF

CC20C=108 fF

LL15

R=L=0.6 nH

LL14

R=L=0.6 nH

CC22C=11 fFC

C24C=11 fF

PortP4Num=4

PortP3Num=3

PortP2Num=2

PortP1Num=1

The frequency content of the simulation pattern is shown in Figure 9. This is the Fourier transform of the PRBS (27-1) pattern emitted by the XFP receiver. It can be seen from this plot that frequencies above 20 GHz contribute little to the output signal produced by the receiver model. As mentioned earlier, for some data formats it can be as im-portant to check the low frequency end of the spectrum, as it is to verify performance at the high frequency end. For the SONET data format, strings of consecutive ones and zeroes as long as 72 bits are allowed. The lowest fre-quency which then needs to pass the channel can be esti-mated according to f_low = BitRate/(2*N), where N is the maximum number of identical bits. Thus, for an OC-192 SONET data pattern, this equates to approximately 69

MHz. The low frequency cutoff of the XFI channel needs to be well below the 69 MHz in order for the link to be usable for SONET data formats. However, even for small values of the cutoff frequency, there is still an influence on Data-Dependent Jitter (DDJ) and eye-closure. The ef-fect is most pronounced for long sequences of ones and zeroes. The R&D department of Avago has estimated the DDJ and the reduction of the inner eye height for the max-imum allowed sequence of 72 identical bits. The results of these worst case calculations are depicted in Figure 10 as a function of cutoff frequency for a 10 Gb/s SONET data pattern.Note:1. Reference: XFP Multisource Agreement, www.XFPMSA.org.

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Figure 6. XFI channel simulation using the full connector model Figure 8. Simulation plot using compact connector modelincorporating the XFI compliance eye mask

Figure 7. TDR simulations of the full Spice connector model and thecompact model.

A Spice model of the pluggable connector,supplied by Tyco Electronics, was also insertedinto the XFI channel model. The pinscorresponding to the RD+/- signals wereterminated with two 50 W resistors as depicted inFigure 2. All other connector pins were grounded.

A simulation was run where the XFP receivermodel was stimulated with a 10 Gb/s PRBS (27-1)bit pattern. The differential waveforms wereprobed between pins RD+ and RD- of the XFPmodule connector (host side), the resultant eye-plot is displayed in Figure 6.

Due to the complexity of the XFP connector modelsimulation times tend to be long.

A compact version of the model was thereforeconstructed in order to save processing time. Thecompact model is an equivalent single-line modelthat ignores the coupling between the pins andconsequently cannot be used for connector-induced crosstalk analysis, however, it accuratelydescribes the impedance discontinuity caused bythe connector. The simulated Time-DomainReflectometry (TDR) responses of the twoconnector models are shown in Figure 7. Theagreement between the 2 models is satisfactory.This is also confirmed by XFI channel simulationswhere the resultant eye-plot together with the XFIcompliant eye mask1 is shown in Figure 8. It canbe seen that the eye-plot with the compact modelis very comparable with the plot using the fullconnector model. All subsequent simulations usedthe compact connector model unless otherwisestated. Furthermore, the eye diagram in Figure 8will serve as a reference for quantitativeevaluations of eye closure as a function of XFI linkdesign parameters.

The frequency content of the simulation pattern isshown in fFigure 9. This is the Fourier transformof the PRBS (27-1) pattern emitted by the XFPreceiver. It can be seen from this plot thatfrequencies above 20 GHz contribute little to theoutput signal produced by the receiver model.

As mentioned earlier, for some data formats it canbe as important to check the low frequency end ofthe spectrum, as it is to verify performance at the

Note:1 Reference: XFP Multisource Agreement, www.XFPMSA.org.

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Figure 9. Frequency content of the 27-1 PRBS bit stream emitted by theXFP receiver

high frequency end. For the SONET data formatstrings of consecutive ones and zeroes as long as72 bits are allowed. The lowest frequency whichthen needs to pass the channel can be estimatedaccording to f_low = BitRate/(2*N), where N is themaximum number of identical bits. Thus, for anOC-192 SONET data pattern, this equates toapproximately 69 MHz. The low frequency cutoffof the XFI channel needs to be well below the 69MHz in order for the link to be usable for SONETdata formats. However, even for small values ofthe cutoff frequency, there is still an influence onData-Dependent Jitter (DDJ) and eye-closure. Theeffect is most pronounced for long sequences ofones and zeroes. The R&D department of Agilenthas estimated the DDJ and the reduction of theinner eye height for the maximum allowedsequence of 72 identical bits. The results of theseworst case calculations are depicted in Figure 10as a function of cutoff frequency for a 10 Gb/sSONET data pattern.

Figure 10. Effect of the low-frequency cut-off on DDJ and inner eyeheight.

Eye MeasurementsIn the following we will focus on the high-frequency aspects of XFI channel design. Afterhaving developed a suitable base model,simulations were carried out to map out thedesign space. In order to quantify the impact onthe electrical eye from varying several of theparameters described earlier, measurements weretaken from eye-plots of transient simulation runs.These are compared to the reference eye-plot inFigure 8. The eye-diagram in Figure 11 shows howthe measurements were taken.

Figure 11. Simulated electrical eye plot showing measurementparameters

Simulations with Microstrip TracksIn a first analysis we will look at the effect of trackdimensions and dielectric loss on the propagationof a 10 Gbit/s signal on microstrip transmissionlines. The configuration adopted for thesimulations is shown in Figure 12. The electricalsignal is emitted by the XFP optical receiver(which acts as an electrical transmitter), andtravels through the XFP connector and along theinterconnect structure on the host PCB to theresistor that provides 100 W differentialtermination. The signal is probed across thetermination resistor as indicated by the redarrows in Figure 12.

This simulation setup is a somewhat “idealized”arrangement which neglects the frequencydependant characteristics of the IC package of areal-world SerDes or Eye Opener IC, and thefinite, albeit small input buffer capacitance of thedie. However, this approach will allow us to analyze

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Eye Measurements

In the following we will focus on the highfrequency as-pects of XFI channel design. After having developed a suitable base model, simulations were carried out to map out the design space. In order to quantify the impact on the electrical eye from varying several of the parameters described earlier, measurements were taken from eye-plots of transient simulation runs. These are compared to the reference eye-plot in Figure 8. The eye-diagram in Fig-ure 11 shows how the measurements were taken.

This simulation setup is a somewhat “idealized” arrange-ment which neglects the frequency dependant charac-teristics of the IC package of a real-world SerDes or Eye Opener IC, and the finite, albeit small, input buffer capaci-tance of the die. However, this approach will allow us to analyze the influence of the trace parameters on the XFI data channel in an unambigiuous manner. In a later chap-ter we will replace the termination resistor with a more realistic electrical receiver model.

For the board-level interconnect, loosely coupled mi-crostrip traces were used with a differential impedance of 100 W. Three combinations of trackwidth and dielectric were simulated for 4, 8, and 12 inches track length each. The details of the configurations together with the results of the eye diagram analysis are listed in Table 3. Please note that for both epoxy laminates the same dielectric constant was employed to enable the use of identical trace geom-etries. The dielectric constant reduces with frequency and differs somewhat for the two laminates, the figure used here is at the higher end of the range of reported values.

It can be seen from the plots below in Figure 13 that the expected eye closure and increased data dependent, i.e. deterministic jitter is evident due to the increase in track length. Both ‘0’ and ‘1’ transitions split into multiple traces and the central area is severely reduced. The central eye mask shown in Figure 13 is based on the “XFI ASIC/SerDes Receiver Input compliance mask”1 and is for relative com-parison only. Please note that 12 inches track length is the maximum recommended in the XFP multi source agree-ment.

The results listed in Table 3 are plotted in Figure 14 to il-lustrate the increased deterministic jitter and the reduced eye opening as a function of the chosen microstrip geom-etry and dielectric material. It is evident that simulation 1 produces the largest losses, which are attributed to the skin- resistance of the relatively narrow, only 5 mil wide track. Widening the tracks to 12 mil considerably reduces the skin effect induced losses as can be seen in the data for Simulation 2. For both of these simulations, a lossier (and therefore cheaper) laminate with a loss tangent of 0.025 was used. To increase eye margin further one can

Traces on PCB

TerminationXFP - Tyco

CONNECTOR

Zdiff ~100 Ω

XFP

Receiver

Model Resistor 100 Ω

Simulations with Microstrip Tracks

In a first analysis we will look at the effect of track dimen-sions and dielectric loss on the propagation of a 10 Gbit/s signal on microstrip transmission lines. The configuration adopted for the simulations is shown in Figure 12. The elec-trical signal is emitted by the XFP optical receiver (which acts as an electrical transmitter), and travels through the XFP connector and along the interconnect structure on the host PCB to the resistor that provides 100 W differen-tial termination. The signal is probed across the termina-tion resistor as indicated by the red arrows in Figure 12.

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Figure 12. Building blocks for XFI data link simulation. The red arrows indicate where the signal is probed.

Figure 11. Simulated electrical eye plot showing measurement parameters

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Figure 12. Building blocks for XFI data link simulation. The red arrows indicate where the signal is probed.

the influence of the trace parameters on the XFIdata channel in an unambigiuous manner. In alater chapter we will replace the terminationresistor with a more realistic electrical receivermodel.

For the board-level interconnect, loosely coupledmicrostrip traces were used with a differentialimpedance of 100 W. Three combinations of track-width and dielectric were simulated for 4, 8, and12 in track length each. The details of theconfigurations together with the results of the eyediagram analysis are listed in Table 3. Please notethat for both epoxy laminates the same dielectricconstant was employed to enable the use ofidentical trace geometries. The dielectric constantreduces with frequency and differs somewhat forthe two laminates, the figure used here is at thehigher end of the range of reported values.

It can be seen from the plots below in Figure 13that the expected eye closure and increased datadependent, i.e. deterministic jitter is evident dueto the increase in track length. Both ‘0’ and ‘1’transitions split into multiple traces and thecentral area is severely reduced. The central eyemask shown in Figure 13 is based on the “XFIASIC/SerDes Receiver Input compliance mask”1

and is for relative comparison only. Please notethat 12 in track length is the maximumrecommended in the XFP multi source agreement.

The results listed in Table 3 are plotted in Figure14 to illustrate the increased deterministic jitterand the reduced eye opening as a function of thechosen microstrip geometry and dielectricmaterial. It is evident that simulation 1 producesthe largest losses, which are attributed to the skin-

Note:1 Reference: XFP Multi Source Agreement.

Figure 13. Comparison of eye plots from 4in (left) to 12in (right) track length for simulation 2.

XFP - Tyco

CONNECTOR

Traces on PCB

XFPReceiver

Model

TerminationXFP - Tyco

CONNECTOR

Traces on PCB

Zdiff ~100

XFP

Receiver

Model

TerminationTermination

Resistor 100

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SimulationConfiguration

Inner Eye Height[mV]

Deterministic Jitter[ps]

Inner Eye Width[ps]

Inner Area[ps*mV]

XFP Reference Eye 508.0 1.9 98.1 24917.4

Simulation 1 : N4000-6 (er=4.1, loss tangent 0.025, 2.8 mil thick), 5 mil wide microstrip, 100 mil track spacing, 0.5 oz copper

4 in track length 428.1 4.1 95.9 20527.4

8 in track length 337.3 7.8 92.3 15558.0

12 in track length 262.1 12.8 87.2 11427.6

Simulation 2 : N4000-6 (er=4.1, loss tangent 0.025, 6.6 mil thick), 12 mil wide microstrip, 100 mil track spacing, 1 oz copper

4 in track length 464.0 3.2 96.8 22457.6

8 in track length 401.6 5.1 94.9 19055.9

12 in track length 347.3 7.4 92.7 16088.7


4 in track length 483.4 2.9 97.1 23469.1

8 in track length 426.6 4.3 95.7 20412.8

12 in track length 379.7 6.0 94.0 17845.9

Table 3. Simulation parameters and results for microstrip interconnects.

resistance of the relatively narrow, only 5 mil widetrack. Widening the tracks to 12 mil considerablyreduces the skin effect induced losses as can beseen in the data for Simulation 2. For both of thesesimulations, a lossier (and therefore cheaper)laminate with a loss tangent of 0.025 was used. Toincrease eye margin further one can use lower losslaminates as per Simulation 3. However, theimprovement is small except for very longinterconnect lengths exceeding about 6 in length.For traces shorter than 6 in standard, i.e. higherloss laminates should be sufficient to meet the XFIchannel requirements.

Simulations with Stripline TracksStripline trace geometries are sandwichedbetween two reference planes, which cansimultaneously act as Power and Ground planes.The various conductive layers are typicallyseparated by about 6 mil thick dielectric layers.This implies that the stripline width needs to befairly narrow, of the order of 5 mils, in order tomeet 100 W differential impedance design targets.It is therefore assumed that skin-effect losses willplay a significant role, even though the wholesurface of the striplines conducts current, incontrast to microstrip traces where most of the

Figure 14. Selected eye diagram parameters for microstrip interconnect XFI link configurations

use lower loss laminates as per Simulation 3. However, the improvement is small except for very long interconnect lengths exceeding about 6 inches length. For traces short-er than 6 inches standard, i.e. higher loss laminates should be sufficient to meet the XFI channel requirements.

10

10




Inner Eye Width[ps]

Inner Area[ps*mV]

XFP Reference Eye 508.0 1.9 98.1 24917.4

Simulation 1 : N4000-6 (er=4.1, loss tangent 0.025, 2.8 mil thick), 5 mil wide microstrip, 100 mil track spacing, 0.5 oz copper

4 in track length 428.1 4.1 95.9 20527.4

8 in track length 337.3 7.8 92.3 15558.0

12 in track length 262.1 12.8 87.2 11427.6


4 in track length 464.0 3.2 96.8 22457.6

8 in track length 401.6 5.1 94.9 19055.9

12 in track length 347.3 7.4 92.7 16088.7


4 in track length 483.4 2.9 97.1 23469.1

8 in track length 426.6 4.3 95.7 20412.8

12 in track length 379.7 6.0 94.0 17845.9

Table 3. Simulation parameters and results for microstrip interconnects.

resistance of the relatively narrow, only 5 mil widetrack. Widening the tracks to 12 mil considerablyreduces the skin effect induced losses as can beseen in the data for Simulation 2. For both of thesesimulations, a lossier (and therefore cheaper)laminate with a loss tangent of 0.025 was used. Toincrease eye margin further one can use lower losslaminates as per Simulation 3. However, theimprovement is small except for very longinterconnect lengths exceeding about 6 in length.For traces shorter than 6 in standard, i.e. higherloss laminates should be sufficient to meet the XFIchannel requirements.

Simulations with Stripline TracksStripline trace geometries are sandwichedbetween two reference planes, which cansimultaneously act as Power and Ground planes.The various conductive layers are typicallyseparated by about 6 mil thick dielectric layers.This implies that the stripline width needs to befairly narrow, of the order of 5 mils, in order tomeet 100 W differential impedance design targets.It is therefore assumed that skin-effect losses willplay a significant role, even though the wholesurface of the striplines conducts current, incontrast to microstrip traces where most of the

Figure 14. Selected eye diagram parameters for microstrip interconnect XFI link configurations

Simulations with Stripline Tracks

Stripline trace geometries are sandwiched between two reference planes, which can simultaneously act as Power and Ground planes. The various conductive layers are typ-ically separated by about 6 mil thick dielectric layers. This implies that the stripline width needs to be fairly narrow, of the order of 5 mils, in order to meet 100 W differential impedance design targets. It is therefore assumed that skin-effect losses will play a significant role, even though the whole surface of the striplines conducts current, in contrast to microstrip traces where most of the current flows on the surface opposite to the reference plane [Hall 2000]. Wider tracks to reduce the skin-effect induced resistance at high frequencies would require thicker layers of dielectric material, however, this may not be feasible as the overall thickness of the stack up may exceed practical limits. Thicker boards may also require thicker vias, which can have adverse effects on routing density and lead to pronounced impedance discontinuities.

Another disadvantage of striplines is the need to contact them with vias. The choice of via design can have a sig-nificant impact on signal integrity and the performance of the whole XFI channel. The XFI MSA offers some guide-lines for the design of vias, differentiating between single-ended and differential vias, as well as analyzing the effect of open-circuit stub length on the via return loss (S11).

The high-frequency properties of vias (e.g. described by S11, S21 parameters) depend on the geometric parameters of the via (drilled hole diameter, length of via, clearance di-ameter, etc.), as well as the stack-up configuration and the precise location of Ground and Power planes. In addition, back drilling can be used to reduce the stub-length of the via for improved high-frequency performance. However, a full investigation of the influence of these parameters on the XFI data channel is neither possible nor within the scope of this white paper. Thus, an equivalent circuit was developed for single-ended vias that produced a similar response to the S11 plot shown in the XFP MSA (Figure 60 in XFP MSA revision 1.0), allowing the appropriate simula-tion of the impedance discontinuity introduced by the via. The equivalent circuit of the employed via model is shown in Figure 15. Some manufacturing variability has been incorporated into the model by using slightly varying capacitance and inductance values. The resultant graph of the via’s return loss is depicted in Figure 16. Similar to the via simulation shown in Figure 60 of the XFP MSA (revision 1.0), the model produces a dominant resonance peak at around 17 GHz.

The via model was subsequently inserted into the XFI data channel at either end of host board stripline interconnect. This allows the signal to flow from the XFP connector to the stripline and back from the stripline to the SMT termi-nation resistor.

11

11

current flows on the surface opposite to thereference plane [Hall 2000]. Wider tracks toreduce the skin-effect induced resistance at highfrequencies would require thicker layers ofdielectric material, however, this may not befeasible as the overall thickness of the stack upmay exceed practical limits. Thicker boards mayalso require thicker vias, which can have adverseeffects on routing density and lead to pronouncedimpedance discontinuities.

Another disadvantage of striplines is the need tocontact them with vias. The choice of via designcan have a significant impact on signal integrityand the performance of the whole XFI channel.The XFI MSA offers some guidelines for the designof vias, differentiating between single-ended anddifferential vias, as well as analyzing the effect ofopen-circuit stub length on the via return loss(S11).

The high-frequency properties of vias (e.g.described by S11, S21 parameters) depend on thegeometric parameters of the via (drilled holediameter, length of via, clearance diameter, etc.),as well as the stack-up configuration and theprecise location of Ground and Power planes. Inaddition, back drilling can be used to reduce thestub-length of the via for improved high-frequencyperformance. However, a full investigation of theinfluence of these parameters on the XFI datachannel is neither possible nor within the scope ofthis white paper. Thus, an equivalent circuit wasdeveloped for single-ended vias that produced asimilar response to the S11 plot shown in the XFPMSA (Figure 60 in XFP MSA revision 1.0),allowing the appropriate simulation of theimpedance discontinuity introduced by the via.

The equivalent circuit of the employed via modelis shown in Figure 15. Some manufacturingvariability has been incorporated into the modelby using slightly varying capacitance andinductance values. The resultant graph of the via’sreturn loss is depicted in Figure 16. Similar to thevia simulation shown in Figure 60 of the XFP MSA(revision 1.0), the model produces a dominantresonance peak at around 17 GHz

Figure 16. S11 return loss of via equivalent circuit

The via model was subsequently inserted into theXFI data channel at either end of host boardstripline interconnect. This allows the signal toflow from the XFP connector to the stripline andback from the stripline to the SMT terminationresistor.

Two sets of simulations were performed, oneusing a standard laminate and another for a lowerloss dielectric having loss tangents of 0.025 and0.016, respectively. For both simulations, thestriplines were 5 mil wide and sandwichedbetween reference planes that were 12.2 mil apart.The tracks were weakly edge-coupled with 50 milspacing.

The simulation parameters and results aresummarized in Table 4, two selected parametersare plotted in Figure 17. As expected, due to therelatively narrow linewidth the skin effect inducedlosses lead to a pronounced reduction in eyeopening caused, predominantly by a greatlyreduced inner eye height. In fact, the XFP MSAonly recommends stripline lengths up to amaximum of 6 inches for standard FR-4.

The use of a lower loss dielectric, however, canlead to a noticeable improvement in eye opening.This is attributed to the fact that dielectric lossesare proportionately larger for stripline than formicrostrip geometries, since the electric field isfully contained in the dielectric in a striplineconfiguration. Lower loss dielectrics cantherefore be used to exceed recommendedstripline lengths to greater than 6 in. A relateddiscussion of the relative importance of skin-effectand dielectric losses can also be found in [Johnson2002].

Figure 15. Via equivalent circuit.

150fF 153fF 156fF 159fF

0.70nH 0.71nH 0.72nHR=0.50

150fF 153fF 156fF 159fF

0.70nH 0.71nH 0.72nHR=0.50

11

current flows on the surface opposite to thereference plane [Hall 2000]. Wider tracks toreduce the skin-effect induced resistance at highfrequencies would require thicker layers ofdielectric material, however, this may not befeasible as the overall thickness of the stack upmay exceed practical limits. Thicker boards mayalso require thicker vias, which can have adverseeffects on routing density and lead to pronouncedimpedance discontinuities.

Another disadvantage of striplines is the need tocontact them with vias. The choice of via designcan have a significant impact on signal integrityand the performance of the whole XFI channel.The XFI MSA offers some guidelines for the designof vias, differentiating between single-ended anddifferential vias, as well as analyzing the effect ofopen-circuit stub length on the via return loss(S11).

The high-frequency properties of vias (e.g.described by S11, S21 parameters) depend on thegeometric parameters of the via (drilled holediameter, length of via, clearance diameter, etc.),as well as the stack-up configuration and theprecise location of Ground and Power planes. Inaddition, back drilling can be used to reduce thestub-length of the via for improved high-frequencyperformance. However, a full investigation of theinfluence of these parameters on the XFI datachannel is neither possible nor within the scope ofthis white paper. Thus, an equivalent circuit wasdeveloped for single-ended vias that produced asimilar response to the S11 plot shown in the XFPMSA (Figure 60 in XFP MSA revision 1.0),allowing the appropriate simulation of theimpedance discontinuity introduced by the via.

The equivalent circuit of the employed via modelis shown in Figure 15. Some manufacturingvariability has been incorporated into the modelby using slightly varying capacitance andinductance values. The resultant graph of the via’sreturn loss is depicted in Figure 16. Similar to thevia simulation shown in Figure 60 of the XFP MSA(revision 1.0), the model produces a dominantresonance peak at around 17 GHz

Figure 16. S11 return loss of via equivalent circuit

The via model was subsequently inserted into theXFI data channel at either end of host boardstripline interconnect. This allows the signal toflow from the XFP connector to the stripline andback from the stripline to the SMT terminationresistor.

Two sets of simulations were performed, oneusing a standard laminate and another for a lowerloss dielectric having loss tangents of 0.025 and0.016, respectively. For both simulations, thestriplines were 5 mil wide and sandwichedbetween reference planes that were 12.2 mil apart.The tracks were weakly edge-coupled with 50 milspacing.

The simulation parameters and results aresummarized in Table 4, two selected parametersare plotted in Figure 17. As expected, due to therelatively narrow linewidth the skin effect inducedlosses lead to a pronounced reduction in eyeopening caused, predominantly by a greatlyreduced inner eye height. In fact, the XFP MSAonly recommends stripline lengths up to amaximum of 6 inches for standard FR-4.

The use of a lower loss dielectric, however, canlead to a noticeable improvement in eye opening.This is attributed to the fact that dielectric lossesare proportionately larger for stripline than formicrostrip geometries, since the electric field isfully contained in the dielectric in a striplineconfiguration. Lower loss dielectrics cantherefore be used to exceed recommendedstripline lengths to greater than 6 in. A relateddiscussion of the relative importance of skin-effectand dielectric losses can also be found in [Johnson2002].

Figure 15. Via equivalent circuit.

150fF 153fF 156fF 159fF

0.70nH 0.71nH 0.72nHR=0.50

150fF 153fF 156fF 159fF

0.70nH 0.71nH 0.72nHR=0.50

Two sets of simulations were performed, one using a standard laminate and another for a lower loss dielec-tric having loss tangents of 0.025 and 0.016, respectively. For both simulations, the striplines were 5 mil wide and sandwiched between reference planes that were 12.2 mil apart. The tracks were weakly edge-coupled with 50 mil spacing.

The simulation parameters and results are summarized in Table 4, two selected parameters are plotted in Figure 17. As expected, due to the relatively narrow linewidth the skin effect induced losses lead to a pronounced reduction in eye opening caused, predominantly by a greatly re-duced inner eye height. In fact, the XFP MSA only recom-mends stripline lengths up to a maximum of 6 inches for standard FR-4. The use of a lower loss dielectric, however, can lead to a noticeable improvement in eye opening. This is attributed to the fact that dielectric losses are pro-portionately larger for stripline than for microstrip geom-etries, since the electric field is fully contained in the di-electric in a stripline configuration. Lower loss dielectrics can therefore be used to exceed recommended stripline lengths to greater than 6 inches. A related discussion of the relative importance of skin-effect and dielectric losses can also be found in [Johnson 2002].

It is also worth noting that the inner eye opening (inner eye height, Figure 17) is reduced even for “zero” inches of trace length due to the presence of the two vias. In the particular case considered here the two vias lead to a re-duction of the eye opening by approximately 10%. Careful via design or the use of differential vias can be employed to minimize this loss.

Another effect of using vias is an increased level of data-dependent jitter, DDJ. For short trace lengths the deter-ministic jitter oscillates with trace length, as is shown

for the lower loss dielectric in Figure 18. This oscillatory behavior is attributed to resonance effects set up by the reflections from the impedance discontinuities caused by the two vias at each end of the stripline. The effect is surprisingly large despite the use of a pseudorandom bit sequence.

To further investigate this phenomenon, the propagation delay of the stripline for simulation configuration 5 was determined (174.17 ps/in). This allows us to plot Figure 18 as a function of the signal round-trip time (twice the trace length) in units of the bit period (100 ps). The result-ing graph is shown in Figure 19. It is clear from Figure 19 that the maxima and minima are periodic with the bit pe-riod which confirms the original interpretation of the jitter magnitude oscillations as a resonance effect.

This effect can lead to variability in system performance for short interconnect lengths. Small variations of the dielec-tric constant of the epoxy laminate between manufactur-ing runs will result in variations of the stripline’s propaga-tion delay. This in turn will cause differences in the signal round-trip time for interconnects with the same nominal length. The overall effect on system performance will be a variability of the total jitter that needs to be tolerated by the receiver. In the interest of consistent system perfor-mance it will be best to user a lower grade laminate that introduces dielectric losses large enough to sufficiently at-tenuate reflections.

1212

It is also worth noting that the inner eye opening(inner eye height, Figure 17) is reduced even for“zero” inches of trace length due to the presence ofthe two vias. In the particular case consideredhere the two vias lead to a reduction of the eyeopening by approximately 10%. Careful via designor the use of differential vias can be employed tominimize this loss.

Another effect of using vias is an increased level ofdata-dependent jitter, DDJ. For short trace lengthsthe deterministic jitter oscillates with trace length,




Inner Eye Width[ps]

Inner Area[ps*mV]

XFP Reference Eye

Simulation 4 : N4000-6 (er=4.1, loss 0.025, 12.2 mil separation between reference planes), 5 mil wide stripline, 50 mil track spacing, 0.5 oz copper

2 in track length 375.7

4 in track length 321.4 7.9 92.1 14800.5

6 in track length 264.0 10.4 89.6 11827.2

8 in track length 225.6 13.4 86.6 9768.5

10 in track length 190.4 17.5 82.5 7854.0

12 in track length 161.3 21.7 78.3 6314.9



4 in track length 345.0 7.1 92.9 16025.3

6 in track length 294.0 8.9 91.1 13391.7

8 in track length 259.6 10.6 89.4 11604.1

10 in track length 227.9 13.6 86.4 9845.3

12 in track length 200.3 16.4 83.6 8372.5

Table 4. Simulation parameters and results for stripline interconnects.

Figure 17. Selected eye diagram parameters for stripline interconnect XFI link configurations

as is shown for the lower loss dielectric in Figure18. This oscillatory behavior is attributed toresonance effects set up by the reflections fromthe impedance discontinuities caused by the twovias at each end of the stripline. The effect issurprisingly large despite the use of apseudorandom bit sequence.

To further investigate this phenomenon, thepropagation delay of the stripline for simulationconfiguration 5 was determined (174.17 ps/in).This allows us to plot Figure 18 as a function of thesignal round-trip time (twice the trace length) in

12

It is also worth noting that the inner eye opening(inner eye height, Figure 17) is reduced even for“zero” inches of trace length due to the presence ofthe two vias. In the particular case consideredhere the two vias lead to a reduction of the eyeopening by approximately 10%. Careful via designor the use of differential vias can be employed tominimize this loss.

Another effect of using vias is an increased level ofdata-dependent jitter, DDJ. For short trace lengthsthe deterministic jitter oscillates with trace length,




Inner Eye Width[ps]

Inner Area[ps*mV]

XFP Reference Eye



4 in track length 321.4 7.9 92.1 14800.5

6 in track length 264.0 10.4 89.6 11827.2

8 in track length 225.6 13.4 86.6 9768.5

10 in track length 190.4 17.5 82.5 7854.0

12 in track length 161.3 21.7 78.3 6314.9



4 in track length 345.0 7.1 92.9 16025.3

6 in track length 294.0 8.9 91.1 13391.7

8 in track length 259.6 10.6 89.4 11604.1

10 in track length 227.9 13.6 86.4 9845.3

12 in track length 200.3 16.4 83.6 8372.5

Table 4. Simulation parameters and results for stripline interconnects.

Figure 17. Selected eye diagram parameters for stripline interconnect XFI link configurations

as is shown for the lower loss dielectric in Figure18. This oscillatory behavior is attributed toresonance effects set up by the reflections fromthe impedance discontinuities caused by the twovias at each end of the stripline. The effect issurprisingly large despite the use of apseudorandom bit sequence.

To further investigate this phenomenon, thepropagation delay of the stripline for simulationconfiguration 5 was determined (174.17 ps/in).This allows us to plot Figure 18 as a function of thesignal round-trip time (twice the trace length) in

13

13

L

C

R

L = td * z0 / N C = td / z0 / N

units of the bit period (100 ps). The resultinggraph is shown in Figure 19. It is clear fromFigure 19 that the maxima and minima areperiodic with the bit period which confirms theoriginal interpretation of the jitter magnitudeoscillations as a resonance effect.

This effect can lead to variability in systemperformance for short interconnect lengths. Smallvariations of the dielectric constant of the epoxylaminate between manufacturing runs will resultin variations of the stripline’s propagation delay.This in turn will cause differences in the signalround-trip time for interconnects with the samenominal length. The overall effect on systemperformance will be a variability of the total jitterthat needs to be tolerated by the receiver. In theinterest of consistent system performance it willbe best to user a lower grade laminate thatintroduces dielectric losses large enough tosufficiently attenuate reflections.

Figure 18. Data dependent jitter as a function of stripline trace length

Figure 19. Data dependent jitter plotted as a function of the signalround-trip in units of the bit period.

XFI Channel Simulations with a SerDes ReceiverSo far the “receiver” circuit was an ideal 100 Wtermination resistor. In a real-world XFI channelthis will in most cases be replaced by an EyeOpener or SerDes IC with the termination resistorimplemented on the Silicon die as part of thedifferential input buffer. This greatly simplifiessystem designs, as no additional surface mountedcomponents are required for a XFI channel.However, this also means that the frequencydependent characteristics of the IC package arebetween the end of the host-board transmissionlines and the termination circuitry. This in turncan have an influence on the quality of thereceived signal.

To evaluate this effect a model for the IC packagewas created. An ideal package for a XFI channelcomponent would be a 50 W impedance (z0, zdiff=100 W) transmission line that would justintroduce a delay to the signal but no reflections.Modern Ball Grid Array (BGA) IC packages mayget fairly close to this transmission line limit,however, the internal structure of the IC package(eg. package vias and bond wires) will introduceimpedance discontinuities. To model thisprogressively, we will take as an example a 50 Wtransmission line with a delay td of 90 ps. Thiscorresponds to an IC package interconnect lengthof approximately 10 mm (~0.4 in), depending onthe refractive index of the package material.Instead of describing the interconnect as atransmission line, however, we will break thepackage interconnect down into a discrete numberof identical RLC circuits. In a circuit diagram thiswould resemble a “ladder” of series resistors andinductors linking capacitors that are connected toground. Each RLC element constitutes a step ofthe “ladder” as is shown schematically in Figure20. The more steps this “ladder” has, the more itwill resemble a transmission line. Fewer steps onthe other hand will lead to increased losses andpronounced resonances in the S11 and S21parameters of this IC package interconnect model.

Figure 20. Constituting elements of an RLC-”ladder” package model.

13

L

C

R

L = td * z0 / N C = td / z0 / N

units of the bit period (100 ps). The resultinggraph is shown in Figure 19. It is clear fromFigure 19 that the maxima and minima areperiodic with the bit period which confirms theoriginal interpretation of the jitter magnitudeoscillations as a resonance effect.

This effect can lead to variability in systemperformance for short interconnect lengths. Smallvariations of the dielectric constant of the epoxylaminate between manufacturing runs will resultin variations of the stripline’s propagation delay.This in turn will cause differences in the signalround-trip time for interconnects with the samenominal length. The overall effect on systemperformance will be a variability of the total jitterthat needs to be tolerated by the receiver. In theinterest of consistent system performance it willbe best to user a lower grade laminate thatintroduces dielectric losses large enough tosufficiently attenuate reflections.

Figure 18. Data dependent jitter as a function of stripline trace length

Figure 19. Data dependent jitter plotted as a function of the signalround-trip in units of the bit period.

XFI Channel Simulations with a SerDes ReceiverSo far the “receiver” circuit was an ideal 100 Wtermination resistor. In a real-world XFI channelthis will in most cases be replaced by an EyeOpener or SerDes IC with the termination resistorimplemented on the Silicon die as part of thedifferential input buffer. This greatly simplifiessystem designs, as no additional surface mountedcomponents are required for a XFI channel.However, this also means that the frequencydependent characteristics of the IC package arebetween the end of the host-board transmissionlines and the termination circuitry. This in turncan have an influence on the quality of thereceived signal.

To evaluate this effect a model for the IC packagewas created. An ideal package for a XFI channelcomponent would be a 50 W impedance (z0, zdiff=100 W) transmission line that would justintroduce a delay to the signal but no reflections.Modern Ball Grid Array (BGA) IC packages mayget fairly close to this transmission line limit,however, the internal structure of the IC package(eg. package vias and bond wires) will introduceimpedance discontinuities. To model thisprogressively, we will take as an example a 50 Wtransmission line with a delay td of 90 ps. Thiscorresponds to an IC package interconnect lengthof approximately 10 mm (~0.4 in), depending onthe refractive index of the package material.Instead of describing the interconnect as atransmission line, however, we will break thepackage interconnect down into a discrete numberof identical RLC circuits. In a circuit diagram thiswould resemble a “ladder” of series resistors andinductors linking capacitors that are connected toground. Each RLC element constitutes a step ofthe “ladder” as is shown schematically in Figure20. The more steps this “ladder” has, the more itwill resemble a transmission line. Fewer steps onthe other hand will lead to increased losses andpronounced resonances in the S11 and S21parameters of this IC package interconnect model.

Figure 20. Constituting elements of an RLC-”ladder” package model.

XFI Channel Simulations with a SerDes Receiver

So far the “receiver” circuit was an ideal 100 W termination resistor. In a real-world XFI channel this will in most cases be replaced by an Eye Opener or SerDes IC with the termi-nation resistor implemented on the Silicon die as part of the differential input buffer. This greatly simplifies system designs, as no additional surface mounted components are required for a XFI channel. However, this also means that the frequency dependent characteristics of the IC package are between the end of the host-board transmis-sion lines and the termination circuitry. This in turn can have an influence on the quality of the received signal.

To evaluate this effect a model for the IC package was created. An ideal package for a XFI channel component would be a 50 W impedance (z0, zdiff =100 W) transmis-sion line that would just introduce a delay to the signal but no reflections. Modern Ball Grid Array (BGA) IC pack-ages may get fairly close to this transmission line limit, however, the internal structure of the IC package (eg. package vias and bond wires) will introduce impedance discontinuities. To model this progressively, we will take as

an example a 50 W transmission line with a delay td of 90 ps. This corresponds to an IC package interconnect length of approximately 10 mm (~0.4 in), depending on the re-fractive index of the package material. Instead of describ-ing the interconnect as a transmission line, however, we will break the package interconnect down into a discrete number of identical RLC circuits. In a circuit diagram this would resemble a “ladder” of series resistors and induc-tors linking capacitors that are connected to ground. Each RLC element constitutes a step of the “ladder” as is shown schematically in Figure 20. The more steps this “ladder” has, the more it will resemble a transmission line. Fewer steps on the other hand will lead to increased losses and pronounced resonances in the S11 and S21 parameters of this IC package interconnect model.

The resonances and the cutoff frequency of this package model move to lower frequencies as the number of RLC circuits is reduced. This is illustrated in Figure 21. For the chosen example of 50 W asymptotic impedance and a delay of 90 ps, the total inductance equates to 4.50 nH, and the total capacitance to 1.80 pF. These are distributed equally between the different “steps” of the “ladder” [Hall 2000].

The thick grey line in Figure 20 is the maximum allowed channel loss in an XFI link as per the XFP MSA. The pack-age model consisting of only 2 RLC circuits is clearly not consistent with the performance requirements of an XFI link.

The effect that a realistic package model has on the XFI link budget was investigated for a microstrip transmission line link model. As an example simulation configuration 2 was chosen with a microstrip length of 8 inches.

The signal was probed at the IC pins (point 5 in Figure 1, point D in the XFP MSA revision 1.0). Two eye diagrams that resulted from these simulations are shown in Figure 22. The eye on the left serves as a reference and shows the signal without an IC package model probed at the end of the microstrip lines. The eye diagram on the right shows the same signal after the insertion of an IC package model consisting of 3 RLC circuits. It is evident that the level of jitter has increased, and the maximum inner eye opening is reduced.

14

14

The resonances and the cutoff frequency of thispackage model move to lower frequencies as thenumber of RLC circuits is reduced. This isillustrated in Figure 21. For the chosen exampleof 50 W asymptotic impedance and a delay of 90ps, the total inductance equates to 4.50 nH, andthe total capacitance to 1.80 pF. These aredistributed equally between the different “steps”of the “ladder” [Hall 2000].

Figure 21. Transmission characteristics (S21) of the SerDes/EyeOpener IC package model. The package is broken down into multipleidentical RLC sections.

The thick grey line in Figure 20 is the maximumallowed channel loss in an XFI link as per the XFPMSA. The package model consisting of only 2 RLCcircuits is clearly not consistent with theperformance requirements of an XFI link.

The effect that a realistic package model has onthe XFI link budget was investigated for amicrostrip transmission line link model. As anexample simulation configuration 2 was chosenwith a microstrip length of 8 in.

Figure 22. Simulation without IC package (left eye diagram) and with an IC package model consisting of 3 RLC circuits. The signal is probed atpoint 5 (figure 1, point D in XFP MSA) of the XFI channel reference model.

The signal was probed at the IC pins (point 5 inFigure 1, point D in the XFP MSA revision 1.0).Two eye diagrams that resulted from thesesimulations are shown in Figure 22. The eye onthe left serves as a reference and shows the signalwithout an IC package model probed at the end ofthe microstrip lines. The eye diagram on the rightshows the same signal after the insertion of an ICpackage model consisting of 3 RLC circuits. It isevident that the level of jitter has increased, andthe maximum inner eye opening is reduced.

The jitter and the inner eye height have beenderived as a figure of merit from simulationswhere the total inductance and capacitance of thechosen package model was broken down into 2, 3,4, 6, 8, and 12 identical RLC circuits. The resultsare shown graphically in Figure 23.

In order to interpret Figure 23 one needs toremember that fewer RLC sections in the packagemodel means a poorer package with a lower cutofffrequency. A high number of sections means thatthe package model asymptotically approaches a 50W transmission line. It is therefore evident fromFigure 23 that a package with a lower bandwidth(fewer RLC sections) leads to increased jitter anda reduced eye opening. For the evaluation of theoverall XFI channel link budget it is thereforeimportant to pay attention to the frequencycharacteristics of the IC package of the eye openeror SerDes IC. The same argument applies ofcourse the other way round, when the SerDes actsas the transmitter of the electrical signal and theXFP transceiver module as the receiver. In orderto keep jitter to a minimum the bandwidth of theXFP transceiver needs to be optimized in a similarfashion in order to keep any parasitics as small aspossible.

14

The resonances and the cutoff frequency of thispackage model move to lower frequencies as thenumber of RLC circuits is reduced. This isillustrated in Figure 21. For the chosen exampleof 50 W asymptotic impedance and a delay of 90ps, the total inductance equates to 4.50 nH, andthe total capacitance to 1.80 pF. These aredistributed equally between the different “steps”of the “ladder” [Hall 2000].

Figure 21. Transmission characteristics (S21) of the SerDes/EyeOpener IC package model. The package is broken down into multipleidentical RLC sections.

The thick grey line in Figure 20 is the maximumallowed channel loss in an XFI link as per the XFPMSA. The package model consisting of only 2 RLCcircuits is clearly not consistent with theperformance requirements of an XFI link.

The effect that a realistic package model has onthe XFI link budget was investigated for amicrostrip transmission line link model. As anexample simulation configuration 2 was chosenwith a microstrip length of 8 in.

Figure 22. Simulation without IC package (left eye diagram) and with an IC package model consisting of 3 RLC circuits. The signal is probed atpoint 5 (figure 1, point D in XFP MSA) of the XFI channel reference model.

The signal was probed at the IC pins (point 5 inFigure 1, point D in the XFP MSA revision 1.0).Two eye diagrams that resulted from thesesimulations are shown in Figure 22. The eye onthe left serves as a reference and shows the signalwithout an IC package model probed at the end ofthe microstrip lines. The eye diagram on the rightshows the same signal after the insertion of an ICpackage model consisting of 3 RLC circuits. It isevident that the level of jitter has increased, andthe maximum inner eye opening is reduced.

The jitter and the inner eye height have beenderived as a figure of merit from simulationswhere the total inductance and capacitance of thechosen package model was broken down into 2, 3,4, 6, 8, and 12 identical RLC circuits. The resultsare shown graphically in Figure 23.

In order to interpret Figure 23 one needs toremember that fewer RLC sections in the packagemodel means a poorer package with a lower cutofffrequency. A high number of sections means thatthe package model asymptotically approaches a 50W transmission line. It is therefore evident fromFigure 23 that a package with a lower bandwidth(fewer RLC sections) leads to increased jitter anda reduced eye opening. For the evaluation of theoverall XFI channel link budget it is thereforeimportant to pay attention to the frequencycharacteristics of the IC package of the eye openeror SerDes IC. The same argument applies ofcourse the other way round, when the SerDes actsas the transmitter of the electrical signal and theXFP transceiver module as the receiver. In orderto keep jitter to a minimum the bandwidth of theXFP transceiver needs to be optimized in a similarfashion in order to keep any parasitics as small aspossible.

The jitter and the inner eye height have been derived as a figure of merit from simulations where the total induc-tance and capacitance of the chosen package model was broken down into 2, 3, 4, 6, 8, and 12 identical RLC circuits. The results are shown graphically in Figure 23.

In order to interpret Figure 23 one needs to remember that fewer RLC sections in the package model means a poorer package with a lower cutoff frequency. A high number of sections means that the package model asymptoti-cally approaches a 50 W transmission line. It is therefore evident from Figure 23 that a package with a lower band-width (fewer RLC sections) leads to increased jitter and a reduced eye opening. For the evaluation of the overall XFI channel link budget it is therefore important to pay attention to the frequency characteristics of the IC pack-age of the eye opener or SerDes IC. The same argument applies of course the other way round, when the SerDes acts as the transmitter of the electrical signal and the XFP

transceiver module as the receiver. In order to keep jitter to a minimum the bandwidth of the XFP transceiver needs to be optimized in a similar fashion in order to keep any parasitics as small as possible.

One counter-intuitive observation in Figure 23 is the fact that the eye opening seems to increase again if the num-ber of RLC sections is reduced to two. However, one needs to remember that this package model does not meet the loss specification of the XFP MSA. It appears that the in-ner height of the eye is increased due to the reflection of the high frequency portion of the 10 Gbit/s data stream by the package parasitics. Thus, from the point of view of the Silicon die the IC package acts as a low-pass filter. The reflected high frequency components of the signal will therefore be missing at the die pads, consequently reduc-ing the edge-rate and inner eye-opening at the input buf-fer where it is most relevant.

15

Figure 23. Jitter and inner eye height as function of the IC packagecharacteristics.

One counter-intuitive observation in Figure 23 isthe fact that the eye opening seems to increaseagain if the number of RLC sections is reduced totwo. However, one needs to remember that thispackage model does not meet the lossspecification of the XFP MSA. It appears that theinner height of the eye is increased due to thereflection of the high frequency portion of the 10Gbit/s data stream by the package parasitics.Thus, from the point of view of the Silicon die theIC package acts as a low-pass filter. The reflectedhigh frequency components of the signal willtherefore be missing at the die pads, consequentlyreducing the edge-rate and inner eye-opening atthe input buffer where it is most relevant.

Conclusions and RecommendationsThe simulation examples and results within thispaper have shown how the design of the XFIchannel can adversely affect the Signal Integrity ofthe link. Special attention was paid to theinfluence on signal quality of the interconnectstructure between the quantizer/ eye openercircuits on the XFP module and the eye opener/SerDes IC on the host board. It became clear thatthe design decisions will depend on a number oftrade-offs:

• For XFI channels where the transceiver andSerDes IC are placed very close to each other,EMI from the traces will contribute little to theoverall EMI of the system. This allows the use ofmicrostrip traces with standard, relatively highloss FR-4. Attention needs to be paid toresonance effects due to reflections fromimpedance discontinuities. The skin-effectresistance of relatively narrow traces and thedielectric losses of standard FR-4 shouldprovide the necessary attenuation forimmunity to these reflections.

· For XFI channels where the design requires alarge separation between the XFP transceiverand the SerDes or Eye Opener IC, striplineinterconnects are the most likely configurationto provide the targeted EMI margin. For goodsignal integrity, however, the use of low loss FR-4 will be necessary. Furthermore, it isrecommended to employ high-speed designrules for vias like increased clearancediameters and back drilling to reduce via stublengths.

· If the XFI channel design falls between theselimits, it is recommended to determine theoptimum configuration through simulation.Agilent will support the activities of systemdesigners and signal integrity engineers byproviding state-of-the art component models. Inaddition, Agilent’s Application Engineeringteams will provide design references andsimulation support to facilitate the adoption ofthe XFP standard for next generation systems.

The overriding theme in the successful design of aXFI data channel is perhaps the requirement for acareful analysis of each constituting link element.“Due diligence” of a XFI link design is to establishcompliance of each element with the frequencydependent loss specifications outlined in the XFPMSA. Furthermore, the sum of all losses needs tobe smaller than the overall link budget.Interactions between the various link elementscan still cause the XFI channel to showunexpected behavior and fail the compliance tests,this will have to be verified by signal integritysimulations. However, following this methodologythe system design should rapidly convergencetowards a solution that will meet therequirements.

AcknowledgmentWe would like to thank our colleagues at Agilent’sTurin Technology Centre for their expert adviceand support during all stages of this work.

Special thanks are due to Giampaolo Bendelli forhis invaluable help at the beginning of this study,which jump-started this white paper.

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved. Obsoletes 5988-8704ENAV02-1490EN - November 11, 2008

Conclusions and Recommendations

The simulation examples and results within this paper have shown how the design of the XFI channel can ad-versely affect the Signal Integrity of the link. Special atten-tion was paid to the influence on signal quality of the in-terconnect structure between the quantizer/ eye opener circuits on the XFP module and the eye opener/ SerDes IC on the host board. It became clear that the design deci-sions will depend on a number of trade-offs:

• For XFI channels where the transceiver and SerDes IC are placed very close to each other, EMI from the traces will contribute little to the overall EMI of the system. This allows the use of microstrip traces with standard, relatively high loss FR-4. Attention needs to be paid to resonance effects due to reflections from impedance discontinuities. The skin-effect resistance of relatively narrow traces and the dielectric losses of standard FR-4 should provide the necessary attenuation for immunity to these reflections.

• For XFI channels where the design requires a large separation between the XFP transceiver and the SerDes or Eye Opener IC, stripline interconnects are the most likely configuration to provide the targeted EMI margin. For good signal integrity, however, the use of low loss FR- 4 will be necessary. Furthermore, it is recommended to employ high-speed design rules for vias like increased clearance diameters and back drilling to reduce via stub lengths.

• If the XFI channel design falls between these limits, it is recommended to determine the optimum configuration through simulation. Avago will support the activities of system designers and signal integrity engineers by providing state-of-the art component models. In addition, Avago’s Application Engineering teams will provide design references and simulation support to facilitate the adoption of the XFP standard for next generation systems.

The overriding theme in the successful design of a XFI data channel is perhaps the requirement for a careful analysis of each constituting link element. “Due diligence” of a XFI link design is to establish compliance of each el-ement with the frequency dependent loss specifications outlined in the XFP MSA. Furthermore, the sum of all loss-es needs to be smaller than the overall link budget. Inter-actions between the various link elements can still cause the XFI channel to show unexpected behavior and fail the compliance tests, this will have to be verified by signal in-tegrity simulations. However, following this methodology the system design should rapidly convergence towards a solution that will meet the requirements.

Acknowledgment

We would like to thank our colleagues at Avago’s Turin Technology Centre for their expert advice and support during all stages of this work. Special thanks are due to Gi-ampaolo Bendelli for his invaluable help at the beginning of this study, which jump-started this white paper.

References

[Hall 2000] Stephen H. Hall, Garrett W. Hall, James A. Call, “High Speed Digital System Design”, John Wiley & Sons, Inc., ISBN 0-471-36090-2.

[Johnson 2002] Howard Johnson, “Mixtures of skin-effect and dielectric loss”, EDM Magazine, September 19, 2002.

[Ritchey 1999] Lee W. Ritchey, “A tutorial on PCB Materials”, www.speedingedge.com

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