Consolidation of software

control for PS Booster kickersMaxime Gauthier – TE-ABT-EC

1

Summary

Personal presentation

“ID Card”

Culture

Activities

CV

Project presentation

Context

Purpose

Phase 1

Phase 2

Status

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Personal presentation – ID Card

Born in 1992 - Lyon

Childhood in Serrières de Briord – Bugey

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Personal presentation - Activities5

Personal presentation - CV

Scholarship

Embedded Electronics – Image Processing – Automatism

DUT & License degree: University Lyon 1

Master degree: Telecom Saint-Étienne

Work experience

CRVI (QC) – Image Processing (C++, Matlab) – Internship 3mo: 2013

Barco (BE) – Embedded Electronics and Image Processing (C++, Matlab, Python)

– Internship 6mo + Employed 1y3mo: 2017

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Personal presentation – CV French Robotic Cup 2016

School organization

12 members – 2 robots

Mechanical, Electrical and Software design

Manufacturing done through partnerships

Assembly and soldering in-house

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Personal presentation – CV8

Barco Demetra: Digital Dermatoscope

Multispectral imaging

Embedded Image processing

Purpose: Help Dermatologist with

integrated analysis tool

eg. Compute skin metrics using

Multispectral data

CERN Project presentation – Context

Consolidate control hardware and software for kickers magnet

PSB

BE.BSW Extraction Bumper

BE.EK Extraction Kicker

BE.TK Recombination Kicker

PS

KFA 71-79

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CERN Project presentation - KFA71-7910

KFA 71-79 system

12 Magnets

Each magnet is powered by a

Generator

Each Generator has his

dedicated control crate

1 FEC to rule them all

FEC and Generator control

crates communicate through

RS232

Project presentation – Purpose

Phase 1 – FEC Crate:

FEC CPU were running old LynxOs and GM framework

Get rid of the old VME FEC CPU (CES RIO) and replace them by MEN A25 CPU

Update FEC side software using latest BE-CO technology FESA 3 and CC7, Lynx OS and GM are not supported anymore

Design software interfacing with standard ABT FESA Classes and old hardware

Phase 2 – Generator Control Crates:

G64 CPU hardware was based on Motorola 6809

G64 software was difficult to maintain, compiler not available anymore

Hardware not produced anymore and few spare parts left

Design KGC as replacement hardware for G64 system based on SbRIO board

Develop software running on the SbRIO board architecture

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Project presentation – phase1FEC

1. CPU

2. RS232

3. Timing

4. External Condition

5. Intershot Delay (Now

suppressed)

6. VMOD I/O

7. Dual Delay

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1 2 3 4 5 6 7

Project presentation – phase1FEC 13

Existing ABT FESA Class Interface FESA Class

State ControlDeveloped by Marco P.

Maintained by Marco P.

Purpose:

• Manage module state

(ON/OFF/Standby)

KITsDeveloped by Christophe C.

Maintained by Christophe C.

Purpose:

• Gather User Requests from

Operators (Kick settings)

• Compute Load balancing

G64 FESA ClassDeveloped by Kim

Maintained by myself

Purpose:

• Read KITs instructions and Send them to the

different generators through RS232

• Read after pulse feedbacks (PFN Voltage)

through RS232

• Send pulse feedbacks to KITs

• Gather modules Interlocks

• Raise external Conditions if necessary

Project presentation – phase2

Generator Controller

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Generator Controller Crate

Content part 1

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1. G64 system

2. Dual Digital Delay

3. Drift Stabilizer

4. Timing Control Main

5. Timing Control SCR

2 3 4 5

Project presentation – phase2

Generator Controller

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6 7 8 9 1

0

1

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2

Generator Controller Crate

Content part 2

6. Module Record (mechanical)

7. Primary protection

8. Voltage measuring

9. Thyratron Protection

10. Interlock

11. Voltage Reference

12. Local Remote

Project presentation – phase2

Generator Controller

G64 System

1 CPU card based on Motorolla

6809 processor (1978) with RS232

Interface.

2 I/O Cards were necessary to

communicate with the control

modules.

(e.g: Read PFN Voltage / Write

Reference voltage)

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Project presentation – phase2

Generator Controller

SbRIO board

Manufactured by NI

Xilinx Zynq SoC – 2 Core ARM 9 + FPGA

Runs on NI Linux distribution

RS232 – Ethernet port

Communicate with up to 4 modules

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Kicker Generator Controller

Designed & Manufactured at CERN

Voltage Adaptation stage

G64 bus connection

6x 26 Pin I/O port

1x RS232 port

1x SbRIO board slot

20x Green LED

Project presentation – phase2

Generator Controller

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Kicker Generator Controller

KGC SoftwareDeveloped by Markaus K.

Maintained by myself

Purpose:

• Load FPGA instance

• Decode FEC messages (RS232)

• Send Commands to FPGA

• Get Modules feedbacks

• Send feedbacks to FEC

FPGA GatewareDeveloped by Jan S.

Maintained by Jan S.

Purpose:

• Gather command from KGC Software

• Write commands to the control modules

• Read module satus after pulse

• Send module status back to KGC

software

Project presentation – Status

Work done Work to be finished

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Phase 1 - FEC Phase 2 – Generator Controller

Work done

• G64 Class compiled with FESA 5 and CC6

already running for KFA 71-79 since YETS

2017

• FEC Renovation completed: MEN A25 –

CC7 Linux

Work done

• KGC card production received

• KGC Software and Gateware tested in

Lab

Work to be finished

• Test G64 Class Using FESA 7 and CC7

• Operation deployment

• Commissioning

Work to be finished

• Test produced KGC card

• Test KGC software and FPGA gateware

• Install new hardware in operation

• Commissioning