constructive computer architecture tutorial 6: five details of smips implementations andy wright
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Constructive Computer Architecture Tutorial 6: Five Details of SMIPS Implementations Andy Wright 6.S195 TA. Introduction. Lab 6 involves creating a 6 stage pipelined SMIPS processor from a 2 stage pipeline - PowerPoint PPT PresentationTRANSCRIPT
Constructive Computer Architecture
Tutorial 6:Five Details of SMIPS ImplementationsAndy Wright6.S195 TA
October 7, 2013 http://csg.csail.mit.edu/6.s195 T05-1
Introduction
Lab 6 involves creating a 6 stage pipelined SMIPS processor from a 2 stage pipeline This requires a lot of attention to
architectural details of the processor, especially at the points of interaction between the stages.
This tutorial will cover some details of the SMIPS architecture that will be useful for the current and future labs
October 7, 2013 T05-2http://csg.csail.mit.edu/6.s195
6 stage SMIPS pipeline
October 7, 2013 T05-3http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
5 Details
Processor StatePoisoning InstructionsASAP Prediction CorrectionPipeline FeedbackRemoving Pipeline Stages
October 7, 2013 T05-4http://csg.csail.mit.edu/6.s195
5 Details
Processor StatePoisoning InstructionsASAP Prediction CorrectionPipeline FeedbackRemoving Pipeline Stages
October 7, 2013 T05-5http://csg.csail.mit.edu/6.s195
Processor State
The processor state is (PC, RFile, Mem)Instructions can be seen as functions of a processor state that return the new processor state addi(PC, RFile, Mem) = (PC+4, RFile’, Mem)
RFile’ is RFile updated with the result of the addi instruction
The instruction memory can be seen as a function of PC that returns Instructions Imem: (PC) ->
( (PC, Rfile, Mem) -> (PC, RFile, Mem) )
October 7, 2013 T05-6http://csg.csail.mit.edu/6.s195
Processor State
If your SMIPS processor from lab is not working: Was an instruction executed on the
wrong processor state? RAW hazards Not using the right PC in the execute stage
Was the wrong instruction executed? A wrong path instruction from branch
misprediction updated the processor state
October 7, 2013 T05-7http://csg.csail.mit.edu/6.s195
Processor State
October 7, 2013 T05-8http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Green blocks make up the processor state. All other state elements make sure the right processor state is used to compute instructions, and to make sure the right instructions are executed.
5 Details
Processor StatePoisoning InstructionsASAP Prediction CorrectionPipeline FeedbackRemoving Pipeline Stages
October 7, 2013 T05-9http://csg.csail.mit.edu/6.s195
Poisoning Instructions
Why poison? It’s a way to mark that an instruction should be killed at a later stage. This mark could be as simple as using
an invalid value in a maybe data type
Instructions are poisoned when epochs don’t matchWhy not kill in place?
October 7, 2013 T05-10http://csg.csail.mit.edu/6.s195
Kill-In-Place Pipeline
October 7, 2013 T05-11http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Scoreboard entries need to be removed when instructions are killed.
Kill-In-Place Pipeline
October 7, 2013 T05-12http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Both Exec and WB try to call sb.remove(). This will cause Exec to conflict with WB. Also, the scoreboard implementation doesn’t allow out-of-order removal.
Poisoning Pipeline
October 7, 2013 T05-13http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Poison Kill
5 Details
Processor StatePoisoning InstructionsASAP Prediction CorrectionPipeline FeedbackRemoving Pipeline Stages
October 7, 2013 T05-14http://csg.csail.mit.edu/6.s195
ASAP Prediction Correction
Different instructions that affect the program flow can be resolved at different times Absolute Jumps – Decode Register Jumps – RFetch Branches – Exec
You can save cycles on each misprediction by correcting the PC once you have computed what the next PC should have been.
October 7, 2013 T05-15http://csg.csail.mit.edu/6.s195
ASAP Prediction Correction
October 7, 2013 T05-16http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
This is the general idea, we want Decode, RFetch, and Exec to be able to correct the PC
ASAP Prediction Correction
How is this actually done?How do you keep from allowing wrong path instructions to update the PC?How do you keep track of everything?How? More Epochs!
October 7, 2013 T05-17http://csg.csail.mit.edu/6.s195
ASAP Prediction Correction
October 7, 2013 T05-18http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Decode, RFetch, and Exec each have their own epoch.
dEpoch rfEpoch
ASAP Prediction Correction
October 7, 2013 T05-19http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Each epoch acts just like eEpoch does
Correcting PC in Execute
October 7, 2013 T05-20http://csg.csail.mit.edu/6.s195
Correcting PC in Execute
October 7, 2013 T05-21http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
123456
Mispredicted Write Back
Correcting PC in Execute
October 7, 2013 T05-22http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
234561
Poisoning Write Back
Correcting PC in Execute
October 7, 2013 T05-23http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
345612
Poisoning Write Back
Correcting PC in Execute
October 7, 2013 T05-24http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
456123
Poisoning Killing
Correcting PC in Execute
October 7, 2013 T05-25http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
561234
Executing Killing
Correcting PC in Execute
October 7, 2013 T05-26http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
612345
Executing Killing
Correcting PC in Execute
October 7, 2013 T05-27http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
123456
Executing Write Back
Correcting PC in Decode
October 7, 2013 T05-28http://csg.csail.mit.edu/6.s195
Correcting PC in Decode
October 7, 2013 T05-29http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem
fEpoch
PC
Redirect
dEpoch
123456
Mispredicted Write Back
Correcting PC in Decode
October 7, 2013 T05-30http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem
fEpoch
PC
Redirect
dEpoch
234561
Killing Write Back
Correcting PC in Decode
October 7, 2013 T05-31http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem
fEpoch
PC
Redirect
dEpoch
34512
Decoding Write Back
Correcting PC in Decode
October 7, 2013 T05-32http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem
fEpoch
PC
Redirect
dEpoch
45123
Decoding Write Back
Correcting PC in Decode
October 7, 2013 T05-33http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem
fEpoch
PC
Redirect
dEpoch
51234
Decoding Write Back
Correcting PC in Decode
October 7, 2013 T05-34http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem
fEpoch
PC
Redirect
dEpoch
12345
Decoding Stall
Correcting PC in Decode
October 7, 2013 T05-35http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem
fEpoch
PC
Redirect
dEpoch
23456
Decoding Write Back
1
Correcting PC in Decode and Execute
October 7, 2013 T05-36http://csg.csail.mit.edu/6.s195
Correcting PC in Decode and Execute
October 7, 2013 T05-37http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
123456
Executing Write Back
dEpoch
Decoding
fdEpoch
feEpoch
Fetch has local estimates of eEpoch and dEpochDecode has a local estimate of eEpoch
Correcting PC in Decode and Execute
What if decode and execute see mispredictions in the same cycle? If execute sees a misprediction, then
the decode instruction is a wrong path instruction. The redirect coming from decode should be ignored.
October 7, 2013 T05-38http://csg.csail.mit.edu/6.s195
Correcting PC in Decode and Execute
What if execute sees a misprediction, then decode sees one in the next cycle? The decode instruction will be a
wrong path instruction, so it should not try to redirect the PC
October 7, 2013 T05-39http://csg.csail.mit.edu/6.s195
Correcting PC in Decode and Execute
October 7, 2013 T05-40http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
123456
Mispredicted Write Back
dEpoch
Decoding
fdEpoch
feEpoch
Assume this instruction is a mispredicted jump instruction. It will be in the decode stage next cycle
Correcting PC in Decode and Execute
October 7, 2013 T05-41http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
234561
Poisoning Write Back
dEpoch
Killing
fdEpoch
feEpoch
The decode stage knows eEpoch, and recognizes this misprediction is a wrong path instruction. The decode stage kills this instruction.
Correcting PC in Decode and Execute
October 7, 2013 T05-42http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
34511
Poisoning Write Back
dEpoch
Decoding
fdEpoch
feEpoch
Correcting PC in Decode and Execute
October 7, 2013 T05-43http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
45123
Stalling Killing
dEpoch
Decoding
fdEpoch
feEpoch
Correcting PC in Decode and Execute
October 7, 2013 T05-44http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
51234
Executing Killing
dEpoch
Decoding
fdEpoch
feEpoch
Correcting PC in Decode and Execute
October 7, 2013 T05-45http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
12345
Executing Stalling
dEpoch
Decoding
fdEpoch
feEpoch
Correcting PC in Decode and Execute
October 7, 2013 T05-46http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
23456
Executing Write Back
dEpoch
Decoding
fdEpoch
feEpoch
1
Correcting PC in Decode and Execute
What if decode sees a misprediction, then execute sees one in the next cycle? The decode instruction will be a
wrong path instruction, but it won’t be known to be wrong path until later
October 7, 2013 T05-47http://csg.csail.mit.edu/6.s195
Correcting PC in Decode and Execute
October 7, 2013 T05-48http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
123456
Executing Write Back
dEpoch
Mispredicted
fdEpoch
feEpoch
Assume this instruction is a mispredicted branch instruction. It will be in the execute stage next cycle
Correcting PC in Decode and Execute
October 7, 2013 T05-49http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
234561
Mispredicted Write Back
dEpoch
Killing
fdEpoch
feEpoch
The PC was just “corrected” to a different wrong path instruction
Correcting PC in Decode and Execute
October 7, 2013 T05-50http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
34511
Poisoning Write Back
dEpoch
Killing
fdEpoch
feEpoch
The PC was just corrected to a correct path instruction
Correcting PC in Decode and Execute
October 7, 2013 T05-51http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
4512
Stalling Write Back
dEpoch
Decoding
fdEpoch
feEpoch
The PC was just corrected to a correct path instruction
Correcting PC in Decode and Execute
October 7, 2013 T05-52http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
5123
Stalling Killing
dEpoch
Decoding
fdEpoch
feEpoch
The PC was just corrected to a correct path instruction
Correcting PC in Decode and Execute
October 7, 2013 T05-53http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
1234
Executing Stalling
dEpoch
Decoding
fdEpoch
feEpoch
The PC was just corrected to a correct path instruction
Correcting PC in Decode and Execute
October 7, 2013 T05-54http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
12345
Executing Stalling
dEpoch
Decoding
fdEpoch
feEpoch
The PC was just corrected to a correct path instruction
Correcting PC in Decode and Execute
October 7, 2013 T05-55http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
feEpoch
PC
Redirect
123456
Executing Write Back
dEpoch
Decoding
fdEpoch
feEpoch
The PC was just corrected to a correct path instruction
5 Details
Processor StatePoisoning InstructionsASAP Prediction CorrectionPipeline FeedbackRemoving Pipeline Stages
October 7, 2013 T05-56http://csg.csail.mit.edu/6.s195
Pipeline Feedback
You can forward changes to the processor state to later instructions in the pipeline Forwarding PC state
Redirect fifo Epoch updates
Forwarding register file state Register file data Scoreboard entries
Forwarding memory state Covered later in class (maybe)
October 7, 2013 T05-57http://csg.csail.mit.edu/6.s195
Pipeline Feedback
October 7, 2013 T05-58http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Pipeline Feedback
Better processor performance can be obtained by faster feedback EHRs can be used to make state
updates appear to happen in less than a cycle
How can Epoch and PC feedback be sped up?
October 7, 2013 T05-59http://csg.csail.mit.edu/6.s195
fEpoch and PC feedback
October 7, 2013 T05-60http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Normally updates to fEpoch and PC epoch have to pass through the redirect fifo. When IFetch sees entries in the redirect fifo, it makes the changes to fEpoch and PC
fEpoch and PC feedback
October 7, 2013 T05-61http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem Epoch [0]
Epoch [1]
PC
Redirect
Changes to the Epoch can now be seen by IFetch in the same cycle that execute made the changes
fEpoch and PC feedback
October 7, 2013 T05-62http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem Epoch [0]
Epoch [1]
PC
Redirect
The PC is still coming through the redirect fifo, so the epoch and the pc will get out of synch!
fEpoch and PC feedback
October 7, 2013 T05-63http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMemEpoch
[0]
Epoch [1]
PC [1]
Make the PC an EHR too! Whenever Execute sees a misprediction, IFetch reads the correct next instruction in the same cycle!
PC [0]
Pipeline Feedback
How can Register File and Scoreboard feedback be sped up?
October 7, 2013 T05-64http://csg.csail.mit.edu/6.s195
RFile and SB feedback
October 7, 2013 T05-65http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Normally updates (writes) to the register file and updates (removes) to the scoreboard are seen in the next cycle.
RFile and SB feedback
October 7, 2013 T05-66http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Bypass Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
A bypass register file will allow the result from a write to be read by RFetch in the same cycle.
RFile and SB feedback
October 7, 2013 T05-67http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Bypass Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
In this case, the scoreboard is still stalling as much as before
RFile and SB feedback
October 7, 2013 T05-68http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Bypass Register File
Pipeline Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
You can use a scoreboard that removes before searching (called a pipeline scoreboard because it is similar to pipeline fifo’s deq<enq behavior)
5 Details
Processor StatePoisoning InstructionsASAP Prediction CorrectionPipeline FeedbackRemoving Pipeline Stages
October 7, 2013 T05-69http://csg.csail.mit.edu/6.s195
Removing Pipeline Stages
You will create a 6 stage SMIPS pipeline in Lab 6 6 is a lot of stages and may not be
necessary How much work would it be to turn it
into a shorter pipeline? Say 4 stages? How much work would it be to shift
work from one pipeline stage to another?
October 7, 2013 T05-70http://csg.csail.mit.edu/6.s195
Removing Pipeline Stages
October 7, 2013 T05-71http://csg.csail.mit.edu/6.s195
IFetch Decode WBExec
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Say you want a 4 stage pipeline where Decode does RFetch and Exec does Memory. How do you make this machine with as little work as possible?
Removing Pipeline Stages
October 7, 2013 T05-72http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Replace CFFifos between stages with bypass fifos. The bypass fifos will act as wires when possible.
Bypass Fifos
Removing Pipeline Stages
October 7, 2013 T05-73http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Now you want to move RFetch to the Exec stage to reduce the amount of time stalled for RAW hazards. How much work is this?
Removing Pipeline Stages
October 7, 2013 T05-74http://csg.csail.mit.edu/6.s195
IFetch Decode WBRFetch Exec Memory
Register File
Scoreboard
DMemIMem eEpoch
fEpoch
PC
Redirect
Just change the types of fifos between Decode and RFetch and between RFetch and Exec.
Removing Pipeline Stages
The 6 stage pipeline is very flexible.You can try out many different stage configurations in FPGA synthesis to see how your IPS (Instructions Per Seconds) changes.
October 7, 2013 T05-75http://csg.csail.mit.edu/6.s195
Conclusion
Processor State Most processor errors can be related to operating on
the wrong processor state
Poisoning Instructions Needed for lab 6
ASAP Prediction Correction This will be covered in more depth in lab 7.
Pipeline Feedback Can be used to speed up processors
Removing pipeline stages Can also be used to speed up processors
October 7, 2013 T05-76http://csg.csail.mit.edu/6.s195
Questions?
October 7, 2013 T05-77http://csg.csail.mit.edu/6.s195