control & execution
DESCRIPTION
Control & Execution. Finite State Machines for Control MIPS Execution. Synchronous Systems. Combinational logic. Flipflop. Flipflop. data. trailing edge. Clock. leading edge. On the leading edge of the clock, the input of a flipflop is transferred to the output and held. - PowerPoint PPT PresentationTRANSCRIPT
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L14 – Control & Execution 1Comp 411 – Fall 2009 11/04/09
Control & Execution
Finite State Machines for Control
MIPS Execution
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L14 – Control & Execution 2Comp 411 – Fall 2009 11/04/09
Synchronous Systems
FlipflopCombinational
logicFlipflop
leading
edge
trailing
edge
On the leading edge of the clock, the input of a flipflop is transferred to the output and held.
We must be sure the output of the combinational logic has settled before the next leading clock edge.
Clock
data
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L14 – Control & Execution 3Comp 411 – Fall 2009 11/04/09
Asynchronous Systems
LatchCombinational
logicLatch
data
valid
No clock!
The data carries a “valid” signal along with it
System goes at greatest possible speed.
Only “computes” when necessary.
Everything we look at in this class will be synchronous
Asynchronous is my specialization!
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L14 – Control & Execution 4Comp 411 – Fall 2009 11/04/09
Fetching Sequential Instructions
P
C
4
Read Address
Instruction
Instruction
Memory
How about branch?
flipflop
+
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L14 – Control & Execution 5Comp 411 – Fall 2009 11/04/09
Datapath for R-type Instructions
Read Reg. 1 (rs)5
5
5
32
Read Reg. 2 (rt)
Write Reg. (rd)
Write Data
data 1
data 2
3
ALU Operation
Inst Bits 25-21
Inst Bits 20-16
Inst Bits 15-11
RegWrite
32
32
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L14 – Control & Execution 6Comp 411 – Fall 2009 11/04/09
Fun with MUXes
Select 0
In 3
In 2
Select 0
In 1
In 0
Select 1
Out
Remember the MUX?
This will route 1 of 4different 1 bit valuesto the output.
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L14 – Control & Execution 7Comp 411 – Fall 2009 11/04/09
MUX Blocks
01234567
Out
2 1 0Select
Inp
ut
8
3
Select
In Out
The select signal determines which of the inputs is connectedto the output
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L14 – Control & Execution 8Comp 411 – Fall 2009 11/04/09
Inside there is a 32 way MUX per bit
Register 0
Register 1
Register 2
Register 3
Register 4
Register ...
Register 30
Register 31
32 to1 MUX
Read Reg 1
Data 1
For EACH bit in the 32 bit register
LOT’S OF CONNECTIONS!
And this is just one port! Remember, there’s data1 and data2 coming out of the register file!
5
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L14 – Control & Execution 9Comp 411 – Fall 2009 11/04/09
Our Register File has 3 ports
Read Reg. 15
5
5
32
Read Reg. 2
Write Reg.
Write Data
data 1
data 2
Inst Bits 25-21
Inst Bits 20-16
Inst Bits 15-11
RegWrite
32
32
2 Read Ports
1 Write Port
REALLY LOTS OF CONNECTIONS!
This is one reason we have only a small number of registers
What’s another reason?
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L14 – Control & Execution 10Comp 411 – Fall 2009 11/04/09
Implementing Logical Functions
Suppose we want to map M input bits to N output bits
For example, we need to take the OPCODE field from the instruction and determine what OPERATION to send to the ALU.
3
ALU Operation
(8 different ops)
32
32
Map to ALU op
OPCODE bitsfrom instruction
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L14 – Control & Execution 11Comp 411 – Fall 2009 11/04/09
We can get 1 bit out with a MUX
01234567
Out
2 1 0Select
Inp
ut
Put the INPUT HERE
Wire these to HIGH or LOW depending on the value you want OUT for that INPUT
For example, 3 input AND has INPUT7 wired HIGH and all the others wired LOW.
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L14 – Control & Execution 12Comp 411 – Fall 2009 11/04/09
Or use a ROM
Read-Only MemoryM-bit Address N-bit Result
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L14 – Control & Execution 13Comp 411 – Fall 2009 11/04/09
Or use sum-of-products
AND layerM-bit Input
OR layerN-bit OutputProduct Terms
Think of the SUM of PRODUCTS form.
The AND layer generates the products of various input bits
The OR layer combines the products into various outputs
You could also use two NAND layers instead
Could be implemented using Boolean gates, or also using a “programmable logic array” (PLA) [similar to a PROM, but both the AND and the OR parts are programmable].
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L14 – Control & Execution 14Comp 411 – Fall 2009 11/04/09
Finite State Machines
•A set of STATES
•A set of INPUTS
•A set of OUTPUTS
•A function to map the STATE and the INPUT into the next STATE and an OUTPUT
Remember automata?
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L14 – Control & Execution 15Comp 411 – Fall 2009 11/04/09
Traffic Light Controller
G E/W
R N/S
Y E/W
R N/S
R E/W
G N/S
R E/W
Y N/S
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L14 – Control & Execution 16Comp 411 – Fall 2009 11/04/09
Implementing an FSM
State(flipflops)
Function
(comb. logic)
Inputs Outputs
Clock
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L14 – Control & Execution 17Comp 411 – Fall 2009 11/04/09
FSM Example: Recognizing Numbers
Recognize the regular expression for floating point numbers
[ \t]* [-+]?[0-9]*(. [0-9]*)? (e[-+]?[0–9]+)?
Examples:+123.456e23.456 1.5e-10-123
“a” matches itself
“[abc]” matches one of a, b, or c
“[a-z]” matches one of a, b, c, d, ..., x, y, or z
“0*” matches zero or more 0’s (“”, “0”, “00”, “0000”)
“Z?” matches zero or 1 Z’s
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L14 – Control & Execution 18Comp 411 – Fall 2009 11/04/09
FSM Diagram
start
‘ ’
sign
‘+’ ‘-’
whole
‘0’ – ‘9’‘0’ – ‘9’
frac
‘.’
‘.’‘.’ ‘0’ – ‘9’
exp
‘e’
‘e’
‘0’ – ‘9’
done‘ ’
‘ ’
‘ ’
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L14 – Control & Execution 19Comp 411 – Fall 2009 11/04/09
FSM TableIN : STATE NEW STATE
‘ ’ : start start
‘0’ | ‘1’ | ... | ‘9’ : start whole
‘+’ | ‘-’ : start sign
‘.’ : start frac
‘0’ | ‘1’ | ... | ‘9’ : sign whole
‘.’ : sign frac
‘0’ | ‘1’ | ... | ‘9’ : whole whole
‘.’ : whole frac
‘ ’ : whole done
‘e’ : whole exp
‘e’ : frac exp
‘0’ | ‘1’ | ... | ‘9’ : frac frac
‘ ’ : frac done
‘0’ | ‘1’ | ... | ‘9’ : exp exp
‘ ’ : exp done
STATE ASSIGNMENTS
start = 0 = 000
sign = 1 = 001
whole = 2 = 010
frac = 3 = 011
exp = 4 = 100
done = 5 = 101
error = 6 = 110
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L14 – Control & Execution 20Comp 411 – Fall 2009 11/04/09
FSM Implementation
ROM or PLAor comb. logic
state3
8char in
error
ok
3
Our PLA has:
•11 inputs
•5 outputs
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L14 – Control & Execution 21Comp 411 – Fall 2009 11/04/09
FSM Summary
With JUST a register and some logic, we can implement complicated sequential functions like recognizing a FP number.
This is useful in its own right for compilers, input routines, etc.
The reason we’re looking at it here is to see how designers implement the complicated sequences of events required to implement instructions
Think of the OP-CODE as playing the role of the input character in the recognizer. The character AND the state determine the next state (and action).
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L14 – Control & Execution 22Comp 411 – Fall 2009 11/04/09
MIPS Execution: Five Steps1. Instruction Fetch
2. Instruction Decode and Register Fetch
3. Execution, Memory Address Computation, or Branch Completion
4. Memory Access or R-type instruction completion
5. Memory Read Completion
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
An FSM looks at the op-code to determine how many...
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L14 – Control & Execution 23Comp 411 – Fall 2009 11/04/09
Use PC to get instruction and put it in the Instruction Register.
Increment the PC by 4 and put the result back in the PC.
Can be described succinctly using RTL "Register-Transfer Language"
IR = Memory[PC]; IR is “Instruction Register”PC = PC + 4;
Step 1: Instruction Fetch
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L14 – Control & Execution 24Comp 411 – Fall 2009 11/04/09
Read registers rs and rt in case we need themCompute the branch address in case the instruction is a
branchRTL:
A = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC + (sign-extend(IR[15-0]) << 2);
We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic)
Step 2: Instruction Decode and Register Fetch
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L14 – Control & Execution 25Comp 411 – Fall 2009 11/04/09
ALU is performing one of three functions, based on instruction type
Memory Reference:ALUOut = A + sign-extend(IR[15-0]);
R-type:ALUOut = A op B;
Branch:if (A==B) PC = ALUOut;
Step 3 (instruction dependent)
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L14 – Control & Execution 26Comp 411 – Fall 2009 11/04/09
Loads and stores access memory
MDR = Memory[ALUOut]; MDR is Memory Data Register
orMemory[ALUOut] = B;
R-type instructions finish
Reg[IR[15-11]] = ALUOut;
Step 4 (R-type or memory-access)
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L14 – Control & Execution 27Comp 411 – Fall 2009 11/04/09
Reg[IR[20-16]]= MDR;
Step 5 Memory Read Completion
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L14 – Control & Execution 28Comp 411 – Fall 2009 11/04/09
Summary:
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction for branches
Action for jumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completion
Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR