control flow graph - cornell university · 2018-10-09 · control flow graph (cfg) a control flow...
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Control Flow Graph
ECE 5775High-Level Digital Design Automation
Fall 2018
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▸ First problem set (HW1) is posted– Due Monday 9/17
▸ Lab 2 will be released on Thursday
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Announcements
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▸ What is a strongly connected component (SCC)?
▸ Is a DAG strongly connected?
▸ Does topological search apply to an SCC?
▸ What is the time complexity of a topological search (in terms of |V| and |E| )?
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Revisiting Some Important Graph Definitions
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Graph Traversal
▸ Purpose: visit all the vertices in a particular order, check/update their properties along the way
▸ Algorithms– Depth-first search (DFS)– Breadth-first search (BFS)– Either can be used to realize
topological sort
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a
c d
b
DFS order = a à ?
BFS order = a à ?
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Outline
▸ More on BDDs and static timing analysis
▸ Basics of control data flow graph– Basic blocks– Control flow graph
▸ Dominance relation– Finding loops
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(a) (b)
Name the logic gates represented by the following BDDs
Review: Two-Input Gates in BDD
x
y
01
x
y
10
y
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More Virtues of BDDs
▸ There are many, but to list a few more:– Can represent an exponential number of paths
with a DAG
– Can evaluate an n-ary Boolean function in at most n steps
• By tracing paths to the 1 node, we can count or enumerate all solutions to equation f = 1
– Every BDD node (not just root) represent some Boolean function in a canonical way
• A BDD can be multi-rooted representing multiple Boolean functions sharing subgraphs
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0 1
y y
x
z
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BDD Application on Functional Verification
▸ Either prove equivalence▸ Or find counterexample(s)
– Input values (x, y) for which these programs produce different results
bool P(bool x, bool y) { return ~(~x & ~y); }
bool Q(bool x, bool y) { return x ^ y; }
v1 = ~x
v2 = ~y
v3 = v1 & v2
P = ~v3
Q = x ^ y
Is (P == Q) true?
Straight-line evaluation
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BDD-based Equivalence Checking
P = ~v3 = ~(~x & ~y)= x | y
Q = x ^ y
T = (P == Q)
x
y
01
CounterexampleSetting x = 1 & y = 1leads to false output
Hence P does not equal Q
x
y
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x
y
10
y
BDD of P
BDD of Q
BDD of T
OR gate
XOR gate
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▸ Cone Cv : a subgraph rooted on a node v– K-feasible cone: #inputs(Cv) £ K (Can occupy a K-input LUT)– K-feasible cut: The set of input nodes of a K-feasible Cv
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FPGA LUT Mapping Revisited
a
b
d f
c
e
g
h
Another 3-feasible cone with an associated cut = {a, b, c}
A 3-feasible cone with a cut = {c, e, f}
i0
i1
i2
i3i4
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▸ Assumptions– K=3– All inputs arrive at time 0 – Unit delay model: 3-LUT delay = 1; Zero edge delay
▸ Question: Minimum arrival time (AT) of each gate output?
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Timing Analysis with LUT Mapping
a
b
d f
c
e
g
h
AT(a) = 1 AT(d) = 1
AT(h) = ?AT(b) = 1 AT(e) = 1 AT(c) = 1
i0
i1
i2
i3i4
AT(f) = ?Associated cut?
AT(g) = ?
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FPGA Design Flow with HLSHigh-level Programming
Languages
Compilation
Scheduling/Pipelining,
Binding
Logic Synth.,Tech. Mapping,
P&R, STA
RTL
if (condition) {…
} else {t1 = a + b;t2 = c * d;t3 = e + f;t4 = t1 * t2;z = t4 – t3;
}
Untimed high-leveldescription
Timed design
Bitstream
HLS Flow
RTLFlow
FPGA
ab
z
d
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High-level Programming Languages
(C/C++, OpenCL, SystemC, ...)
Parsing
Transformations
RTLgeneration
S0
S1
S2
S0
S1
S2
ab
z
d
3 cycles
*–
Control data flow graph (CDFG)
Finite state machines with datapath
BB3
BB1
BB2
BB4
T F
+
-
*+
*
if (condition) {…
} else {t1 = a + b;t2 = c * d;t3 = e + f;t4 = t1 * t2;z = t4 – t3;
}
Scheduling Binding
Allocation
A Typical HLS Flow
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Intermediate Representation (IR)
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Intermediate Representation (IR)
▸ Purposes of creating and operating on an IR
– Encode the behavior of the program– Facilitate analysis– Facilitate optimization– Facilitate retargeting
▸ The IR we will focus on is control data flow graph (CDFG)
Front end
Codegeneration
Optimization
Source code
Target code
AnalysisIR
IR’
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Program Flow Analysis
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Basic block
Program
Function
Inter-procedural
Intra-procedural
Local
Flow analysis
Data flow analysis
Control flow analysis
▸ Control flow analysis: determine control structure of a program and build control flow graphs (CFGs)
▸ Data flow analysis: determine the flow of data values and build data flow graphs (DFGs)
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Basic Blocks
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▸ Basic block: a sequence of consecutive intermediate language statements in which flow of control can only enter at the beginning and leave at the end
– Only the last statement of a basic block can be a branch statement and only the first statement of a basic block can be a target of a branch
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Partitioning a Program into Basic Blocks
▸ Each basic block begins with a leader statement
▸ Identify leader statements (i.e., the first statements of basic blocks) by using the following rules:
– (i) The first statement in the program is a leader
– (ii) Any statement that is the target of a branch statement is a leader (for most intermediate languages these are statements with an associated label)
– (iii) Any statement that immediately follows a branch or returnstatement is a leader
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Example: Forming the Basic Blocks
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Basic Blocks: (1) p = 0(2) i = 1
(3) t1 = 4 * i(4) t2 = a[t1](5) t3 = 4 * i(6) t4 = b[t3](7) t5 = t2 * t4(8) t6 = p + t5(9) p = t6(10) t7 = i + 1(11) i = t7(12) if i <= 20 goto (3)
(13) j = …
B1
B2
B3
(1) p = 0(2) i = 1(3) t1 = 4 * i(4) t2 = a[t1](5) t3 = 4 * i(6) t4 = b[t3](7) t5 = t2 * t4(8) t6 = p + t5(9) p = t6(10) t7 = i + 1(11) i = t7(12) if i <= 20 goto (3)(13) j = …
Leader statement is: (1) the first in the program(2) any that is the target of a branch (3) any that immediately follows a branch
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Control Flow Graph (CFG)
▸ A control flow graph (CFG), or simply a flow graph, is a directed graph in which:
– (i) the nodes are basic blocks; and – (ii) the edges are induced from the possible flow of the program
▸ The basic block whose leader is the first intermediate language statement is called the entry node
▸ In a CFG we assume no information about data values – an edge in the CFG means that the program may take that path
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Example: Control Flow Graph Formation
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(1) p = 0(2) i = 1
(3) t1 = 4 * i(4) t2 = a[t1](5) t3 = 4 * i(6) t4 = b[t3](7) t5 = t2 * t4(8) t6 = p + t5(9) p = t6(10) t7 = i + 1(11) i = t7(12) if i <= 20 goto (3)
(13) j = …
B1
B2
B3
BranchTarget
B1
B2
B3
Next Inst.
CFG
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▸ A node p in a CFG dominates a node q if every path from the entry node to q goes through p. We say that node p is a dominator of node q
▸ The dominator set of node q, DOM(q), is formed by all nodes that dominate q
– By definition, each node dominates itself therefore, q Î DOM(q)
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Dominators
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▸ Definition: Let G = (N, E, s) denote a CFG, where N: set of nodes E: set of edges s: entry node and let p Î N, q Î N– p dominates q, written p £ q
• p Î DOM(q)– p properly (strictly) dominates q, written p < q if p £ q and p ¹ q– p immediately (or directly) dominates q, written p <d q if p < q
and there is no t ÎN such that p < t < q• p = IDOM(q)
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Dominance Relation
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▸ Dominator sets:DOM(1) = {1}DOM(2) = {1, 2}DOM(3) = {1, 2, 3}DOM(10) = {1, 2, 10}
▸ Immediate domination:1 <d 2, 2 <d 3, …IDOM(2) = 1, IDOM(3) = 2 …
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Example: Dominance Relation
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entry
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Dominance Question
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entryAssume that node P is an immediate dominator of node Q
Question: Is P necessarily an immediate predecessor of Q in the CFG?
Answer: NO
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Identifying Loops
▸ Motivation: Programs spend most of the execution time in loops, therefore there is a larger payoff for optimizations that exploit loop structure
▸ Goal: Identify loops in a CFG, not sensitive to input syntax
– Create an uniform treatment for program loops written using different syntactical constructs (e.g. while, for, goto)
▸ Approach: Use a general approach based on analyzing graph-theoretical properties of the CFG
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▸ Definition: A strongly connected component(SCC) of the CFG, with– a single entry point called the header which
dominates all nodes in the SCC
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Loop Definition
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2
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3 4
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Loop Header
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▸ Question: In the CFG below, nodes 2 and 3 form an SCC; but do they form a loop?
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Is it a Loop?
1
2 3
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Finding Loops
▸ Loop identification algorithm– Find an edge B®H where H dominates B;
This edge is called a back-edge
– Find all nodes that (1) are dominated by H and (2) can reach B through nodes dominated by H; add them to the loop
• H and B are naturally included
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Finding Loops
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2
3
5 6
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Find all back edges in this graphand the natural loop associated with each back edge
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Summary
▸ Basic Blocks– Group of statements that execute atomically
▸ Control Flow Graphs– Model the control dependences between basic blocks
▸ Dominance relations– Shows control dependences between BBs– Used to determine natural loops
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▸ Next lecture: Static single assignment
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Next Class
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▸ These slides contain/adapt materials developed by– Forrest Brewer (UCSB)– Ryan Kastner (UCSD)– Prof. José Amaral (Alberta)
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Acknowledgements