convergence in vp methodology by employing tlm based ... · •systemc, tlm based virtual...

Convergence in VP methodology by

employing TLM based SystemC model

as a component for RTL co-verification

Primary Author: Rajashekar Somashekar

Secondary Author(s): Kesavan Prasanna

Presenter: Rajashekar Somashekar

Company/Organization: Infineon Technologies

ISCUG – India SystemC User Group 2

Technical Background

• SystemC, TLM based Virtual prototyping of Infineon microcontrollers for early software development.

• Primary tools: Virtualizer-Comet & Meteor from Synopsys

• Selectively RTL verification environments (directed as well as Constraint Random driven Verification languages like specman) used for verifying SystemC models.

• Used SystemC models in co-simulation for early RTL SoC environment bring-up.


Modeling across design phases*

• Requirements & Architectural exploration

– Functional or(and) system performance exploration

– Rapid development is the primary metric

• Virtual Prototyping for early software development

– High simulation performance

– cycle approximate equivalent modeling

• RTL verification

– Functional and Timing accuracy

• System validation

– Functional and Interface/Protocol accuracy

Results in multiple implementations!


Agenda

• Explore a unified methodology that results in a single implementation that satisfies the orthogonal requirements across the design phases.

• RTL level accuracy with (~) behavioral modeling performance!!!

• and hence the Title


Basics: TLM

…

HW/SW Split

Gate level

Register transfer level

(RTL)

Transaction level

(TLM)

Algorithm/Communicating

processes (CP)

Transactions across interfaces are modeled via

function calls instead of signals and complex

protocols

Register interface handling through callbacks

Event based modeling, clocks are abstracted

(>1000x faster than RTL)

Possibility to model complete systems (VP)

Abstraction/accuracy levels:

• Programmers View (PV - loosely coupled)

• PV + Timing (PVT – tightly coupled)

• Bus Cycle Accurate (BCA)

• Cycle Accurate (CA)

Languages:

• C/C++

• SystemC

• SystemVerilog (modelling or verification)

hig

her a

ccura

cy

faste

r execution tim

e


Basics: Sample TLM interface

• A serial port is typically TLM modeled as below with the strobe bits identifying the start and stop of the transaction and data available as a packet instead of serial data.


Basics: TLM Event Scheduling

• On event A, schedule an event B after 10 clocks.

• No explicit synchronization of clock is done.

• For perfect timing, we need to delay (actual residue) the event_B scheduling precisely till the next clock edge should happen.

SC_METHOD(fnEventA);

sensitive << event_A;

void fnEventA() {

event_B.notify(10*clk_period);

}


Co-verification: Methodology

• Rapid prototyping with very (very) early version of the spec

– Quite a few improvements were fed back to the spec itself!!!

• Exchange this with all the stakeholders, including end users.

– Any major misunderstanding (like endian, IO incompatibility etc) will get filtered here.

• Build the testbench components (monitor, driver etc) with the TLM interface in mind.

• Assemble the verification environment with these testbench components, RTL DUT and the model and start driving the stimulus…


Co-verification: Environment

DUT 1 - RTL

DUT 2 - Model

Input/Stimulus

Compare

Output

Output

Mismatch

???

Signal to

TLM

TLM to

Signal


Co-verification: Additional Requirement

• Support for legacy TLM interfaces

• Reusability of the model and the associated testbench components at SOC level

• Interface at mixed-languages (PLI, DPI, Stub ….)

These lead to modifications to the testbench components – Driver & Monitor and also verification specific handling within

the Model.


Co-verification: Enhanced Environment

DUT 1 - RTL

DUT 2 - Model

Input/Stimulus

Compare

Output

Output

Mismatch

???

Monitor

TLM to

Signal

Driver

Simple TLM

Socket (GP)


Co-verification: Timing critical regions

• Interface

– Delayed inputs to SystemC (due to reuse at SOC level verification)

– Leads to verification specific adjustments within the model.

• FIFOs

– Identical occurrences of write and read strobes between RTL and model is absolutely mandatory.

– Mandates Identical clocks generation on both sides.

• Register read/write

– Issuing of bus read/write is not the point of reference, but the actual updating/fetching is.


Co-verification: Proposed Guidelines

• Identical clocks generation with every corner case considered is of paramount importance

– Corner cases could arise due to fractional dividers, cascaded dividers etc

– Few of the RTL behaviors may not be captured in the spec!!! (partial writes 1st byte, 2nd byte only etc trigger recalculations differently)

– Unless modeled with extreme care this will drain away the performance of the model.

– Ideal candidate for reuse.

– Centralized clock handling with client-server approach with the sub-modules suits reusability.


Co-verification: Proposed Guidelines

• Keep the TLM abstraction for IOs to the minimum necessary.

• As changes to the spec is inevitable, keeping the model design modularized will help manage the changes easier.


Co-simulation: Requirements

• RTL equivalent C-Model with certain degree on cycle accuracy.

• TLM to/from signal Interface adapter for the model.

- simple tlm socket binding at the model (with blocking transport).

• Clock period to Clock ticks handling at the interface level.

• Configurability at the SoC for the different device handling.

• Back-door interfaces for the faster simulation, debugging / error injection to the internal methods.

• Generic interfaces at the SoC testbench to handle between the model and RTL.


Co-simulation: Use case

Clock & Reset Generator

Stimulus / Test case /

Receiver

RTL System

VHDL / Verilog / Wrapper

DMA / Bus / System

IP’s in RTL

Peripheral SystemC

Model (DUT)

Core /

Peripherals in RTL


Co-simulation: Use case

Clock & Reset Generator

Stimulus / Test case /

Receiver / Error Injection

to SystemC Models

RTL Sub System

RTL in Verilog / VHDL

(DUT – example DMA)

Bus Interface at Signal

Interface (RTL)

Core /

Peripherals in SystemC

with Adapter


Improved Methodology

• Identify the clocks and make sure the critical clock events are generated accurately and optimally.

– Reuse the clock generation logic from earlier IPs, since these tend to remain same across IPs.

– Start early discussion with the RTL designer to get these clock perfect.

• Rest of the steps follow the above as identified earlier here


Additional gains

• For modeling team

– Free verification for the model*

– Constrained Random based Verification

– RTL certified functional accuracy

• For verification team

– Elimination of reference model development

– Truly independent viewpoint to compare the RTL against*


Summary

• Matching the Clocks perfectly is of paramount importance and should start very early.

• Optimization of the clock generation is critical for the performance of the model.

• Reduce or eliminate the constraints like legacy TLM, reuse at SOC level verification etc, if not very important.

RTL level accuracy with (~) behavioral modeling performance

convergence in vp methodology by employing tlm based ... · •systemc, tlm based virtual...

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