coping with interconnect

Digital Integrated Circuits © Prentice Hall 1995Interconnect

COPING WITH INTERCONNECT


Impact of Interconnect Parasitics

• Reduce Reliability

• Affect Performance

Classes of Parasitics

• Capacitive

• Resistive

• Inductive


Nature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnology

SGlobal = SDie


INTERCONNECT

Dealing with Capacitance


Capacitance: The Parallel Plate Model

SiO2

Substrate

L

W

H

tox


Typical Wiring Capacitance Values


Fringing Capacitance

W - H/2H

+

(a)

(b)


Fringing Capacitance: Values


How to counter Clock Skew?

(from [Bakoglu89])


Interwire Capacitance

Substrate

SiO2

Insulator

Level1

Level2

Creates Cross-talk


Interwire Capacitance


Impact of Interwire Capacitance

(from [Bakoglu89])


Capacitance Crosstalk

VDD

PDN

In1

In2

In3

CX

CXY

X

Y

5V

OV

5x5 m Overlap: 0.35 V Interference


How to Battle Capacitive Crosstalk

Substrate (GND)

GND

ShieldinglayerVDD

GND

Shieldingwire

• Avoid parallel wires

• Shielding


Driving Large Capacitances

VDD

Vin Vout

CL

tpHL = CL Vswing/2

Iav

Transistor

Sizing


Using Cascaded Buffers

C2C1

Ci

CL

1 u u2 uN-1

In Out

uopt = e


tp in function of u and x

1.0 3.0 5.0 7.0u

0.0

20.0

40.0

60.0

u/l

n(u

)

x=10

x=100

x=1000

x=10,000


Impact of Cascading Buffers


Output Driver Design


How to Design Large Transistors

G(ate)

S(ource)

D(rain)

Multiple

Contacts

S

S

G

D

(a) small transistors in parallel(b) circular transistors


Bonding Pad Design

Bonding Pad

Out

InVDD GND

100 m

GND

Out


Reducing the swing

tpHL = CL Vswing/2

Iav

• Reducing the swing potentially yields linear reduction in delay• Also results in reduction in power dissipation• Requires use of “sense amplifier” to restore signal level


Charge Redistribution Amplifier

M1

M2 M3

Vref

VBVA

CBCA

(a)

0.0 1.00 2.00 3.00time (nsec)

0.0

1.0

2.0

3.0

4.0

5.0

V

VB

VA

Vin

Vref = 3V


Precharged Bus

In1.f

VDD

In2.f

Bus

CbusM1

M2

VDD

Out

CoutM3

M4f

0 5 10t (nsec)

-1.0

1.0

3.0

5.0

V

Vbus

Vsym

f

Vasym

Cbus =1pF


Tristate Buffers

In

VDD

En

EnOut

VDD

Out

In

En

En


Using Bipolar Versus MOS

But: Bipolar does not scale well with voltage!


Bipolar Versus MOS (cont.)

0 5 10 15 20t (nsec)

0.0

1.0

2.0

3.0

4.0

5.0

Vo

ut

Vin

Vout (bipolar)

Vout (mos)

Driving a 10 pF Capacitance

using Emitter(Source)-Followers


INTERCONNECT

Dealing with Resistance


Wire Resistance

W

L

H

R = H W

L

Sheet ResistanceRo

R1 R2


Interconnect Resistance


Dealing with Resistance

• Selective Technology Scaling

• Use Better Interconnect Materials

• More Interconnect Layersreduce average wire-length

e.g. silicides, bypasses


Polycide Gate Mosfet

n+n+

SiO2

PolySilicon

Silicide

p

Silicides: WSi2, TiSi2, PtSi2 and TaSi

Conductivity: 8-10 times better than Poly


Modern Interconnect


RI Introduced Noise

VDD

X

I

I

R’

R

VDD - V’

V

V

pre


Power and Ground Distribution

GND

VDD

Logic

GND

VDD

Logic

GND

VDD

(a) Finger-shaped network (b) Network with multiple supply pins


Electromigration (1)

Limits dc-current to 1 mA/m


Electromigration (2)


RC-Delay


RC-Models


Reducing RC-delay

Repeater


The Ellmore Delay


Penfield-Rubinstein-Horowitz


INTERCONNECT

Dealing with Inductance


Inductive Effects in Integrated Circuits

CoaxialCable

TriplateStrip Line

MicroStrip Wire aboveGround Plane


L di/dt

VDD

L

L

VoutVin

CL

i(t)


L di/dt: Simulation

t

t

t

vout

iL

vL

20mA

40mA

5V

0.2V

0.0

1.0

2.0

3.0

4.0

5.0

Vo

ut(

V)

0

10

20

I L (

mA

)

2 4 6 8 10t (nsec)

-0.3

-0.1

0.1

0.3

0.5

VL(V

)

tfall = 0.5 nsec

tfall = 4 nsec

Signals Waveforms for Output Driver connected To Bonding Pads(a) vout; (b) iL and (c) vL.

The Results of an Actual Simulation are Shown on the Right Side.


Choosing the Right Pin

Chip

MountingCavity

Lead Frame

Bonding Wire

Pin

L

L’

Make Rise- and Fall Times as slow as possible


Decoupling Capacitors

CHIPSUPPLY

Bonding

WireBoard

Wiring

Cd

Decoupling

Capacitor

+

-


The Transmission Line

Vin

r l

c

r l

c

r l

c

r l

c

Voutx

g g g g


Lossless Transmission Line - Parameters

vacuumspeed of light in


Wave Propagation Speed


Wave Reflection for Different Terminations


Transmission Line Response (RL=

0.0

1.0

2.0

3.0

4.0

5.0

V

0.0

1.0

2.0

3.0

4.0

V

0.0 5.0 10.0 15.0t (in tlightf)0.0

2.0

4.0

6.0

8.0

V

RS = 5Z0

RS = Z0

RS = Z0/5

(a)

(b)

(c)

VDest

VSource


Lattice Diagram

VSource VDest

0.8333 V

1.6666 V

+ 0.8333

+ 0.8333

+ 0.5556

+ 0.5556

+ 0.3704

+ 0.2469

+ 0.3704

+ 0.2469

2.2222 V

3.1482 V

3.7655 V

...

2.7778 V

3.5186 V

4.0124 V

L/

t


ECL Gate Line Response

Vc c

RC

Vc c

RC

Vref

Vin

IEE

VEE

Vcc

VEE

RB

Vcc

RC

IEEV

EE

RB

Z0= 100

L=2cm

(a)

0 0.5 1.0 1.5 2.00t (nsec)

-2.0

-1.5

-1.0

-0.5

Vo

ut

10k

100


Output Buffer Model

VDD

L = 10nH

L = 10nH

Vin L = 5nH

CL= 5pF

Z0 = 100

CL RL

Vout

(a)

VDD

Clamping

Diodes

8 43 224 900

20 106 562 1500


Output Buffer - Response

-5.0

0.0

5.0

10.0

Vo

ut

-2.0

0.0

2.0

4.0

Vo

ut

0 20 40 60t (nsec)-2.0

0.0

2.0

4.0

Vo

ut

CL = 25pFRL = 100

CL = 5pFRL = 100

CL = 5pFRL = 10k

Unclamped

Clamped

(b)

Vin


When to Consider Transmission Line Effects?


Packaging

Requirements

• Electrical: Low parasitics

• Mechanical: Reliable and Robust

• Thermal: Efficient Heat Removal

• Economical: Cheap


Bonding Techniques

Lead Frame

Substrate

Die

Pad

Wire Bonding


Tape-Automated Bonding (TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Die

Solder BumpFilm + Pattern

Sprockethole

Polymer film

Leadframe

Testpads


Flip-Chip Bonding

Solder bumps

Substrate

Die

Interconnect

layers


Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount


Package Types


Package Parameters


Multi-Chip Modules

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