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Copyright 1995-1999 SCRA 1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Technology Overview RASSP Education & Facilitation Program Module 43 Version 3.00 Copyright 1995-1999 SCRA All rights reserved. This information is copyrighted by the SCRA, through its Advanced Technology Institute (ATI), and may only be used for non-commercial educational purposes. Any other use of this information without the express written permission of the ATI is prohibited. Certain parts of this work belong to other copyright holders and are used with their permission. All information contained, may be duplicated for non-commercial educational use only provided this copyright notice and the copyright acknowledgements herein are included. No warranty of any kind is provided or implied, nor is any liability accepted regardless of use. The United States Government holds Unlimited Rights in all data contained herein under Contract F33615-94-C-1457. Such data may be liberally reproduced and disseminated by the Government, in whole or in part, without restriction except as follows: Certain parts of this work to other copyright holders and are used with their permission; This information contained herein may be duplicated only for non-commercial educational use. Any vehicle, in which part or all of this data is incorporated into, shall carry this notice. Slide 2 Copyright 1995-1999 SCRA 2 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Rapid Prototyping Design Process Test Technology SYSTEM DEF. FUNCTION DESIGN HW & SW PART. HW DESIGN SW DESIGN HW FAB SW CODE INTEG. & TEST VIRTUAL PROTOTYPE RASSP DESIGN LIBRARIES AND DATABASE Primarily software Primarily hardware HW & SW CODESIGN Slide 3 Copyright 1995-1999 SCRA 3 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Goals l To educate the general digital systems designer on the fundamentals of test technology in a manner that will assist him/her in designing testable systems l Provide information on the goals and techniques for testing systems m Provide information on techniques to increase the testability of designs m Provide information on how to incorporate these techniques into a general digital design methodology Slide 4 Copyright 1995-1999 SCRA 4 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques m Ad hoc design for testability techniques m Structured design for testability techniques q Scan design q Boundary scan Slide 5 Copyright 1995-1999 SCRA 5 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline (Cont.) l Built-In Self Test m Definitions m Test generation techniques for BIST m Signature analysis m BIST case study m Autonomous Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards m IEEE Std. 1149.1 m IEEE Std. 1149.1b m IEEE Std. 1149.5 m IEEE Std. 1029.1 m MIL-HDBK-XX47 Slide 6 Copyright 1995-1999 SCRA 6 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline (Cont.) l Design Flows with DFT l Summary l References Slide 7 Copyright 1995-1999 SCRA 7 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary Slide 8 Copyright 1995-1999 SCRA 8 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Introduction The Testing Problem l This module presents techniques that are used to detect defects in digital ICs and PC board systems l The goal of testing is to apply a minimum set of input vectors to each device to determine if it contains a defect l The first step is to detect defects at the manufacturing level at the earliest point possible Slide 9 Copyright 1995-1999 SCRA 9 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP The Testing Problem l Costs increase dramatically as faulty components find their way into higher levels of integration m $1.00 to fix an IC (throw it out) m $10.00 to find and replace bad IC on a PC board m $100.00 to find bad PC board in a system m $1000.00 to find bad component in fielded system Slide 10 Copyright 1995-1999 SCRA 1010 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP The Testing Problem (Cont.) l Apply a set of test vectors to each device off the manufacturing line and compare outputs to the known good response l The optimum test set will detect the greatest number of defects that can be present in a device with the least number of test vectors (high defect coverage) l Types of test sets: m Exhaustive - apply every possible input vector m Functional - test every function of the device m Fault Model Derived - find a test for every modeled fault Slide 11 Copyright 1995-1999 SCRA1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Testing Which Type is Closest to Optimum? Consider a 74181 ALU Chip - 14 inputs l Exhaustive testing m Will detect 100% of detectable faults m Requires 2 14 = 16,384 test vectors m A 16 bit ALU with 38 inputs would take 7.64 hours to exhaustively test at 10 MHz l Functional testing m Will detect 100% of detectable faults m Total functional testing will take over 448 vectors q Each logical mode can be tested with about 8 vectors q Each arithmetic mode can be tested with about 20 vectors m There is no algorithmic way to verify that all functional modes have been tested (designer expertise required) Slide 12 Copyright 1995-1999 SCRA 1212 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Testing Which Type is Closest to Optimum? (Cont.) l Modeled fault testing (consider single-stuck-at faults) m Will detect 100% of detectable modeled faults m Requires only 47 vectors m Vectors can be generated and analyzed (for fault coverage) using computer programs m The number of defects actually detected by this test vector set depends on the quality of the fault model m The key is to select a fault model that can be applied to the appropriate level of circuit abstraction (logic level) and that maps to the most possible physical defects Slide 13 Copyright 1995-1999 SCRA 1313 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Testing Current Practice l Use fault simulation on functional test set developed during design to determine list of undetected faults l Use this list of undetected faults as input to ATPG tool l If fault coverage is unsatisfactory, redesign or use DFT techniques to make undetected faults testable OR l Use structured DFT/BIST techniques from the bottom up Slide 14 Copyright 1995-1999 SCRA 1414 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Testing and Rapid Prototyping l To be effective, test must be incorporated into the design process at the highest levels l To avoid having a major impact on the speed of the design process, techniques for incorporating test must be efficient Test Technology SYSTEM DEF. FUNCTION DESIGN HW & SW PART. HW DESIGN SW DESIGN HW FAB SW CODE INTEG. & TEST VIRTUAL PROTOTYPE RASSP DESIGN LIBRARIES AND DATABASE Primarily software Primarily hardware HW & SW CODESIGN Model Year Slide 15 Copyright 1995-1999 SCRA 1515 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary Slide 16 Copyright 1995-1999 SCRA 1616 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Attributes Cause n Specification Mistakes n Implementation Mistakes n External Component Defects n Disturbances Interval Constant Intermittent Transient Characteristics Hardware Software Value Certain Unpredictable Breadth Local Global Slide 17 Copyright 1995-1999 SCRA 1717 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Modeling l Goals m Model defects in the device at the highest level of abstraction possible q Reduces the number of individual defects that have to be considered q Reduces the complexity of the device description that must be used in test generation and analysis q Allows test generation and analysis to be done as early in the design process as possible m Model as high a percentage as possible of the actual physical defects that can occur in the device Slide 18 Copyright 1995-1999 SCRA 1818 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Models l Stuck-at faults m Single stuck-at faults m Multiple stuck-at faults l Stuck-open faults l Bridging faults l Delay faults Slide 19 Copyright 1995-1999 SCRA 1919 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Single Stuck-at Fault Model l Assumptions m Only one line in the circuit is faulty at a time m The fault is permanent (as opposed to transient) m The effect of the fault is as if the faulty node is tied to either Vcc (s-a-1), or Gnd (s-a-0) m The function of the gates in the circuit is unaffected by the fault A B C 0 0 0 0 1 0 1 0 0 1 1 1 Fault-Free Gate V cc A B C Fault: A s-a-1 A B C 0 0 0 0 1 1 1 0 0 1 1 1 Faulty Gate Slide 20 Copyright 1995-1999 SCRA 2020 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Single Stuck-at Fault Model (Cont.) l Advantages m Can be applied at the logic level or module level m Reasonable numbers of faults 2n (n=number of circuit nodes) m Algorithms for automatic test pattern generation (ATPG) and faults simulation are well developed and efficient m Research indicates that the single stuck-at fault model covers about 90% of the possible manufacturing defects in CMOS circuits q Source-drain shorts, oxide pinholes, missing features, diffusion contaminants, metallization shorts, etc. m Other useful fault models (stuck-open, bridging faults) can be mapped into (sequences of) stuck-at faults l Disadvantages m Does not cover all defects in CMOS or other devices Slide 21 Copyright 1995-1999 SCRA 2121 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Multiple Stuck-at Fault Model l Assumptions m Same as single stuck-at faults except: m 2 or more lines in the circuit can be faulty at the same time l Advantage m If used in conjunction with single stuck-at faults, it covers a greater percentage of physical defects l Disadvantages m Large number of faults 3 n -1 (n=number of circuit nodes) m Algorithms for ATPG and fault simulation are much more complex and not as well developed m Does not cover a significantly larger number of detects that single stuck-at faults Slide 22 Copyright 1995-1999 SCRA2 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Stuck-open Fault Model l Assumptions m A single physical line in the circuit is broken m The resulting unconnected node is not tied to either Vcc or Gnd V DD V SS A B F Line Break Break above results in a memory-effect in the behavior of the circuit With AB=10, there is not path from either VDD or VSS to the output - F retains the previous value for some undetermined discharge time Slide 23 Copyright 1995-1999 SCRA 2323 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Stuck-open Fault Model (Cont.) l Advantages m Covers physical defects not covered by single or multiple stuck-at fault models m Can be tested with sequences of stuck-at fault tests q In the previous example (Nor gate), apply AB=00 (test for F s-a-0) and force F to Vcc q Apply AB=10 (test for A s-a-0) to force F to Gnd and observe results l Disadvantages m Requires a larger number of tests (sequence for each fault) m Algorithms for ATPG and fault simulation are more complex and less well developed m Requires a lower level circuit description (transistor level), at least for development of the fault list Slide 24 Copyright 1995-1999 SCRA 2424 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Bridging Fault Model l Assumptions m Two nodes of a circuit are shorted together m Usually assumed to be a low resistance path (hard short) m Three classes are typically considered: q Bridging within a logic element (transistor gates, sources, or drains shorted together) q Bridging between logic nodes (i.e. inputs or outputs of logic elements) without feedback q Bridging between logic nodes with feedback m Typically not considered is bridging of non-logical nodes between logic elements (transistor shorts across logic elements) Slide 25 Copyright 1995-1999 SCRA 2525 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Bridging Fault Model (Cont.) l Advantages m Covers a large percentage of physical defects - some research indicates that bridging faults account for up to 30% of all defects m Disadvantages m ATPG algorithms are more complex - testing requires setting the two bridged nodes to opposite values and observing the effect m Requires a lower level circuit description for bridging faults within logic elements Slide 26 Copyright 1995-1999 SCRA 2626 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Delay Fault Model l Assumptions m The logic function of the circuit-under-test is error free m Some physical defect, such as process variations, etc., makes some delays in the circuit-under-test greater than some defined bounds m Two delay fault models are typically used: q Gate delay, or transitional fault model q Path delay fault model Slide 27 Copyright 1995-1999 SCRA 2727 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Transitional Delay Fault Model l A logical model for a defect that delays either a rising or falling transition on a specific line in the circuit m Slow-to-rise m Slow-to-fall l Advantage m If a delay fault is large enough, it behaves as a temporary stuck-at fault, and single stuck-at fault testing techniques can be applied m Disadvantages m Two patterns are required for detection initialization and transition detection (propagation) m The minimum delay fault size that can be detected is difficult to determine Slide 28 Copyright 1995-1999 SCRA 2828 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Transitional Fault Model Example of Minimum Delay Fault Detectable B A C D E 0 0 1 1 Delay = 2 Delay = 6 Delay = 2 01 Slow-to- Rise Fault 681012 Z [Waicukauski87] IEEE 1987 Slide 29 Copyright 1995-1999 SCRA 2929 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Path Delay Fault Model l A fault model in which the total delays in a path from inputs to outputs in a circuit exceeds some maximum value l Advantages m Detects more delay faults - i.e., in transitional fault model, the delay of a faulty gate may be compensated for by other faster gates in the path m Can be used with more aggressive statistical design philosophy l Disadvantages m Large number of possible paths in circuit - exponential with number of gates m Algorithms for test generation are more complex and less well developed Slide 30 Copyright 1995-1999 SCRA 3030 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary Slide 31 Copyright 1995-1999 SCRA 3131 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation Definitions Test Vector An input vector for the circuit-under-test that causes the presence of a fault to be observable at a primary output Automatic Test Pattern Generation The process of generating a test pattern for a specific fault using some type of algorithm Detected Fault A fault for which a valid test vector has been generated Undetected Fault A fault for which a test vector has not been generated Redundant Fault A fault for which no test pattern exists (because of redundant logic in the circuit) Slide 32 Copyright 1995-1999 SCRA 3232 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation Definitions (Cont.) Fault Coverage The percentage of total faults for which test patterns have been generated: Fault Efficiency The percentage of faults that either are detected or PROVEN redundant (usually used to measure the effectiveness of a test generator): Fault Efficiency = 100 X Number of Detected Faults + Number of Redundant Faults Total Number of Faults in the CUT Fault Coverage = 100 X Number of Detected Faults Total Number of Faults in the CUT Slide 33 Copyright 1995-1999 SCRA3 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation Definitions (Cont.) Controllability A testability metric that measures the difficulty in driving a node to a specific value Observability A testability metric that measures the difficulty in propagating the value on node to a primary output Testability Measure A metric that attempts to determine how difficult it will be to generate a test for a specific line in the circuit. This metric: -Provides feedback to the designer on testability without actually performing test generation -Assists in the test generation process -Is based on controllability and observability Slide 34 Copyright 1995-1999 SCRA 3434 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation Definitions (Cont.) Sensitization The process of driving the circuit to a state where the fault causes an actual erroneous value in the device at the point of the fault. E.g., for single stuck-at faults, driving the node to the value opposite the stuck-at value Propagation The process of driving the circuit to a state where the error becomes observable at the primary outputs Justification The process of determining the input combination necessary to drive an internal circuit node to a specified value (consistency) Slide 35 Copyright 1995-1999 SCRA 3535 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation Process Circuit Under Test A s-a-0 A s-a-1 B s-a-0 B s-a-1 C s-a-0 C s-a-1 D s-a-0 D s-a-1 E s-a-0 E s-a-1 F s-a-0 F s-a-1... A s-a-0 Generate list of undetected faults (collapse) Select a fault for test generation A B C D E 1 0 1 X X Generate a test vector for that fault (ATPG) A s-a-0 F s-a-1 H s-a-0 N s-a-0 M s-a-1... Generate a list of other faults detected by that test vector (Fault Simulation) 4A s-a-0 A s-a-1 B s-a-0 B s-a-1 C s-a-0 C s-a-1 D s-a-0 D s-a-1 E s-a-0 E s-a-1 F s-a-0 4F s-a-1... Mark those detected faults off of the fault list Exit when all faults are detected or proven untestable LOOP: Select an undetected fault for test generation Slide 36 Copyright 1995-1999 SCRA 3636 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation/Testing Disconnect l Test vectors developed by the design team often must be significantly modified by the test team m Vectors are incompatible with the Automatic Test Equipment (ATE) q Test vectors overflow scan-data, format-data, or timing-data memory q Test vector set is not compact enough to fit in pattern memory q Test vectors dont address bi-directional conflicts q Test vectors included comparisons with tristate values Slide 37 Copyright 1995-1999 SCRA 3737 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation/Testing Disconnect (Cont.) l Solution - virtual testing 100101 001010 100101 101010 101001 010100 010110 111101 101010 000100 100101 001010 100101 101010 101001 010100 010110 111101 101010 000100 Virtual Prototype ATPG Vectors & Timing Data HDL Model of ATE system Virtual Tester Slide 38 Copyright 1995-1999 SCRA 3838 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Hierarchical Design for Test l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary Slide 39 Copyright 1995-1999 SCRA 3939 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Automatic Test Pattern Generation (ATPG) Algorithms l The objective is to automatically generate a test for faults in the circuit-under-test l Major classes of methods: m Pseudorandom m Ad-Hoc m Algorithmic q D-algorithm q PODEM q FAN and related algorithms q Others... Slide 40 Copyright 1995-1999 SCRA 4040 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Pseudorandom Test Generation l Simply generate an input vector using a pseudorandom number generator and perform fault simulation to determine if it detects the target fault l The characteristics of the fault greatly influence how well pseudorandom test generation will work m Easy-to-detect faults m Hard-to-detect faults l Typically used in the beginning of the test generation process to remove easy-to-detect faults from the fault list Slide 41 Copyright 1995-1999 SCRA 4141 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Pseudorandom Test Generation (Cont.) Fault Coverage vs. Number of Pseudorandom Test Vectors Fault Coverage Number of Test Vectors Cutoff Point 100% Deterministic ATPG Slide 42 Copyright 1995-1999 SCRA 4242 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Ad-Hoc l Uses functional test vectors developed by designers for functional verification and design debugging by: m Fault simulating to determine fault coverage m Determining locations of undetected faults m Adding additional functional tests to exercise areas of design with undetected faults m Re-fault simulating and repeating until desired fault coverage is achieved l No special test generation system is required, only fault simulator l Utilizes existing vectors and designer expertise l Achieving high fault coverage may be difficult and time consuming - especially for synthesized designs Slide 43 Copyright 1995-1999 SCRA 4343 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP D Algorithm l First algorithm proved complete - developed by Roth at IBM in 1966 m Complete - can be proven that the algorithm will generate a test for a fault if it exists l Introduced D notation m D - 1 in the good circuit 0 in the faulty m D - 0 in the good circuit 1 in the faulty (Dbar) l PDCF - Primitive D cube of failure - a set of inputs to a module that will sensitize a specific fault within the module l PDC - Propagation D cube - a set of inputs to a module that will propagate a D from the inputs to the outputs Slide 44 Copyright 1995-1999 SCRA4 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP D Algorithm (Cont.) A B C A B C 1 D D D 1 D 1 D D D 1 D D D D D D D AND Gate PDCs Good Faulty Circuit Circuit D Value Value Value 1 0 D 0 1 D Fault PDCF A B C A s-a-0 1 1 D B s-a-0 1 1 D C s-a-0 1 1 D A s-a-1 0 1 D B s-a-1 1 0 D C s-a-1 X 0 D C s-a-1 0 X D AND Gate PDCFs D Notation Slide 45 Copyright 1995-1999 SCRA 4545 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP D Algorithm (Cont.) Example B A C D E F G H J K L I s-a-1 [Klenke92] IEEE 1992 A B C D E F G H I J K L D 1 X D 1 1 1 X D 1 1 0 1 0 D 0 1 1 0 0 1 0 0 D 0 D 1 1 0 X 0 0 1 0 0 D 0 D TC0 TC1 TC2 TC3 TC4 TC5 Initial test cube Pick PDCF Imply from G to A and B Set objective K=0 and imply I and F Imply from I to E and H Justify H A B C D E F G H I J K L D X 1 D X 1 D 1 1 TC0 TC1 TC2 Initial test cube Pick PDCF Imply K and L from I ; no test Slide 46 Copyright 1995-1999 SCRA 4646 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP PODEM l Path Oriented DEcision Making - developed in 1981 by Goel to address the problem D algorithm had with XOR gates m D algorithm is exponentially complex to the number of internal circuit nodes - XOR gates make the complexity of the D algorithm approach this limit m PODEM expresses the search space in terms of assignments to the primary inputs only l PODEM is also a branch-and-bound algorithm which is exponentially complex to the number for circuit inputs - usually a much smaller number than circuit nodes Slide 47 Copyright 1995-1999 SCRA 4747 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP PODEM (Cont.) Example B A C D E F G H J K L I s-a-1 A B C D E F 10 10 10 10 10 10 Inconsistent Test [Klenke92] IEEE 1992 Slide 48 Copyright 1995-1999 SCRA 4848 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP FAN and Related Algorithms l FAN is an improvement on PODEM designed to utilize circuit topology information to increase search efficiency l Both the D algorithm and PODEM have trouble with areas of reconvergent fanout l Reconvergent fanout can cause complex interactions between internal circuit nodes l Example: M Copyright 1995-1999 SCRA 112112 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Signature Analysis (Cont.) + +... SR G(x)Q(x) Initial state: I(x) = 0 Final State: R(x) G(x) P(x) = Q(x) + R(x) P(x) or G(x) = P(x)Q(x) + R(x) number of bit streams that produce a specific signature: 2m2m 2n2n = 2 m-n m - bits in input stream n - bits in signature register number of erroneous bits streams that produce the same signature as a particular fault-free response: 2 m-n - 1 total proportion of masking error streams: 2 m-n - 1 2 m - 1 P SA (M | m,n) = 2 -n for m >> n [Abramovici90] IEEE 1990 Slide 113 Copyright 1995-1999 SCRA 113113 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Signature Analysis Example 12345 +++ XZ P(x) = 1 + x 2 + x 4 + x 5 Input sequence: 1 1 1 1 0 1 0 1 (8 bits) G(x) = x 7 + x 6 + x 5 + x 4 + x 2 + 1 Time Input Stream Register contents Output stream 1 2 3 4 5 0 1 0 1 0 1 1 1 1 0 0 0 0 0 Initial state 1 1 0 1 0 1 1 1 1 0 0 0 0 5 1 0 1 0 1 1 1 1 6 1 0 0 0 0 1 0 1 7 1 0 0 0 0 1 0 1 8 Remainder 0 0 1 0 1 1 0 1 Remainder Quotient R(x) = x 2 + x 4 Q(x) = 1 + x 2...... Check: P(x): x 5 + x 4 + x 2 + 1 x 2 + 1 Q(x): x 7 + x 6 + x 4 + x 2 + x 5 + x 4 + x 2 + 1 = x 7 + x 6 + x 5 + 1 Thus: P(x)Q(x) + R(x) = x 7 + x 6 + x 5 + x 4 + x 2 + 1 = G(x) [Abramovici90] IEEE 1990 Slide 114 Copyright 1995-1999 SCRA 114114 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Multiple Input Signature Register... DQDQ DQ DQ + + + Q1Q1 Q2Q2 Q3Q3 QnQn C n-2 C1C1 C n-1 CnCn + D1D1 D2D2 D3D3 DnDn [Abramovici90] IEEE 1990 Slide 115 Copyright 1995-1999 SCRA 115115 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Built-In Logic Block Observer (BILBO) Mu x B1B1 B2B2 S in S out Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q6Q6 Q7Q7 Q8Q8 Z1Z1 Z2Z2 Z3Z3 Z4Z4 Z5Z5 Z6Z6 Z7Z7 Z8Z8 Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q6Q6 Q7Q7 Q8Q8 Z1Z1 Z2Z2 Z3Z3 Z4Z4 Z5Z5 Z6Z6 Z7Z7 Z8Z8 System Orientation Mode B 1 B 2 = 11 L1L1 L2L2 L3L3 L4L4 L5L5 L6L6 L7L7 L8L8 [Williams83] IEEE 1983 Slide 116 Copyright 1995-1999 SCRA 116116 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP BILBO (Cont.) Shift Register Mode B 1 B 2 = 00 L1L1 L2L2 L3L3 L4L4 L5L5 L6L6 L7L7 L8L8 S in S out Multiple Input Signature Register Mode B 1 B 2 = 10 Z1Z1 Z2Z2 Z3Z3 Z4Z4 Z5Z5 Z6Z6 Z7Z7 Z8Z8 L1L1 L2L2 L3L3 L4L4 L5L5 L6L6 L7L7 L8L8 [Williams83] IEEE 1983 Slide 117 Copyright 1995-1999 SCRA 117117 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP BILBO Testing BILBO Combina- tional Network 1 Combina- tional Network 2 SA RegPN Gen BILBO Combina- tional Network 1 Combina- tional Network 2 PN GenSA Reg [Williams83] IEEE 1983 Slide 118 Copyright 1995-1999 SCRA 118118 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP BIST Case Study - TMS32010 Data Path ALU R2 R3 R1a R1b Multiplier 88 6 16 Control Inputs [Kim88] IEEE 1988 Slide 119 Copyright 1995-1999 SCRA 119119 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP BILBO Scheme ALU R2 R3 R1a R1b Multiplier 88 6 16 Control Inputs PRPG BILBO PRPG MISR 2 testing sessions required [Kim88] IEEE 1988 Slide 120 Copyright 1995-1999 SCRA 120120 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Single Signature Testing Scheme ALU R2 R3 R1a R1b Multiplier 88 6 16 Control Inputs PRPG MISR 1 testing session required [Kim88] IEEE 1988 Slide 121 Copyright 1995-1999 SCRA 121121 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MISR Scheme I ALU R3 R1a R1b Multiplier 88 6 16 Control Inputs PRPG MISR 1 testing session required 0 22 Extended R2 [Kim88] IEEE 1988 Slide 122 Copyright 1995-1999 SCRA 122122 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MISR Scheme II ALU R2 R3 R1a R1b Multiplier 88 6 16 Control Inputs PRPG MISR PRPG MISR 1 testing session required [Kim88] IEEE 1988 Slide 123 Copyright 1995-1999 SCRA 123123 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Case Results No. of test patterns BILBO scheme Single signature testing MISR scheme I Average Minimum Maximum Fault coverage (%) 2,177 830 3,619 100 > 3,000 - - 64.5 1,457 634 2,531 100 MISR scheme II 1,378 721 2,121 100 [Kim88] IEEE 1988 Slide 124 Copyright 1995-1999 SCRA 124124 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Autonomous Built-In Self-Test (ABIST) l An approach to testing in which a module contains logic that allows it to test itself IC, PCB or SYSTEM BISTed Module n BISTed Module 1 [Agarwal95] BIST Controller Circuit Under Test Test Data Response Turn BIST On Go/No Go Status Diagnostic Data To Other Circuits Slide 125 Copyright 1995-1999 SCRA 125125 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Memory BIST Overview TAP BIST Controller Collar SRAM Control ADDR: DIN DOUT DO b log2w b bist control memory control bist address memory address serial data-in data-in serial data-out BIST go done COMPSTAT [Agarwal95] Slide 126 Copyright 1995-1999 SCRA 126126 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Self-Testing System Architecture Field Diagnosis System Software test & maint. processor card 1149 Master and BIST Memory CPU ASIC PCB LogicMemory BIST 1149.1 TAP 1149.1 Boundary Scan ASIC [Agarwal95] Slide 127 Copyright 1995-1999 SCRA 127127 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Generations of Test Solutions l Completely External Testing: m Generation 1: Functional verification vectors used as manufacturing test vectors (fault simulate & supplement with additional functional vectors to raise fault coverage) m Generation 2: Scan insertion and Automatic Test Pattern Generation l Electronic Systems Test Automation (ESTA) m Generation 3: Automatic Built-In Self-Test (ABIST) using 1149.X m Generation 4: Hierarchical and integrated BIST (HIBIST) from chip to system [Agarwal95] Slide 128 Copyright 1995-1999 SCRA 128128 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Benefits of ESTA l Reduces time to market during design and manufacturing m Production test development time can be reduced from weeks to days m Simplifies and manages the test development process m Handles very complex designs m Compatible with HDL and synthesis-based design flow l Reduces cost over full product test lifecycle m Reduces tester capital costs m Spans the test hierarchy from IC to MCM/PCB to system m Allows test data to be manipulated for reuse at higher levels m Permits field diagnosis [Agarwal95] Slide 129 Copyright 1995-1999 SCRA 129129 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Benefits of ESTA (Cont.) l Enhances quality m Permits very high fault coverage tests m Supports at-speed test m Tests embedded or hard-to-reach functionality m Supports validation of test structures and data [Agarwal95] Slide 130 Copyright 1995-1999 SCRA 130130 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary Slide 131 Copyright 1995-1999 SCRA 131131 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Hierarchical Design For Test l Testability must be considered at all levels of the design m ASIC/FPGA m MCM m Board m System l System-level test requirements must be propagated down to the lower level of the design to exploit design options at these levels l Additional DFT features could be added to an ASIC to assist in testing other chips connected to it l The alternative is to rigidly specify DFT rules for each level of the design m Does not support COTS use [MAbadir94] Slide 132 Copyright 1995-1999 SCRA 132132 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Hierarchical Design For Test (Cont.) l Testability requirements must be captured at an early stage of the design process l Standard interfaces should be used to simplify testing interconnects l A hierarchical test strategy has three main components: m Partitioning of the design into independently testable units (test kernels) m Specification of test methods for each test kernel q Full scan, functional testing, boundary scan m Setting of targets for trade-off parameters q Fault coverage, test application time, test cost [MAbadir94] Slide 133 Copyright 1995-1999 SCRA 133133 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Hierarchical Design For Test (Cont.) MCM SEM-E U1 U2 System Test Bus LRM Test Controller RAM ASIC DSP Proc. MCM Test Controller 1149.1 bus ASIC Chip Internal Circuit Partition On-chip Test Controller [MAbadir94] Slide 134 Copyright 1995-1999 SCRA 134134 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary Slide 135 Copyright 1995-1999 SCRA 135135 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Synthesis for Test l Synthesis for test is: m Synthesizing inherently testable circuits m Incorporating BIST circuitry into a behaviorally synthesized circuit m Constraining logic synthesis to conform to structured DFT techniques like scan m Developing a complete test program for a synthesized circuit l The definition depends on the user and on the level of synthesis supported m Gate-level test synthesis m RTL test synthesis Slide 136 Copyright 1995-1999 SCRA 136136 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Elements of Synthesis for Test l Methodology selection - selection of the overall set of rules, structures, and design constraints to be used in including testability in the design process l Test structure insertion - the actual insertion of the selected test structures into the description of the circuit-under-test l Circuit verification - insuring that the test circuitry and the circuit-under-test operate as intended during test as well as normal operation l Program preparation - generation of the actual test programs used during manufacture - generation of test patterns, construction of scan strings, etc. Slide 137 Copyright 1995-1999 SCRA 137137 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Gate-Level Synthesis for Test l Most mature technology - commercially available l Five separate activities: m Methodology selection - usually a limited number of fixed DFT method available m Automatic test structure insertion q Select which flip-flops belong in which scan chain(s) q Connect successive elements in the chain(s) q Connect global signals m DFT rule checking - check for design techniques which could cause a problem with the selected methodology m Automatic test pattern generation - generate tests for the circuit-under-test given the DFT method and fault model m Test vector translation - reformatting test vectors for specific ATE equipment used Slide 138 Copyright 1995-1999 SCRA 138138 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Gate-Level Synthesis for Test (Cont.) A B C D CLK F DQ DQ DQ Slide 139 Copyright 1995-1999 SCRA 139139 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP RTL Synthesis for Test l Tools less mature from a commercial standpoint l Activities: m Methodology selection - selection of a test methodology for a specific module(s) m Automatic test structure insertion - insertion of RTL statements necessary to generate DFT circuitry m Test structure verification - tools may be available to actually fix DFT violations m Test program preparation - conversion of RTL level test vectors to gate level compatible vectors may be difficult Slide 140 Copyright 1995-1999 SCRA 140140 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary Slide 141 Copyright 1995-1999 SCRA 141141 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Section Outline l DFT Standards m IEEE Std. 1149.1 m IEEE Std. 1149.1b m IEEE Std. 1149.5 m IEEE Std. 1029.1 m MIL-HDBK-XX47 Slide 142 Copyright 1995-1999 SCRA 142142 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP DFT Standards l IEEE Std. 1149.1 - Test Access Port and Boundary-Scan Architecture m Defines the architecture of the TAP and Boundary Scan cells m IEEE 1149.1b - defines the Boundary-Scan Description Language (BSDL) l IEEE Std. P1149.2 - Extended Serial-Digital Interface Standard m Defines a scheme that supports board-level interconnect testing and internal-scan testing of components l IEEE Std. P1149.3 - Real Time Test Bus Standard m Proposed to define standards for real-time testability bus (work discontinued) Slide 143 Copyright 1995-1999 SCRA 143143 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP DFT Standards (Cont.) l IEEE Std. P1149.4 - Mixed-Signal Test Bus Standard m Proposed to extend the concept of boundary-scan to analog and mixed signal devices l IEEE Std. P1149.5 - Module Test and Maintenance Bus Standard m Defines specifications for a serial test and maintenance bus for systems with two or more modules plugged into a backplane l IEEE Std. 1029.1 - Waveform and Vector Exchange Specification (WAVES) m Defines standard for VHDL description of stimulus vectors and responses l MIL-HDBK-XX47 Testability Analysis Handbook m Defined the DoD view of Design for Test Slide 144 Copyright 1995-1999 SCRA 144144 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture l Defines standard terms l Defines the boundary-scan cell architecture, TAP controller architecture, and board-under-test architecture described previously l Defines the test modes described previously l Defines alternative cell and board architectures l Defines the actual state diagram for the TAP controller l Defines timing relationships for controller states and TAP port events l Defines the functionality of the Instruction, Test Data, and Bypass registers Slide 145 Copyright 1995-1999 SCRA 145145 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP TAP Controller State Diagram Test-Logic- Reset Run-Test-/ Idle TMS=1 0 Select- DR-Scan Capture-DR Shift-DR Exit-DR Pause-DR Exit2-DR Update-DR Select- IR-Scan Capture-IR Shift-IR Exit-IR Pause-IR Exit2-IR Update-IR 0 0 0 0 11 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 1 1 1 1100 0 [IEEE 1149.1] IEEE 1990 Slide 146 Copyright 1995-1999 SCRA 146146 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Logic Operation: Data Scan TCK TMS Controller state TDI Data input to IR IR shift-register Data input to TDR TDR shift-register Parallel output of TDR TDO Select-DR-Scan Run-Test/Idle Capture-DR Exit1-DRExit2-DRExit1-DR Update-DR Shift-DR Pause-DR Shift-DR Select-DR-Scan Select-IR-Scan Run-Test/Idle Test-Logic-Reset Parallel output of IR = Dont care or Undefined Output Inactive Output from selected test data register InstructionIDCODE Old DataNew Data [IEEE 1149.1] IEEE 1990 Slide 147 Copyright 1995-1999 SCRA 147147 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std. 1149.1b BSDL l BSDL is intended to provide a machine-readable means of representing some parts of the documentary information specified in 1149.1 l The goal of the language is to facilitate communication between companies, individuals, and tools that need to exchange information on the design of test logic; for example: l Suppliers can supply BSDL descriptions of components that support 1149.1 to purchasers m ATPG tools could use BSDL description of components on a board to generate test vectors m BSDL descriptions of 1149.1-compliant components could be used for synthesis Slide 148 Copyright 1995-1999 SCRA 148148 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std. 1149.1b BSDL (Cont.) l BSDL is a subset of IEEE Std 1076-1993 VHDL l A standard VHDL package STD_1149_1_1994 is defined m Attributes q TAP Ports q TAP Instructions m Types q Cell Data q ID Codes m Constants q Cell Types Slide 149 Copyright 1995-1999 SCRA 149149 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std. P1149.5 Standard Module Test and Maintenance (MTM) Bus Protocol l Defines a standardized serial, backplane Test and Maintenance bus l Intended for use in the test, diagnosis, and maintenance of electronic subsystems and modules m Module Test m Subsystem Test m Subsystem Diagnosis m Software/Hardware Development l Defines MTM-Bus architecture l Defines MTM-Bus protocol m Physical layer m Link layer m Message layer Slide 150 Copyright 1995-1999 SCRA 150150 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MTM-Bus Signals... M-moduleS-module Clock Source Master Data (MMD) Slave Data (MSD) Pause Request (MPR) Control (MCTL) Clock (MCLK) [IEEEP1149.5] IEEE 1995 Slide 151 Copyright 1995-1999 SCRA 151151 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MTM Protocol Layers Physical Layer Master Link Layer Master Message Layer Slave Link Layer Slave Message Layer Applications [IEEEP1149.5 ] IEEE 1995 Slide 152 Copyright 1995-1999 SCRA 152152 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module to MTM Test Bus Translation IEEE Std. 1149.5 MTM-Bus Bus Transceiver ANSI/IEEE Std. 1149.1 Bus Other Board-level Test Buses.................. Test-bus Interface [IEEEP1149.5] IEEE 1995 Slide 153 Copyright 1995-1999 SCRA 153153 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std. 1029.1 Waveform and Vector Exchange Specification (WAVES) l A language for specifying stimulus and response patterns for digital electronic systems l Provides for unambiguously exchanging such patterns between and among design and test environments l Can represent various levels of waveform detail m Simulator event trace data m Highly structured test vectors typical of automatic test equipment l WAVES is a subset of IEEE Standard 1076-1987 VHDL l WAVES declarations and procedures declared in separate package - instantiated with circuit- under-test in test bench Slide 154 Copyright 1995-1999 SCRA 154154 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std. 1029.1 WAVES (Cont.) l WAVES Package: m Required Declarations q Logic Value - values to be applied directly to DUT q Pin Codes - input values used to list waveform q Test Pins - list of pins in the waveform m Waveform Generator Procedure - reads input values and applies them to the DUT q Values can be build in to the generator procedure Simple list Generator algorithm q Values can be read from an external file Slide 155 Copyright 1995-1999 SCRA 155155 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MIL-HDBK-XX47 Testability Analysis Handbook l Outlines the DoD documents that relate to DFT m MIL-STD-2165A, Testability Program for Systems and Equipment m MIL-STD-499A, Engineering Management m MIL-STD-470A, Maintainability Program Requirements for Systems and Equipments m MIL-STD-1388-1A, Logistics Support Analysis m MIL-STD-785, Reliability Program for Systems and Equipments Development and Production m MIL-HDBK-59, Department of Defense Computer-Aided Acquisition and Logistics Support (CALS) Program Implementation Guide m MIL-STD-1814, Integrated Diagnostics, Roadmap, and Requirements Document Slide 156 Copyright 1995-1999 SCRA 156156 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MIL-HDBK-XX47 (Cont.) l Test Design and Assessment m Incorporate embedded and external test capability for a system or equipment that will satisfy testability performance requirements m Assess the level of test effectiveness that will be achieved for a system or equipment m Ensure the effective integration and compatibility of this test capability with other diagnostic elements l Outputs m Product fault detection and fault isolation performance levels that achieve the specified test effectiveness requirements Slide 157 Copyright 1995-1999 SCRA 157157 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary Slide 158 Copyright 1995-1999 SCRA 158158 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Lockheed Martin ATL DFT Methodology The Expanded Definition of Testing in the DFT Methodology System Definition Architecture Definition Detailed Design Manufacturing Field Support The Testing Process [Sedmak95] Slide 159 Copyright 1995-1999 SCRA 159159 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP ATL DFT Methodology Terms and Definitions Prediction The assessment of the degree of compliance to test requirements through analysis or comparison with similar library elements Examples of means: Circuit level testability measures, topological dependency models Verification The assessment of the degree of compliance to test requirements through simulation or closed form proof Examples of means: Deterministic fault simulation, exhaustive test coverage proofs Measurement The assessment of the degree of compliance to test requirements through monitoring test performance on a physical item under test Examples of means: Automatic fault history logging, ATE- based data collection [Sedmak95] Slide 160 Copyright 1995-1999 SCRA 160160 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP ATL DFT Methodology Additional Terms and Definitions Metrics Quantitative parameters used for requirements specification, compliance tracking, tradeoff analysis, and selection TMAT The Test Metrics/Tool Application Table, used in the Methodology to select a metric and tool(s), or method, to predict, verify, or measure compliance [Sedmak95] Slide 161 Copyright 1995-1999 SCRA 161161 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Relationship of Test Requirements, Test Strategies and Test Architectures Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures [Sedmak95] Slide 162 Copyright 1995-1999 SCRA 162162 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP System Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures Subsystem Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures Board Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures MCM Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures Chip Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures Requirements Predict, Verify & Measure Relationship of Test Requirements, Test Strategies, and Test Architectures across Packaging Hierarchy [Sedmak95] Slide 163 Copyright 1995-1999 SCRA 163163 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Strategy Diagram (TSD) l Used to bridge from requirements to implementation and through to manufacturing and field support m Organizes and manages the key data generated during, and flowing between the methodology process steps m Based on simple three dimensional spreadsheet type structures and operations m Fault populations flow through various test means until they are Detected, Isolated and Corrected [Sedmak95] Slide 164 Copyright 1995-1999 SCRA 164164 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Strategy Diagram (Cont.) l Examples of applications include: m Capturing quantitative test requirements m Developing test strategies and making tradeoffs, including analysis of the mixing of test means m Flowing requirements down to lower assembly levels m Capturing predicted, verified, and measured (PVM) test performance data and comparing it against requirements for compliance tracking m Rolling up test performance PVM data from lower levels for system level analysis m Performing parametric analysis such as test time, product quality [Sedmak95] Slide 165 Copyright 1995-1999 SCRA 165165 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP ATL DFT Methodology in the RASSP Methodology Manufacturing/ Integration & Test Field Support DFT/BIST Flowdown and Implementation Detailed Design DFT/BIST HW DFT/BIST SW DFT/BIST Strategy and Architecture Development Architecture Definition DFT/BIST HW Ver DFT/BIST SW Ver RASSP Design Process HW/SW Codesign System Definition Detailed Design HW SW RASSP Reuse Library Systems Hardware Test Architecture Software Etc.. Architecture Definition HW SW HW SW F.D. Model Year N-1 Results F.D. Manufacturing Test Req.'s. Customer & Derived Consolidated Test Requirements System Definition Field Test & ARM Req.'s. Customer & Derived Development Test Req.'s. Customer & Derived PREDICT VERIFY MEASURE Test Requirements Compliance Tracking Model Year Architecture Test Architecture Manufacturing/ Integration & Test Field Support DFT HW Select DFT SW Select [Sedmak95] Slide 166 Copyright 1995-1999 SCRA 166166 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP ATL HW Testability Architecture l Bias towards Boundary Scan and BIST but accommodate COTS and use ATE when required and/or practical l Lead - Follow - or Get out of the Way philosophy for MCM/ board and system test l Hierarchical array of dedicated Test & Maintenance Busses and controllers (IEEE 1149.1, P1149.5, Scan Bridge, and/or ASP as required) l Re-useable (within and between packaging level) BIST controllers, PRPGs and SARs l Accommodates Spoilers m COTS m NDI m Development Only Contracts m Expendables LRU LRU Test Controller Module Executive Board Backplane Board Test Controls Test Bus Chip Test Bus TAP Chip TAP Chip TAP Chip System Maintenance Controller System Maintenance Bus Operating System [Sedmak95] Slide 167 Copyright 1995-1999 SCRA 167167 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP RASSP Concepts which DFT Leverages RASSP concepts provides a good framework for integrating design with test. [Sedmak95] Slide 168 Copyright 1995-1999 SCRA 168168 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Benefits of Integrating DFT into RASSP 1. Consolidate test requirements 2. Incorporate TSD construct 3. Extend concept of re- use 4. Implement conformance checking (via TSD). 5. Model test resources in VP 6. Integrate test architecture with MYA ApproachBenefit 1. Reduce overall test development efforts and cost 2. Bridge requirements to implementation 3. Minimize impact of test on schedule and cost 4. Consistent framework for feedback of model year results. 5. Concurrent test development shortens schedule 6. Consistent use; Model year upgrades of test resources [Sedmak95] Slide 169 Copyright 1995-1999 SCRA 169169 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Design-For-Test Integration Tasks l Work Flows and Activity Definitions l DFT Tool Integration's m CAT or Test Specific (Fault simulation, Testability Analysis, DFT/ BIST insertion, ATPG,...) m CAE or Re-use of functional engineering tools (HDL Entry, SW development, simulation, Data Management,...) l Re-use Libraries m Object Class Hierarchy (DOCH) m Contents of re-use elements (what data constitutes a re- use element) m Initial population of critical elements l Templates and standards for test related product data l Training m Benefits m Process m Tools [Sedmak95] Slide 170 Copyright 1995-1999 SCRA 170170 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary Slide 171 Copyright 1995-1999 SCRA 171171 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Summary l A background on general testing was provided m Fault Modeling m Test Generation m Faults Simulation m I DDQ Testing l A background on Design for Test was provided m DFT Techniques m Built-in Self Test Techniques m Hierarchical DFT Techniques m Synthesis for Test l Finally, a background on how testing and DFT is used in the design process was provided m DFT Standards m Design flows with DFT Slide 172 Copyright 1995-1999 SCRA 172172 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP References [Aitken95] Aitken, R. C., An Overview of Test Synthesis Tools, IEEE Design and Test of Computers, pp. 8-15, Summer 1995. [Abadir94] Abadir, M., G. McFall, S. Spencer, K. Drake, J. Evans A Hierarchical Design for Test (DFT) Methodology for the Rapid Prototyping of Application Specific Signal Processing (RASSP), Preliminary Working Document, Version 0.73, August 10, 1994. [Abramovici90] Abramovici, M., M. A. Breuer, A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Computer Society Press, 1990 ; IEEE 1990 [Agarwal95] Agarwal, V. K., Hierarchical and Integrated Build-In Self-Test CAD Tools, Proceedings of the RASSP PI Meeting January 9-13, 1995. [Fujiwara85] Fujiwara, H. Logic Testing and Design for Testability, The MIT Press, 1985. [Hayes85] Hayes, John P., Fault Modeling, IEEE Design and Test of Computers, April, 1985, pp. 37- 44. [Hemmady94] Hemmady, S., VLSI Test Automation: Fact or Fiction?, ASIC $ EDA, September 1994, pp. 56-58. [IEEE] All referenced IEEE material is used with permission. [IEEE1149.1] IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture; IEEE 1990 [IEEEP1149.5] IEEE P1149.5 Standard Module Test and Maintenance (MTM) Bus Protocol; ; IEEE 1995 [Johnson89] Johnson, B. W., Design and Analysis of Fault Tolerant Digital Systems, Addison-Wesley, 1989. [Kim88] Kim, K., D. S. Ha, On Using Signature Registers as Pseudorandom Pattern Generators in Built-In Self-Testing, IEEE Transactions on Computer-Aided Design, Vol. 7, No. 8, August 1988, pp. 919-928 ; IEEE 1988 Slide 173 Copyright 1995-1999 SCRA 173173 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP References (cont.) [Klenke92] Klenke, R. H., R. D. Williams, J. H. Aylor, Parallel-Processing Techniques for Automatic Test Pattern Generation, IEEE Computer, January 1992, pp. 71-84 ; IEEE 1992 [Lesser80] Lesser, J. D., J. J. Shedletsky, An Experimental Delay Test Generator for LSI Logic,, IEEE Transactions on Computers, March, 1980, pp. 235-248. [Richards97] Richards, M., Gadient, A., Frank, G., eds. Rapid Prototyping of Application Specific Signal Processors, Kluwer Academic Publishers, Norwell, MA, 1997 [Sedmak95] Sedmak, R., J. Evans, Tutorial on the RASSP Design-for-Test ability Methodology, 2nd Annual RASSP Conference, 1995. [Soden92] Soden, J. M., C. F. Hawkins, R. K. Gulati, and W. Mao, I DDQ Testing: A Review, Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Norwell, MA, 1992, pp. 5-17. [MAbadir94] Abadir, M. S., Hierarchical Design for Testability Tools for RASSP, Supplemental presentation material for the Martin Marietta RASSP Semi-Annual Government Review, February, 23 & 24, 1994. [Maxwell92] Maxwell, P. C., R. C. Aitken, IDDQ Testing as a Component of a Test Suite: The Need for Several Fault Coverage Metrics, Journal of Electronic Testing: Theory and Applications (JETTA), Kluwer Academic Publishers, Norwell, MA, Vol. 3, No. 4, December 1992, pp. 19-30. [Maly87] Maly, W., Realistic Fault Modeling for VLSI Testing, Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, pp. 173-180. [Malaiya86] Malaiya, Y. K., A. P. Jayasumana, R. Rajsuman, A Detailed Examination of Bridging Faults, IEEE, 1986, pp. 78-81. [Waicukauski87] Waicukauski, J. A., et. al., Transitional Fault Simulation, IEEE Design & Test, April, 1987, pp. 32-38; IEEE 1987 [Williams83] Williams, T. W., K. P. Parker, Design for Testability - A Survey, Proceedings of the IEEE, Vol. 71, No. 1, January 1983, pp. 98 - 112; IEEE 1983