copyright 2006 daniel d. gajski 1 extreme makeover of system design science daniel gajski center...

Copyright 2006 Daniel D. Gajski 1

Extreme Makeoverof

System Design Science

Daniel Gajski

Center for Embedded Computer Systems (CECS)

University of California, Irvine

[email protected]


History of design flow

Specs

Algorithms

Capture &Simulate

Specs

Algorithms

Describe &Synthesize

ExecutableSpec

Algorithms

Specify, Explore& Refine

Architecture

Network

SW/HW

Logic

Physical

SW? SW?

Design

Logic

Physical

Design

Logic

Physical

Manufacturing Manufacturing Manufacturing

1960's 1980's 2000's

Functionality

Simulate Simulate

Describe

Algorithms

Connectivity

Protocols

Performance

Timing

System Gap

Design Gap: HW, SW, Application

Real gap: behavior and structure (semantics and syntax)


Simulation based methodology

case X is when X1=> . . . when X2=>

Finite state machine

Controller

3.415

2.715

--

--

Look-up table

Memory

Simuletable but not synthesizable or verifiable

Ambiguous semantics of hardware/system level languages


Arithmetic algebra

a*(b+c) = a*b + a*c

< objects, operations>

Arithmetic algebra allows creation of expressions and equations


Model algebra

B1

B2 B3

B1

B2 B3

PE1 PE2

=

<objects, compositions>

Model algebra allows creation of models and model equivalences


Methodology based on model algebra

Algebra := < {objects}, {operations} >

Model algebra := < {objects}, {compositions} >

Refinement is an ordered set of model transformations

< tm, … , t2, t1 > if and only if

model B = tm( … ( t2( t1( model A ) ) ) … )

Design methodology := < {models}, {refinements} >

Question: { models }? ; { transformations }?


Why Model Algebra?

1. Defines SL semantics

2. Defines SL languages and styles

3. Identifies SL methodology

4. Enables SL design automation

5. Closes SW-HW gap

6. Introduces interoperability

7. Supports IP trade


Specify-Explore-Refine Methodology

System specificationmodel

Cycle accurateimplementation model

SER

Intermediate models

Design decisions

Model refinement

Replacement or re-composition


Y-Chart

Behavior(Function)

Structure(Netlist)

Physical(Layout)

Logic

Circuit

Processor

System

F(...)

F(...)

F(...)

F(...)


Processor behavioral model

o1 o2

o1 o2

o3

o2 o3

o4

o1

o6o5

s3

s1 s2

FSM

a b

x y

b c

z

DFG1

DFG3 DFG2

a c d

x w z

Language C -> CDFG -> FSMD (FSM +DFG)


Processor structure

RF / Scratch pad

ALU MUL

Sta

tus

B3

PC

AG

CW

offset

status

address

const

CMem

Memory

B2

B1

Programmable controller

FU pipelining

Datapath pipelining

Data forwarding

Configurable datapath

Controller pipelining

(Processor-level structural model: NISC)


Processor synthesis

Op1 Op2

Op3

Op1 Op2

S1 S2

S3

FSMD model

Component selection

CA scheduling

Variable binding Operation Binding

Bus Binding

Controller Synthesis

Processor

D Q

D Q

D Q

Controlinputs

Next-statelogic

orAddress

generator

Outputlogic

orProgrammemory

Stateregister

orPC

Controloutputs

Controlsignals

Bus1

Bus2

Selector

Register

Datapathoutputs

ALU

Bus3

Datapath

Signalstatus

Controller

Register Memory

RF

SR

IR

Latch

Datamemory

Op2 Op3

Op4

Op6

Op1

Op5

Processor


System behavioral model

Proc3

Proc4

Proc5

Proc1

Proc2

(Serial-parallel processes: UML + C/ SystemC)


System structure

MemoryIP comp.

Interface Interface

Memory

Interface

Processor

Interface

Custom HW

BUS

(Netlist of system components: processors, memories, buses)


System Synthesis

System behavior

Proc

Proc

Proc

Proc

Proc

Memory

Memory

µProcessor

Interface

Comp.IP

Bus

Interface

Interface

Interface

Custom HW

System structure

Profiling

Allocation IF Synthesis

Refinement

Behavior Binding Channel Binding

System

Scheduling


Does it work?

• Intuitively it does– Well defined models, rules, transformations, refinements– System level complexity simplified– Worked in the past: layout, logic, RTL?

• Proof of concept demonstrated– Embedded System Environment (ESE)– Automatic model generation– Model synthesis and verification– Universal IP: NISC– Productivity gains order of 1000 – 10000

• What is next?– More contributions needed– Change of mind


Conclusions

• Extreme makeover is necessary for a new paradigm, where

– SW = HW = SOC = Embedded Systems– Simulation based chaos is not acceptable– Design methodology is based on scientific principles

• Model algebra is enabling technology for– Embedded system design– System methodology– CAD tools– Design science education

• Formalism introduces simplicity that allows– Automatic model generation (No need for languages)– Automatic synthesis and verification (No need for system designers)– Application driven system design (Application experts only needed)

copyright 2006 daniel d. gajski 1 extreme makeover of system design science daniel gajski center...

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